2 * PCIe host controller driver for Samsung EXYNOS SoCs
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
29 #include "pcie-designware.h"
31 #define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
33 /* PCIe ELBI registers */
34 #define PCIE_IRQ_PULSE 0x000
35 #define IRQ_INTA_ASSERT BIT(0)
36 #define IRQ_INTB_ASSERT BIT(2)
37 #define IRQ_INTC_ASSERT BIT(4)
38 #define IRQ_INTD_ASSERT BIT(6)
39 #define PCIE_IRQ_LEVEL 0x004
40 #define PCIE_IRQ_SPECIAL 0x008
41 #define PCIE_IRQ_EN_PULSE 0x00c
42 #define PCIE_IRQ_EN_LEVEL 0x010
43 #define IRQ_MSI_ENABLE BIT(2)
44 #define PCIE_IRQ_EN_SPECIAL 0x014
45 #define PCIE_PWR_RESET 0x018
46 #define PCIE_CORE_RESET 0x01c
47 #define PCIE_CORE_RESET_ENABLE BIT(0)
48 #define PCIE_STICKY_RESET 0x020
49 #define PCIE_NONSTICKY_RESET 0x024
50 #define PCIE_APP_INIT_RESET 0x028
51 #define PCIE_APP_LTSSM_ENABLE 0x02c
52 #define PCIE_ELBI_RDLH_LINKUP 0x064
53 #define PCIE_ELBI_LTSSM_ENABLE 0x1
54 #define PCIE_ELBI_SLV_AWMISC 0x11c
55 #define PCIE_ELBI_SLV_ARMISC 0x120
56 #define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
58 /* PCIe Purple registers */
59 #define PCIE_PHY_GLOBAL_RESET 0x000
60 #define PCIE_PHY_COMMON_RESET 0x004
61 #define PCIE_PHY_CMN_REG 0x008
62 #define PCIE_PHY_MAC_RESET 0x00c
63 #define PCIE_PHY_PLL_LOCKED 0x010
64 #define PCIE_PHY_TRSVREG_RESET 0x020
65 #define PCIE_PHY_TRSV_RESET 0x024
67 /* PCIe PHY registers */
68 #define PCIE_PHY_IMPEDANCE 0x004
69 #define PCIE_PHY_PLL_DIV_0 0x008
70 #define PCIE_PHY_PLL_BIAS 0x00c
71 #define PCIE_PHY_DCC_FEEDBACK 0x014
72 #define PCIE_PHY_PLL_DIV_1 0x05c
73 #define PCIE_PHY_COMMON_POWER 0x064
74 #define PCIE_PHY_COMMON_PD_CMN BIT(3)
75 #define PCIE_PHY_TRSV0_EMP_LVL 0x084
76 #define PCIE_PHY_TRSV0_DRV_LVL 0x088
77 #define PCIE_PHY_TRSV0_RXCDR 0x0ac
78 #define PCIE_PHY_TRSV0_POWER 0x0c4
79 #define PCIE_PHY_TRSV0_PD_TSV BIT(7)
80 #define PCIE_PHY_TRSV0_LVCC 0x0dc
81 #define PCIE_PHY_TRSV1_EMP_LVL 0x144
82 #define PCIE_PHY_TRSV1_RXCDR 0x16c
83 #define PCIE_PHY_TRSV1_POWER 0x184
84 #define PCIE_PHY_TRSV1_PD_TSV BIT(7)
85 #define PCIE_PHY_TRSV1_LVCC 0x19c
86 #define PCIE_PHY_TRSV2_EMP_LVL 0x204
87 #define PCIE_PHY_TRSV2_RXCDR 0x22c
88 #define PCIE_PHY_TRSV2_POWER 0x244
89 #define PCIE_PHY_TRSV2_PD_TSV BIT(7)
90 #define PCIE_PHY_TRSV2_LVCC 0x25c
91 #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
92 #define PCIE_PHY_TRSV3_RXCDR 0x2ec
93 #define PCIE_PHY_TRSV3_POWER 0x304
94 #define PCIE_PHY_TRSV3_PD_TSV BIT(7)
95 #define PCIE_PHY_TRSV3_LVCC 0x31c
97 struct exynos_pcie_mem_res
{
98 void __iomem
*elbi_base
; /* DT 0th resource: PCIe CTRL */
99 void __iomem
*phy_base
; /* DT 1st resource: PHY CTRL */
100 void __iomem
*block_base
; /* DT 2nd resource: PHY ADDITIONAL CTRL */
103 struct exynos_pcie_clk_res
{
110 struct exynos_pcie_mem_res
*mem_res
;
111 struct exynos_pcie_clk_res
*clk_res
;
112 const struct exynos_pcie_ops
*ops
;
115 /* For Generic PHY Framework */
120 struct exynos_pcie_ops
{
121 int (*get_mem_resources
)(struct platform_device
*pdev
,
122 struct exynos_pcie
*ep
);
123 int (*get_clk_resources
)(struct exynos_pcie
*ep
);
124 int (*init_clk_resources
)(struct exynos_pcie
*ep
);
125 void (*deinit_clk_resources
)(struct exynos_pcie
*ep
);
128 static int exynos5440_pcie_get_mem_resources(struct platform_device
*pdev
,
129 struct exynos_pcie
*ep
)
131 struct dw_pcie
*pci
= ep
->pci
;
132 struct device
*dev
= pci
->dev
;
133 struct resource
*res
;
135 ep
->mem_res
= devm_kzalloc(dev
, sizeof(*ep
->mem_res
), GFP_KERNEL
);
139 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
140 ep
->mem_res
->elbi_base
= devm_ioremap_resource(dev
, res
);
141 if (IS_ERR(ep
->mem_res
->elbi_base
))
142 return PTR_ERR(ep
->mem_res
->elbi_base
);
144 /* If using the PHY framework, doesn't need to get other resource */
148 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
149 ep
->mem_res
->phy_base
= devm_ioremap_resource(dev
, res
);
150 if (IS_ERR(ep
->mem_res
->phy_base
))
151 return PTR_ERR(ep
->mem_res
->phy_base
);
153 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
154 ep
->mem_res
->block_base
= devm_ioremap_resource(dev
, res
);
155 if (IS_ERR(ep
->mem_res
->block_base
))
156 return PTR_ERR(ep
->mem_res
->block_base
);
161 static int exynos5440_pcie_get_clk_resources(struct exynos_pcie
*ep
)
163 struct dw_pcie
*pci
= ep
->pci
;
164 struct device
*dev
= pci
->dev
;
166 ep
->clk_res
= devm_kzalloc(dev
, sizeof(*ep
->clk_res
), GFP_KERNEL
);
170 ep
->clk_res
->clk
= devm_clk_get(dev
, "pcie");
171 if (IS_ERR(ep
->clk_res
->clk
)) {
172 dev_err(dev
, "Failed to get pcie rc clock\n");
173 return PTR_ERR(ep
->clk_res
->clk
);
176 ep
->clk_res
->bus_clk
= devm_clk_get(dev
, "pcie_bus");
177 if (IS_ERR(ep
->clk_res
->bus_clk
)) {
178 dev_err(dev
, "Failed to get pcie bus clock\n");
179 return PTR_ERR(ep
->clk_res
->bus_clk
);
185 static int exynos5440_pcie_init_clk_resources(struct exynos_pcie
*ep
)
187 struct dw_pcie
*pci
= ep
->pci
;
188 struct device
*dev
= pci
->dev
;
191 ret
= clk_prepare_enable(ep
->clk_res
->clk
);
193 dev_err(dev
, "cannot enable pcie rc clock");
197 ret
= clk_prepare_enable(ep
->clk_res
->bus_clk
);
199 dev_err(dev
, "cannot enable pcie bus clock");
206 clk_disable_unprepare(ep
->clk_res
->clk
);
211 static void exynos5440_pcie_deinit_clk_resources(struct exynos_pcie
*ep
)
213 clk_disable_unprepare(ep
->clk_res
->bus_clk
);
214 clk_disable_unprepare(ep
->clk_res
->clk
);
217 static const struct exynos_pcie_ops exynos5440_pcie_ops
= {
218 .get_mem_resources
= exynos5440_pcie_get_mem_resources
,
219 .get_clk_resources
= exynos5440_pcie_get_clk_resources
,
220 .init_clk_resources
= exynos5440_pcie_init_clk_resources
,
221 .deinit_clk_resources
= exynos5440_pcie_deinit_clk_resources
,
224 static void exynos_pcie_writel(void __iomem
*base
, u32 val
, u32 reg
)
226 writel(val
, base
+ reg
);
229 static u32
exynos_pcie_readl(void __iomem
*base
, u32 reg
)
231 return readl(base
+ reg
);
234 static void exynos_pcie_sideband_dbi_w_mode(struct exynos_pcie
*ep
, bool on
)
238 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_ELBI_SLV_AWMISC
);
240 val
|= PCIE_ELBI_SLV_DBI_ENABLE
;
242 val
&= ~PCIE_ELBI_SLV_DBI_ENABLE
;
243 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_ELBI_SLV_AWMISC
);
246 static void exynos_pcie_sideband_dbi_r_mode(struct exynos_pcie
*ep
, bool on
)
250 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_ELBI_SLV_ARMISC
);
252 val
|= PCIE_ELBI_SLV_DBI_ENABLE
;
254 val
&= ~PCIE_ELBI_SLV_DBI_ENABLE
;
255 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_ELBI_SLV_ARMISC
);
258 static void exynos_pcie_assert_core_reset(struct exynos_pcie
*ep
)
262 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_CORE_RESET
);
263 val
&= ~PCIE_CORE_RESET_ENABLE
;
264 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_CORE_RESET
);
265 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 0, PCIE_PWR_RESET
);
266 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 0, PCIE_STICKY_RESET
);
267 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 0, PCIE_NONSTICKY_RESET
);
270 static void exynos_pcie_deassert_core_reset(struct exynos_pcie
*ep
)
274 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_CORE_RESET
);
275 val
|= PCIE_CORE_RESET_ENABLE
;
277 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_CORE_RESET
);
278 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 1, PCIE_STICKY_RESET
);
279 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 1, PCIE_NONSTICKY_RESET
);
280 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 1, PCIE_APP_INIT_RESET
);
281 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 0, PCIE_APP_INIT_RESET
);
282 exynos_pcie_writel(ep
->mem_res
->block_base
, 1, PCIE_PHY_MAC_RESET
);
285 static void exynos_pcie_assert_phy_reset(struct exynos_pcie
*ep
)
287 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_MAC_RESET
);
288 exynos_pcie_writel(ep
->mem_res
->block_base
, 1, PCIE_PHY_GLOBAL_RESET
);
291 static void exynos_pcie_deassert_phy_reset(struct exynos_pcie
*ep
)
293 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_GLOBAL_RESET
);
294 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 1, PCIE_PWR_RESET
);
295 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_COMMON_RESET
);
296 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_CMN_REG
);
297 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_TRSVREG_RESET
);
298 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_TRSV_RESET
);
301 static void exynos_pcie_power_on_phy(struct exynos_pcie
*ep
)
305 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_COMMON_POWER
);
306 val
&= ~PCIE_PHY_COMMON_PD_CMN
;
307 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_COMMON_POWER
);
309 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV0_POWER
);
310 val
&= ~PCIE_PHY_TRSV0_PD_TSV
;
311 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV0_POWER
);
313 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV1_POWER
);
314 val
&= ~PCIE_PHY_TRSV1_PD_TSV
;
315 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV1_POWER
);
317 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV2_POWER
);
318 val
&= ~PCIE_PHY_TRSV2_PD_TSV
;
319 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV2_POWER
);
321 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV3_POWER
);
322 val
&= ~PCIE_PHY_TRSV3_PD_TSV
;
323 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV3_POWER
);
326 static void exynos_pcie_power_off_phy(struct exynos_pcie
*ep
)
330 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_COMMON_POWER
);
331 val
|= PCIE_PHY_COMMON_PD_CMN
;
332 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_COMMON_POWER
);
334 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV0_POWER
);
335 val
|= PCIE_PHY_TRSV0_PD_TSV
;
336 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV0_POWER
);
338 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV1_POWER
);
339 val
|= PCIE_PHY_TRSV1_PD_TSV
;
340 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV1_POWER
);
342 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV2_POWER
);
343 val
|= PCIE_PHY_TRSV2_PD_TSV
;
344 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV2_POWER
);
346 val
= exynos_pcie_readl(ep
->mem_res
->phy_base
, PCIE_PHY_TRSV3_POWER
);
347 val
|= PCIE_PHY_TRSV3_PD_TSV
;
348 exynos_pcie_writel(ep
->mem_res
->phy_base
, val
, PCIE_PHY_TRSV3_POWER
);
351 static void exynos_pcie_init_phy(struct exynos_pcie
*ep
)
353 /* DCC feedback control off */
354 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x29, PCIE_PHY_DCC_FEEDBACK
);
356 /* set TX/RX impedance */
357 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0xd5, PCIE_PHY_IMPEDANCE
);
359 /* set 50Mhz PHY clock */
360 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x14, PCIE_PHY_PLL_DIV_0
);
361 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x12, PCIE_PHY_PLL_DIV_1
);
363 /* set TX Differential output for lane 0 */
364 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x7f, PCIE_PHY_TRSV0_DRV_LVL
);
366 /* set TX Pre-emphasis Level Control for lane 0 to minimum */
367 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x0, PCIE_PHY_TRSV0_EMP_LVL
);
369 /* set RX clock and data recovery bandwidth */
370 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0xe7, PCIE_PHY_PLL_BIAS
);
371 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x82, PCIE_PHY_TRSV0_RXCDR
);
372 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x82, PCIE_PHY_TRSV1_RXCDR
);
373 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x82, PCIE_PHY_TRSV2_RXCDR
);
374 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x82, PCIE_PHY_TRSV3_RXCDR
);
376 /* change TX Pre-emphasis Level Control for lanes */
377 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x39, PCIE_PHY_TRSV0_EMP_LVL
);
378 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x39, PCIE_PHY_TRSV1_EMP_LVL
);
379 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x39, PCIE_PHY_TRSV2_EMP_LVL
);
380 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x39, PCIE_PHY_TRSV3_EMP_LVL
);
383 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0x20, PCIE_PHY_TRSV0_LVCC
);
384 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0xa0, PCIE_PHY_TRSV1_LVCC
);
385 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0xa0, PCIE_PHY_TRSV2_LVCC
);
386 exynos_pcie_writel(ep
->mem_res
->phy_base
, 0xa0, PCIE_PHY_TRSV3_LVCC
);
389 static void exynos_pcie_assert_reset(struct exynos_pcie
*ep
)
391 struct dw_pcie
*pci
= ep
->pci
;
392 struct device
*dev
= pci
->dev
;
394 if (ep
->reset_gpio
>= 0)
395 devm_gpio_request_one(dev
, ep
->reset_gpio
,
396 GPIOF_OUT_INIT_HIGH
, "RESET");
399 static int exynos_pcie_establish_link(struct exynos_pcie
*ep
)
401 struct dw_pcie
*pci
= ep
->pci
;
402 struct pcie_port
*pp
= &pci
->pp
;
403 struct device
*dev
= pci
->dev
;
406 if (dw_pcie_link_up(pci
)) {
407 dev_err(dev
, "Link already up\n");
411 exynos_pcie_assert_core_reset(ep
);
416 exynos_pcie_writel(ep
->mem_res
->elbi_base
, 1,
419 phy_power_on(ep
->phy
);
422 exynos_pcie_assert_phy_reset(ep
);
423 exynos_pcie_deassert_phy_reset(ep
);
424 exynos_pcie_power_on_phy(ep
);
425 exynos_pcie_init_phy(ep
);
427 /* pulse for common reset */
428 exynos_pcie_writel(ep
->mem_res
->block_base
, 1,
429 PCIE_PHY_COMMON_RESET
);
431 exynos_pcie_writel(ep
->mem_res
->block_base
, 0,
432 PCIE_PHY_COMMON_RESET
);
435 /* pulse for common reset */
436 exynos_pcie_writel(ep
->mem_res
->block_base
, 1, PCIE_PHY_COMMON_RESET
);
438 exynos_pcie_writel(ep
->mem_res
->block_base
, 0, PCIE_PHY_COMMON_RESET
);
440 exynos_pcie_deassert_core_reset(ep
);
441 dw_pcie_setup_rc(pp
);
442 exynos_pcie_assert_reset(ep
);
444 /* assert LTSSM enable */
445 exynos_pcie_writel(ep
->mem_res
->elbi_base
, PCIE_ELBI_LTSSM_ENABLE
,
446 PCIE_APP_LTSSM_ENABLE
);
448 /* check if the link is up or not */
449 if (!dw_pcie_wait_for_link(pci
))
453 phy_power_off(ep
->phy
);
457 while (exynos_pcie_readl(ep
->mem_res
->phy_base
,
458 PCIE_PHY_PLL_LOCKED
) == 0) {
459 val
= exynos_pcie_readl(ep
->mem_res
->block_base
,
460 PCIE_PHY_PLL_LOCKED
);
461 dev_info(dev
, "PLL Locked: 0x%x\n", val
);
463 exynos_pcie_power_off_phy(ep
);
467 static void exynos_pcie_clear_irq_pulse(struct exynos_pcie
*ep
)
471 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_IRQ_PULSE
);
472 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_IRQ_PULSE
);
475 static void exynos_pcie_enable_irq_pulse(struct exynos_pcie
*ep
)
479 /* enable INTX interrupt */
480 val
= IRQ_INTA_ASSERT
| IRQ_INTB_ASSERT
|
481 IRQ_INTC_ASSERT
| IRQ_INTD_ASSERT
;
482 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_IRQ_EN_PULSE
);
485 static irqreturn_t
exynos_pcie_irq_handler(int irq
, void *arg
)
487 struct exynos_pcie
*ep
= arg
;
489 exynos_pcie_clear_irq_pulse(ep
);
493 static irqreturn_t
exynos_pcie_msi_irq_handler(int irq
, void *arg
)
495 struct exynos_pcie
*ep
= arg
;
496 struct dw_pcie
*pci
= ep
->pci
;
497 struct pcie_port
*pp
= &pci
->pp
;
499 return dw_handle_msi_irq(pp
);
502 static void exynos_pcie_msi_init(struct exynos_pcie
*ep
)
504 struct dw_pcie
*pci
= ep
->pci
;
505 struct pcie_port
*pp
= &pci
->pp
;
508 dw_pcie_msi_init(pp
);
510 /* enable MSI interrupt */
511 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_IRQ_EN_LEVEL
);
512 val
|= IRQ_MSI_ENABLE
;
513 exynos_pcie_writel(ep
->mem_res
->elbi_base
, val
, PCIE_IRQ_EN_LEVEL
);
516 static void exynos_pcie_enable_interrupts(struct exynos_pcie
*ep
)
518 exynos_pcie_enable_irq_pulse(ep
);
520 if (IS_ENABLED(CONFIG_PCI_MSI
))
521 exynos_pcie_msi_init(ep
);
524 static u32
exynos_pcie_read_dbi(struct dw_pcie
*pci
, void __iomem
*base
,
525 u32 reg
, size_t size
)
527 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
530 exynos_pcie_sideband_dbi_r_mode(ep
, true);
531 dw_pcie_read(base
+ reg
, size
, &val
);
532 exynos_pcie_sideband_dbi_r_mode(ep
, false);
536 static void exynos_pcie_write_dbi(struct dw_pcie
*pci
, void __iomem
*base
,
537 u32 reg
, size_t size
, u32 val
)
539 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
541 exynos_pcie_sideband_dbi_w_mode(ep
, true);
542 dw_pcie_write(base
+ reg
, size
, val
);
543 exynos_pcie_sideband_dbi_w_mode(ep
, false);
546 static int exynos_pcie_rd_own_conf(struct pcie_port
*pp
, int where
, int size
,
549 struct dw_pcie
*pci
= to_dw_pcie_from_pp(pp
);
550 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
553 exynos_pcie_sideband_dbi_r_mode(ep
, true);
554 ret
= dw_pcie_read(pci
->dbi_base
+ where
, size
, val
);
555 exynos_pcie_sideband_dbi_r_mode(ep
, false);
559 static int exynos_pcie_wr_own_conf(struct pcie_port
*pp
, int where
, int size
,
562 struct dw_pcie
*pci
= to_dw_pcie_from_pp(pp
);
563 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
566 exynos_pcie_sideband_dbi_w_mode(ep
, true);
567 ret
= dw_pcie_write(pci
->dbi_base
+ where
, size
, val
);
568 exynos_pcie_sideband_dbi_w_mode(ep
, false);
572 static int exynos_pcie_link_up(struct dw_pcie
*pci
)
574 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
577 val
= exynos_pcie_readl(ep
->mem_res
->elbi_base
, PCIE_ELBI_RDLH_LINKUP
);
578 if (val
== PCIE_ELBI_LTSSM_ENABLE
)
584 static int exynos_pcie_host_init(struct pcie_port
*pp
)
586 struct dw_pcie
*pci
= to_dw_pcie_from_pp(pp
);
587 struct exynos_pcie
*ep
= to_exynos_pcie(pci
);
589 exynos_pcie_establish_link(ep
);
590 exynos_pcie_enable_interrupts(ep
);
595 static const struct dw_pcie_host_ops exynos_pcie_host_ops
= {
596 .rd_own_conf
= exynos_pcie_rd_own_conf
,
597 .wr_own_conf
= exynos_pcie_wr_own_conf
,
598 .host_init
= exynos_pcie_host_init
,
601 static int __init
exynos_add_pcie_port(struct exynos_pcie
*ep
,
602 struct platform_device
*pdev
)
604 struct dw_pcie
*pci
= ep
->pci
;
605 struct pcie_port
*pp
= &pci
->pp
;
606 struct device
*dev
= &pdev
->dev
;
609 pp
->irq
= platform_get_irq(pdev
, 1);
611 dev_err(dev
, "failed to get irq\n");
614 ret
= devm_request_irq(dev
, pp
->irq
, exynos_pcie_irq_handler
,
615 IRQF_SHARED
, "exynos-pcie", ep
);
617 dev_err(dev
, "failed to request irq\n");
621 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
622 pp
->msi_irq
= platform_get_irq(pdev
, 0);
623 if (pp
->msi_irq
< 0) {
624 dev_err(dev
, "failed to get msi irq\n");
628 ret
= devm_request_irq(dev
, pp
->msi_irq
,
629 exynos_pcie_msi_irq_handler
,
630 IRQF_SHARED
| IRQF_NO_THREAD
,
633 dev_err(dev
, "failed to request msi irq\n");
638 pp
->root_bus_nr
= -1;
639 pp
->ops
= &exynos_pcie_host_ops
;
641 ret
= dw_pcie_host_init(pp
);
643 dev_err(dev
, "failed to initialize host\n");
650 static const struct dw_pcie_ops dw_pcie_ops
= {
651 .read_dbi
= exynos_pcie_read_dbi
,
652 .write_dbi
= exynos_pcie_write_dbi
,
653 .link_up
= exynos_pcie_link_up
,
656 static int __init
exynos_pcie_probe(struct platform_device
*pdev
)
658 struct device
*dev
= &pdev
->dev
;
660 struct exynos_pcie
*ep
;
661 struct device_node
*np
= dev
->of_node
;
664 ep
= devm_kzalloc(dev
, sizeof(*ep
), GFP_KERNEL
);
668 pci
= devm_kzalloc(dev
, sizeof(*pci
), GFP_KERNEL
);
673 pci
->ops
= &dw_pcie_ops
;
676 ep
->ops
= (const struct exynos_pcie_ops
*)
677 of_device_get_match_data(dev
);
679 ep
->reset_gpio
= of_get_named_gpio(np
, "reset-gpio", 0);
681 /* Assume that controller doesn't use the PHY framework */
682 ep
->using_phy
= false;
684 ep
->phy
= devm_of_phy_get(dev
, np
, NULL
);
685 if (IS_ERR(ep
->phy
)) {
686 if (PTR_ERR(ep
->phy
) != -ENODEV
)
687 return PTR_ERR(ep
->phy
);
688 dev_warn(dev
, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
690 ep
->using_phy
= true;
692 if (ep
->ops
&& ep
->ops
->get_mem_resources
) {
693 ret
= ep
->ops
->get_mem_resources(pdev
, ep
);
698 if (ep
->ops
&& ep
->ops
->get_clk_resources
&&
699 ep
->ops
->init_clk_resources
) {
700 ret
= ep
->ops
->get_clk_resources(ep
);
703 ret
= ep
->ops
->init_clk_resources(ep
);
708 platform_set_drvdata(pdev
, ep
);
710 ret
= exynos_add_pcie_port(ep
, pdev
);
720 if (ep
->ops
&& ep
->ops
->deinit_clk_resources
)
721 ep
->ops
->deinit_clk_resources(ep
);
725 static int __exit
exynos_pcie_remove(struct platform_device
*pdev
)
727 struct exynos_pcie
*ep
= platform_get_drvdata(pdev
);
729 if (ep
->ops
&& ep
->ops
->deinit_clk_resources
)
730 ep
->ops
->deinit_clk_resources(ep
);
735 static const struct of_device_id exynos_pcie_of_match
[] = {
737 .compatible
= "samsung,exynos5440-pcie",
738 .data
= &exynos5440_pcie_ops
743 static struct platform_driver exynos_pcie_driver
= {
744 .remove
= __exit_p(exynos_pcie_remove
),
746 .name
= "exynos-pcie",
747 .of_match_table
= exynos_pcie_of_match
,
751 /* Exynos PCIe driver does not allow module unload */
753 static int __init
exynos_pcie_init(void)
755 return platform_driver_probe(&exynos_pcie_driver
, exynos_pcie_probe
);
757 subsys_initcall(exynos_pcie_init
);