drivers/pci/dwc/pci-imx6.c

   1 /*
   2  * PCIe host controller driver for Freescale i.MX6 SoCs
   3  *
   4  * Copyright (C) 2013 Kosagi
   5  *              http://www.kosagi.com
   6  *
   7  * Author: Sean Cross <xobs@kosagi.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/of_device.h>
  23 #include <linux/pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/resource.h>
  27 #include <linux/signal.h>
  28 #include <linux/types.h>
  29 #include <linux/interrupt.h>
  30
  31 #include "pcie-designware.h"
  32
  33 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
  34
  35 enum imx6_pcie_variants {
  36         IMX6Q,
  37         IMX6SX,
  38         IMX6QP,
  39 };
  40
  41 struct imx6_pcie {
  42         struct dw_pcie          *pci;
  43         int                     reset_gpio;
  44         bool                    gpio_active_high;
  45         struct clk              *pcie_bus;
  46         struct clk              *pcie_phy;
  47         struct clk              *pcie_inbound_axi;
  48         struct clk              *pcie;
  49         struct regmap           *iomuxc_gpr;
  50         enum imx6_pcie_variants variant;
  51         u32                     tx_deemph_gen1;
  52         u32                     tx_deemph_gen2_3p5db;
  53         u32                     tx_deemph_gen2_6db;
  54         u32                     tx_swing_full;
  55         u32                     tx_swing_low;
  56         int                     link_gen;
  57 };
  58
  59 /* PCIe Root Complex registers (memory-mapped) */
  60 #define PCIE_RC_LCR                             0x7c
  61 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1        0x1
  62 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2        0x2
  63 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK        0xf
  64
  65 #define PCIE_RC_LCSR                            0x80
  66
  67 /* PCIe Port Logic registers (memory-mapped) */
  68 #define PL_OFFSET 0x700
  69 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
  70 #define PCIE_PL_PFLR_LINK_STATE_MASK            (0x3f << 16)
  71 #define PCIE_PL_PFLR_FORCE_LINK                 (1 << 15)
  72 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  73 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  74 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
  75 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP          (1 << 4)
  76
  77 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  78 #define PCIE_PHY_CTRL_DATA_LOC 0
  79 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  80 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  81 #define PCIE_PHY_CTRL_WR_LOC 18
  82 #define PCIE_PHY_CTRL_RD_LOC 19
  83
  84 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  85 #define PCIE_PHY_STAT_ACK_LOC 16
  86
  87 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
  88 #define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
  89
  90 /* PHY registers (not memory-mapped) */
  91 #define PCIE_PHY_RX_ASIC_OUT 0x100D
  92 #define PCIE_PHY_RX_ASIC_OUT_VALID      (1 << 0)
  93
  94 #define PHY_RX_OVRD_IN_LO 0x1005
  95 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  96 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  97
  98 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
  99 {
 100         struct dw_pcie *pci = imx6_pcie->pci;
 101         u32 val;
 102         u32 max_iterations = 10;
 103         u32 wait_counter = 0;
 104
 105         do {
 106                 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
 107                 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
 108                 wait_counter++;
 109
 110                 if (val == exp_val)
 111                         return 0;
 112
 113                 udelay(1);
 114         } while (wait_counter < max_iterations);
 115
 116         return -ETIMEDOUT;
 117 }
 118
 119 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
 120 {
 121         struct dw_pcie *pci = imx6_pcie->pci;
 122         u32 val;
 123         int ret;
 124
 125         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 126         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 127
 128         val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
 129         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 130
 131         ret = pcie_phy_poll_ack(imx6_pcie, 1);
 132         if (ret)
 133                 return ret;
 134
 135         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 136         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 137
 138         return pcie_phy_poll_ack(imx6_pcie, 0);
 139 }
 140
 141 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 142 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
 143 {
 144         struct dw_pcie *pci = imx6_pcie->pci;
 145         u32 val, phy_ctl;
 146         int ret;
 147
 148         ret = pcie_phy_wait_ack(imx6_pcie, addr);
 149         if (ret)
 150                 return ret;
 151
 152         /* assert Read signal */
 153         phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
 154         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
 155
 156         ret = pcie_phy_poll_ack(imx6_pcie, 1);
 157         if (ret)
 158                 return ret;
 159
 160         val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
 161         *data = val & 0xffff;
 162
 163         /* deassert Read signal */
 164         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
 165
 166         return pcie_phy_poll_ack(imx6_pcie, 0);
 167 }
 168
 169 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
 170 {
 171         struct dw_pcie *pci = imx6_pcie->pci;
 172         u32 var;
 173         int ret;
 174
 175         /* write addr */
 176         /* cap addr */
 177         ret = pcie_phy_wait_ack(imx6_pcie, addr);
 178         if (ret)
 179                 return ret;
 180
 181         var = data << PCIE_PHY_CTRL_DATA_LOC;
 182         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 183
 184         /* capture data */
 185         var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
 186         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 187
 188         ret = pcie_phy_poll_ack(imx6_pcie, 1);
 189         if (ret)
 190                 return ret;
 191
 192         /* deassert cap data */
 193         var = data << PCIE_PHY_CTRL_DATA_LOC;
 194         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 195
 196         /* wait for ack de-assertion */
 197         ret = pcie_phy_poll_ack(imx6_pcie, 0);
 198         if (ret)
 199                 return ret;
 200
 201         /* assert wr signal */
 202         var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
 203         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 204
 205         /* wait for ack */
 206         ret = pcie_phy_poll_ack(imx6_pcie, 1);
 207         if (ret)
 208                 return ret;
 209
 210         /* deassert wr signal */
 211         var = data << PCIE_PHY_CTRL_DATA_LOC;
 212         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 213
 214         /* wait for ack de-assertion */
 215         ret = pcie_phy_poll_ack(imx6_pcie, 0);
 216         if (ret)
 217                 return ret;
 218
 219         dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
 220
 221         return 0;
 222 }
 223
 224 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
 225 {
 226         u32 tmp;
 227
 228         pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 229         tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 230                 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 231         pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 232
 233         usleep_range(2000, 3000);
 234
 235         pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 236         tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 237                   PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 238         pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 239 }
 240
 241 /*  Added for PCI abort handling */
 242 static int imx6q_pcie_abort_handler(unsigned long addr,
 243                 unsigned int fsr, struct pt_regs *regs)
 244 {
 245         return 0;
 246 }
 247
 248 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 249 {
 250         switch (imx6_pcie->variant) {
 251         case IMX6SX:
 252                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 253                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
 254                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
 255                 /* Force PCIe PHY reset */
 256                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 257                                    IMX6SX_GPR5_PCIE_BTNRST_RESET,
 258                                    IMX6SX_GPR5_PCIE_BTNRST_RESET);
 259                 break;
 260         case IMX6QP:
 261                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 262                                    IMX6Q_GPR1_PCIE_SW_RST,
 263                                    IMX6Q_GPR1_PCIE_SW_RST);
 264                 break;
 265         case IMX6Q:
 266                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 267                                    IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 268                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 269                                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 270                 break;
 271         }
 272 }
 273
 274 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 275 {
 276         struct dw_pcie *pci = imx6_pcie->pci;
 277         struct device *dev = pci->dev;
 278         int ret = 0;
 279
 280         switch (imx6_pcie->variant) {
 281         case IMX6SX:
 282                 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
 283                 if (ret) {
 284                         dev_err(dev, "unable to enable pcie_axi clock\n");
 285                         break;
 286                 }
 287
 288                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 289                                    IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
 290                 break;
 291         case IMX6QP:            /* FALLTHROUGH */
 292         case IMX6Q:
 293                 /* power up core phy and enable ref clock */
 294                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 295                                    IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 296                 /*
 297                  * the async reset input need ref clock to sync internally,
 298                  * when the ref clock comes after reset, internal synced
 299                  * reset time is too short, cannot meet the requirement.
 300                  * add one ~10us delay here.
 301                  */
 302                 udelay(10);
 303                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 304                                    IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 305                 break;
 306         }
 307
 308         return ret;
 309 }
 310
 311 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 312 {
 313         struct dw_pcie *pci = imx6_pcie->pci;
 314         struct device *dev = pci->dev;
 315         int ret;
 316
 317         ret = clk_prepare_enable(imx6_pcie->pcie_phy);
 318         if (ret) {
 319                 dev_err(dev, "unable to enable pcie_phy clock\n");
 320                 return;
 321         }
 322
 323         ret = clk_prepare_enable(imx6_pcie->pcie_bus);
 324         if (ret) {
 325                 dev_err(dev, "unable to enable pcie_bus clock\n");
 326                 goto err_pcie_bus;
 327         }
 328
 329         ret = clk_prepare_enable(imx6_pcie->pcie);
 330         if (ret) {
 331                 dev_err(dev, "unable to enable pcie clock\n");
 332                 goto err_pcie;
 333         }
 334
 335         ret = imx6_pcie_enable_ref_clk(imx6_pcie);
 336         if (ret) {
 337                 dev_err(dev, "unable to enable pcie ref clock\n");
 338                 goto err_ref_clk;
 339         }
 340
 341         /* allow the clocks to stabilize */
 342         usleep_range(200, 500);
 343
 344         /* Some boards don't have PCIe reset GPIO. */
 345         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 346                 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 347                                         imx6_pcie->gpio_active_high);
 348                 msleep(100);
 349                 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 350                                         !imx6_pcie->gpio_active_high);
 351         }
 352
 353         switch (imx6_pcie->variant) {
 354         case IMX6SX:
 355                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 356                                    IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
 357                 break;
 358         case IMX6QP:
 359                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 360                                    IMX6Q_GPR1_PCIE_SW_RST, 0);
 361
 362                 usleep_range(200, 500);
 363                 break;
 364         case IMX6Q:             /* Nothing to do */
 365                 break;
 366         }
 367
 368         return;
 369
 370 err_ref_clk:
 371         clk_disable_unprepare(imx6_pcie->pcie);
 372 err_pcie:
 373         clk_disable_unprepare(imx6_pcie->pcie_bus);
 374 err_pcie_bus:
 375         clk_disable_unprepare(imx6_pcie->pcie_phy);
 376 }
 377
 378 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 379 {
 380         if (imx6_pcie->variant == IMX6SX)
 381                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 382                                    IMX6SX_GPR12_PCIE_RX_EQ_MASK,
 383                                    IMX6SX_GPR12_PCIE_RX_EQ_2);
 384
 385         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 386                         IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 387
 388         /* configure constant input signal to the pcie ctrl and phy */
 389         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 390                         IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 391         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 392                         IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 393
 394         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 395                            IMX6Q_GPR8_TX_DEEMPH_GEN1,
 396                            imx6_pcie->tx_deemph_gen1 << 0);
 397         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 398                            IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
 399                            imx6_pcie->tx_deemph_gen2_3p5db << 6);
 400         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 401                            IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
 402                            imx6_pcie->tx_deemph_gen2_6db << 12);
 403         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 404                            IMX6Q_GPR8_TX_SWING_FULL,
 405                            imx6_pcie->tx_swing_full << 18);
 406         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 407                            IMX6Q_GPR8_TX_SWING_LOW,
 408                            imx6_pcie->tx_swing_low << 25);
 409 }
 410
 411 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
 412 {
 413         struct dw_pcie *pci = imx6_pcie->pci;
 414         struct device *dev = pci->dev;
 415
 416         /* check if the link is up or not */
 417         if (!dw_pcie_wait_for_link(pci))
 418                 return 0;
 419
 420         dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 421                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
 422                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
 423         return -ETIMEDOUT;
 424 }
 425
 426 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
 427 {
 428         struct dw_pcie *pci = imx6_pcie->pci;
 429         struct device *dev = pci->dev;
 430         u32 tmp;
 431         unsigned int retries;
 432
 433         for (retries = 0; retries < 200; retries++) {
 434                 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 435                 /* Test if the speed change finished. */
 436                 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 437                         return 0;
 438                 usleep_range(100, 1000);
 439         }
 440
 441         dev_err(dev, "Speed change timeout\n");
 442         return -EINVAL;
 443 }
 444
 445 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
 446 {
 447         struct imx6_pcie *imx6_pcie = arg;
 448         struct dw_pcie *pci = imx6_pcie->pci;
 449         struct pcie_port *pp = &pci->pp;
 450
 451         return dw_handle_msi_irq(pp);
 452 }
 453
 454 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 455 {
 456         struct dw_pcie *pci = imx6_pcie->pci;
 457         struct device *dev = pci->dev;
 458         u32 tmp;
 459         int ret;
 460
 461         /*
 462          * Force Gen1 operation when starting the link.  In case the link is
 463          * started in Gen2 mode, there is a possibility the devices on the
 464          * bus will not be detected at all.  This happens with PCIe switches.
 465          */
 466         tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
 467         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 468         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
 469         dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
 470
 471         /* Start LTSSM. */
 472         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 473                         IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
 474
 475         ret = imx6_pcie_wait_for_link(imx6_pcie);
 476         if (ret)
 477                 goto err_reset_phy;
 478
 479         if (imx6_pcie->link_gen == 2) {
 480                 /* Allow Gen2 mode after the link is up. */
 481                 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
 482                 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 483                 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
 484                 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
 485         } else {
 486                 dev_info(dev, "Link: Gen2 disabled\n");
 487         }
 488
 489         /*
 490          * Start Directed Speed Change so the best possible speed both link
 491          * partners support can be negotiated.
 492          */
 493         tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 494         tmp |= PORT_LOGIC_SPEED_CHANGE;
 495         dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
 496
 497         ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
 498         if (ret) {
 499                 dev_err(dev, "Failed to bring link up!\n");
 500                 goto err_reset_phy;
 501         }
 502
 503         /* Make sure link training is finished as well! */
 504         ret = imx6_pcie_wait_for_link(imx6_pcie);
 505         if (ret) {
 506                 dev_err(dev, "Failed to bring link up!\n");
 507                 goto err_reset_phy;
 508         }
 509
 510         tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
 511         dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
 512         return 0;
 513
 514 err_reset_phy:
 515         dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
 516                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
 517                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
 518         imx6_pcie_reset_phy(imx6_pcie);
 519         return ret;
 520 }
 521
 522 static void imx6_pcie_host_init(struct pcie_port *pp)
 523 {
 524         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 525         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
 526
 527         imx6_pcie_assert_core_reset(imx6_pcie);
 528         imx6_pcie_init_phy(imx6_pcie);
 529         imx6_pcie_deassert_core_reset(imx6_pcie);
 530         dw_pcie_setup_rc(pp);
 531         imx6_pcie_establish_link(imx6_pcie);
 532
 533         if (IS_ENABLED(CONFIG_PCI_MSI))
 534                 dw_pcie_msi_init(pp);
 535 }
 536
 537 static int imx6_pcie_link_up(struct dw_pcie *pci)
 538 {
 539         return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) &
 540                         PCIE_PHY_DEBUG_R1_XMLH_LINK_UP;
 541 }
 542
 543 static struct dw_pcie_host_ops imx6_pcie_host_ops = {
 544         .host_init = imx6_pcie_host_init,
 545 };
 546
 547 static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
 548                                      struct platform_device *pdev)
 549 {
 550         struct dw_pcie *pci = imx6_pcie->pci;
 551         struct pcie_port *pp = &pci->pp;
 552         struct device *dev = &pdev->dev;
 553         int ret;
 554
 555         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 556                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 557                 if (pp->msi_irq <= 0) {
 558                         dev_err(dev, "failed to get MSI irq\n");
 559                         return -ENODEV;
 560                 }
 561
 562                 ret = devm_request_irq(dev, pp->msi_irq,
 563                                        imx6_pcie_msi_handler,
 564                                        IRQF_SHARED | IRQF_NO_THREAD,
 565                                        "mx6-pcie-msi", imx6_pcie);
 566                 if (ret) {
 567                         dev_err(dev, "failed to request MSI irq\n");
 568                         return ret;
 569                 }
 570         }
 571
 572         pp->root_bus_nr = -1;
 573         pp->ops = &imx6_pcie_host_ops;
 574
 575         ret = dw_pcie_host_init(pp);
 576         if (ret) {
 577                 dev_err(dev, "failed to initialize host\n");
 578                 return ret;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static const struct dw_pcie_ops dw_pcie_ops = {
 585         .link_up = imx6_pcie_link_up,
 586 };
 587
 588 static int __init imx6_pcie_probe(struct platform_device *pdev)
 589 {
 590         struct device *dev = &pdev->dev;
 591         struct dw_pcie *pci;
 592         struct imx6_pcie *imx6_pcie;
 593         struct resource *dbi_base;
 594         struct device_node *node = dev->of_node;
 595         int ret;
 596
 597         imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
 598         if (!imx6_pcie)
 599                 return -ENOMEM;
 600
 601         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 602         if (!pci)
 603                 return -ENOMEM;
 604
 605         pci->dev = dev;
 606         pci->ops = &dw_pcie_ops;
 607
 608         imx6_pcie->pci = pci;
 609         imx6_pcie->variant =
 610                 (enum imx6_pcie_variants)of_device_get_match_data(dev);
 611
 612         /* Added for PCI abort handling */
 613         hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 614                 "imprecise external abort");
 615
 616         dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 617         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
 618         if (IS_ERR(pci->dbi_base))
 619                 return PTR_ERR(pci->dbi_base);
 620
 621         /* Fetch GPIOs */
 622         imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
 623         imx6_pcie->gpio_active_high = of_property_read_bool(node,
 624                                                 "reset-gpio-active-high");
 625         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 626                 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
 627                                 imx6_pcie->gpio_active_high ?
 628                                         GPIOF_OUT_INIT_HIGH :
 629                                         GPIOF_OUT_INIT_LOW,
 630                                 "PCIe reset");
 631                 if (ret) {
 632                         dev_err(dev, "unable to get reset gpio\n");
 633                         return ret;
 634                 }
 635         }
 636
 637         /* Fetch clocks */
 638         imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
 639         if (IS_ERR(imx6_pcie->pcie_phy)) {
 640                 dev_err(dev, "pcie_phy clock source missing or invalid\n");
 641                 return PTR_ERR(imx6_pcie->pcie_phy);
 642         }
 643
 644         imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
 645         if (IS_ERR(imx6_pcie->pcie_bus)) {
 646                 dev_err(dev, "pcie_bus clock source missing or invalid\n");
 647                 return PTR_ERR(imx6_pcie->pcie_bus);
 648         }
 649
 650         imx6_pcie->pcie = devm_clk_get(dev, "pcie");
 651         if (IS_ERR(imx6_pcie->pcie)) {
 652                 dev_err(dev, "pcie clock source missing or invalid\n");
 653                 return PTR_ERR(imx6_pcie->pcie);
 654         }
 655
 656         if (imx6_pcie->variant == IMX6SX) {
 657                 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
 658                                                            "pcie_inbound_axi");
 659                 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
 660                         dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
 661                         return PTR_ERR(imx6_pcie->pcie_inbound_axi);
 662                 }
 663         }
 664
 665         /* Grab GPR config register range */
 666         imx6_pcie->iomuxc_gpr =
 667                  syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 668         if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 669                 dev_err(dev, "unable to find iomuxc registers\n");
 670                 return PTR_ERR(imx6_pcie->iomuxc_gpr);
 671         }
 672
 673         /* Grab PCIe PHY Tx Settings */
 674         if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
 675                                  &imx6_pcie->tx_deemph_gen1))
 676                 imx6_pcie->tx_deemph_gen1 = 0;
 677
 678         if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
 679                                  &imx6_pcie->tx_deemph_gen2_3p5db))
 680                 imx6_pcie->tx_deemph_gen2_3p5db = 0;
 681
 682         if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
 683                                  &imx6_pcie->tx_deemph_gen2_6db))
 684                 imx6_pcie->tx_deemph_gen2_6db = 20;
 685
 686         if (of_property_read_u32(node, "fsl,tx-swing-full",
 687                                  &imx6_pcie->tx_swing_full))
 688                 imx6_pcie->tx_swing_full = 127;
 689
 690         if (of_property_read_u32(node, "fsl,tx-swing-low",
 691                                  &imx6_pcie->tx_swing_low))
 692                 imx6_pcie->tx_swing_low = 127;
 693
 694         /* Limit link speed */
 695         ret = of_property_read_u32(node, "fsl,max-link-speed",
 696                                    &imx6_pcie->link_gen);
 697         if (ret)
 698                 imx6_pcie->link_gen = 1;
 699
 700         platform_set_drvdata(pdev, imx6_pcie);
 701
 702         ret = imx6_add_pcie_port(imx6_pcie, pdev);
 703         if (ret < 0)
 704                 return ret;
 705
 706         return 0;
 707 }
 708
 709 static void imx6_pcie_shutdown(struct platform_device *pdev)
 710 {
 711         struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
 712
 713         /* bring down link, so bootloader gets clean state in case of reboot */
 714         imx6_pcie_assert_core_reset(imx6_pcie);
 715 }
 716
 717 static const struct of_device_id imx6_pcie_of_match[] = {
 718         { .compatible = "fsl,imx6q-pcie",  .data = (void *)IMX6Q,  },
 719         { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
 720         { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
 721         {},
 722 };
 723
 724 static struct platform_driver imx6_pcie_driver = {
 725         .driver = {
 726                 .name   = "imx6q-pcie",
 727                 .of_match_table = imx6_pcie_of_match,
 728         },
 729         .shutdown = imx6_pcie_shutdown,
 730 };
 731
 732 static int __init imx6_pcie_init(void)
 733 {
 734         return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
 735 }
 736 device_initcall(imx6_pcie_init);