drivers/pci/dwc/pci-layerscape.c

   1 /*
   2  * PCIe host controller driver for Freescale Layerscape SoCs
   3  *
   4  * Copyright (C) 2014 Freescale Semiconductor.
   5  *
   6  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/init.h>
  16 #include <linux/of_pci.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/pci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/resource.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include "pcie-designware.h"
  27
  28 /* PEX1/2 Misc Ports Status Register */
  29 #define SCFG_PEXMSCPORTSR(pex_idx)      (0x94 + (pex_idx) * 4)
  30 #define LTSSM_STATE_SHIFT       20
  31 #define LTSSM_STATE_MASK        0x3f
  32 #define LTSSM_PCIE_L0           0x11 /* L0 state */
  33
  34 /* PEX Internal Configuration Registers */
  35 #define PCIE_STRFMR1            0x71c /* Symbol Timer & Filter Mask Register1 */
  36 #define PCIE_DBI_RO_WR_EN       0x8bc /* DBI Read-Only Write Enable Register */
  37
  38 struct ls_pcie_drvdata {
  39         u32 lut_offset;
  40         u32 ltssm_shift;
  41         u32 lut_dbg;
  42         struct dw_pcie_host_ops *ops;
  43         const struct dw_pcie_ops *dw_pcie_ops;
  44 };
  45
  46 struct ls_pcie {
  47         struct dw_pcie *pci;
  48         void __iomem *lut;
  49         struct regmap *scfg;
  50         const struct ls_pcie_drvdata *drvdata;
  51         int index;
  52 };
  53
  54 #define to_ls_pcie(x)   dev_get_drvdata((x)->dev)
  55
  56 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
  57 {
  58         struct dw_pcie *pci = pcie->pci;
  59         u32 header_type;
  60
  61         header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
  62         header_type &= 0x7f;
  63
  64         return header_type == PCI_HEADER_TYPE_BRIDGE;
  65 }
  66
  67 /* Clear multi-function bit */
  68 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
  69 {
  70         struct dw_pcie *pci = pcie->pci;
  71
  72         iowrite8(PCI_HEADER_TYPE_BRIDGE, pci->dbi_base + PCI_HEADER_TYPE);
  73 }
  74
  75 /* Fix class value */
  76 static void ls_pcie_fix_class(struct ls_pcie *pcie)
  77 {
  78         struct dw_pcie *pci = pcie->pci;
  79
  80         iowrite16(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
  81 }
  82
  83 /* Drop MSG TLP except for Vendor MSG */
  84 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
  85 {
  86         u32 val;
  87         struct dw_pcie *pci = pcie->pci;
  88
  89         val = ioread32(pci->dbi_base + PCIE_STRFMR1);
  90         val &= 0xDFFFFFFF;
  91         iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
  92 }
  93
  94 static int ls1021_pcie_link_up(struct dw_pcie *pci)
  95 {
  96         u32 state;
  97         struct ls_pcie *pcie = to_ls_pcie(pci);
  98
  99         if (!pcie->scfg)
 100                 return 0;
 101
 102         regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
 103         state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
 104
 105         if (state < LTSSM_PCIE_L0)
 106                 return 0;
 107
 108         return 1;
 109 }
 110
 111 static void ls1021_pcie_host_init(struct pcie_port *pp)
 112 {
 113         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 114         struct ls_pcie *pcie = to_ls_pcie(pci);
 115         struct device *dev = pci->dev;
 116         u32 index[2];
 117
 118         pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
 119                                                      "fsl,pcie-scfg");
 120         if (IS_ERR(pcie->scfg)) {
 121                 dev_err(dev, "No syscfg phandle specified\n");
 122                 pcie->scfg = NULL;
 123                 return;
 124         }
 125
 126         if (of_property_read_u32_array(dev->of_node,
 127                                        "fsl,pcie-scfg", index, 2)) {
 128                 pcie->scfg = NULL;
 129                 return;
 130         }
 131         pcie->index = index[1];
 132
 133         dw_pcie_setup_rc(pp);
 134
 135         ls_pcie_drop_msg_tlp(pcie);
 136 }
 137
 138 static int ls_pcie_link_up(struct dw_pcie *pci)
 139 {
 140         struct ls_pcie *pcie = to_ls_pcie(pci);
 141         u32 state;
 142
 143         state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
 144                  pcie->drvdata->ltssm_shift) &
 145                  LTSSM_STATE_MASK;
 146
 147         if (state < LTSSM_PCIE_L0)
 148                 return 0;
 149
 150         return 1;
 151 }
 152
 153 static void ls_pcie_host_init(struct pcie_port *pp)
 154 {
 155         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 156         struct ls_pcie *pcie = to_ls_pcie(pci);
 157
 158         iowrite32(1, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 159         ls_pcie_fix_class(pcie);
 160         ls_pcie_clear_multifunction(pcie);
 161         ls_pcie_drop_msg_tlp(pcie);
 162         iowrite32(0, pci->dbi_base + PCIE_DBI_RO_WR_EN);
 163 }
 164
 165 static int ls_pcie_msi_host_init(struct pcie_port *pp,
 166                                  struct msi_controller *chip)
 167 {
 168         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 169         struct device *dev = pci->dev;
 170         struct device_node *np = dev->of_node;
 171         struct device_node *msi_node;
 172
 173         /*
 174          * The MSI domain is set by the generic of_msi_configure().  This
 175          * .msi_host_init() function keeps us from doing the default MSI
 176          * domain setup in dw_pcie_host_init() and also enforces the
 177          * requirement that "msi-parent" exists.
 178          */
 179         msi_node = of_parse_phandle(np, "msi-parent", 0);
 180         if (!msi_node) {
 181                 dev_err(dev, "failed to find msi-parent\n");
 182                 return -EINVAL;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static struct dw_pcie_host_ops ls1021_pcie_host_ops = {
 189         .host_init = ls1021_pcie_host_init,
 190         .msi_host_init = ls_pcie_msi_host_init,
 191 };
 192
 193 static struct dw_pcie_host_ops ls_pcie_host_ops = {
 194         .host_init = ls_pcie_host_init,
 195         .msi_host_init = ls_pcie_msi_host_init,
 196 };
 197
 198 static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
 199         .link_up = ls1021_pcie_link_up,
 200 };
 201
 202 static const struct dw_pcie_ops dw_ls_pcie_ops = {
 203         .link_up = ls_pcie_link_up,
 204 };
 205
 206 static struct ls_pcie_drvdata ls1021_drvdata = {
 207         .ops = &ls1021_pcie_host_ops,
 208         .dw_pcie_ops = &dw_ls1021_pcie_ops,
 209 };
 210
 211 static struct ls_pcie_drvdata ls1043_drvdata = {
 212         .lut_offset = 0x10000,
 213         .ltssm_shift = 24,
 214         .lut_dbg = 0x7fc,
 215         .ops = &ls_pcie_host_ops,
 216         .dw_pcie_ops = &dw_ls_pcie_ops,
 217 };
 218
 219 static struct ls_pcie_drvdata ls1046_drvdata = {
 220         .lut_offset = 0x80000,
 221         .ltssm_shift = 24,
 222         .lut_dbg = 0x407fc,
 223         .ops = &ls_pcie_host_ops,
 224         .dw_pcie_ops = &dw_ls_pcie_ops,
 225 };
 226
 227 static struct ls_pcie_drvdata ls2080_drvdata = {
 228         .lut_offset = 0x80000,
 229         .ltssm_shift = 0,
 230         .lut_dbg = 0x7fc,
 231         .ops = &ls_pcie_host_ops,
 232         .dw_pcie_ops = &dw_ls_pcie_ops,
 233 };
 234
 235 static const struct of_device_id ls_pcie_of_match[] = {
 236         { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
 237         { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
 238         { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
 239         { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
 240         { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
 241         { },
 242 };
 243
 244 static int __init ls_add_pcie_port(struct ls_pcie *pcie)
 245 {
 246         struct dw_pcie *pci = pcie->pci;
 247         struct pcie_port *pp = &pci->pp;
 248         struct device *dev = pci->dev;
 249         int ret;
 250
 251         pp->ops = pcie->drvdata->ops;
 252
 253         ret = dw_pcie_host_init(pp);
 254         if (ret) {
 255                 dev_err(dev, "failed to initialize host\n");
 256                 return ret;
 257         }
 258
 259         return 0;
 260 }
 261
 262 static int __init ls_pcie_probe(struct platform_device *pdev)
 263 {
 264         struct device *dev = &pdev->dev;
 265         struct dw_pcie *pci;
 266         struct ls_pcie *pcie;
 267         struct resource *dbi_base;
 268         int ret;
 269
 270         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 271         if (!pcie)
 272                 return -ENOMEM;
 273
 274         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 275         if (!pci)
 276                 return -ENOMEM;
 277
 278         pcie->drvdata = of_device_get_match_data(dev);
 279
 280         pci->dev = dev;
 281         pci->ops = pcie->drvdata->dw_pcie_ops;
 282
 283         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 284         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
 285         if (IS_ERR(pci->dbi_base))
 286                 return PTR_ERR(pci->dbi_base);
 287
 288         pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
 289
 290         if (!ls_pcie_is_bridge(pcie))
 291                 return -ENODEV;
 292
 293         platform_set_drvdata(pdev, pcie);
 294
 295         ret = ls_add_pcie_port(pcie);
 296         if (ret < 0)
 297                 return ret;
 298
 299         return 0;
 300 }
 301
 302 static struct platform_driver ls_pcie_driver = {
 303         .driver = {
 304                 .name = "layerscape-pcie",
 305                 .of_match_table = ls_pcie_of_match,
 306         },
 307 };
 308 builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);