drivers/pci/dwc/pcie-armada8k.c

   1 /*
   2  * PCIe host controller driver for Marvell Armada-8K SoCs
   3  *
   4  * Armada-8K PCIe Glue Layer Source Code
   5  *
   6  * Copyright (C) 2016 Marvell Technology Group Ltd.
   7  *
   8  * Author: Yehuda Yitshak <yehuday@marvell.com>
   9  * Author: Shadi Ammouri <shadi@marvell.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/of.h>
  22 #include <linux/pci.h>
  23 #include <linux/phy/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/resource.h>
  26 #include <linux/of_pci.h>
  27 #include <linux/of_irq.h>
  28
  29 #include "pcie-designware.h"
  30
  31 struct armada8k_pcie {
  32         struct dw_pcie *pci;
  33         struct clk *clk;
  34 };
  35
  36 #define PCIE_VENDOR_REGS_OFFSET         0x8000
  37
  38 #define PCIE_GLOBAL_CONTROL_REG         (PCIE_VENDOR_REGS_OFFSET + 0x0)
  39 #define PCIE_APP_LTSSM_EN               BIT(2)
  40 #define PCIE_DEVICE_TYPE_SHIFT          4
  41 #define PCIE_DEVICE_TYPE_MASK           0xF
  42 #define PCIE_DEVICE_TYPE_RC             0x4 /* Root complex */
  43
  44 #define PCIE_GLOBAL_STATUS_REG          (PCIE_VENDOR_REGS_OFFSET + 0x8)
  45 #define PCIE_GLB_STS_RDLH_LINK_UP       BIT(1)
  46 #define PCIE_GLB_STS_PHY_LINK_UP        BIT(9)
  47
  48 #define PCIE_GLOBAL_INT_CAUSE1_REG      (PCIE_VENDOR_REGS_OFFSET + 0x1C)
  49 #define PCIE_GLOBAL_INT_MASK1_REG       (PCIE_VENDOR_REGS_OFFSET + 0x20)
  50 #define PCIE_INT_A_ASSERT_MASK          BIT(9)
  51 #define PCIE_INT_B_ASSERT_MASK          BIT(10)
  52 #define PCIE_INT_C_ASSERT_MASK          BIT(11)
  53 #define PCIE_INT_D_ASSERT_MASK          BIT(12)
  54
  55 #define PCIE_ARCACHE_TRC_REG            (PCIE_VENDOR_REGS_OFFSET + 0x50)
  56 #define PCIE_AWCACHE_TRC_REG            (PCIE_VENDOR_REGS_OFFSET + 0x54)
  57 #define PCIE_ARUSER_REG                 (PCIE_VENDOR_REGS_OFFSET + 0x5C)
  58 #define PCIE_AWUSER_REG                 (PCIE_VENDOR_REGS_OFFSET + 0x60)
  59 /*
  60  * AR/AW Cache defauls: Normal memory, Write-Back, Read / Write
  61  * allocate
  62  */
  63 #define ARCACHE_DEFAULT_VALUE           0x3511
  64 #define AWCACHE_DEFAULT_VALUE           0x5311
  65
  66 #define DOMAIN_OUTER_SHAREABLE          0x2
  67 #define AX_USER_DOMAIN_MASK             0x3
  68 #define AX_USER_DOMAIN_SHIFT            4
  69
  70 #define to_armada8k_pcie(x)     dev_get_drvdata((x)->dev)
  71
  72 static int armada8k_pcie_link_up(struct dw_pcie *pci)
  73 {
  74         u32 reg;
  75         u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
  76
  77         reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
  78
  79         if ((reg & mask) == mask)
  80                 return 1;
  81
  82         dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
  83         return 0;
  84 }
  85
  86 static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
  87 {
  88         struct dw_pcie *pci = pcie->pci;
  89         u32 reg;
  90
  91         if (!dw_pcie_link_up(pci)) {
  92                 /* Disable LTSSM state machine to enable configuration */
  93                 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
  94                 reg &= ~(PCIE_APP_LTSSM_EN);
  95                 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
  96         }
  97
  98         /* Set the device to root complex mode */
  99         reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
 100         reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
 101         reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
 102         dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
 103
 104         /* Set the PCIe master AxCache attributes */
 105         dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
 106         dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
 107
 108         /* Set the PCIe master AxDomain attributes */
 109         reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
 110         reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
 111         reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
 112         dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
 113
 114         reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
 115         reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
 116         reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
 117         dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
 118
 119         /* Enable INT A-D interrupts */
 120         reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
 121         reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
 122                PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
 123         dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
 124
 125         if (!dw_pcie_link_up(pci)) {
 126                 /* Configuration done. Start LTSSM */
 127                 reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
 128                 reg |= PCIE_APP_LTSSM_EN;
 129                 dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
 130         }
 131
 132         /* Wait until the link becomes active again */
 133         if (dw_pcie_wait_for_link(pci))
 134                 dev_err(pci->dev, "Link not up after reconfiguration\n");
 135 }
 136
 137 static void armada8k_pcie_host_init(struct pcie_port *pp)
 138 {
 139         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 140         struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
 141
 142         dw_pcie_setup_rc(pp);
 143         armada8k_pcie_establish_link(pcie);
 144 }
 145
 146 static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
 147 {
 148         struct armada8k_pcie *pcie = arg;
 149         struct dw_pcie *pci = pcie->pci;
 150         u32 val;
 151
 152         /*
 153          * Interrupts are directly handled by the device driver of the
 154          * PCI device. However, they are also latched into the PCIe
 155          * controller, so we simply discard them.
 156          */
 157         val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
 158         dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
 159
 160         return IRQ_HANDLED;
 161 }
 162
 163 static struct dw_pcie_host_ops armada8k_pcie_host_ops = {
 164         .host_init = armada8k_pcie_host_init,
 165 };
 166
 167 static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
 168                                   struct platform_device *pdev)
 169 {
 170         struct dw_pcie *pci = pcie->pci;
 171         struct pcie_port *pp = &pci->pp;
 172         struct device *dev = &pdev->dev;
 173         int ret;
 174
 175         pp->root_bus_nr = -1;
 176         pp->ops = &armada8k_pcie_host_ops;
 177
 178         pp->irq = platform_get_irq(pdev, 0);
 179         if (!pp->irq) {
 180                 dev_err(dev, "failed to get irq for port\n");
 181                 return -ENODEV;
 182         }
 183
 184         ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
 185                                IRQF_SHARED, "armada8k-pcie", pcie);
 186         if (ret) {
 187                 dev_err(dev, "failed to request irq %d\n", pp->irq);
 188                 return ret;
 189         }
 190
 191         ret = dw_pcie_host_init(pp);
 192         if (ret) {
 193                 dev_err(dev, "failed to initialize host: %d\n", ret);
 194                 return ret;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static const struct dw_pcie_ops dw_pcie_ops = {
 201         .link_up = armada8k_pcie_link_up,
 202 };
 203
 204 static int armada8k_pcie_probe(struct platform_device *pdev)
 205 {
 206         struct dw_pcie *pci;
 207         struct armada8k_pcie *pcie;
 208         struct device *dev = &pdev->dev;
 209         struct resource *base;
 210         int ret;
 211
 212         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 213         if (!pcie)
 214                 return -ENOMEM;
 215
 216         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 217         if (!pci)
 218                 return -ENOMEM;
 219
 220         pci->dev = dev;
 221         pci->ops = &dw_pcie_ops;
 222
 223         pcie->clk = devm_clk_get(dev, NULL);
 224         if (IS_ERR(pcie->clk))
 225                 return PTR_ERR(pcie->clk);
 226
 227         clk_prepare_enable(pcie->clk);
 228
 229         /* Get the dw-pcie unit configuration/control registers base. */
 230         base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
 231         pci->dbi_base = devm_ioremap_resource(dev, base);
 232         if (IS_ERR(pci->dbi_base)) {
 233                 dev_err(dev, "couldn't remap regs base %p\n", base);
 234                 ret = PTR_ERR(pci->dbi_base);
 235                 goto fail;
 236         }
 237
 238         platform_set_drvdata(pdev, pcie);
 239
 240         ret = armada8k_add_pcie_port(pcie, pdev);
 241         if (ret)
 242                 goto fail;
 243
 244         return 0;
 245
 246 fail:
 247         if (!IS_ERR(pcie->clk))
 248                 clk_disable_unprepare(pcie->clk);
 249
 250         return ret;
 251 }
 252
 253 static const struct of_device_id armada8k_pcie_of_match[] = {
 254         { .compatible = "marvell,armada8k-pcie", },
 255         {},
 256 };
 257
 258 static struct platform_driver armada8k_pcie_driver = {
 259         .probe          = armada8k_pcie_probe,
 260         .driver = {
 261                 .name   = "armada8k-pcie",
 262                 .of_match_table = of_match_ptr(armada8k_pcie_of_match),
 263         },
 264 };
 265 builtin_platform_driver(armada8k_pcie_driver);