drivers/pci/dwc/pcie-artpec6.c

   1 /*
   2  * PCIe host controller driver for Axis ARTPEC-6 SoC
   3  *
   4  * Author: Niklas Cassel <niklas.cassel@axis.com>
   5  *
   6  * Based on work done by Phil Edworthy <phil@edworthys.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/resource.h>
  19 #include <linux/signal.h>
  20 #include <linux/types.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24
  25 #include "pcie-designware.h"
  26
  27 #define to_artpec6_pcie(x)      dev_get_drvdata((x)->dev)
  28
  29 struct artpec6_pcie {
  30         struct dw_pcie          *pci;
  31         struct regmap           *regmap;        /* DT axis,syscon-pcie */
  32         void __iomem            *phy_base;      /* DT phy */
  33 };
  34
  35 /* PCIe Port Logic registers (memory-mapped) */
  36 #define PL_OFFSET                       0x700
  37 #define PCIE_PHY_DEBUG_R0               (PL_OFFSET + 0x28)
  38 #define PCIE_PHY_DEBUG_R1               (PL_OFFSET + 0x2c)
  39
  40 #define MISC_CONTROL_1_OFF              (PL_OFFSET + 0x1bc)
  41 #define  DBI_RO_WR_EN                   1
  42
  43 /* ARTPEC-6 specific registers */
  44 #define PCIECFG                         0x18
  45 #define  PCIECFG_DBG_OEN                (1 << 24)
  46 #define  PCIECFG_CORE_RESET_REQ         (1 << 21)
  47 #define  PCIECFG_LTSSM_ENABLE           (1 << 20)
  48 #define  PCIECFG_CLKREQ_B               (1 << 11)
  49 #define  PCIECFG_REFCLK_ENABLE          (1 << 10)
  50 #define  PCIECFG_PLL_ENABLE             (1 << 9)
  51 #define  PCIECFG_PCLK_ENABLE            (1 << 8)
  52 #define  PCIECFG_RISRCREN               (1 << 4)
  53 #define  PCIECFG_MODE_TX_DRV_EN         (1 << 3)
  54 #define  PCIECFG_CISRREN                (1 << 2)
  55 #define  PCIECFG_MACRO_ENABLE           (1 << 0)
  56
  57 #define NOCCFG                          0x40
  58 #define NOCCFG_ENABLE_CLK_PCIE          (1 << 4)
  59 #define NOCCFG_POWER_PCIE_IDLEACK       (1 << 3)
  60 #define NOCCFG_POWER_PCIE_IDLE          (1 << 2)
  61 #define NOCCFG_POWER_PCIE_IDLEREQ       (1 << 1)
  62
  63 #define PHY_STATUS                      0x118
  64 #define PHY_COSPLLLOCK                  (1 << 0)
  65
  66 #define ARTPEC6_CPU_TO_BUS_ADDR         0x0fffffff
  67
  68 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
  69 {
  70         u32 val;
  71
  72         regmap_read(artpec6_pcie->regmap, offset, &val);
  73         return val;
  74 }
  75
  76 static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
  77 {
  78         regmap_write(artpec6_pcie->regmap, offset, val);
  79 }
  80
  81 static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
  82 {
  83         struct dw_pcie *pci = artpec6_pcie->pci;
  84         struct pcie_port *pp = &pci->pp;
  85         u32 val;
  86         unsigned int retries;
  87
  88         /* Hold DW core in reset */
  89         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  90         val |= PCIECFG_CORE_RESET_REQ;
  91         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  92
  93         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  94         val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
  95                 PCIECFG_MODE_TX_DRV_EN |
  96                 PCIECFG_CISRREN |       /* Reference clock term. 100 Ohm */
  97                 PCIECFG_MACRO_ENABLE;
  98         val |= PCIECFG_REFCLK_ENABLE;
  99         val &= ~PCIECFG_DBG_OEN;
 100         val &= ~PCIECFG_CLKREQ_B;
 101         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 102         usleep_range(5000, 6000);
 103
 104         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 105         val |= NOCCFG_ENABLE_CLK_PCIE;
 106         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 107         usleep_range(20, 30);
 108
 109         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 110         val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
 111         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 112         usleep_range(6000, 7000);
 113
 114         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 115         val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
 116         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 117
 118         retries = 50;
 119         do {
 120                 usleep_range(1000, 2000);
 121                 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 122                 retries--;
 123         } while (retries &&
 124                 (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
 125
 126         retries = 50;
 127         do {
 128                 usleep_range(1000, 2000);
 129                 val = readl(artpec6_pcie->phy_base + PHY_STATUS);
 130                 retries--;
 131         } while (retries && !(val & PHY_COSPLLLOCK));
 132
 133         /* Take DW core out of reset */
 134         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 135         val &= ~PCIECFG_CORE_RESET_REQ;
 136         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 137         usleep_range(100, 200);
 138
 139         /*
 140          * Enable writing to config regs. This is required as the Synopsys
 141          * driver changes the class code. That register needs DBI write enable.
 142          */
 143         dw_pcie_writel_dbi(pci, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
 144
 145         pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 146         pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 147         pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 148         pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 149
 150         /* setup root complex */
 151         dw_pcie_setup_rc(pp);
 152
 153         /* assert LTSSM enable */
 154         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 155         val |= PCIECFG_LTSSM_ENABLE;
 156         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 157
 158         /* check if the link is up or not */
 159         if (!dw_pcie_wait_for_link(pci))
 160                 return 0;
 161
 162         dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 163                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
 164                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
 165
 166         return -ETIMEDOUT;
 167 }
 168
 169 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
 170 {
 171         struct dw_pcie *pci = artpec6_pcie->pci;
 172         struct pcie_port *pp = &pci->pp;
 173
 174         if (IS_ENABLED(CONFIG_PCI_MSI))
 175                 dw_pcie_msi_init(pp);
 176 }
 177
 178 static void artpec6_pcie_host_init(struct pcie_port *pp)
 179 {
 180         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 181         struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
 182
 183         artpec6_pcie_establish_link(artpec6_pcie);
 184         artpec6_pcie_enable_interrupts(artpec6_pcie);
 185 }
 186
 187 static struct dw_pcie_host_ops artpec6_pcie_host_ops = {
 188         .host_init = artpec6_pcie_host_init,
 189 };
 190
 191 static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
 192 {
 193         struct artpec6_pcie *artpec6_pcie = arg;
 194         struct dw_pcie *pci = artpec6_pcie->pci;
 195         struct pcie_port *pp = &pci->pp;
 196
 197         return dw_handle_msi_irq(pp);
 198 }
 199
 200 static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
 201                                  struct platform_device *pdev)
 202 {
 203         struct dw_pcie *pci = artpec6_pcie->pci;
 204         struct pcie_port *pp = &pci->pp;
 205         struct device *dev = pci->dev;
 206         int ret;
 207
 208         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 209                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 210                 if (pp->msi_irq <= 0) {
 211                         dev_err(dev, "failed to get MSI irq\n");
 212                         return -ENODEV;
 213                 }
 214
 215                 ret = devm_request_irq(dev, pp->msi_irq,
 216                                        artpec6_pcie_msi_handler,
 217                                        IRQF_SHARED | IRQF_NO_THREAD,
 218                                        "artpec6-pcie-msi", artpec6_pcie);
 219                 if (ret) {
 220                         dev_err(dev, "failed to request MSI irq\n");
 221                         return ret;
 222                 }
 223         }
 224
 225         pp->root_bus_nr = -1;
 226         pp->ops = &artpec6_pcie_host_ops;
 227
 228         ret = dw_pcie_host_init(pp);
 229         if (ret) {
 230                 dev_err(dev, "failed to initialize host\n");
 231                 return ret;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static const struct dw_pcie_ops dw_pcie_ops = {
 238 };
 239
 240 static int artpec6_pcie_probe(struct platform_device *pdev)
 241 {
 242         struct device *dev = &pdev->dev;
 243         struct dw_pcie *pci;
 244         struct artpec6_pcie *artpec6_pcie;
 245         struct resource *dbi_base;
 246         struct resource *phy_base;
 247         int ret;
 248
 249         artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
 250         if (!artpec6_pcie)
 251                 return -ENOMEM;
 252
 253         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 254         if (!pci)
 255                 return -ENOMEM;
 256
 257         pci->dev = dev;
 258         pci->ops = &dw_pcie_ops;
 259
 260         artpec6_pcie->pci = pci;
 261
 262         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 263         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
 264         if (IS_ERR(pci->dbi_base))
 265                 return PTR_ERR(pci->dbi_base);
 266
 267         phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 268         artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
 269         if (IS_ERR(artpec6_pcie->phy_base))
 270                 return PTR_ERR(artpec6_pcie->phy_base);
 271
 272         artpec6_pcie->regmap =
 273                 syscon_regmap_lookup_by_phandle(dev->of_node,
 274                                                 "axis,syscon-pcie");
 275         if (IS_ERR(artpec6_pcie->regmap))
 276                 return PTR_ERR(artpec6_pcie->regmap);
 277
 278         platform_set_drvdata(pdev, artpec6_pcie);
 279
 280         ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
 281         if (ret < 0)
 282                 return ret;
 283
 284         return 0;
 285 }
 286
 287 static const struct of_device_id artpec6_pcie_of_match[] = {
 288         { .compatible = "axis,artpec6-pcie", },
 289         {},
 290 };
 291
 292 static struct platform_driver artpec6_pcie_driver = {
 293         .probe = artpec6_pcie_probe,
 294         .driver = {
 295                 .name   = "artpec6-pcie",
 296                 .of_match_table = artpec6_pcie_of_match,
 297         },
 298 };
 299 builtin_platform_driver(artpec6_pcie_driver);