drivers/pci/dwc/pcie-artpec6.c

   1 /*
   2  * PCIe host controller driver for Axis ARTPEC-6 SoC
   3  *
   4  * Author: Niklas Cassel <niklas.cassel@axis.com>
   5  *
   6  * Based on work done by Phil Edworthy <phil@edworthys.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/resource.h>
  19 #include <linux/signal.h>
  20 #include <linux/types.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24
  25 #include "pcie-designware.h"
  26
  27 #define to_artpec6_pcie(x)      dev_get_drvdata((x)->dev)
  28
  29 struct artpec6_pcie {
  30         struct dw_pcie          *pci;
  31         struct regmap           *regmap;        /* DT axis,syscon-pcie */
  32         void __iomem            *phy_base;      /* DT phy */
  33 };
  34
  35 /* PCIe Port Logic registers (memory-mapped) */
  36 #define PL_OFFSET                       0x700
  37 #define PCIE_PHY_DEBUG_R0               (PL_OFFSET + 0x28)
  38 #define PCIE_PHY_DEBUG_R1               (PL_OFFSET + 0x2c)
  39
  40 #define MISC_CONTROL_1_OFF              (PL_OFFSET + 0x1bc)
  41 #define  DBI_RO_WR_EN                   1
  42
  43 /* ARTPEC-6 specific registers */
  44 #define PCIECFG                         0x18
  45 #define  PCIECFG_DBG_OEN                (1 << 24)
  46 #define  PCIECFG_CORE_RESET_REQ         (1 << 21)
  47 #define  PCIECFG_LTSSM_ENABLE           (1 << 20)
  48 #define  PCIECFG_CLKREQ_B               (1 << 11)
  49 #define  PCIECFG_REFCLK_ENABLE          (1 << 10)
  50 #define  PCIECFG_PLL_ENABLE             (1 << 9)
  51 #define  PCIECFG_PCLK_ENABLE            (1 << 8)
  52 #define  PCIECFG_RISRCREN               (1 << 4)
  53 #define  PCIECFG_MODE_TX_DRV_EN         (1 << 3)
  54 #define  PCIECFG_CISRREN                (1 << 2)
  55 #define  PCIECFG_MACRO_ENABLE           (1 << 0)
  56
  57 #define NOCCFG                          0x40
  58 #define NOCCFG_ENABLE_CLK_PCIE          (1 << 4)
  59 #define NOCCFG_POWER_PCIE_IDLEACK       (1 << 3)
  60 #define NOCCFG_POWER_PCIE_IDLE          (1 << 2)
  61 #define NOCCFG_POWER_PCIE_IDLEREQ       (1 << 1)
  62
  63 #define PHY_STATUS                      0x118
  64 #define PHY_COSPLLLOCK                  (1 << 0)
  65
  66 #define ARTPEC6_CPU_TO_BUS_ADDR         0x0fffffff
  67
  68 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
  69 {
  70         u32 val;
  71
  72         regmap_read(artpec6_pcie->regmap, offset, &val);
  73         return val;
  74 }
  75
  76 static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
  77 {
  78         regmap_write(artpec6_pcie->regmap, offset, val);
  79 }
  80
  81 static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
  82 {
  83         return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
  84 }
  85
  86 static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
  87 {
  88         struct dw_pcie *pci = artpec6_pcie->pci;
  89         struct pcie_port *pp = &pci->pp;
  90         u32 val;
  91         unsigned int retries;
  92
  93         /* Hold DW core in reset */
  94         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  95         val |= PCIECFG_CORE_RESET_REQ;
  96         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  97
  98         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  99         val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
 100                 PCIECFG_MODE_TX_DRV_EN |
 101                 PCIECFG_CISRREN |       /* Reference clock term. 100 Ohm */
 102                 PCIECFG_MACRO_ENABLE;
 103         val |= PCIECFG_REFCLK_ENABLE;
 104         val &= ~PCIECFG_DBG_OEN;
 105         val &= ~PCIECFG_CLKREQ_B;
 106         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 107         usleep_range(5000, 6000);
 108
 109         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 110         val |= NOCCFG_ENABLE_CLK_PCIE;
 111         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 112         usleep_range(20, 30);
 113
 114         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 115         val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
 116         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 117         usleep_range(6000, 7000);
 118
 119         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 120         val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
 121         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 122
 123         retries = 50;
 124         do {
 125                 usleep_range(1000, 2000);
 126                 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 127                 retries--;
 128         } while (retries &&
 129                 (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
 130
 131         retries = 50;
 132         do {
 133                 usleep_range(1000, 2000);
 134                 val = readl(artpec6_pcie->phy_base + PHY_STATUS);
 135                 retries--;
 136         } while (retries && !(val & PHY_COSPLLLOCK));
 137
 138         /* Take DW core out of reset */
 139         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 140         val &= ~PCIECFG_CORE_RESET_REQ;
 141         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 142         usleep_range(100, 200);
 143
 144         /* setup root complex */
 145         dw_pcie_setup_rc(pp);
 146
 147         /* assert LTSSM enable */
 148         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 149         val |= PCIECFG_LTSSM_ENABLE;
 150         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 151
 152         /* check if the link is up or not */
 153         if (!dw_pcie_wait_for_link(pci))
 154                 return 0;
 155
 156         dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 157                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
 158                 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
 159
 160         return -ETIMEDOUT;
 161 }
 162
 163 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
 164 {
 165         struct dw_pcie *pci = artpec6_pcie->pci;
 166         struct pcie_port *pp = &pci->pp;
 167
 168         if (IS_ENABLED(CONFIG_PCI_MSI))
 169                 dw_pcie_msi_init(pp);
 170 }
 171
 172 static int artpec6_pcie_host_init(struct pcie_port *pp)
 173 {
 174         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 175         struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
 176
 177         artpec6_pcie_establish_link(artpec6_pcie);
 178         artpec6_pcie_enable_interrupts(artpec6_pcie);
 179
 180         return 0;
 181 }
 182
 183 static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
 184         .host_init = artpec6_pcie_host_init,
 185 };
 186
 187 static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
 188 {
 189         struct artpec6_pcie *artpec6_pcie = arg;
 190         struct dw_pcie *pci = artpec6_pcie->pci;
 191         struct pcie_port *pp = &pci->pp;
 192
 193         return dw_handle_msi_irq(pp);
 194 }
 195
 196 static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
 197                                  struct platform_device *pdev)
 198 {
 199         struct dw_pcie *pci = artpec6_pcie->pci;
 200         struct pcie_port *pp = &pci->pp;
 201         struct device *dev = pci->dev;
 202         int ret;
 203
 204         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 205                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 206                 if (pp->msi_irq < 0) {
 207                         dev_err(dev, "failed to get MSI irq\n");
 208                         return pp->msi_irq;
 209                 }
 210
 211                 ret = devm_request_irq(dev, pp->msi_irq,
 212                                        artpec6_pcie_msi_handler,
 213                                        IRQF_SHARED | IRQF_NO_THREAD,
 214                                        "artpec6-pcie-msi", artpec6_pcie);
 215                 if (ret) {
 216                         dev_err(dev, "failed to request MSI irq\n");
 217                         return ret;
 218                 }
 219         }
 220
 221         pp->root_bus_nr = -1;
 222         pp->ops = &artpec6_pcie_host_ops;
 223
 224         ret = dw_pcie_host_init(pp);
 225         if (ret) {
 226                 dev_err(dev, "failed to initialize host\n");
 227                 return ret;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static const struct dw_pcie_ops dw_pcie_ops = {
 234         .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
 235 };
 236
 237 static int artpec6_pcie_probe(struct platform_device *pdev)
 238 {
 239         struct device *dev = &pdev->dev;
 240         struct dw_pcie *pci;
 241         struct artpec6_pcie *artpec6_pcie;
 242         struct resource *dbi_base;
 243         struct resource *phy_base;
 244         int ret;
 245
 246         artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
 247         if (!artpec6_pcie)
 248                 return -ENOMEM;
 249
 250         pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 251         if (!pci)
 252                 return -ENOMEM;
 253
 254         pci->dev = dev;
 255         pci->ops = &dw_pcie_ops;
 256
 257         artpec6_pcie->pci = pci;
 258
 259         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 260         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
 261         if (IS_ERR(pci->dbi_base))
 262                 return PTR_ERR(pci->dbi_base);
 263
 264         phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 265         artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
 266         if (IS_ERR(artpec6_pcie->phy_base))
 267                 return PTR_ERR(artpec6_pcie->phy_base);
 268
 269         artpec6_pcie->regmap =
 270                 syscon_regmap_lookup_by_phandle(dev->of_node,
 271                                                 "axis,syscon-pcie");
 272         if (IS_ERR(artpec6_pcie->regmap))
 273                 return PTR_ERR(artpec6_pcie->regmap);
 274
 275         platform_set_drvdata(pdev, artpec6_pcie);
 276
 277         ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
 278         if (ret < 0)
 279                 return ret;
 280
 281         return 0;
 282 }
 283
 284 static const struct of_device_id artpec6_pcie_of_match[] = {
 285         { .compatible = "axis,artpec6-pcie", },
 286         {},
 287 };
 288
 289 static struct platform_driver artpec6_pcie_driver = {
 290         .probe = artpec6_pcie_probe,
 291         .driver = {
 292                 .name   = "artpec6-pcie",
 293                 .of_match_table = artpec6_pcie_of_match,
 294                 .suppress_bind_attrs = true,
 295         },
 296 };
 297 builtin_platform_driver(artpec6_pcie_driver);