2 * PCIe host controller driver for Axis ARTPEC-6 SoC
4 * Author: Niklas Cassel <niklas.cassel@axis.com>
6 * Based on work done by Phil Edworthy <phil@edworthys.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/platform_device.h>
18 #include <linux/resource.h>
19 #include <linux/signal.h>
20 #include <linux/types.h>
21 #include <linux/interrupt.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
25 #include "pcie-designware.h"
27 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
31 struct regmap
*regmap
; /* DT axis,syscon-pcie */
32 void __iomem
*phy_base
; /* DT phy */
35 /* PCIe Port Logic registers (memory-mapped) */
36 #define PL_OFFSET 0x700
37 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
38 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
40 #define MISC_CONTROL_1_OFF (PL_OFFSET + 0x1bc)
41 #define DBI_RO_WR_EN 1
43 /* ARTPEC-6 specific registers */
45 #define PCIECFG_DBG_OEN (1 << 24)
46 #define PCIECFG_CORE_RESET_REQ (1 << 21)
47 #define PCIECFG_LTSSM_ENABLE (1 << 20)
48 #define PCIECFG_CLKREQ_B (1 << 11)
49 #define PCIECFG_REFCLK_ENABLE (1 << 10)
50 #define PCIECFG_PLL_ENABLE (1 << 9)
51 #define PCIECFG_PCLK_ENABLE (1 << 8)
52 #define PCIECFG_RISRCREN (1 << 4)
53 #define PCIECFG_MODE_TX_DRV_EN (1 << 3)
54 #define PCIECFG_CISRREN (1 << 2)
55 #define PCIECFG_MACRO_ENABLE (1 << 0)
58 #define NOCCFG_ENABLE_CLK_PCIE (1 << 4)
59 #define NOCCFG_POWER_PCIE_IDLEACK (1 << 3)
60 #define NOCCFG_POWER_PCIE_IDLE (1 << 2)
61 #define NOCCFG_POWER_PCIE_IDLEREQ (1 << 1)
63 #define PHY_STATUS 0x118
64 #define PHY_COSPLLLOCK (1 << 0)
66 #define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
68 static u32
artpec6_pcie_readl(struct artpec6_pcie
*artpec6_pcie
, u32 offset
)
72 regmap_read(artpec6_pcie
->regmap
, offset
, &val
);
76 static void artpec6_pcie_writel(struct artpec6_pcie
*artpec6_pcie
, u32 offset
, u32 val
)
78 regmap_write(artpec6_pcie
->regmap
, offset
, val
);
81 static u64
artpec6_pcie_cpu_addr_fixup(u64 pci_addr
)
83 return pci_addr
& ARTPEC6_CPU_TO_BUS_ADDR
;
86 static int artpec6_pcie_establish_link(struct artpec6_pcie
*artpec6_pcie
)
88 struct dw_pcie
*pci
= artpec6_pcie
->pci
;
89 struct pcie_port
*pp
= &pci
->pp
;
93 /* Hold DW core in reset */
94 val
= artpec6_pcie_readl(artpec6_pcie
, PCIECFG
);
95 val
|= PCIECFG_CORE_RESET_REQ
;
96 artpec6_pcie_writel(artpec6_pcie
, PCIECFG
, val
);
98 val
= artpec6_pcie_readl(artpec6_pcie
, PCIECFG
);
99 val
|= PCIECFG_RISRCREN
| /* Receiver term. 50 Ohm */
100 PCIECFG_MODE_TX_DRV_EN
|
101 PCIECFG_CISRREN
| /* Reference clock term. 100 Ohm */
102 PCIECFG_MACRO_ENABLE
;
103 val
|= PCIECFG_REFCLK_ENABLE
;
104 val
&= ~PCIECFG_DBG_OEN
;
105 val
&= ~PCIECFG_CLKREQ_B
;
106 artpec6_pcie_writel(artpec6_pcie
, PCIECFG
, val
);
107 usleep_range(5000, 6000);
109 val
= artpec6_pcie_readl(artpec6_pcie
, NOCCFG
);
110 val
|= NOCCFG_ENABLE_CLK_PCIE
;
111 artpec6_pcie_writel(artpec6_pcie
, NOCCFG
, val
);
112 usleep_range(20, 30);
114 val
= artpec6_pcie_readl(artpec6_pcie
, PCIECFG
);
115 val
|= PCIECFG_PCLK_ENABLE
| PCIECFG_PLL_ENABLE
;
116 artpec6_pcie_writel(artpec6_pcie
, PCIECFG
, val
);
117 usleep_range(6000, 7000);
119 val
= artpec6_pcie_readl(artpec6_pcie
, NOCCFG
);
120 val
&= ~NOCCFG_POWER_PCIE_IDLEREQ
;
121 artpec6_pcie_writel(artpec6_pcie
, NOCCFG
, val
);
125 usleep_range(1000, 2000);
126 val
= artpec6_pcie_readl(artpec6_pcie
, NOCCFG
);
129 (val
& (NOCCFG_POWER_PCIE_IDLEACK
| NOCCFG_POWER_PCIE_IDLE
)));
133 usleep_range(1000, 2000);
134 val
= readl(artpec6_pcie
->phy_base
+ PHY_STATUS
);
136 } while (retries
&& !(val
& PHY_COSPLLLOCK
));
138 /* Take DW core out of reset */
139 val
= artpec6_pcie_readl(artpec6_pcie
, PCIECFG
);
140 val
&= ~PCIECFG_CORE_RESET_REQ
;
141 artpec6_pcie_writel(artpec6_pcie
, PCIECFG
, val
);
142 usleep_range(100, 200);
144 /* setup root complex */
145 dw_pcie_setup_rc(pp
);
147 /* assert LTSSM enable */
148 val
= artpec6_pcie_readl(artpec6_pcie
, PCIECFG
);
149 val
|= PCIECFG_LTSSM_ENABLE
;
150 artpec6_pcie_writel(artpec6_pcie
, PCIECFG
, val
);
152 /* check if the link is up or not */
153 if (!dw_pcie_wait_for_link(pci
))
156 dev_dbg(pci
->dev
, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
157 dw_pcie_readl_dbi(pci
, PCIE_PHY_DEBUG_R0
),
158 dw_pcie_readl_dbi(pci
, PCIE_PHY_DEBUG_R1
));
163 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie
*artpec6_pcie
)
165 struct dw_pcie
*pci
= artpec6_pcie
->pci
;
166 struct pcie_port
*pp
= &pci
->pp
;
168 if (IS_ENABLED(CONFIG_PCI_MSI
))
169 dw_pcie_msi_init(pp
);
172 static int artpec6_pcie_host_init(struct pcie_port
*pp
)
174 struct dw_pcie
*pci
= to_dw_pcie_from_pp(pp
);
175 struct artpec6_pcie
*artpec6_pcie
= to_artpec6_pcie(pci
);
177 artpec6_pcie_establish_link(artpec6_pcie
);
178 artpec6_pcie_enable_interrupts(artpec6_pcie
);
183 static const struct dw_pcie_host_ops artpec6_pcie_host_ops
= {
184 .host_init
= artpec6_pcie_host_init
,
187 static irqreturn_t
artpec6_pcie_msi_handler(int irq
, void *arg
)
189 struct artpec6_pcie
*artpec6_pcie
= arg
;
190 struct dw_pcie
*pci
= artpec6_pcie
->pci
;
191 struct pcie_port
*pp
= &pci
->pp
;
193 return dw_handle_msi_irq(pp
);
196 static int artpec6_add_pcie_port(struct artpec6_pcie
*artpec6_pcie
,
197 struct platform_device
*pdev
)
199 struct dw_pcie
*pci
= artpec6_pcie
->pci
;
200 struct pcie_port
*pp
= &pci
->pp
;
201 struct device
*dev
= pci
->dev
;
204 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
205 pp
->msi_irq
= platform_get_irq_byname(pdev
, "msi");
206 if (pp
->msi_irq
< 0) {
207 dev_err(dev
, "failed to get MSI irq\n");
211 ret
= devm_request_irq(dev
, pp
->msi_irq
,
212 artpec6_pcie_msi_handler
,
213 IRQF_SHARED
| IRQF_NO_THREAD
,
214 "artpec6-pcie-msi", artpec6_pcie
);
216 dev_err(dev
, "failed to request MSI irq\n");
221 pp
->root_bus_nr
= -1;
222 pp
->ops
= &artpec6_pcie_host_ops
;
224 ret
= dw_pcie_host_init(pp
);
226 dev_err(dev
, "failed to initialize host\n");
233 static const struct dw_pcie_ops dw_pcie_ops
= {
234 .cpu_addr_fixup
= artpec6_pcie_cpu_addr_fixup
,
237 static int artpec6_pcie_probe(struct platform_device
*pdev
)
239 struct device
*dev
= &pdev
->dev
;
241 struct artpec6_pcie
*artpec6_pcie
;
242 struct resource
*dbi_base
;
243 struct resource
*phy_base
;
246 artpec6_pcie
= devm_kzalloc(dev
, sizeof(*artpec6_pcie
), GFP_KERNEL
);
250 pci
= devm_kzalloc(dev
, sizeof(*pci
), GFP_KERNEL
);
255 pci
->ops
= &dw_pcie_ops
;
257 artpec6_pcie
->pci
= pci
;
259 dbi_base
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dbi");
260 pci
->dbi_base
= devm_ioremap_resource(dev
, dbi_base
);
261 if (IS_ERR(pci
->dbi_base
))
262 return PTR_ERR(pci
->dbi_base
);
264 phy_base
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "phy");
265 artpec6_pcie
->phy_base
= devm_ioremap_resource(dev
, phy_base
);
266 if (IS_ERR(artpec6_pcie
->phy_base
))
267 return PTR_ERR(artpec6_pcie
->phy_base
);
269 artpec6_pcie
->regmap
=
270 syscon_regmap_lookup_by_phandle(dev
->of_node
,
272 if (IS_ERR(artpec6_pcie
->regmap
))
273 return PTR_ERR(artpec6_pcie
->regmap
);
275 platform_set_drvdata(pdev
, artpec6_pcie
);
277 ret
= artpec6_add_pcie_port(artpec6_pcie
, pdev
);
284 static const struct of_device_id artpec6_pcie_of_match
[] = {
285 { .compatible
= "axis,artpec6-pcie", },
289 static struct platform_driver artpec6_pcie_driver
= {
290 .probe
= artpec6_pcie_probe
,
292 .name
= "artpec6-pcie",
293 .of_match_table
= artpec6_pcie_of_match
,
294 .suppress_bind_attrs
= true,
297 builtin_platform_driver(artpec6_pcie_driver
);