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git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/pci/dwc/pcie-designware.h
2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #ifndef _PCIE_DESIGNWARE_H
15 #define _PCIE_DESIGNWARE_H
17 #include <linux/irq.h>
18 #include <linux/msi.h>
19 #include <linux/pci.h>
21 #include <linux/pci-epc.h>
22 #include <linux/pci-epf.h>
24 /* Parameters for the waiting for link up routine */
25 #define LINK_WAIT_MAX_RETRIES 10
26 #define LINK_WAIT_USLEEP_MIN 90000
27 #define LINK_WAIT_USLEEP_MAX 100000
29 /* Parameters for the waiting for iATU enabled routine */
30 #define LINK_WAIT_MAX_IATU_RETRIES 5
31 #define LINK_WAIT_IATU_MIN 9000
32 #define LINK_WAIT_IATU_MAX 10000
34 /* Synopsys-specific PCIe configuration registers */
35 #define PCIE_PORT_LINK_CONTROL 0x710
36 #define PORT_LINK_MODE_MASK (0x3f << 16)
37 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
38 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
39 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
40 #define PORT_LINK_MODE_8_LANES (0xf << 16)
42 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
43 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
44 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
45 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
46 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
47 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
48 #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
50 #define PCIE_MSI_ADDR_LO 0x820
51 #define PCIE_MSI_ADDR_HI 0x824
52 #define PCIE_MSI_INTR0_ENABLE 0x828
53 #define PCIE_MSI_INTR0_MASK 0x82C
54 #define PCIE_MSI_INTR0_STATUS 0x830
56 #define PCIE_ATU_VIEWPORT 0x900
57 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
58 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
59 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
60 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
61 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
62 #define PCIE_ATU_CR1 0x904
63 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
64 #define PCIE_ATU_TYPE_IO (0x2 << 0)
65 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
66 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
67 #define PCIE_ATU_CR2 0x908
68 #define PCIE_ATU_ENABLE (0x1 << 31)
69 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
70 #define PCIE_ATU_LOWER_BASE 0x90C
71 #define PCIE_ATU_UPPER_BASE 0x910
72 #define PCIE_ATU_LIMIT 0x914
73 #define PCIE_ATU_LOWER_TARGET 0x918
74 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
75 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
76 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
77 #define PCIE_ATU_UPPER_TARGET 0x91C
80 * iATU Unroll-specific register definitions
81 * From 4.80 core version the address translation will be made by unroll
83 #define PCIE_ATU_UNR_REGION_CTRL1 0x00
84 #define PCIE_ATU_UNR_REGION_CTRL2 0x04
85 #define PCIE_ATU_UNR_LOWER_BASE 0x08
86 #define PCIE_ATU_UNR_UPPER_BASE 0x0C
87 #define PCIE_ATU_UNR_LIMIT 0x10
88 #define PCIE_ATU_UNR_LOWER_TARGET 0x14
89 #define PCIE_ATU_UNR_UPPER_TARGET 0x18
91 /* Register address builder */
92 #define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) \
93 ((0x3 << 20) | ((region) << 9))
95 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
96 ((0x3 << 20) | ((region) << 9) | (0x1 << 8))
98 #define MSI_MESSAGE_CONTROL 0x52
99 #define MSI_CAP_MMC_SHIFT 1
100 #define MSI_CAP_MME_SHIFT 4
101 #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
102 #define MSI_MESSAGE_ADDR_L32 0x54
103 #define MSI_MESSAGE_ADDR_U32 0x58
106 * Maximum number of MSI IRQs can be 256 per controller. But keep
107 * it 32 as of now. Probably we will never need more than 32. If needed,
108 * then increment it in multiple of 32.
110 #define MAX_MSI_IRQS 32
111 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
117 enum dw_pcie_region_type
{
118 DW_PCIE_REGION_UNKNOWN
,
119 DW_PCIE_REGION_INBOUND
,
120 DW_PCIE_REGION_OUTBOUND
,
123 enum dw_pcie_device_mode
{
124 DW_PCIE_UNKNOWN_TYPE
,
130 struct dw_pcie_host_ops
{
131 int (*rd_own_conf
)(struct pcie_port
*pp
, int where
, int size
, u32
*val
);
132 int (*wr_own_conf
)(struct pcie_port
*pp
, int where
, int size
, u32 val
);
133 int (*rd_other_conf
)(struct pcie_port
*pp
, struct pci_bus
*bus
,
134 unsigned int devfn
, int where
, int size
, u32
*val
);
135 int (*wr_other_conf
)(struct pcie_port
*pp
, struct pci_bus
*bus
,
136 unsigned int devfn
, int where
, int size
, u32 val
);
137 void (*host_init
)(struct pcie_port
*pp
);
138 void (*msi_set_irq
)(struct pcie_port
*pp
, int irq
);
139 void (*msi_clear_irq
)(struct pcie_port
*pp
, int irq
);
140 phys_addr_t (*get_msi_addr
)(struct pcie_port
*pp
);
141 u32 (*get_msi_data
)(struct pcie_port
*pp
, int pos
);
142 void (*scan_bus
)(struct pcie_port
*pp
);
143 int (*msi_host_init
)(struct pcie_port
*pp
, struct msi_controller
*chip
);
149 void __iomem
*va_cfg0_base
;
152 void __iomem
*va_cfg1_base
;
154 resource_size_t io_base
;
155 phys_addr_t io_bus_addr
;
158 phys_addr_t mem_bus_addr
;
160 struct resource
*cfg
;
162 struct resource
*mem
;
163 struct resource
*busn
;
165 struct dw_pcie_host_ops
*ops
;
167 struct irq_domain
*irq_domain
;
168 unsigned long msi_data
;
169 DECLARE_BITMAP(msi_irq_in_use
, MAX_MSI_IRQS
);
172 enum dw_pcie_as_type
{
178 struct dw_pcie_ep_ops
{
179 void (*ep_init
)(struct dw_pcie_ep
*ep
);
180 int (*raise_irq
)(struct dw_pcie_ep
*ep
, enum pci_epc_irq_type type
,
186 struct dw_pcie_ep_ops
*ops
;
187 phys_addr_t phys_base
;
190 phys_addr_t
*outbound_addr
;
191 unsigned long ib_window_map
;
192 unsigned long ob_window_map
;
198 u64 (*cpu_addr_fixup
)(u64 cpu_addr
);
199 u32 (*read_dbi
)(struct dw_pcie
*pcie
, void __iomem
*base
, u32 reg
,
201 void (*write_dbi
)(struct dw_pcie
*pcie
, void __iomem
*base
, u32 reg
,
202 size_t size
, u32 val
);
203 int (*link_up
)(struct dw_pcie
*pcie
);
204 int (*start_link
)(struct dw_pcie
*pcie
);
205 void (*stop_link
)(struct dw_pcie
*pcie
);
210 void __iomem
*dbi_base
;
211 void __iomem
*dbi_base2
;
213 u8 iatu_unroll_enabled
;
215 struct dw_pcie_ep ep
;
216 const struct dw_pcie_ops
*ops
;
219 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
221 #define to_dw_pcie_from_ep(endpoint) \
222 container_of((endpoint), struct dw_pcie, ep)
224 int dw_pcie_read(void __iomem
*addr
, int size
, u32
*val
);
225 int dw_pcie_write(void __iomem
*addr
, int size
, u32 val
);
227 u32
__dw_pcie_read_dbi(struct dw_pcie
*pci
, void __iomem
*base
, u32 reg
,
229 void __dw_pcie_write_dbi(struct dw_pcie
*pci
, void __iomem
*base
, u32 reg
,
230 size_t size
, u32 val
);
231 int dw_pcie_link_up(struct dw_pcie
*pci
);
232 int dw_pcie_wait_for_link(struct dw_pcie
*pci
);
233 void dw_pcie_prog_outbound_atu(struct dw_pcie
*pci
, int index
,
234 int type
, u64 cpu_addr
, u64 pci_addr
,
236 int dw_pcie_prog_inbound_atu(struct dw_pcie
*pci
, int index
, int bar
,
237 u64 cpu_addr
, enum dw_pcie_as_type as_type
);
238 void dw_pcie_disable_atu(struct dw_pcie
*pci
, int index
,
239 enum dw_pcie_region_type type
);
240 void dw_pcie_setup(struct dw_pcie
*pci
);
242 static inline void dw_pcie_writel_dbi(struct dw_pcie
*pci
, u32 reg
, u32 val
)
244 __dw_pcie_write_dbi(pci
, pci
->dbi_base
, reg
, 0x4, val
);
247 static inline u32
dw_pcie_readl_dbi(struct dw_pcie
*pci
, u32 reg
)
249 return __dw_pcie_read_dbi(pci
, pci
->dbi_base
, reg
, 0x4);
252 static inline void dw_pcie_writew_dbi(struct dw_pcie
*pci
, u32 reg
, u16 val
)
254 __dw_pcie_write_dbi(pci
, pci
->dbi_base
, reg
, 0x2, val
);
257 static inline u16
dw_pcie_readw_dbi(struct dw_pcie
*pci
, u32 reg
)
259 return __dw_pcie_read_dbi(pci
, pci
->dbi_base
, reg
, 0x2);
262 static inline void dw_pcie_writeb_dbi(struct dw_pcie
*pci
, u32 reg
, u8 val
)
264 __dw_pcie_write_dbi(pci
, pci
->dbi_base
, reg
, 0x1, val
);
267 static inline u8
dw_pcie_readb_dbi(struct dw_pcie
*pci
, u32 reg
)
269 return __dw_pcie_read_dbi(pci
, pci
->dbi_base
, reg
, 0x1);
272 static inline void dw_pcie_writel_dbi2(struct dw_pcie
*pci
, u32 reg
, u32 val
)
274 __dw_pcie_write_dbi(pci
, pci
->dbi_base2
, reg
, 0x4, val
);
277 static inline u32
dw_pcie_readl_dbi2(struct dw_pcie
*pci
, u32 reg
)
279 return __dw_pcie_read_dbi(pci
, pci
->dbi_base2
, reg
, 0x4);
282 #ifdef CONFIG_PCIE_DW_HOST
283 irqreturn_t
dw_handle_msi_irq(struct pcie_port
*pp
);
284 void dw_pcie_msi_init(struct pcie_port
*pp
);
285 void dw_pcie_setup_rc(struct pcie_port
*pp
);
286 int dw_pcie_host_init(struct pcie_port
*pp
);
288 static inline irqreturn_t
dw_handle_msi_irq(struct pcie_port
*pp
)
293 static inline void dw_pcie_msi_init(struct pcie_port
*pp
)
297 static inline void dw_pcie_setup_rc(struct pcie_port
*pp
)
301 static inline int dw_pcie_host_init(struct pcie_port
*pp
)
307 #ifdef CONFIG_PCIE_DW_EP
308 void dw_pcie_ep_linkup(struct dw_pcie_ep
*ep
);
309 int dw_pcie_ep_init(struct dw_pcie_ep
*ep
);
310 void dw_pcie_ep_exit(struct dw_pcie_ep
*ep
);
312 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep
*ep
)
316 static inline int dw_pcie_ep_init(struct dw_pcie_ep
*ep
)
321 static inline void dw_pcie_ep_exit(struct dw_pcie_ep
*ep
)
325 #endif /* _PCIE_DESIGNWARE_H */