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[mirror_ubuntu-focal-kernel.git] / drivers / pci / host / pci-aardvark.c
1 /*
2 * Driver for the Aardvark PCIe controller, used on Marvell Armada
3 * 3700.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/of_address.h>
23 #include <linux/of_pci.h>
24
25 /* PCIe core registers */
26 #define PCIE_CORE_CMD_STATUS_REG 0x4
27 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
28 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
29 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
30 #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
31 #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
32 #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
33 #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
34 #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
35 #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
36 #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
37 #define PCIE_CORE_LINK_TRAINING BIT(5)
38 #define PCIE_CORE_LINK_WIDTH_SHIFT 20
39 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
42 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
43 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
44
45 /* PIO registers base address and register offsets */
46 #define PIO_BASE_ADDR 0x4000
47 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
48 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
50 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
51 #define PIO_COMPLETION_STATUS_SHIFT 7
52 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
53 #define PIO_COMPLETION_STATUS_OK 0
54 #define PIO_COMPLETION_STATUS_UR 1
55 #define PIO_COMPLETION_STATUS_CRS 2
56 #define PIO_COMPLETION_STATUS_CA 4
57 #define PIO_NON_POSTED_REQ BIT(0)
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
66
67 /* Aardvark Control registers */
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define SPEED_GEN_1 0
73 #define SPEED_GEN_2 1
74 #define SPEED_GEN_3 2
75 #define IS_RC_MSK 1
76 #define IS_RC_SHIFT 2
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
80 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
83 #define LINK_TRAINING_EN BIT(6)
84 #define LEGACY_INTA BIT(28)
85 #define LEGACY_INTB BIT(29)
86 #define LEGACY_INTC BIT(30)
87 #define LEGACY_INTD BIT(31)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
92 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
93 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
94 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
95 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
96 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
97 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
98 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
99 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
100 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
101 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
102 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
103 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
104 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
105 #define PCIE_ISR1_FLUSH BIT(5)
106 #define PCIE_ISR1_ALL_MASK GENMASK(5, 4)
107 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
108 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
109 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
110 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
111 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
112
113 /* PCIe window configuration */
114 #define OB_WIN_BASE_ADDR 0x4c00
115 #define OB_WIN_BLOCK_SIZE 0x20
116 #define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
117 OB_WIN_BLOCK_SIZE * (win) + \
118 (offset))
119 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
120 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
121 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
122 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
123 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
124 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
125 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
126
127 /* PCIe window types */
128 #define OB_PCIE_MEM 0x0
129 #define OB_PCIE_IO 0x4
130
131 /* LMI registers base address and register offsets */
132 #define LMI_BASE_ADDR 0x6000
133 #define CFG_REG (LMI_BASE_ADDR + 0x0)
134 #define LTSSM_SHIFT 24
135 #define LTSSM_MASK 0x3f
136 #define LTSSM_L0 0x10
137 #define RC_BAR_CONFIG 0x300
138
139 /* PCIe core controller registers */
140 #define CTRL_CORE_BASE_ADDR 0x18000
141 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
142 #define CTRL_MODE_SHIFT 0x0
143 #define CTRL_MODE_MASK 0x1
144 #define PCIE_CORE_MODE_DIRECT 0x0
145 #define PCIE_CORE_MODE_COMMAND 0x1
146
147 /* PCIe Central Interrupts Registers */
148 #define CENTRAL_INT_BASE_ADDR 0x1b000
149 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
150 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
151 #define PCIE_IRQ_CMDQ_INT BIT(0)
152 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
153 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
154 #define PCIE_IRQ_DMA_INT BIT(4)
155 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
156 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
157 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
158 #define PCIE_IRQ_COMPQ_INT BIT(12)
159 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
160 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
161 #define PCIE_IRQ_CORE_INT BIT(16)
162 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
163 #define PCIE_IRQ_DPMU_INT BIT(18)
164 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
165 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
166 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
167 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
168 #define PCIE_IRQ_EP_STATUS BIT(23)
169 #define PCIE_IRQ_ALL_MASK 0xfff0fb
170 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
171
172 /* Transaction types */
173 #define PCIE_CONFIG_RD_TYPE0 0x8
174 #define PCIE_CONFIG_RD_TYPE1 0x9
175 #define PCIE_CONFIG_WR_TYPE0 0xa
176 #define PCIE_CONFIG_WR_TYPE1 0xb
177
178 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
179 #define PCIE_BDF(dev) (dev << 4)
180 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
181 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
182 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
183 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
184 #define PCIE_CONF_ADDR(bus, devfn, where) \
185 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
186 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
187
188 #define PIO_TIMEOUT_MS 1
189
190 #define LINK_WAIT_MAX_RETRIES 10
191 #define LINK_WAIT_USLEEP_MIN 90000
192 #define LINK_WAIT_USLEEP_MAX 100000
193
194 #define MSI_IRQ_NUM 32
195
196 struct advk_pcie {
197 struct platform_device *pdev;
198 void __iomem *base;
199 struct list_head resources;
200 struct irq_domain *irq_domain;
201 struct irq_chip irq_chip;
202 struct irq_domain *msi_domain;
203 struct irq_domain *msi_inner_domain;
204 struct irq_chip msi_bottom_irq_chip;
205 struct irq_chip msi_irq_chip;
206 struct msi_domain_info msi_domain_info;
207 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
208 struct mutex msi_used_lock;
209 u16 msi_msg;
210 int root_bus_nr;
211 };
212
213 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
214 {
215 writel(val, pcie->base + reg);
216 }
217
218 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
219 {
220 return readl(pcie->base + reg);
221 }
222
223 static int advk_pcie_link_up(struct advk_pcie *pcie)
224 {
225 u32 val, ltssm_state;
226
227 val = advk_readl(pcie, CFG_REG);
228 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
229 return ltssm_state >= LTSSM_L0;
230 }
231
232 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
233 {
234 struct device *dev = &pcie->pdev->dev;
235 int retries;
236
237 /* check if the link is up or not */
238 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
239 if (advk_pcie_link_up(pcie)) {
240 dev_info(dev, "link up\n");
241 return 0;
242 }
243
244 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
245 }
246
247 dev_err(dev, "link never came up\n");
248 return -ETIMEDOUT;
249 }
250
251 /*
252 * Set PCIe address window register which could be used for memory
253 * mapping.
254 */
255 static void advk_pcie_set_ob_win(struct advk_pcie *pcie,
256 u32 win_num, u32 match_ms,
257 u32 match_ls, u32 mask_ms,
258 u32 mask_ls, u32 remap_ms,
259 u32 remap_ls, u32 action)
260 {
261 advk_writel(pcie, match_ls, OB_WIN_MATCH_LS(win_num));
262 advk_writel(pcie, match_ms, OB_WIN_MATCH_MS(win_num));
263 advk_writel(pcie, mask_ms, OB_WIN_MASK_MS(win_num));
264 advk_writel(pcie, mask_ls, OB_WIN_MASK_LS(win_num));
265 advk_writel(pcie, remap_ms, OB_WIN_REMAP_MS(win_num));
266 advk_writel(pcie, remap_ls, OB_WIN_REMAP_LS(win_num));
267 advk_writel(pcie, action, OB_WIN_ACTIONS(win_num));
268 advk_writel(pcie, match_ls | BIT(0), OB_WIN_MATCH_LS(win_num));
269 }
270
271 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
272 {
273 u32 reg;
274 int i;
275
276 /* Point PCIe unit MBUS decode windows to DRAM space */
277 for (i = 0; i < 8; i++)
278 advk_pcie_set_ob_win(pcie, i, 0, 0, 0, 0, 0, 0, 0);
279
280 /* Set to Direct mode */
281 reg = advk_readl(pcie, CTRL_CONFIG_REG);
282 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
283 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
284 advk_writel(pcie, reg, CTRL_CONFIG_REG);
285
286 /* Set PCI global control register to RC mode */
287 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
288 reg |= (IS_RC_MSK << IS_RC_SHIFT);
289 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
290
291 /* Set Advanced Error Capabilities and Control PF0 register */
292 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
293 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
294 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
295 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
296 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
297
298 /* Set PCIe Device Control and Status 1 PF0 register */
299 reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
300 (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
301 PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
302 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;
303 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
304
305 /* Program PCIe Control 2 to disable strict ordering */
306 reg = PCIE_CORE_CTRL2_RESERVED |
307 PCIE_CORE_CTRL2_TD_ENABLE;
308 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
309
310 /* Set GEN2 */
311 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
312 reg &= ~PCIE_GEN_SEL_MSK;
313 reg |= SPEED_GEN_2;
314 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
315
316 /* Set lane X1 */
317 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
318 reg &= ~LANE_CNT_MSK;
319 reg |= LANE_COUNT_1;
320 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
321
322 /* Enable link training */
323 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
324 reg |= LINK_TRAINING_EN;
325 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
326
327 /* Enable MSI */
328 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
329 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
330 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
331
332 /* Clear all interrupts */
333 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
334 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
335 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
336
337 /* Disable All ISR0/1 Sources */
338 reg = PCIE_ISR0_ALL_MASK;
339 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
340 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
341
342 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
343
344 /* Unmask all MSI's */
345 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
346
347 /* Enable summary interrupt for GIC SPI source */
348 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
349 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
350
351 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
352 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
353 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
354
355 /* Bypass the address window mapping for PIO */
356 reg = advk_readl(pcie, PIO_CTRL);
357 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
358 advk_writel(pcie, reg, PIO_CTRL);
359
360 /* Start link training */
361 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
362 reg |= PCIE_CORE_LINK_TRAINING;
363 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
364
365 advk_pcie_wait_for_link(pcie);
366
367 reg = PCIE_CORE_LINK_L0S_ENTRY |
368 (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
369 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
370
371 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
372 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
373 PCIE_CORE_CMD_IO_ACCESS_EN |
374 PCIE_CORE_CMD_MEM_IO_REQ_EN;
375 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
376 }
377
378 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
379 {
380 struct device *dev = &pcie->pdev->dev;
381 u32 reg;
382 unsigned int status;
383 char *strcomp_status, *str_posted;
384
385 reg = advk_readl(pcie, PIO_STAT);
386 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
387 PIO_COMPLETION_STATUS_SHIFT;
388
389 if (!status)
390 return;
391
392 switch (status) {
393 case PIO_COMPLETION_STATUS_UR:
394 strcomp_status = "UR";
395 break;
396 case PIO_COMPLETION_STATUS_CRS:
397 strcomp_status = "CRS";
398 break;
399 case PIO_COMPLETION_STATUS_CA:
400 strcomp_status = "CA";
401 break;
402 default:
403 strcomp_status = "Unknown";
404 break;
405 }
406
407 if (reg & PIO_NON_POSTED_REQ)
408 str_posted = "Non-posted";
409 else
410 str_posted = "Posted";
411
412 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
413 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
414 }
415
416 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
417 {
418 struct device *dev = &pcie->pdev->dev;
419 unsigned long timeout;
420
421 timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
422
423 while (time_before(jiffies, timeout)) {
424 u32 start, isr;
425
426 start = advk_readl(pcie, PIO_START);
427 isr = advk_readl(pcie, PIO_ISR);
428 if (!start && isr)
429 return 0;
430 }
431
432 dev_err(dev, "config read/write timed out\n");
433 return -ETIMEDOUT;
434 }
435
436 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
437 int where, int size, u32 *val)
438 {
439 struct advk_pcie *pcie = bus->sysdata;
440 u32 reg;
441 int ret;
442
443 if (PCI_SLOT(devfn) != 0) {
444 *val = 0xffffffff;
445 return PCIBIOS_DEVICE_NOT_FOUND;
446 }
447
448 /* Start PIO */
449 advk_writel(pcie, 0, PIO_START);
450 advk_writel(pcie, 1, PIO_ISR);
451
452 /* Program the control register */
453 reg = advk_readl(pcie, PIO_CTRL);
454 reg &= ~PIO_CTRL_TYPE_MASK;
455 if (bus->number == pcie->root_bus_nr)
456 reg |= PCIE_CONFIG_RD_TYPE0;
457 else
458 reg |= PCIE_CONFIG_RD_TYPE1;
459 advk_writel(pcie, reg, PIO_CTRL);
460
461 /* Program the address registers */
462 reg = PCIE_BDF(devfn) | PCIE_CONF_REG(where);
463 advk_writel(pcie, reg, PIO_ADDR_LS);
464 advk_writel(pcie, 0, PIO_ADDR_MS);
465
466 /* Program the data strobe */
467 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
468
469 /* Start the transfer */
470 advk_writel(pcie, 1, PIO_START);
471
472 ret = advk_pcie_wait_pio(pcie);
473 if (ret < 0)
474 return PCIBIOS_SET_FAILED;
475
476 advk_pcie_check_pio_status(pcie);
477
478 /* Get the read result */
479 *val = advk_readl(pcie, PIO_RD_DATA);
480 if (size == 1)
481 *val = (*val >> (8 * (where & 3))) & 0xff;
482 else if (size == 2)
483 *val = (*val >> (8 * (where & 3))) & 0xffff;
484
485 return PCIBIOS_SUCCESSFUL;
486 }
487
488 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
489 int where, int size, u32 val)
490 {
491 struct advk_pcie *pcie = bus->sysdata;
492 u32 reg;
493 u32 data_strobe = 0x0;
494 int offset;
495 int ret;
496
497 if (PCI_SLOT(devfn) != 0)
498 return PCIBIOS_DEVICE_NOT_FOUND;
499
500 if (where % size)
501 return PCIBIOS_SET_FAILED;
502
503 /* Start PIO */
504 advk_writel(pcie, 0, PIO_START);
505 advk_writel(pcie, 1, PIO_ISR);
506
507 /* Program the control register */
508 reg = advk_readl(pcie, PIO_CTRL);
509 reg &= ~PIO_CTRL_TYPE_MASK;
510 if (bus->number == pcie->root_bus_nr)
511 reg |= PCIE_CONFIG_WR_TYPE0;
512 else
513 reg |= PCIE_CONFIG_WR_TYPE1;
514 advk_writel(pcie, reg, PIO_CTRL);
515
516 /* Program the address registers */
517 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
518 advk_writel(pcie, reg, PIO_ADDR_LS);
519 advk_writel(pcie, 0, PIO_ADDR_MS);
520
521 /* Calculate the write strobe */
522 offset = where & 0x3;
523 reg = val << (8 * offset);
524 data_strobe = GENMASK(size - 1, 0) << offset;
525
526 /* Program the data register */
527 advk_writel(pcie, reg, PIO_WR_DATA);
528
529 /* Program the data strobe */
530 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
531
532 /* Start the transfer */
533 advk_writel(pcie, 1, PIO_START);
534
535 ret = advk_pcie_wait_pio(pcie);
536 if (ret < 0)
537 return PCIBIOS_SET_FAILED;
538
539 advk_pcie_check_pio_status(pcie);
540
541 return PCIBIOS_SUCCESSFUL;
542 }
543
544 static struct pci_ops advk_pcie_ops = {
545 .read = advk_pcie_rd_conf,
546 .write = advk_pcie_wr_conf,
547 };
548
549 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
550 struct msi_msg *msg)
551 {
552 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
553 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
554
555 msg->address_lo = lower_32_bits(msi_msg);
556 msg->address_hi = upper_32_bits(msi_msg);
557 msg->data = data->irq;
558 }
559
560 static int advk_msi_set_affinity(struct irq_data *irq_data,
561 const struct cpumask *mask, bool force)
562 {
563 return -EINVAL;
564 }
565
566 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
567 unsigned int virq,
568 unsigned int nr_irqs, void *args)
569 {
570 struct advk_pcie *pcie = domain->host_data;
571 int hwirq, i;
572
573 mutex_lock(&pcie->msi_used_lock);
574 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
575 0, nr_irqs, 0);
576 if (hwirq >= MSI_IRQ_NUM) {
577 mutex_unlock(&pcie->msi_used_lock);
578 return -ENOSPC;
579 }
580
581 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
582 mutex_unlock(&pcie->msi_used_lock);
583
584 for (i = 0; i < nr_irqs; i++)
585 irq_domain_set_info(domain, virq + i, hwirq + i,
586 &pcie->msi_bottom_irq_chip,
587 domain->host_data, handle_simple_irq,
588 NULL, NULL);
589
590 return hwirq;
591 }
592
593 static void advk_msi_irq_domain_free(struct irq_domain *domain,
594 unsigned int virq, unsigned int nr_irqs)
595 {
596 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
597 struct advk_pcie *pcie = domain->host_data;
598
599 mutex_lock(&pcie->msi_used_lock);
600 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
601 mutex_unlock(&pcie->msi_used_lock);
602 }
603
604 static const struct irq_domain_ops advk_msi_domain_ops = {
605 .alloc = advk_msi_irq_domain_alloc,
606 .free = advk_msi_irq_domain_free,
607 };
608
609 static void advk_pcie_irq_mask(struct irq_data *d)
610 {
611 struct advk_pcie *pcie = d->domain->host_data;
612 irq_hw_number_t hwirq = irqd_to_hwirq(d);
613 u32 mask;
614
615 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
616 mask |= PCIE_ISR0_INTX_ASSERT(hwirq);
617 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
618 }
619
620 static void advk_pcie_irq_unmask(struct irq_data *d)
621 {
622 struct advk_pcie *pcie = d->domain->host_data;
623 irq_hw_number_t hwirq = irqd_to_hwirq(d);
624 u32 mask;
625
626 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
627 mask &= ~PCIE_ISR0_INTX_ASSERT(hwirq);
628 advk_writel(pcie, mask, PCIE_ISR0_MASK_REG);
629 }
630
631 static int advk_pcie_irq_map(struct irq_domain *h,
632 unsigned int virq, irq_hw_number_t hwirq)
633 {
634 struct advk_pcie *pcie = h->host_data;
635
636 advk_pcie_irq_mask(irq_get_irq_data(virq));
637 irq_set_status_flags(virq, IRQ_LEVEL);
638 irq_set_chip_and_handler(virq, &pcie->irq_chip,
639 handle_level_irq);
640 irq_set_chip_data(virq, pcie);
641
642 return 0;
643 }
644
645 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
646 .map = advk_pcie_irq_map,
647 .xlate = irq_domain_xlate_onecell,
648 };
649
650 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
651 {
652 struct device *dev = &pcie->pdev->dev;
653 struct device_node *node = dev->of_node;
654 struct irq_chip *bottom_ic, *msi_ic;
655 struct msi_domain_info *msi_di;
656 phys_addr_t msi_msg_phys;
657
658 mutex_init(&pcie->msi_used_lock);
659
660 bottom_ic = &pcie->msi_bottom_irq_chip;
661
662 bottom_ic->name = "MSI";
663 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
664 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
665
666 msi_ic = &pcie->msi_irq_chip;
667 msi_ic->name = "advk-MSI";
668
669 msi_di = &pcie->msi_domain_info;
670 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
671 MSI_FLAG_MULTI_PCI_MSI;
672 msi_di->chip = msi_ic;
673
674 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
675
676 advk_writel(pcie, lower_32_bits(msi_msg_phys),
677 PCIE_MSI_ADDR_LOW_REG);
678 advk_writel(pcie, upper_32_bits(msi_msg_phys),
679 PCIE_MSI_ADDR_HIGH_REG);
680
681 pcie->msi_inner_domain =
682 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
683 &advk_msi_domain_ops, pcie);
684 if (!pcie->msi_inner_domain)
685 return -ENOMEM;
686
687 pcie->msi_domain =
688 pci_msi_create_irq_domain(of_node_to_fwnode(node),
689 msi_di, pcie->msi_inner_domain);
690 if (!pcie->msi_domain) {
691 irq_domain_remove(pcie->msi_inner_domain);
692 return -ENOMEM;
693 }
694
695 return 0;
696 }
697
698 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
699 {
700 irq_domain_remove(pcie->msi_domain);
701 irq_domain_remove(pcie->msi_inner_domain);
702 }
703
704 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
705 {
706 struct device *dev = &pcie->pdev->dev;
707 struct device_node *node = dev->of_node;
708 struct device_node *pcie_intc_node;
709 struct irq_chip *irq_chip;
710
711 pcie_intc_node = of_get_next_child(node, NULL);
712 if (!pcie_intc_node) {
713 dev_err(dev, "No PCIe Intc node found\n");
714 return -ENODEV;
715 }
716
717 irq_chip = &pcie->irq_chip;
718
719 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
720 dev_name(dev));
721 if (!irq_chip->name) {
722 of_node_put(pcie_intc_node);
723 return -ENOMEM;
724 }
725
726 irq_chip->irq_mask = advk_pcie_irq_mask;
727 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
728 irq_chip->irq_unmask = advk_pcie_irq_unmask;
729
730 pcie->irq_domain =
731 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
732 &advk_pcie_irq_domain_ops, pcie);
733 if (!pcie->irq_domain) {
734 dev_err(dev, "Failed to get a INTx IRQ domain\n");
735 of_node_put(pcie_intc_node);
736 return -ENOMEM;
737 }
738
739 return 0;
740 }
741
742 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
743 {
744 irq_domain_remove(pcie->irq_domain);
745 }
746
747 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
748 {
749 u32 msi_val, msi_mask, msi_status, msi_idx;
750 u16 msi_data;
751
752 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
753 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
754 msi_status = msi_val & ~msi_mask;
755
756 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
757 if (!(BIT(msi_idx) & msi_status))
758 continue;
759
760 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
761 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
762 generic_handle_irq(msi_data);
763 }
764
765 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
766 PCIE_ISR0_REG);
767 }
768
769 static void advk_pcie_handle_int(struct advk_pcie *pcie)
770 {
771 u32 val, mask, status;
772 int i, virq;
773
774 val = advk_readl(pcie, PCIE_ISR0_REG);
775 mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
776 status = val & ((~mask) & PCIE_ISR0_ALL_MASK);
777
778 if (!status) {
779 advk_writel(pcie, val, PCIE_ISR0_REG);
780 return;
781 }
782
783 /* Process MSI interrupts */
784 if (status & PCIE_ISR0_MSI_INT_PENDING)
785 advk_pcie_handle_msi(pcie);
786
787 /* Process legacy interrupts */
788 for (i = 0; i < PCI_NUM_INTX; i++) {
789 if (!(status & PCIE_ISR0_INTX_ASSERT(i)))
790 continue;
791
792 advk_writel(pcie, PCIE_ISR0_INTX_ASSERT(i),
793 PCIE_ISR0_REG);
794
795 virq = irq_find_mapping(pcie->irq_domain, i);
796 generic_handle_irq(virq);
797 }
798 }
799
800 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
801 {
802 struct advk_pcie *pcie = arg;
803 u32 status;
804
805 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
806 if (!(status & PCIE_IRQ_CORE_INT))
807 return IRQ_NONE;
808
809 advk_pcie_handle_int(pcie);
810
811 /* Clear interrupt */
812 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
813
814 return IRQ_HANDLED;
815 }
816
817 static int advk_pcie_parse_request_of_pci_ranges(struct advk_pcie *pcie)
818 {
819 int err, res_valid = 0;
820 struct device *dev = &pcie->pdev->dev;
821 struct device_node *np = dev->of_node;
822 struct resource_entry *win, *tmp;
823 resource_size_t iobase;
824
825 INIT_LIST_HEAD(&pcie->resources);
826
827 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
828 &iobase);
829 if (err)
830 return err;
831
832 err = devm_request_pci_bus_resources(dev, &pcie->resources);
833 if (err)
834 goto out_release_res;
835
836 resource_list_for_each_entry_safe(win, tmp, &pcie->resources) {
837 struct resource *res = win->res;
838
839 switch (resource_type(res)) {
840 case IORESOURCE_IO:
841 advk_pcie_set_ob_win(pcie, 1,
842 upper_32_bits(res->start),
843 lower_32_bits(res->start),
844 0, 0xF8000000, 0,
845 lower_32_bits(res->start),
846 OB_PCIE_IO);
847 err = pci_remap_iospace(res, iobase);
848 if (err) {
849 dev_warn(dev, "error %d: failed to map resource %pR\n",
850 err, res);
851 resource_list_destroy_entry(win);
852 }
853 break;
854 case IORESOURCE_MEM:
855 advk_pcie_set_ob_win(pcie, 0,
856 upper_32_bits(res->start),
857 lower_32_bits(res->start),
858 0x0, 0xF8000000, 0,
859 lower_32_bits(res->start),
860 (2 << 20) | OB_PCIE_MEM);
861 res_valid |= !(res->flags & IORESOURCE_PREFETCH);
862 break;
863 case IORESOURCE_BUS:
864 pcie->root_bus_nr = res->start;
865 break;
866 }
867 }
868
869 if (!res_valid) {
870 dev_err(dev, "non-prefetchable memory resource required\n");
871 err = -EINVAL;
872 goto out_release_res;
873 }
874
875 return 0;
876
877 out_release_res:
878 pci_free_resource_list(&pcie->resources);
879 return err;
880 }
881
882 static int advk_pcie_probe(struct platform_device *pdev)
883 {
884 struct device *dev = &pdev->dev;
885 struct advk_pcie *pcie;
886 struct resource *res;
887 struct pci_bus *bus, *child;
888 struct pci_host_bridge *bridge;
889 int ret, irq;
890
891 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
892 if (!bridge)
893 return -ENOMEM;
894
895 pcie = pci_host_bridge_priv(bridge);
896 pcie->pdev = pdev;
897
898 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
899 pcie->base = devm_ioremap_resource(dev, res);
900 if (IS_ERR(pcie->base))
901 return PTR_ERR(pcie->base);
902
903 irq = platform_get_irq(pdev, 0);
904 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
905 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
906 pcie);
907 if (ret) {
908 dev_err(dev, "Failed to register interrupt\n");
909 return ret;
910 }
911
912 ret = advk_pcie_parse_request_of_pci_ranges(pcie);
913 if (ret) {
914 dev_err(dev, "Failed to parse resources\n");
915 return ret;
916 }
917
918 advk_pcie_setup_hw(pcie);
919
920 ret = advk_pcie_init_irq_domain(pcie);
921 if (ret) {
922 dev_err(dev, "Failed to initialize irq\n");
923 return ret;
924 }
925
926 ret = advk_pcie_init_msi_irq_domain(pcie);
927 if (ret) {
928 dev_err(dev, "Failed to initialize irq\n");
929 advk_pcie_remove_irq_domain(pcie);
930 return ret;
931 }
932
933 list_splice_init(&pcie->resources, &bridge->windows);
934 bridge->dev.parent = dev;
935 bridge->sysdata = pcie;
936 bridge->busnr = 0;
937 bridge->ops = &advk_pcie_ops;
938
939 ret = pci_scan_root_bus_bridge(bridge);
940 if (ret < 0) {
941 advk_pcie_remove_msi_irq_domain(pcie);
942 advk_pcie_remove_irq_domain(pcie);
943 return ret;
944 }
945
946 bus = bridge->bus;
947
948 pci_bus_assign_resources(bus);
949
950 list_for_each_entry(child, &bus->children, node)
951 pcie_bus_configure_settings(child);
952
953 pci_bus_add_devices(bus);
954 return 0;
955 }
956
957 static const struct of_device_id advk_pcie_of_match_table[] = {
958 { .compatible = "marvell,armada-3700-pcie", },
959 {},
960 };
961
962 static struct platform_driver advk_pcie_driver = {
963 .driver = {
964 .name = "advk-pcie",
965 .of_match_table = advk_pcie_of_match_table,
966 /* Driver unloading/unbinding currently not supported */
967 .suppress_bind_attrs = true,
968 },
969 .probe = advk_pcie_probe,
970 };
971 builtin_platform_driver(advk_pcie_driver);
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