drivers/pci/host/pci-imx6.c

   1 /*
   2  * PCIe host controller driver for Freescale i.MX6 SoCs
   3  *
   4  * Copyright (C) 2013 Kosagi
   5  *              http://www.kosagi.com
   6  *
   7  * Author: Sean Cross <xobs@kosagi.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  20 #include <linux/module.h>
  21 #include <linux/of_gpio.h>
  22 #include <linux/pci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/resource.h>
  26 #include <linux/signal.h>
  27 #include <linux/types.h>
  28 #include <linux/interrupt.h>
  29
  30 #include "pcie-designware.h"
  31
  32 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
  33
  34 struct imx6_pcie {
  35         int                     reset_gpio;
  36         struct clk              *pcie_bus;
  37         struct clk              *pcie_phy;
  38         struct clk              *pcie;
  39         struct pcie_port        pp;
  40         struct regmap           *iomuxc_gpr;
  41         void __iomem            *mem_base;
  42 };
  43
  44 /* PCIe Root Complex registers (memory-mapped) */
  45 #define PCIE_RC_LCR                             0x7c
  46 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1        0x1
  47 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2        0x2
  48 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK        0xf
  49
  50 /* PCIe Port Logic registers (memory-mapped) */
  51 #define PL_OFFSET 0x700
  52 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
  53 #define PCIE_PL_PFLR_LINK_STATE_MASK            (0x3f << 16)
  54 #define PCIE_PL_PFLR_FORCE_LINK                 (1 << 15)
  55 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
  56 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
  57 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
  58 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP          (1 << 4)
  59
  60 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
  61 #define PCIE_PHY_CTRL_DATA_LOC 0
  62 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
  63 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
  64 #define PCIE_PHY_CTRL_WR_LOC 18
  65 #define PCIE_PHY_CTRL_RD_LOC 19
  66
  67 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
  68 #define PCIE_PHY_STAT_ACK_LOC 16
  69
  70 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
  71 #define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
  72
  73 /* PHY registers (not memory-mapped) */
  74 #define PCIE_PHY_RX_ASIC_OUT 0x100D
  75
  76 #define PHY_RX_OVRD_IN_LO 0x1005
  77 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
  78 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
  79
  80 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
  81 {
  82         u32 val;
  83         u32 max_iterations = 10;
  84         u32 wait_counter = 0;
  85
  86         do {
  87                 val = readl(dbi_base + PCIE_PHY_STAT);
  88                 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
  89                 wait_counter++;
  90
  91                 if (val == exp_val)
  92                         return 0;
  93
  94                 udelay(1);
  95         } while (wait_counter < max_iterations);
  96
  97         return -ETIMEDOUT;
  98 }
  99
 100 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
 101 {
 102         u32 val;
 103         int ret;
 104
 105         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 106         writel(val, dbi_base + PCIE_PHY_CTRL);
 107
 108         val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
 109         writel(val, dbi_base + PCIE_PHY_CTRL);
 110
 111         ret = pcie_phy_poll_ack(dbi_base, 1);
 112         if (ret)
 113                 return ret;
 114
 115         val = addr << PCIE_PHY_CTRL_DATA_LOC;
 116         writel(val, dbi_base + PCIE_PHY_CTRL);
 117
 118         ret = pcie_phy_poll_ack(dbi_base, 0);
 119         if (ret)
 120                 return ret;
 121
 122         return 0;
 123 }
 124
 125 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 126 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
 127 {
 128         u32 val, phy_ctl;
 129         int ret;
 130
 131         ret = pcie_phy_wait_ack(dbi_base, addr);
 132         if (ret)
 133                 return ret;
 134
 135         /* assert Read signal */
 136         phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
 137         writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
 138
 139         ret = pcie_phy_poll_ack(dbi_base, 1);
 140         if (ret)
 141                 return ret;
 142
 143         val = readl(dbi_base + PCIE_PHY_STAT);
 144         *data = val & 0xffff;
 145
 146         /* deassert Read signal */
 147         writel(0x00, dbi_base + PCIE_PHY_CTRL);
 148
 149         ret = pcie_phy_poll_ack(dbi_base, 0);
 150         if (ret)
 151                 return ret;
 152
 153         return 0;
 154 }
 155
 156 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 157 {
 158         u32 var;
 159         int ret;
 160
 161         /* write addr */
 162         /* cap addr */
 163         ret = pcie_phy_wait_ack(dbi_base, addr);
 164         if (ret)
 165                 return ret;
 166
 167         var = data << PCIE_PHY_CTRL_DATA_LOC;
 168         writel(var, dbi_base + PCIE_PHY_CTRL);
 169
 170         /* capture data */
 171         var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
 172         writel(var, dbi_base + PCIE_PHY_CTRL);
 173
 174         ret = pcie_phy_poll_ack(dbi_base, 1);
 175         if (ret)
 176                 return ret;
 177
 178         /* deassert cap data */
 179         var = data << PCIE_PHY_CTRL_DATA_LOC;
 180         writel(var, dbi_base + PCIE_PHY_CTRL);
 181
 182         /* wait for ack de-assertion */
 183         ret = pcie_phy_poll_ack(dbi_base, 0);
 184         if (ret)
 185                 return ret;
 186
 187         /* assert wr signal */
 188         var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
 189         writel(var, dbi_base + PCIE_PHY_CTRL);
 190
 191         /* wait for ack */
 192         ret = pcie_phy_poll_ack(dbi_base, 1);
 193         if (ret)
 194                 return ret;
 195
 196         /* deassert wr signal */
 197         var = data << PCIE_PHY_CTRL_DATA_LOC;
 198         writel(var, dbi_base + PCIE_PHY_CTRL);
 199
 200         /* wait for ack de-assertion */
 201         ret = pcie_phy_poll_ack(dbi_base, 0);
 202         if (ret)
 203                 return ret;
 204
 205         writel(0x0, dbi_base + PCIE_PHY_CTRL);
 206
 207         return 0;
 208 }
 209
 210 /*  Added for PCI abort handling */
 211 static int imx6q_pcie_abort_handler(unsigned long addr,
 212                 unsigned int fsr, struct pt_regs *regs)
 213 {
 214         return 0;
 215 }
 216
 217 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 218 {
 219         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 220         u32 val, gpr1, gpr12;
 221
 222         /*
 223          * If the bootloader already enabled the link we need some special
 224          * handling to get the core back into a state where it is safe to
 225          * touch it for configuration.  As there is no dedicated reset signal
 226          * wired up for MX6QDL, we need to manually force LTSSM into "detect"
 227          * state before completely disabling LTSSM, which is a prerequisite
 228          * for core configuration.
 229          *
 230          * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
 231          * indication that the bootloader activated the link.
 232          */
 233         regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, &gpr1);
 234         regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, &gpr12);
 235
 236         if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
 237             (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
 238                 val = readl(pp->dbi_base + PCIE_PL_PFLR);
 239                 val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
 240                 val |= PCIE_PL_PFLR_FORCE_LINK;
 241                 writel(val, pp->dbi_base + PCIE_PL_PFLR);
 242
 243                 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 244                                 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 245         }
 246
 247         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 248                         IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 249         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 250                         IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 251
 252         return 0;
 253 }
 254
 255 static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
 256 {
 257         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 258         int ret;
 259
 260         ret = clk_prepare_enable(imx6_pcie->pcie_phy);
 261         if (ret) {
 262                 dev_err(pp->dev, "unable to enable pcie_phy clock\n");
 263                 goto err_pcie_phy;
 264         }
 265
 266         ret = clk_prepare_enable(imx6_pcie->pcie_bus);
 267         if (ret) {
 268                 dev_err(pp->dev, "unable to enable pcie_bus clock\n");
 269                 goto err_pcie_bus;
 270         }
 271
 272         ret = clk_prepare_enable(imx6_pcie->pcie);
 273         if (ret) {
 274                 dev_err(pp->dev, "unable to enable pcie clock\n");
 275                 goto err_pcie;
 276         }
 277
 278         /* power up core phy and enable ref clock */
 279         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 280                         IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 281         /*
 282          * the async reset input need ref clock to sync internally,
 283          * when the ref clock comes after reset, internal synced
 284          * reset time is too short, cannot meet the requirement.
 285          * add one ~10us delay here.
 286          */
 287         udelay(10);
 288         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 289                         IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 290
 291         /* allow the clocks to stabilize */
 292         usleep_range(200, 500);
 293
 294         /* Some boards don't have PCIe reset GPIO. */
 295         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 296                 gpio_set_value(imx6_pcie->reset_gpio, 0);
 297                 msleep(100);
 298                 gpio_set_value(imx6_pcie->reset_gpio, 1);
 299         }
 300         return 0;
 301
 302 err_pcie:
 303         clk_disable_unprepare(imx6_pcie->pcie_bus);
 304 err_pcie_bus:
 305         clk_disable_unprepare(imx6_pcie->pcie_phy);
 306 err_pcie_phy:
 307         return ret;
 308
 309 }
 310
 311 static void imx6_pcie_init_phy(struct pcie_port *pp)
 312 {
 313         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 314
 315         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 316                         IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 317
 318         /* configure constant input signal to the pcie ctrl and phy */
 319         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 320                         IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
 321         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 322                         IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 323
 324         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 325                         IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0);
 326         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 327                         IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6);
 328         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 329                         IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12);
 330         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 331                         IMX6Q_GPR8_TX_SWING_FULL, 127 << 18);
 332         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 333                         IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
 334 }
 335
 336 static int imx6_pcie_wait_for_link(struct pcie_port *pp)
 337 {
 338         int count = 200;
 339
 340         while (!dw_pcie_link_up(pp)) {
 341                 usleep_range(100, 1000);
 342                 if (--count)
 343                         continue;
 344
 345                 dev_err(pp->dev, "phy link never came up\n");
 346                 dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 347                         readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
 348                         readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
 349                 return -EINVAL;
 350         }
 351
 352         return 0;
 353 }
 354
 355 static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
 356 {
 357         struct pcie_port *pp = arg;
 358
 359         return dw_handle_msi_irq(pp);
 360 }
 361
 362 static int imx6_pcie_start_link(struct pcie_port *pp)
 363 {
 364         struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 365         uint32_t tmp;
 366         int ret, count;
 367
 368         /*
 369          * Force Gen1 operation when starting the link.  In case the link is
 370          * started in Gen2 mode, there is a possibility the devices on the
 371          * bus will not be detected at all.  This happens with PCIe switches.
 372          */
 373         tmp = readl(pp->dbi_base + PCIE_RC_LCR);
 374         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 375         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
 376         writel(tmp, pp->dbi_base + PCIE_RC_LCR);
 377
 378         /* Start LTSSM. */
 379         regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 380                         IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
 381
 382         ret = imx6_pcie_wait_for_link(pp);
 383         if (ret)
 384                 return ret;
 385
 386         /* Allow Gen2 mode after the link is up. */
 387         tmp = readl(pp->dbi_base + PCIE_RC_LCR);
 388         tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
 389         tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
 390         writel(tmp, pp->dbi_base + PCIE_RC_LCR);
 391
 392         /*
 393          * Start Directed Speed Change so the best possible speed both link
 394          * partners support can be negotiated.
 395          */
 396         tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 397         tmp |= PORT_LOGIC_SPEED_CHANGE;
 398         writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 399
 400         count = 200;
 401         while (count--) {
 402                 tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 403                 /* Test if the speed change finished. */
 404                 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 405                         break;
 406                 usleep_range(100, 1000);
 407         }
 408
 409         /* Make sure link training is finished as well! */
 410         if (count)
 411                 ret = imx6_pcie_wait_for_link(pp);
 412         else
 413                 ret = -EINVAL;
 414
 415         if (ret) {
 416                 dev_err(pp->dev, "Failed to bring link up!\n");
 417         } else {
 418                 tmp = readl(pp->dbi_base + 0x80);
 419                 dev_dbg(pp->dev, "Link up, Gen=%i\n", (tmp >> 16) & 0xf);
 420         }
 421
 422         return ret;
 423 }
 424
 425 static void imx6_pcie_host_init(struct pcie_port *pp)
 426 {
 427         imx6_pcie_assert_core_reset(pp);
 428
 429         imx6_pcie_init_phy(pp);
 430
 431         imx6_pcie_deassert_core_reset(pp);
 432
 433         dw_pcie_setup_rc(pp);
 434
 435         imx6_pcie_start_link(pp);
 436
 437         if (IS_ENABLED(CONFIG_PCI_MSI))
 438                 dw_pcie_msi_init(pp);
 439 }
 440
 441 static void imx6_pcie_reset_phy(struct pcie_port *pp)
 442 {
 443         uint32_t temp;
 444
 445         pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
 446         temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 447                  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 448         pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
 449
 450         usleep_range(2000, 3000);
 451
 452         pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
 453         temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 454                   PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 455         pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
 456 }
 457
 458 static int imx6_pcie_link_up(struct pcie_port *pp)
 459 {
 460         u32 rc, debug_r0, rx_valid;
 461         int count = 5;
 462
 463         /*
 464          * Test if the PHY reports that the link is up and also that the LTSSM
 465          * training finished. There are three possible states of the link when
 466          * this code is called:
 467          * 1) The link is DOWN (unlikely)
 468          *     The link didn't come up yet for some reason. This usually means
 469          *     we have a real problem somewhere. Reset the PHY and exit. This
 470          *     state calls for inspection of the DEBUG registers.
 471          * 2) The link is UP, but still in LTSSM training
 472          *     Wait for the training to finish, which should take a very short
 473          *     time. If the training does not finish, we have a problem and we
 474          *     need to inspect the DEBUG registers. If the training does finish,
 475          *     the link is up and operating correctly.
 476          * 3) The link is UP and no longer in LTSSM training
 477          *     The link is up and operating correctly.
 478          */
 479         while (1) {
 480                 rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
 481                 if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_UP))
 482                         break;
 483                 if (!(rc & PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING))
 484                         return 1;
 485                 if (!count--)
 486                         break;
 487                 dev_dbg(pp->dev, "Link is up, but still in training\n");
 488                 /*
 489                  * Wait a little bit, then re-check if the link finished
 490                  * the training.
 491                  */
 492                 usleep_range(1000, 2000);
 493         }
 494         /*
 495          * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
 496          * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
 497          * If (MAC/LTSSM.state == Recovery.RcvrLock)
 498          * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
 499          * to gen2 is stuck
 500          */
 501         pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);
 502         debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);
 503
 504         if (rx_valid & 0x01)
 505                 return 0;
 506
 507         if ((debug_r0 & 0x3f) != 0x0d)
 508                 return 0;
 509
 510         dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
 511         dev_dbg(pp->dev, "debug_r0=%08x debug_r1=%08x\n", debug_r0, rc);
 512
 513         imx6_pcie_reset_phy(pp);
 514
 515         return 0;
 516 }
 517
 518 static struct pcie_host_ops imx6_pcie_host_ops = {
 519         .link_up = imx6_pcie_link_up,
 520         .host_init = imx6_pcie_host_init,
 521 };
 522
 523 static int __init imx6_add_pcie_port(struct pcie_port *pp,
 524                         struct platform_device *pdev)
 525 {
 526         int ret;
 527
 528         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 529                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 530                 if (pp->msi_irq <= 0) {
 531                         dev_err(&pdev->dev, "failed to get MSI irq\n");
 532                         return -ENODEV;
 533                 }
 534
 535                 ret = devm_request_irq(&pdev->dev, pp->msi_irq,
 536                                        imx6_pcie_msi_handler,
 537                                        IRQF_SHARED, "mx6-pcie-msi", pp);
 538                 if (ret) {
 539                         dev_err(&pdev->dev, "failed to request MSI irq\n");
 540                         return -ENODEV;
 541                 }
 542         }
 543
 544         pp->root_bus_nr = -1;
 545         pp->ops = &imx6_pcie_host_ops;
 546
 547         ret = dw_pcie_host_init(pp);
 548         if (ret) {
 549                 dev_err(&pdev->dev, "failed to initialize host\n");
 550                 return ret;
 551         }
 552
 553         return 0;
 554 }
 555
 556 static int __init imx6_pcie_probe(struct platform_device *pdev)
 557 {
 558         struct imx6_pcie *imx6_pcie;
 559         struct pcie_port *pp;
 560         struct device_node *np = pdev->dev.of_node;
 561         struct resource *dbi_base;
 562         int ret;
 563
 564         imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL);
 565         if (!imx6_pcie)
 566                 return -ENOMEM;
 567
 568         pp = &imx6_pcie->pp;
 569         pp->dev = &pdev->dev;
 570
 571         /* Added for PCI abort handling */
 572         hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0,
 573                 "imprecise external abort");
 574
 575         dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 576         pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
 577         if (IS_ERR(pp->dbi_base))
 578                 return PTR_ERR(pp->dbi_base);
 579
 580         /* Fetch GPIOs */
 581         imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 582         if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 583                 ret = devm_gpio_request_one(&pdev->dev, imx6_pcie->reset_gpio,
 584                                             GPIOF_OUT_INIT_LOW, "PCIe reset");
 585                 if (ret) {
 586                         dev_err(&pdev->dev, "unable to get reset gpio\n");
 587                         return ret;
 588                 }
 589         }
 590
 591         /* Fetch clocks */
 592         imx6_pcie->pcie_phy = devm_clk_get(&pdev->dev, "pcie_phy");
 593         if (IS_ERR(imx6_pcie->pcie_phy)) {
 594                 dev_err(&pdev->dev,
 595                         "pcie_phy clock source missing or invalid\n");
 596                 return PTR_ERR(imx6_pcie->pcie_phy);
 597         }
 598
 599         imx6_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_bus");
 600         if (IS_ERR(imx6_pcie->pcie_bus)) {
 601                 dev_err(&pdev->dev,
 602                         "pcie_bus clock source missing or invalid\n");
 603                 return PTR_ERR(imx6_pcie->pcie_bus);
 604         }
 605
 606         imx6_pcie->pcie = devm_clk_get(&pdev->dev, "pcie");
 607         if (IS_ERR(imx6_pcie->pcie)) {
 608                 dev_err(&pdev->dev,
 609                         "pcie clock source missing or invalid\n");
 610                 return PTR_ERR(imx6_pcie->pcie);
 611         }
 612
 613         /* Grab GPR config register range */
 614         imx6_pcie->iomuxc_gpr =
 615                  syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
 616         if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
 617                 dev_err(&pdev->dev, "unable to find iomuxc registers\n");
 618                 return PTR_ERR(imx6_pcie->iomuxc_gpr);
 619         }
 620
 621         ret = imx6_add_pcie_port(pp, pdev);
 622         if (ret < 0)
 623                 return ret;
 624
 625         platform_set_drvdata(pdev, imx6_pcie);
 626         return 0;
 627 }
 628
 629 static void imx6_pcie_shutdown(struct platform_device *pdev)
 630 {
 631         struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
 632
 633         /* bring down link, so bootloader gets clean state in case of reboot */
 634         imx6_pcie_assert_core_reset(&imx6_pcie->pp);
 635 }
 636
 637 static const struct of_device_id imx6_pcie_of_match[] = {
 638         { .compatible = "fsl,imx6q-pcie", },
 639         {},
 640 };
 641 MODULE_DEVICE_TABLE(of, imx6_pcie_of_match);
 642
 643 static struct platform_driver imx6_pcie_driver = {
 644         .driver = {
 645                 .name   = "imx6q-pcie",
 646                 .of_match_table = imx6_pcie_of_match,
 647         },
 648         .shutdown = imx6_pcie_shutdown,
 649 };
 650
 651 /* Freescale PCIe driver does not allow module unload */
 652
 653 static int __init imx6_pcie_init(void)
 654 {
 655         return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
 656 }
 657 module_init(imx6_pcie_init);
 658
 659 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
 660 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
 661 MODULE_LICENSE("GPL v2");