2 * PCIe host controller driver for Freescale i.MX6 SoCs
4 * Copyright (C) 2013 Kosagi
5 * http://www.kosagi.com
7 * Author: Sean Cross <xobs@kosagi.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/gpio.h>
17 #include <linux/kernel.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <linux/module.h>
21 #include <linux/of_gpio.h>
22 #include <linux/pci.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
30 #include "pcie-designware.h"
32 #define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp)
40 struct regmap
*iomuxc_gpr
;
41 void __iomem
*mem_base
;
44 /* PCIe Root Complex registers (memory-mapped) */
45 #define PCIE_RC_LCR 0x7c
46 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
47 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
48 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
50 #define PCIE_RC_LCSR 0x80
52 /* PCIe Port Logic registers (memory-mapped) */
53 #define PL_OFFSET 0x700
54 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
55 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
56 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
57 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
58 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
59 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29)
60 #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4)
62 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
63 #define PCIE_PHY_CTRL_DATA_LOC 0
64 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
65 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
66 #define PCIE_PHY_CTRL_WR_LOC 18
67 #define PCIE_PHY_CTRL_RD_LOC 19
69 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
70 #define PCIE_PHY_STAT_ACK_LOC 16
72 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
73 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
75 /* PHY registers (not memory-mapped) */
76 #define PCIE_PHY_RX_ASIC_OUT 0x100D
78 #define PHY_RX_OVRD_IN_LO 0x1005
79 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
80 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
82 static int pcie_phy_poll_ack(void __iomem
*dbi_base
, int exp_val
)
85 u32 max_iterations
= 10;
89 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
90 val
= (val
>> PCIE_PHY_STAT_ACK_LOC
) & 0x1;
97 } while (wait_counter
< max_iterations
);
102 static int pcie_phy_wait_ack(void __iomem
*dbi_base
, int addr
)
107 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
108 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
110 val
|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC
);
111 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
113 ret
= pcie_phy_poll_ack(dbi_base
, 1);
117 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
118 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
120 return pcie_phy_poll_ack(dbi_base
, 0);
123 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
124 static int pcie_phy_read(void __iomem
*dbi_base
, int addr
, int *data
)
129 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
133 /* assert Read signal */
134 phy_ctl
= 0x1 << PCIE_PHY_CTRL_RD_LOC
;
135 writel(phy_ctl
, dbi_base
+ PCIE_PHY_CTRL
);
137 ret
= pcie_phy_poll_ack(dbi_base
, 1);
141 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
142 *data
= val
& 0xffff;
144 /* deassert Read signal */
145 writel(0x00, dbi_base
+ PCIE_PHY_CTRL
);
147 return pcie_phy_poll_ack(dbi_base
, 0);
150 static int pcie_phy_write(void __iomem
*dbi_base
, int addr
, int data
)
157 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
161 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
162 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
165 var
|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC
);
166 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
168 ret
= pcie_phy_poll_ack(dbi_base
, 1);
172 /* deassert cap data */
173 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
174 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
176 /* wait for ack de-assertion */
177 ret
= pcie_phy_poll_ack(dbi_base
, 0);
181 /* assert wr signal */
182 var
= 0x1 << PCIE_PHY_CTRL_WR_LOC
;
183 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
186 ret
= pcie_phy_poll_ack(dbi_base
, 1);
190 /* deassert wr signal */
191 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
192 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
194 /* wait for ack de-assertion */
195 ret
= pcie_phy_poll_ack(dbi_base
, 0);
199 writel(0x0, dbi_base
+ PCIE_PHY_CTRL
);
204 /* Added for PCI abort handling */
205 static int imx6q_pcie_abort_handler(unsigned long addr
,
206 unsigned int fsr
, struct pt_regs
*regs
)
211 static int imx6_pcie_assert_core_reset(struct pcie_port
*pp
)
213 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
214 u32 val
, gpr1
, gpr12
;
217 * If the bootloader already enabled the link we need some special
218 * handling to get the core back into a state where it is safe to
219 * touch it for configuration. As there is no dedicated reset signal
220 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
221 * state before completely disabling LTSSM, which is a prerequisite
222 * for core configuration.
224 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
225 * indication that the bootloader activated the link.
227 regmap_read(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
, &gpr1
);
228 regmap_read(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
, &gpr12
);
230 if ((gpr1
& IMX6Q_GPR1_PCIE_REF_CLK_EN
) &&
231 (gpr12
& IMX6Q_GPR12_PCIE_CTL_2
)) {
232 val
= readl(pp
->dbi_base
+ PCIE_PL_PFLR
);
233 val
&= ~PCIE_PL_PFLR_LINK_STATE_MASK
;
234 val
|= PCIE_PL_PFLR_FORCE_LINK
;
235 writel(val
, pp
->dbi_base
+ PCIE_PL_PFLR
);
237 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
238 IMX6Q_GPR12_PCIE_CTL_2
, 0 << 10);
241 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
242 IMX6Q_GPR1_PCIE_TEST_PD
, 1 << 18);
243 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
244 IMX6Q_GPR1_PCIE_REF_CLK_EN
, 0 << 16);
249 static int imx6_pcie_deassert_core_reset(struct pcie_port
*pp
)
251 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
254 ret
= clk_prepare_enable(imx6_pcie
->pcie_phy
);
256 dev_err(pp
->dev
, "unable to enable pcie_phy clock\n");
260 ret
= clk_prepare_enable(imx6_pcie
->pcie_bus
);
262 dev_err(pp
->dev
, "unable to enable pcie_bus clock\n");
266 ret
= clk_prepare_enable(imx6_pcie
->pcie
);
268 dev_err(pp
->dev
, "unable to enable pcie clock\n");
272 /* power up core phy and enable ref clock */
273 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
274 IMX6Q_GPR1_PCIE_TEST_PD
, 0 << 18);
276 * the async reset input need ref clock to sync internally,
277 * when the ref clock comes after reset, internal synced
278 * reset time is too short, cannot meet the requirement.
279 * add one ~10us delay here.
282 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR1
,
283 IMX6Q_GPR1_PCIE_REF_CLK_EN
, 1 << 16);
285 /* allow the clocks to stabilize */
286 usleep_range(200, 500);
288 /* Some boards don't have PCIe reset GPIO. */
289 if (gpio_is_valid(imx6_pcie
->reset_gpio
)) {
290 gpio_set_value(imx6_pcie
->reset_gpio
, 0);
292 gpio_set_value(imx6_pcie
->reset_gpio
, 1);
297 clk_disable_unprepare(imx6_pcie
->pcie_bus
);
299 clk_disable_unprepare(imx6_pcie
->pcie_phy
);
305 static void imx6_pcie_init_phy(struct pcie_port
*pp
)
307 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
309 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
310 IMX6Q_GPR12_PCIE_CTL_2
, 0 << 10);
312 /* configure constant input signal to the pcie ctrl and phy */
313 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
314 IMX6Q_GPR12_DEVICE_TYPE
, PCI_EXP_TYPE_ROOT_PORT
<< 12);
315 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
316 IMX6Q_GPR12_LOS_LEVEL
, 9 << 4);
318 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
319 IMX6Q_GPR8_TX_DEEMPH_GEN1
, 0 << 0);
320 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
321 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB
, 0 << 6);
322 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
323 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB
, 20 << 12);
324 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
325 IMX6Q_GPR8_TX_SWING_FULL
, 127 << 18);
326 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR8
,
327 IMX6Q_GPR8_TX_SWING_LOW
, 127 << 25);
330 static int imx6_pcie_wait_for_link(struct pcie_port
*pp
)
332 unsigned int retries
;
334 for (retries
= 0; retries
< 200; retries
++) {
335 if (dw_pcie_link_up(pp
))
337 usleep_range(100, 1000);
340 dev_err(pp
->dev
, "phy link never came up\n");
341 dev_dbg(pp
->dev
, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
342 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R0
),
343 readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
));
347 static int imx6_pcie_wait_for_speed_change(struct pcie_port
*pp
)
350 unsigned int retries
;
352 for (retries
= 0; retries
< 200; retries
++) {
353 tmp
= readl(pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
354 /* Test if the speed change finished. */
355 if (!(tmp
& PORT_LOGIC_SPEED_CHANGE
))
357 usleep_range(100, 1000);
360 dev_err(pp
->dev
, "Speed change timeout\n");
364 static irqreturn_t
imx6_pcie_msi_handler(int irq
, void *arg
)
366 struct pcie_port
*pp
= arg
;
368 return dw_handle_msi_irq(pp
);
371 static int imx6_pcie_establish_link(struct pcie_port
*pp
)
373 struct imx6_pcie
*imx6_pcie
= to_imx6_pcie(pp
);
378 * Force Gen1 operation when starting the link. In case the link is
379 * started in Gen2 mode, there is a possibility the devices on the
380 * bus will not be detected at all. This happens with PCIe switches.
382 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCR
);
383 tmp
&= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
;
384 tmp
|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1
;
385 writel(tmp
, pp
->dbi_base
+ PCIE_RC_LCR
);
388 regmap_update_bits(imx6_pcie
->iomuxc_gpr
, IOMUXC_GPR12
,
389 IMX6Q_GPR12_PCIE_CTL_2
, 1 << 10);
391 ret
= imx6_pcie_wait_for_link(pp
);
395 /* Allow Gen2 mode after the link is up. */
396 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCR
);
397 tmp
&= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK
;
398 tmp
|= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2
;
399 writel(tmp
, pp
->dbi_base
+ PCIE_RC_LCR
);
402 * Start Directed Speed Change so the best possible speed both link
403 * partners support can be negotiated.
405 tmp
= readl(pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
406 tmp
|= PORT_LOGIC_SPEED_CHANGE
;
407 writel(tmp
, pp
->dbi_base
+ PCIE_LINK_WIDTH_SPEED_CONTROL
);
409 ret
= imx6_pcie_wait_for_speed_change(pp
);
411 dev_err(pp
->dev
, "Failed to bring link up!\n");
415 /* Make sure link training is finished as well! */
416 ret
= imx6_pcie_wait_for_link(pp
);
418 dev_err(pp
->dev
, "Failed to bring link up!\n");
422 tmp
= readl(pp
->dbi_base
+ PCIE_RC_LCSR
);
423 dev_dbg(pp
->dev
, "Link up, Gen=%i\n", (tmp
>> 16) & 0xf);
427 static void imx6_pcie_host_init(struct pcie_port
*pp
)
429 imx6_pcie_assert_core_reset(pp
);
431 imx6_pcie_init_phy(pp
);
433 imx6_pcie_deassert_core_reset(pp
);
435 dw_pcie_setup_rc(pp
);
437 imx6_pcie_establish_link(pp
);
439 if (IS_ENABLED(CONFIG_PCI_MSI
))
440 dw_pcie_msi_init(pp
);
443 static void imx6_pcie_reset_phy(struct pcie_port
*pp
)
447 pcie_phy_read(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, &tmp
);
448 tmp
|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
449 PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
450 pcie_phy_write(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, tmp
);
452 usleep_range(2000, 3000);
454 pcie_phy_read(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, &tmp
);
455 tmp
&= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
|
456 PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
457 pcie_phy_write(pp
->dbi_base
, PHY_RX_OVRD_IN_LO
, tmp
);
460 static int imx6_pcie_link_up(struct pcie_port
*pp
)
462 u32 rc
, debug_r0
, rx_valid
;
466 * Test if the PHY reports that the link is up and also that the LTSSM
467 * training finished. There are three possible states of the link when
468 * this code is called:
469 * 1) The link is DOWN (unlikely)
470 * The link didn't come up yet for some reason. This usually means
471 * we have a real problem somewhere. Reset the PHY and exit. This
472 * state calls for inspection of the DEBUG registers.
473 * 2) The link is UP, but still in LTSSM training
474 * Wait for the training to finish, which should take a very short
475 * time. If the training does not finish, we have a problem and we
476 * need to inspect the DEBUG registers. If the training does finish,
477 * the link is up and operating correctly.
478 * 3) The link is UP and no longer in LTSSM training
479 * The link is up and operating correctly.
482 rc
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R1
);
483 if (!(rc
& PCIE_PHY_DEBUG_R1_XMLH_LINK_UP
))
485 if (!(rc
& PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING
))
489 dev_dbg(pp
->dev
, "Link is up, but still in training\n");
491 * Wait a little bit, then re-check if the link finished
494 usleep_range(1000, 2000);
497 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
498 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
499 * If (MAC/LTSSM.state == Recovery.RcvrLock)
500 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
503 pcie_phy_read(pp
->dbi_base
, PCIE_PHY_RX_ASIC_OUT
, &rx_valid
);
504 debug_r0
= readl(pp
->dbi_base
+ PCIE_PHY_DEBUG_R0
);
509 if ((debug_r0
& 0x3f) != 0x0d)
512 dev_err(pp
->dev
, "transition to gen2 is stuck, reset PHY!\n");
513 dev_dbg(pp
->dev
, "debug_r0=%08x debug_r1=%08x\n", debug_r0
, rc
);
515 imx6_pcie_reset_phy(pp
);
520 static struct pcie_host_ops imx6_pcie_host_ops
= {
521 .link_up
= imx6_pcie_link_up
,
522 .host_init
= imx6_pcie_host_init
,
525 static int __init
imx6_add_pcie_port(struct pcie_port
*pp
,
526 struct platform_device
*pdev
)
530 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
531 pp
->msi_irq
= platform_get_irq_byname(pdev
, "msi");
532 if (pp
->msi_irq
<= 0) {
533 dev_err(&pdev
->dev
, "failed to get MSI irq\n");
537 ret
= devm_request_irq(&pdev
->dev
, pp
->msi_irq
,
538 imx6_pcie_msi_handler
,
539 IRQF_SHARED
, "mx6-pcie-msi", pp
);
541 dev_err(&pdev
->dev
, "failed to request MSI irq\n");
546 pp
->root_bus_nr
= -1;
547 pp
->ops
= &imx6_pcie_host_ops
;
549 ret
= dw_pcie_host_init(pp
);
551 dev_err(&pdev
->dev
, "failed to initialize host\n");
558 static int __init
imx6_pcie_probe(struct platform_device
*pdev
)
560 struct imx6_pcie
*imx6_pcie
;
561 struct pcie_port
*pp
;
562 struct device_node
*np
= pdev
->dev
.of_node
;
563 struct resource
*dbi_base
;
566 imx6_pcie
= devm_kzalloc(&pdev
->dev
, sizeof(*imx6_pcie
), GFP_KERNEL
);
571 pp
->dev
= &pdev
->dev
;
573 /* Added for PCI abort handling */
574 hook_fault_code(16 + 6, imx6q_pcie_abort_handler
, SIGBUS
, 0,
575 "imprecise external abort");
577 dbi_base
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
578 pp
->dbi_base
= devm_ioremap_resource(&pdev
->dev
, dbi_base
);
579 if (IS_ERR(pp
->dbi_base
))
580 return PTR_ERR(pp
->dbi_base
);
583 imx6_pcie
->reset_gpio
= of_get_named_gpio(np
, "reset-gpio", 0);
584 if (gpio_is_valid(imx6_pcie
->reset_gpio
)) {
585 ret
= devm_gpio_request_one(&pdev
->dev
, imx6_pcie
->reset_gpio
,
586 GPIOF_OUT_INIT_LOW
, "PCIe reset");
588 dev_err(&pdev
->dev
, "unable to get reset gpio\n");
594 imx6_pcie
->pcie_phy
= devm_clk_get(&pdev
->dev
, "pcie_phy");
595 if (IS_ERR(imx6_pcie
->pcie_phy
)) {
597 "pcie_phy clock source missing or invalid\n");
598 return PTR_ERR(imx6_pcie
->pcie_phy
);
601 imx6_pcie
->pcie_bus
= devm_clk_get(&pdev
->dev
, "pcie_bus");
602 if (IS_ERR(imx6_pcie
->pcie_bus
)) {
604 "pcie_bus clock source missing or invalid\n");
605 return PTR_ERR(imx6_pcie
->pcie_bus
);
608 imx6_pcie
->pcie
= devm_clk_get(&pdev
->dev
, "pcie");
609 if (IS_ERR(imx6_pcie
->pcie
)) {
611 "pcie clock source missing or invalid\n");
612 return PTR_ERR(imx6_pcie
->pcie
);
615 /* Grab GPR config register range */
616 imx6_pcie
->iomuxc_gpr
=
617 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
618 if (IS_ERR(imx6_pcie
->iomuxc_gpr
)) {
619 dev_err(&pdev
->dev
, "unable to find iomuxc registers\n");
620 return PTR_ERR(imx6_pcie
->iomuxc_gpr
);
623 ret
= imx6_add_pcie_port(pp
, pdev
);
627 platform_set_drvdata(pdev
, imx6_pcie
);
631 static void imx6_pcie_shutdown(struct platform_device
*pdev
)
633 struct imx6_pcie
*imx6_pcie
= platform_get_drvdata(pdev
);
635 /* bring down link, so bootloader gets clean state in case of reboot */
636 imx6_pcie_assert_core_reset(&imx6_pcie
->pp
);
639 static const struct of_device_id imx6_pcie_of_match
[] = {
640 { .compatible
= "fsl,imx6q-pcie", },
643 MODULE_DEVICE_TABLE(of
, imx6_pcie_of_match
);
645 static struct platform_driver imx6_pcie_driver
= {
647 .name
= "imx6q-pcie",
648 .of_match_table
= imx6_pcie_of_match
,
650 .shutdown
= imx6_pcie_shutdown
,
653 /* Freescale PCIe driver does not allow module unload */
655 static int __init
imx6_pcie_init(void)
657 return platform_driver_probe(&imx6_pcie_driver
, imx6_pcie_probe
);
659 module_init(imx6_pcie_init
);
661 MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
662 MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
663 MODULE_LICENSE("GPL v2");