drivers/pci/host/pci-layerscape.c

   1 /*
   2  * PCIe host controller driver for Freescale Layerscape SoCs
   3  *
   4  * Copyright (C) 2014 Freescale Semiconductor.
   5  *
   6  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/module.h>
  16 #include <linux/of_pci.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/pci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/resource.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include "pcie-designware.h"
  27
  28 /* PEX1/2 Misc Ports Status Register */
  29 #define SCFG_PEXMSCPORTSR(pex_idx)      (0x94 + (pex_idx) * 4)
  30 #define LTSSM_STATE_SHIFT       20
  31 #define LTSSM_STATE_MASK        0x3f
  32 #define LTSSM_PCIE_L0           0x11 /* L0 state */
  33
  34 /* PEX Internal Configuration Registers */
  35 #define PCIE_STRFMR1            0x71c /* Symbol Timer & Filter Mask Register1 */
  36 #define PCIE_DBI_RO_WR_EN       0x8bc /* DBI Read-Only Write Enable Register */
  37
  38 /* PEX LUT registers */
  39 #define PCIE_LUT_DBG            0x7FC /* PEX LUT Debug Register */
  40
  41 struct ls_pcie_drvdata {
  42         u32 lut_offset;
  43         u32 ltssm_shift;
  44         struct pcie_host_ops *ops;
  45 };
  46
  47 struct ls_pcie {
  48         void __iomem *dbi;
  49         void __iomem *lut;
  50         struct regmap *scfg;
  51         struct pcie_port pp;
  52         const struct ls_pcie_drvdata *drvdata;
  53         int index;
  54 };
  55
  56 #define to_ls_pcie(x)   container_of(x, struct ls_pcie, pp)
  57
  58 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
  59 {
  60         u32 header_type;
  61
  62         header_type = ioread8(pcie->dbi + PCI_HEADER_TYPE);
  63         header_type &= 0x7f;
  64
  65         return header_type == PCI_HEADER_TYPE_BRIDGE;
  66 }
  67
  68 /* Clear multi-function bit */
  69 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
  70 {
  71         iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE);
  72 }
  73
  74 /* Fix class value */
  75 static void ls_pcie_fix_class(struct ls_pcie *pcie)
  76 {
  77         iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE);
  78 }
  79
  80 /* Drop MSG TLP except for Vendor MSG */
  81 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
  82 {
  83         u32 val;
  84
  85         val = ioread32(pcie->dbi + PCIE_STRFMR1);
  86         val &= 0xDFFFFFFF;
  87         iowrite32(val, pcie->dbi + PCIE_STRFMR1);
  88 }
  89
  90 static int ls1021_pcie_link_up(struct pcie_port *pp)
  91 {
  92         u32 state;
  93         struct ls_pcie *pcie = to_ls_pcie(pp);
  94
  95         if (!pcie->scfg)
  96                 return 0;
  97
  98         regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
  99         state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
 100
 101         if (state < LTSSM_PCIE_L0)
 102                 return 0;
 103
 104         return 1;
 105 }
 106
 107 static void ls1021_pcie_host_init(struct pcie_port *pp)
 108 {
 109         struct ls_pcie *pcie = to_ls_pcie(pp);
 110         u32 index[2];
 111
 112         pcie->scfg = syscon_regmap_lookup_by_phandle(pp->dev->of_node,
 113                                                      "fsl,pcie-scfg");
 114         if (IS_ERR(pcie->scfg)) {
 115                 dev_err(pp->dev, "No syscfg phandle specified\n");
 116                 pcie->scfg = NULL;
 117                 return;
 118         }
 119
 120         if (of_property_read_u32_array(pp->dev->of_node,
 121                                        "fsl,pcie-scfg", index, 2)) {
 122                 pcie->scfg = NULL;
 123                 return;
 124         }
 125         pcie->index = index[1];
 126
 127         dw_pcie_setup_rc(pp);
 128
 129         ls_pcie_drop_msg_tlp(pcie);
 130 }
 131
 132 static int ls_pcie_link_up(struct pcie_port *pp)
 133 {
 134         struct ls_pcie *pcie = to_ls_pcie(pp);
 135         u32 state;
 136
 137         state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
 138                  pcie->drvdata->ltssm_shift) &
 139                  LTSSM_STATE_MASK;
 140
 141         if (state < LTSSM_PCIE_L0)
 142                 return 0;
 143
 144         return 1;
 145 }
 146
 147 static void ls_pcie_host_init(struct pcie_port *pp)
 148 {
 149         struct ls_pcie *pcie = to_ls_pcie(pp);
 150
 151         iowrite32(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
 152         ls_pcie_fix_class(pcie);
 153         ls_pcie_clear_multifunction(pcie);
 154         ls_pcie_drop_msg_tlp(pcie);
 155         iowrite32(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
 156 }
 157
 158 static int ls_pcie_msi_host_init(struct pcie_port *pp,
 159                                  struct msi_controller *chip)
 160 {
 161         struct device_node *msi_node;
 162         struct device_node *np = pp->dev->of_node;
 163
 164         /*
 165          * The MSI domain is set by the generic of_msi_configure().  This
 166          * .msi_host_init() function keeps us from doing the default MSI
 167          * domain setup in dw_pcie_host_init() and also enforces the
 168          * requirement that "msi-parent" exists.
 169          */
 170         msi_node = of_parse_phandle(np, "msi-parent", 0);
 171         if (!msi_node) {
 172                 dev_err(pp->dev, "failed to find msi-parent\n");
 173                 return -EINVAL;
 174         }
 175
 176         return 0;
 177 }
 178
 179 static struct pcie_host_ops ls1021_pcie_host_ops = {
 180         .link_up = ls1021_pcie_link_up,
 181         .host_init = ls1021_pcie_host_init,
 182         .msi_host_init = ls_pcie_msi_host_init,
 183 };
 184
 185 static struct pcie_host_ops ls_pcie_host_ops = {
 186         .link_up = ls_pcie_link_up,
 187         .host_init = ls_pcie_host_init,
 188         .msi_host_init = ls_pcie_msi_host_init,
 189 };
 190
 191 static struct ls_pcie_drvdata ls1021_drvdata = {
 192         .ops = &ls1021_pcie_host_ops,
 193 };
 194
 195 static struct ls_pcie_drvdata ls1043_drvdata = {
 196         .lut_offset = 0x10000,
 197         .ltssm_shift = 24,
 198         .ops = &ls_pcie_host_ops,
 199 };
 200
 201 static struct ls_pcie_drvdata ls2080_drvdata = {
 202         .lut_offset = 0x80000,
 203         .ltssm_shift = 0,
 204         .ops = &ls_pcie_host_ops,
 205 };
 206
 207 static const struct of_device_id ls_pcie_of_match[] = {
 208         { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
 209         { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
 210         { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
 211         { },
 212 };
 213 MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
 214
 215 static int __init ls_add_pcie_port(struct pcie_port *pp,
 216                                    struct platform_device *pdev)
 217 {
 218         int ret;
 219         struct ls_pcie *pcie = to_ls_pcie(pp);
 220
 221         pp->dev = &pdev->dev;
 222         pp->dbi_base = pcie->dbi;
 223         pp->ops = pcie->drvdata->ops;
 224
 225         ret = dw_pcie_host_init(pp);
 226         if (ret) {
 227                 dev_err(pp->dev, "failed to initialize host\n");
 228                 return ret;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int __init ls_pcie_probe(struct platform_device *pdev)
 235 {
 236         const struct of_device_id *match;
 237         struct ls_pcie *pcie;
 238         struct resource *dbi_base;
 239         int ret;
 240
 241         match = of_match_device(ls_pcie_of_match, &pdev->dev);
 242         if (!match)
 243                 return -ENODEV;
 244
 245         pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
 246         if (!pcie)
 247                 return -ENOMEM;
 248
 249         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 250         pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
 251         if (IS_ERR(pcie->dbi)) {
 252                 dev_err(&pdev->dev, "missing *regs* space\n");
 253                 return PTR_ERR(pcie->dbi);
 254         }
 255
 256         pcie->drvdata = match->data;
 257         pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
 258
 259         if (!ls_pcie_is_bridge(pcie))
 260                 return -ENODEV;
 261
 262         ret = ls_add_pcie_port(&pcie->pp, pdev);
 263         if (ret < 0)
 264                 return ret;
 265
 266         platform_set_drvdata(pdev, pcie);
 267
 268         return 0;
 269 }
 270
 271 static struct platform_driver ls_pcie_driver = {
 272         .driver = {
 273                 .name = "layerscape-pcie",
 274                 .of_match_table = ls_pcie_of_match,
 275         },
 276 };
 277
 278 module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
 279
 280 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
 281 MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
 282 MODULE_LICENSE("GPL v2");