2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
26 * PCIe unit register offsets.
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
63 /* PCI configuration space of a PCI-to-PCI bridge */
64 struct mvebu_sw_pci_bridge
{
79 u8 secondary_latency_timer
;
96 struct mvebu_pcie_port
;
98 /* Structure representing all PCIe interfaces */
100 struct platform_device
*pdev
;
101 struct mvebu_pcie_port
*ports
;
102 struct msi_controller
*msi
;
104 struct resource realio
;
106 struct resource busn
;
110 /* Structure representing one PCIe interface */
111 struct mvebu_pcie_port
{
117 unsigned int mem_target
;
118 unsigned int mem_attr
;
119 unsigned int io_target
;
120 unsigned int io_attr
;
123 int reset_active_low
;
125 struct mvebu_sw_pci_bridge bridge
;
126 struct device_node
*dn
;
127 struct mvebu_pcie
*pcie
;
128 phys_addr_t memwin_base
;
130 phys_addr_t iowin_base
;
135 static inline void mvebu_writel(struct mvebu_pcie_port
*port
, u32 val
, u32 reg
)
137 writel(val
, port
->base
+ reg
);
140 static inline u32
mvebu_readl(struct mvebu_pcie_port
*port
, u32 reg
)
142 return readl(port
->base
+ reg
);
145 static inline bool mvebu_has_ioport(struct mvebu_pcie_port
*port
)
147 return port
->io_target
!= -1 && port
->io_attr
!= -1;
150 static bool mvebu_pcie_link_up(struct mvebu_pcie_port
*port
)
152 return !(mvebu_readl(port
, PCIE_STAT_OFF
) & PCIE_STAT_LINK_DOWN
);
155 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port
*port
, int nr
)
159 stat
= mvebu_readl(port
, PCIE_STAT_OFF
);
160 stat
&= ~PCIE_STAT_BUS
;
162 mvebu_writel(port
, stat
, PCIE_STAT_OFF
);
165 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port
*port
, int nr
)
169 stat
= mvebu_readl(port
, PCIE_STAT_OFF
);
170 stat
&= ~PCIE_STAT_DEV
;
172 mvebu_writel(port
, stat
, PCIE_STAT_OFF
);
176 * Setup PCIE BARs and Address Decode Wins:
177 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
178 * WIN[0-3] -> DRAM bank[0-3]
180 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port
*port
)
182 const struct mbus_dram_target_info
*dram
;
186 dram
= mv_mbus_dram_info();
188 /* First, disable and clear BARs and windows. */
189 for (i
= 1; i
< 3; i
++) {
190 mvebu_writel(port
, 0, PCIE_BAR_CTRL_OFF(i
));
191 mvebu_writel(port
, 0, PCIE_BAR_LO_OFF(i
));
192 mvebu_writel(port
, 0, PCIE_BAR_HI_OFF(i
));
195 for (i
= 0; i
< 5; i
++) {
196 mvebu_writel(port
, 0, PCIE_WIN04_CTRL_OFF(i
));
197 mvebu_writel(port
, 0, PCIE_WIN04_BASE_OFF(i
));
198 mvebu_writel(port
, 0, PCIE_WIN04_REMAP_OFF(i
));
201 mvebu_writel(port
, 0, PCIE_WIN5_CTRL_OFF
);
202 mvebu_writel(port
, 0, PCIE_WIN5_BASE_OFF
);
203 mvebu_writel(port
, 0, PCIE_WIN5_REMAP_OFF
);
205 /* Setup windows for DDR banks. Count total DDR size on the fly. */
207 for (i
= 0; i
< dram
->num_cs
; i
++) {
208 const struct mbus_dram_window
*cs
= dram
->cs
+ i
;
210 mvebu_writel(port
, cs
->base
& 0xffff0000,
211 PCIE_WIN04_BASE_OFF(i
));
212 mvebu_writel(port
, 0, PCIE_WIN04_REMAP_OFF(i
));
214 ((cs
->size
- 1) & 0xffff0000) |
215 (cs
->mbus_attr
<< 8) |
216 (dram
->mbus_dram_target_id
<< 4) | 1,
217 PCIE_WIN04_CTRL_OFF(i
));
222 /* Round up 'size' to the nearest power of two. */
223 if ((size
& (size
- 1)) != 0)
224 size
= 1 << fls(size
);
226 /* Setup BAR[1] to all DRAM banks. */
227 mvebu_writel(port
, dram
->cs
[0].base
, PCIE_BAR_LO_OFF(1));
228 mvebu_writel(port
, 0, PCIE_BAR_HI_OFF(1));
229 mvebu_writel(port
, ((size
- 1) & 0xffff0000) | 1,
230 PCIE_BAR_CTRL_OFF(1));
233 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port
*port
)
237 /* Point PCIe unit MBUS decode windows to DRAM space. */
238 mvebu_pcie_setup_wins(port
);
240 /* Master + slave enable. */
241 cmd
= mvebu_readl(port
, PCIE_CMD_OFF
);
242 cmd
|= PCI_COMMAND_IO
;
243 cmd
|= PCI_COMMAND_MEMORY
;
244 cmd
|= PCI_COMMAND_MASTER
;
245 mvebu_writel(port
, cmd
, PCIE_CMD_OFF
);
247 /* Enable interrupt lines A-D. */
248 mask
= mvebu_readl(port
, PCIE_MASK_OFF
);
249 mask
|= PCIE_MASK_ENABLE_INTS
;
250 mvebu_writel(port
, mask
, PCIE_MASK_OFF
);
253 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port
*port
,
255 u32 devfn
, int where
, int size
, u32
*val
)
257 mvebu_writel(port
, PCIE_CONF_ADDR(bus
->number
, devfn
, where
),
260 *val
= mvebu_readl(port
, PCIE_CONF_DATA_OFF
);
263 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
265 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
267 return PCIBIOS_SUCCESSFUL
;
270 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port
*port
,
272 u32 devfn
, int where
, int size
, u32 val
)
274 u32 _val
, shift
= 8 * (where
& 3);
276 mvebu_writel(port
, PCIE_CONF_ADDR(bus
->number
, devfn
, where
),
278 _val
= mvebu_readl(port
, PCIE_CONF_DATA_OFF
);
283 _val
= (_val
& ~(0xffff << shift
)) | ((val
& 0xffff) << shift
);
285 _val
= (_val
& ~(0xff << shift
)) | ((val
& 0xff) << shift
);
287 return PCIBIOS_BAD_REGISTER_NUMBER
;
289 mvebu_writel(port
, _val
, PCIE_CONF_DATA_OFF
);
291 return PCIBIOS_SUCCESSFUL
;
295 * Remove windows, starting from the largest ones to the smallest
298 static void mvebu_pcie_del_windows(struct mvebu_pcie_port
*port
,
299 phys_addr_t base
, size_t size
)
302 size_t sz
= 1 << (fls(size
) - 1);
304 mvebu_mbus_del_window(base
, sz
);
311 * MBus windows can only have a power of two size, but PCI BARs do not
312 * have this constraint. Therefore, we have to split the PCI BAR into
313 * areas each having a power of two size. We start from the largest
314 * one (i.e highest order bit set in the size).
316 static void mvebu_pcie_add_windows(struct mvebu_pcie_port
*port
,
317 unsigned int target
, unsigned int attribute
,
318 phys_addr_t base
, size_t size
,
321 size_t size_mapped
= 0;
324 size_t sz
= 1 << (fls(size
) - 1);
327 ret
= mvebu_mbus_add_window_remap_by_id(target
, attribute
, base
,
330 phys_addr_t end
= base
+ sz
- 1;
332 dev_err(&port
->pcie
->pdev
->dev
,
333 "Could not create MBus window at [mem %pa-%pa]: %d\n",
335 mvebu_pcie_del_windows(port
, base
- size_mapped
,
343 if (remap
!= MVEBU_MBUS_NO_REMAP
)
348 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port
*port
)
352 /* Are the new iobase/iolimit values invalid? */
353 if (port
->bridge
.iolimit
< port
->bridge
.iobase
||
354 port
->bridge
.iolimitupper
< port
->bridge
.iobaseupper
||
355 !(port
->bridge
.command
& PCI_COMMAND_IO
)) {
357 /* If a window was configured, remove it */
358 if (port
->iowin_base
) {
359 mvebu_pcie_del_windows(port
, port
->iowin_base
,
361 port
->iowin_base
= 0;
362 port
->iowin_size
= 0;
368 if (!mvebu_has_ioport(port
)) {
369 dev_WARN(&port
->pcie
->pdev
->dev
,
370 "Attempt to set IO when IO is disabled\n");
375 * We read the PCI-to-PCI bridge emulated registers, and
376 * calculate the base address and size of the address decoding
377 * window to setup, according to the PCI-to-PCI bridge
378 * specifications. iobase is the bus address, port->iowin_base
379 * is the CPU address.
381 iobase
= ((port
->bridge
.iobase
& 0xF0) << 8) |
382 (port
->bridge
.iobaseupper
<< 16);
383 port
->iowin_base
= port
->pcie
->io
.start
+ iobase
;
384 port
->iowin_size
= ((0xFFF | ((port
->bridge
.iolimit
& 0xF0) << 8) |
385 (port
->bridge
.iolimitupper
<< 16)) -
388 mvebu_pcie_add_windows(port
, port
->io_target
, port
->io_attr
,
389 port
->iowin_base
, port
->iowin_size
,
393 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port
*port
)
395 /* Are the new membase/memlimit values invalid? */
396 if (port
->bridge
.memlimit
< port
->bridge
.membase
||
397 !(port
->bridge
.command
& PCI_COMMAND_MEMORY
)) {
399 /* If a window was configured, remove it */
400 if (port
->memwin_base
) {
401 mvebu_pcie_del_windows(port
, port
->memwin_base
,
403 port
->memwin_base
= 0;
404 port
->memwin_size
= 0;
411 * We read the PCI-to-PCI bridge emulated registers, and
412 * calculate the base address and size of the address decoding
413 * window to setup, according to the PCI-to-PCI bridge
416 port
->memwin_base
= ((port
->bridge
.membase
& 0xFFF0) << 16);
418 (((port
->bridge
.memlimit
& 0xFFF0) << 16) | 0xFFFFF) -
419 port
->memwin_base
+ 1;
421 mvebu_pcie_add_windows(port
, port
->mem_target
, port
->mem_attr
,
422 port
->memwin_base
, port
->memwin_size
,
423 MVEBU_MBUS_NO_REMAP
);
427 * Initialize the configuration space of the PCI-to-PCI bridge
428 * associated with the given PCIe interface.
430 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port
*port
)
432 struct mvebu_sw_pci_bridge
*bridge
= &port
->bridge
;
434 memset(bridge
, 0, sizeof(struct mvebu_sw_pci_bridge
));
436 bridge
->class = PCI_CLASS_BRIDGE_PCI
;
437 bridge
->vendor
= PCI_VENDOR_ID_MARVELL
;
438 bridge
->device
= mvebu_readl(port
, PCIE_DEV_ID_OFF
) >> 16;
439 bridge
->revision
= mvebu_readl(port
, PCIE_DEV_REV_OFF
) & 0xff;
440 bridge
->header_type
= PCI_HEADER_TYPE_BRIDGE
;
441 bridge
->cache_line_size
= 0x10;
443 /* We support 32 bits I/O addressing */
444 bridge
->iobase
= PCI_IO_RANGE_TYPE_32
;
445 bridge
->iolimit
= PCI_IO_RANGE_TYPE_32
;
449 * Read the configuration space of the PCI-to-PCI bridge associated to
450 * the given PCIe interface.
452 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port
*port
,
453 unsigned int where
, int size
, u32
*value
)
455 struct mvebu_sw_pci_bridge
*bridge
= &port
->bridge
;
457 switch (where
& ~3) {
459 *value
= bridge
->device
<< 16 | bridge
->vendor
;
463 *value
= bridge
->command
;
466 case PCI_CLASS_REVISION
:
467 *value
= bridge
->class << 16 | bridge
->interface
<< 8 |
471 case PCI_CACHE_LINE_SIZE
:
472 *value
= bridge
->bist
<< 24 | bridge
->header_type
<< 16 |
473 bridge
->latency_timer
<< 8 | bridge
->cache_line_size
;
476 case PCI_BASE_ADDRESS_0
... PCI_BASE_ADDRESS_1
:
477 *value
= bridge
->bar
[((where
& ~3) - PCI_BASE_ADDRESS_0
) / 4];
480 case PCI_PRIMARY_BUS
:
481 *value
= (bridge
->secondary_latency_timer
<< 24 |
482 bridge
->subordinate_bus
<< 16 |
483 bridge
->secondary_bus
<< 8 |
484 bridge
->primary_bus
);
488 if (!mvebu_has_ioport(port
))
489 *value
= bridge
->secondary_status
<< 16;
491 *value
= (bridge
->secondary_status
<< 16 |
492 bridge
->iolimit
<< 8 |
496 case PCI_MEMORY_BASE
:
497 *value
= (bridge
->memlimit
<< 16 | bridge
->membase
);
500 case PCI_PREF_MEMORY_BASE
:
504 case PCI_IO_BASE_UPPER16
:
505 *value
= (bridge
->iolimitupper
<< 16 | bridge
->iobaseupper
);
508 case PCI_ROM_ADDRESS1
:
512 case PCI_INTERRUPT_LINE
:
513 /* LINE PIN MIN_GNT MAX_LAT */
519 return PCIBIOS_BAD_REGISTER_NUMBER
;
523 *value
= (*value
>> (8 * (where
& 3))) & 0xffff;
525 *value
= (*value
>> (8 * (where
& 3))) & 0xff;
527 return PCIBIOS_SUCCESSFUL
;
530 /* Write to the PCI-to-PCI bridge configuration space */
531 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port
*port
,
532 unsigned int where
, int size
, u32 value
)
534 struct mvebu_sw_pci_bridge
*bridge
= &port
->bridge
;
541 mask
= ~(0xffff << ((where
& 3) * 8));
543 mask
= ~(0xff << ((where
& 3) * 8));
545 return PCIBIOS_BAD_REGISTER_NUMBER
;
547 err
= mvebu_sw_pci_bridge_read(port
, where
& ~3, 4, ®
);
551 value
= (reg
& mask
) | value
<< ((where
& 3) * 8);
553 switch (where
& ~3) {
556 u32 old
= bridge
->command
;
558 if (!mvebu_has_ioport(port
))
559 value
&= ~PCI_COMMAND_IO
;
561 bridge
->command
= value
& 0xffff;
562 if ((old
^ bridge
->command
) & PCI_COMMAND_IO
)
563 mvebu_pcie_handle_iobase_change(port
);
564 if ((old
^ bridge
->command
) & PCI_COMMAND_MEMORY
)
565 mvebu_pcie_handle_membase_change(port
);
569 case PCI_BASE_ADDRESS_0
... PCI_BASE_ADDRESS_1
:
570 bridge
->bar
[((where
& ~3) - PCI_BASE_ADDRESS_0
) / 4] = value
;
575 * We also keep bit 1 set, it is a read-only bit that
576 * indicates we support 32 bits addressing for the
579 bridge
->iobase
= (value
& 0xff) | PCI_IO_RANGE_TYPE_32
;
580 bridge
->iolimit
= ((value
>> 8) & 0xff) | PCI_IO_RANGE_TYPE_32
;
581 mvebu_pcie_handle_iobase_change(port
);
584 case PCI_MEMORY_BASE
:
585 bridge
->membase
= value
& 0xffff;
586 bridge
->memlimit
= value
>> 16;
587 mvebu_pcie_handle_membase_change(port
);
590 case PCI_IO_BASE_UPPER16
:
591 bridge
->iobaseupper
= value
& 0xffff;
592 bridge
->iolimitupper
= value
>> 16;
593 mvebu_pcie_handle_iobase_change(port
);
596 case PCI_PRIMARY_BUS
:
597 bridge
->primary_bus
= value
& 0xff;
598 bridge
->secondary_bus
= (value
>> 8) & 0xff;
599 bridge
->subordinate_bus
= (value
>> 16) & 0xff;
600 bridge
->secondary_latency_timer
= (value
>> 24) & 0xff;
601 mvebu_pcie_set_local_bus_nr(port
, bridge
->secondary_bus
);
608 return PCIBIOS_SUCCESSFUL
;
611 static inline struct mvebu_pcie
*sys_to_pcie(struct pci_sys_data
*sys
)
613 return sys
->private_data
;
616 static struct mvebu_pcie_port
*mvebu_pcie_find_port(struct mvebu_pcie
*pcie
,
622 for (i
= 0; i
< pcie
->nports
; i
++) {
623 struct mvebu_pcie_port
*port
= &pcie
->ports
[i
];
625 if (bus
->number
== 0 && port
->devfn
== devfn
)
627 if (bus
->number
!= 0 &&
628 bus
->number
>= port
->bridge
.secondary_bus
&&
629 bus
->number
<= port
->bridge
.subordinate_bus
)
636 /* PCI configuration space write function */
637 static int mvebu_pcie_wr_conf(struct pci_bus
*bus
, u32 devfn
,
638 int where
, int size
, u32 val
)
640 struct mvebu_pcie
*pcie
= sys_to_pcie(bus
->sysdata
);
641 struct mvebu_pcie_port
*port
;
644 port
= mvebu_pcie_find_port(pcie
, bus
, devfn
);
646 return PCIBIOS_DEVICE_NOT_FOUND
;
648 /* Access the emulated PCI-to-PCI bridge */
649 if (bus
->number
== 0)
650 return mvebu_sw_pci_bridge_write(port
, where
, size
, val
);
652 if (!mvebu_pcie_link_up(port
))
653 return PCIBIOS_DEVICE_NOT_FOUND
;
656 * On the secondary bus, we don't want to expose any other
657 * device than the device physically connected in the PCIe
658 * slot, visible in slot 0. In slot 1, there's a special
659 * Marvell device that only makes sense when the Armada is
660 * used as a PCIe endpoint.
662 if (bus
->number
== port
->bridge
.secondary_bus
&&
663 PCI_SLOT(devfn
) != 0)
664 return PCIBIOS_DEVICE_NOT_FOUND
;
666 /* Access the real PCIe interface */
667 ret
= mvebu_pcie_hw_wr_conf(port
, bus
, devfn
,
673 /* PCI configuration space read function */
674 static int mvebu_pcie_rd_conf(struct pci_bus
*bus
, u32 devfn
, int where
,
677 struct mvebu_pcie
*pcie
= sys_to_pcie(bus
->sysdata
);
678 struct mvebu_pcie_port
*port
;
681 port
= mvebu_pcie_find_port(pcie
, bus
, devfn
);
684 return PCIBIOS_DEVICE_NOT_FOUND
;
687 /* Access the emulated PCI-to-PCI bridge */
688 if (bus
->number
== 0)
689 return mvebu_sw_pci_bridge_read(port
, where
, size
, val
);
691 if (!mvebu_pcie_link_up(port
)) {
693 return PCIBIOS_DEVICE_NOT_FOUND
;
697 * On the secondary bus, we don't want to expose any other
698 * device than the device physically connected in the PCIe
699 * slot, visible in slot 0. In slot 1, there's a special
700 * Marvell device that only makes sense when the Armada is
701 * used as a PCIe endpoint.
703 if (bus
->number
== port
->bridge
.secondary_bus
&&
704 PCI_SLOT(devfn
) != 0) {
706 return PCIBIOS_DEVICE_NOT_FOUND
;
709 /* Access the real PCIe interface */
710 ret
= mvebu_pcie_hw_rd_conf(port
, bus
, devfn
,
716 static struct pci_ops mvebu_pcie_ops
= {
717 .read
= mvebu_pcie_rd_conf
,
718 .write
= mvebu_pcie_wr_conf
,
721 static int mvebu_pcie_setup(int nr
, struct pci_sys_data
*sys
)
723 struct mvebu_pcie
*pcie
= sys_to_pcie(sys
);
726 pcie
->mem
.name
= "PCI MEM";
727 pcie
->realio
.name
= "PCI I/O";
729 if (request_resource(&iomem_resource
, &pcie
->mem
))
732 if (resource_size(&pcie
->realio
) != 0) {
733 if (request_resource(&ioport_resource
, &pcie
->realio
)) {
734 release_resource(&pcie
->mem
);
737 pci_add_resource_offset(&sys
->resources
, &pcie
->realio
,
740 pci_add_resource_offset(&sys
->resources
, &pcie
->mem
, sys
->mem_offset
);
741 pci_add_resource(&sys
->resources
, &pcie
->busn
);
743 for (i
= 0; i
< pcie
->nports
; i
++) {
744 struct mvebu_pcie_port
*port
= &pcie
->ports
[i
];
748 mvebu_pcie_setup_hw(port
);
754 static resource_size_t
mvebu_pcie_align_resource(struct pci_dev
*dev
,
755 const struct resource
*res
,
756 resource_size_t start
,
757 resource_size_t size
,
758 resource_size_t align
)
760 if (dev
->bus
->number
!= 0)
764 * On the PCI-to-PCI bridge side, the I/O windows must have at
765 * least a 64 KB size and the memory windows must have at
766 * least a 1 MB size. Moreover, MBus windows need to have a
767 * base address aligned on their size, and their size must be
768 * a power of two. This means that if the BAR doesn't have a
769 * power of two size, several MBus windows will actually be
770 * created. We need to ensure that the biggest MBus window
771 * (which will be the first one) is aligned on its size, which
772 * explains the rounddown_pow_of_two() being done here.
774 if (res
->flags
& IORESOURCE_IO
)
775 return round_up(start
, max_t(resource_size_t
, SZ_64K
,
776 rounddown_pow_of_two(size
)));
777 else if (res
->flags
& IORESOURCE_MEM
)
778 return round_up(start
, max_t(resource_size_t
, SZ_1M
,
779 rounddown_pow_of_two(size
)));
784 static void mvebu_pcie_enable(struct mvebu_pcie
*pcie
)
788 memset(&hw
, 0, sizeof(hw
));
790 #ifdef CONFIG_PCI_MSI
791 hw
.msi_ctrl
= pcie
->msi
;
794 hw
.nr_controllers
= 1;
795 hw
.private_data
= (void **)&pcie
;
796 hw
.setup
= mvebu_pcie_setup
;
797 hw
.map_irq
= of_irq_parse_and_map_pci
;
798 hw
.ops
= &mvebu_pcie_ops
;
799 hw
.align_resource
= mvebu_pcie_align_resource
;
801 pci_common_init_dev(&pcie
->pdev
->dev
, &hw
);
805 * Looks up the list of register addresses encoded into the reg =
806 * <...> property for one that matches the given port/lane. Once
809 static void __iomem
*mvebu_pcie_map_registers(struct platform_device
*pdev
,
810 struct device_node
*np
,
811 struct mvebu_pcie_port
*port
)
813 struct resource regs
;
816 ret
= of_address_to_resource(np
, 0, ®s
);
820 return devm_ioremap_resource(&pdev
->dev
, ®s
);
823 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
824 #define DT_TYPE_IO 0x1
825 #define DT_TYPE_MEM32 0x2
826 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
827 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
829 static int mvebu_get_tgt_attr(struct device_node
*np
, int devfn
,
834 const int na
= 3, ns
= 2;
836 int rlen
, nranges
, rangesz
, pna
, i
;
841 range
= of_get_property(np
, "ranges", &rlen
);
845 pna
= of_n_addr_cells(np
);
846 rangesz
= pna
+ na
+ ns
;
847 nranges
= rlen
/ sizeof(__be32
) / rangesz
;
849 for (i
= 0; i
< nranges
; i
++, range
+= rangesz
) {
850 u32 flags
= of_read_number(range
, 1);
851 u32 slot
= of_read_number(range
+ 1, 1);
852 u64 cpuaddr
= of_read_number(range
+ na
, pna
);
855 if (DT_FLAGS_TO_TYPE(flags
) == DT_TYPE_IO
)
856 rtype
= IORESOURCE_IO
;
857 else if (DT_FLAGS_TO_TYPE(flags
) == DT_TYPE_MEM32
)
858 rtype
= IORESOURCE_MEM
;
862 if (slot
== PCI_SLOT(devfn
) && type
== rtype
) {
863 *tgt
= DT_CPUADDR_TO_TARGET(cpuaddr
);
864 *attr
= DT_CPUADDR_TO_ATTR(cpuaddr
);
872 static void mvebu_pcie_msi_enable(struct mvebu_pcie
*pcie
)
874 struct device_node
*msi_node
;
876 msi_node
= of_parse_phandle(pcie
->pdev
->dev
.of_node
,
881 pcie
->msi
= of_pci_find_msi_chip_by_node(msi_node
);
882 of_node_put(msi_node
);
885 pcie
->msi
->dev
= &pcie
->pdev
->dev
;
888 static int mvebu_pcie_suspend(struct device
*dev
)
890 struct mvebu_pcie
*pcie
;
893 pcie
= dev_get_drvdata(dev
);
894 for (i
= 0; i
< pcie
->nports
; i
++) {
895 struct mvebu_pcie_port
*port
= pcie
->ports
+ i
;
896 port
->saved_pcie_stat
= mvebu_readl(port
, PCIE_STAT_OFF
);
902 static int mvebu_pcie_resume(struct device
*dev
)
904 struct mvebu_pcie
*pcie
;
907 pcie
= dev_get_drvdata(dev
);
908 for (i
= 0; i
< pcie
->nports
; i
++) {
909 struct mvebu_pcie_port
*port
= pcie
->ports
+ i
;
910 mvebu_writel(port
, port
->saved_pcie_stat
, PCIE_STAT_OFF
);
911 mvebu_pcie_setup_hw(port
);
917 static int mvebu_pcie_probe(struct platform_device
*pdev
)
919 struct mvebu_pcie
*pcie
;
920 struct device_node
*np
= pdev
->dev
.of_node
;
921 struct device_node
*child
;
924 pcie
= devm_kzalloc(&pdev
->dev
, sizeof(struct mvebu_pcie
),
930 platform_set_drvdata(pdev
, pcie
);
932 /* Get the PCIe memory and I/O aperture */
933 mvebu_mbus_get_pcie_mem_aperture(&pcie
->mem
);
934 if (resource_size(&pcie
->mem
) == 0) {
935 dev_err(&pdev
->dev
, "invalid memory aperture size\n");
939 mvebu_mbus_get_pcie_io_aperture(&pcie
->io
);
941 if (resource_size(&pcie
->io
) != 0) {
942 pcie
->realio
.flags
= pcie
->io
.flags
;
943 pcie
->realio
.start
= PCIBIOS_MIN_IO
;
944 pcie
->realio
.end
= min_t(resource_size_t
,
946 resource_size(&pcie
->io
));
948 pcie
->realio
= pcie
->io
;
950 /* Get the bus range */
951 ret
= of_pci_parse_bus_range(np
, &pcie
->busn
);
953 dev_err(&pdev
->dev
, "failed to parse bus-range property: %d\n",
959 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
960 if (!of_device_is_available(child
))
965 pcie
->ports
= devm_kzalloc(&pdev
->dev
, i
*
966 sizeof(struct mvebu_pcie_port
),
972 for_each_child_of_node(pdev
->dev
.of_node
, child
) {
973 struct mvebu_pcie_port
*port
= &pcie
->ports
[i
];
974 enum of_gpio_flags flags
;
976 if (!of_device_is_available(child
))
981 if (of_property_read_u32(child
, "marvell,pcie-port",
984 "ignoring PCIe DT node, missing pcie-port property\n");
988 if (of_property_read_u32(child
, "marvell,pcie-lane",
992 port
->name
= kasprintf(GFP_KERNEL
, "pcie%d.%d",
993 port
->port
, port
->lane
);
995 port
->devfn
= of_pci_get_devfn(child
);
999 ret
= mvebu_get_tgt_attr(np
, port
->devfn
, IORESOURCE_MEM
,
1000 &port
->mem_target
, &port
->mem_attr
);
1002 dev_err(&pdev
->dev
, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
1003 port
->port
, port
->lane
);
1007 if (resource_size(&pcie
->io
) != 0)
1008 mvebu_get_tgt_attr(np
, port
->devfn
, IORESOURCE_IO
,
1009 &port
->io_target
, &port
->io_attr
);
1011 port
->io_target
= -1;
1015 port
->reset_gpio
= of_get_named_gpio_flags(child
,
1016 "reset-gpios", 0, &flags
);
1017 if (gpio_is_valid(port
->reset_gpio
)) {
1018 u32 reset_udelay
= 20000;
1020 port
->reset_active_low
= flags
& OF_GPIO_ACTIVE_LOW
;
1021 port
->reset_name
= kasprintf(GFP_KERNEL
,
1022 "pcie%d.%d-reset", port
->port
, port
->lane
);
1023 of_property_read_u32(child
, "reset-delay-us",
1026 ret
= devm_gpio_request_one(&pdev
->dev
,
1027 port
->reset_gpio
, GPIOF_DIR_OUT
, port
->reset_name
);
1029 if (ret
== -EPROBE_DEFER
)
1034 gpio_set_value(port
->reset_gpio
,
1035 (port
->reset_active_low
) ? 1 : 0);
1036 msleep(reset_udelay
/1000);
1039 port
->clk
= of_clk_get_by_name(child
, NULL
);
1040 if (IS_ERR(port
->clk
)) {
1041 dev_err(&pdev
->dev
, "PCIe%d.%d: cannot get clock\n",
1042 port
->port
, port
->lane
);
1046 ret
= clk_prepare_enable(port
->clk
);
1050 port
->base
= mvebu_pcie_map_registers(pdev
, child
, port
);
1051 if (IS_ERR(port
->base
)) {
1052 dev_err(&pdev
->dev
, "PCIe%d.%d: cannot map registers\n",
1053 port
->port
, port
->lane
);
1055 clk_disable_unprepare(port
->clk
);
1059 mvebu_pcie_set_local_dev_nr(port
, 1);
1062 mvebu_sw_pci_bridge_init(port
);
1068 for (i
= 0; i
< (IO_SPACE_LIMIT
- SZ_64K
); i
+= SZ_64K
)
1069 pci_ioremap_io(i
, pcie
->io
.start
+ i
);
1071 mvebu_pcie_msi_enable(pcie
);
1072 mvebu_pcie_enable(pcie
);
1074 platform_set_drvdata(pdev
, pcie
);
1079 static const struct of_device_id mvebu_pcie_of_match_table
[] = {
1080 { .compatible
= "marvell,armada-xp-pcie", },
1081 { .compatible
= "marvell,armada-370-pcie", },
1082 { .compatible
= "marvell,dove-pcie", },
1083 { .compatible
= "marvell,kirkwood-pcie", },
1086 MODULE_DEVICE_TABLE(of
, mvebu_pcie_of_match_table
);
1088 static struct dev_pm_ops mvebu_pcie_pm_ops
= {
1089 .suspend_noirq
= mvebu_pcie_suspend
,
1090 .resume_noirq
= mvebu_pcie_resume
,
1093 static struct platform_driver mvebu_pcie_driver
= {
1095 .name
= "mvebu-pcie",
1096 .of_match_table
= mvebu_pcie_of_match_table
,
1097 /* driver unloading/unbinding currently not supported */
1098 .suppress_bind_attrs
= true,
1099 .pm
= &mvebu_pcie_pm_ops
,
1101 .probe
= mvebu_pcie_probe
,
1103 module_platform_driver(mvebu_pcie_driver
);
1105 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1106 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1107 MODULE_LICENSE("GPL v2");