drivers/pci/host/pcie-artpec6.c

   1 /*
   2  * PCIe host controller driver for Axis ARTPEC-6 SoC
   3  *
   4  * Author: Niklas Cassel <niklas.cassel@axis.com>
   5  *
   6  * Based on work done by Phil Edworthy <phil@edworthys.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/resource.h>
  19 #include <linux/signal.h>
  20 #include <linux/types.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/mfd/syscon.h>
  23 #include <linux/regmap.h>
  24
  25 #include "pcie-designware.h"
  26
  27 #define to_artpec6_pcie(x)      container_of(x, struct artpec6_pcie, pp)
  28
  29 struct artpec6_pcie {
  30         struct pcie_port        pp;
  31         struct regmap           *regmap;
  32         void __iomem            *phy_base;
  33 };
  34
  35 /* PCIe Port Logic registers (memory-mapped) */
  36 #define PL_OFFSET                       0x700
  37 #define PCIE_PHY_DEBUG_R0               (PL_OFFSET + 0x28)
  38 #define PCIE_PHY_DEBUG_R1               (PL_OFFSET + 0x2c)
  39
  40 #define MISC_CONTROL_1_OFF              (PL_OFFSET + 0x1bc)
  41 #define  DBI_RO_WR_EN                   1
  42
  43 /* ARTPEC-6 specific registers */
  44 #define PCIECFG                         0x18
  45 #define  PCIECFG_DBG_OEN                (1 << 24)
  46 #define  PCIECFG_CORE_RESET_REQ         (1 << 21)
  47 #define  PCIECFG_LTSSM_ENABLE           (1 << 20)
  48 #define  PCIECFG_CLKREQ_B               (1 << 11)
  49 #define  PCIECFG_REFCLK_ENABLE          (1 << 10)
  50 #define  PCIECFG_PLL_ENABLE             (1 << 9)
  51 #define  PCIECFG_PCLK_ENABLE            (1 << 8)
  52 #define  PCIECFG_RISRCREN               (1 << 4)
  53 #define  PCIECFG_MODE_TX_DRV_EN         (1 << 3)
  54 #define  PCIECFG_CISRREN                (1 << 2)
  55 #define  PCIECFG_MACRO_ENABLE           (1 << 0)
  56
  57 #define NOCCFG                          0x40
  58 #define NOCCFG_ENABLE_CLK_PCIE          (1 << 4)
  59 #define NOCCFG_POWER_PCIE_IDLEACK       (1 << 3)
  60 #define NOCCFG_POWER_PCIE_IDLE          (1 << 2)
  61 #define NOCCFG_POWER_PCIE_IDLEREQ       (1 << 1)
  62
  63 #define PHY_STATUS                      0x118
  64 #define PHY_COSPLLLOCK                  (1 << 0)
  65
  66 #define ARTPEC6_CPU_TO_BUS_ADDR         0x0fffffff
  67
  68 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
  69 {
  70         u32 val;
  71
  72         regmap_read(artpec6_pcie->regmap, offset, &val);
  73         return val;
  74 }
  75
  76 static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
  77 {
  78         regmap_write(artpec6_pcie->regmap, offset, val);
  79 }
  80
  81 static int artpec6_pcie_establish_link(struct pcie_port *pp)
  82 {
  83         struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp);
  84         u32 val;
  85         unsigned int retries;
  86
  87         /* Hold DW core in reset */
  88         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  89         val |= PCIECFG_CORE_RESET_REQ;
  90         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
  91
  92         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
  93         val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
  94                 PCIECFG_MODE_TX_DRV_EN |
  95                 PCIECFG_CISRREN |       /* Reference clock term. 100 Ohm */
  96                 PCIECFG_MACRO_ENABLE;
  97         val |= PCIECFG_REFCLK_ENABLE;
  98         val &= ~PCIECFG_DBG_OEN;
  99         val &= ~PCIECFG_CLKREQ_B;
 100         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 101         usleep_range(5000, 6000);
 102
 103         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 104         val |= NOCCFG_ENABLE_CLK_PCIE;
 105         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 106         usleep_range(20, 30);
 107
 108         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 109         val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
 110         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 111         usleep_range(6000, 7000);
 112
 113         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 114         val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
 115         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
 116
 117         retries = 50;
 118         do {
 119                 usleep_range(1000, 2000);
 120                 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
 121                 retries--;
 122         } while (retries &&
 123                 (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
 124
 125         retries = 50;
 126         do {
 127                 usleep_range(1000, 2000);
 128                 val = readl(artpec6_pcie->phy_base + PHY_STATUS);
 129                 retries--;
 130         } while (retries && !(val & PHY_COSPLLLOCK));
 131
 132         /* Take DW core out of reset */
 133         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 134         val &= ~PCIECFG_CORE_RESET_REQ;
 135         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 136         usleep_range(100, 200);
 137
 138         /*
 139          * Enable writing to config regs. This is required as the Synopsys
 140          * driver changes the class code. That register needs DBI write enable.
 141          */
 142         dw_pcie_writel_rc(pp, MISC_CONTROL_1_OFF, DBI_RO_WR_EN);
 143
 144         pp->io_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 145         pp->mem_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 146         pp->cfg0_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 147         pp->cfg1_base &= ARTPEC6_CPU_TO_BUS_ADDR;
 148
 149         /* setup root complex */
 150         dw_pcie_setup_rc(pp);
 151
 152         /* assert LTSSM enable */
 153         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
 154         val |= PCIECFG_LTSSM_ENABLE;
 155         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
 156
 157         /* check if the link is up or not */
 158         if (!dw_pcie_wait_for_link(pp))
 159                 return 0;
 160
 161         dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
 162                 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R0),
 163                 dw_pcie_readl_rc(pp, PCIE_PHY_DEBUG_R1));
 164
 165         return -ETIMEDOUT;
 166 }
 167
 168 static void artpec6_pcie_enable_interrupts(struct pcie_port *pp)
 169 {
 170         if (IS_ENABLED(CONFIG_PCI_MSI))
 171                 dw_pcie_msi_init(pp);
 172 }
 173
 174 static void artpec6_pcie_host_init(struct pcie_port *pp)
 175 {
 176         artpec6_pcie_establish_link(pp);
 177         artpec6_pcie_enable_interrupts(pp);
 178 }
 179
 180 static struct pcie_host_ops artpec6_pcie_host_ops = {
 181         .host_init = artpec6_pcie_host_init,
 182 };
 183
 184 static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
 185 {
 186         struct pcie_port *pp = arg;
 187
 188         return dw_handle_msi_irq(pp);
 189 }
 190
 191 static int artpec6_add_pcie_port(struct pcie_port *pp,
 192                                  struct platform_device *pdev)
 193 {
 194         struct device *dev = pp->dev;
 195         int ret;
 196
 197         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 198                 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 199                 if (pp->msi_irq <= 0) {
 200                         dev_err(dev, "failed to get MSI irq\n");
 201                         return -ENODEV;
 202                 }
 203
 204                 ret = devm_request_irq(dev, pp->msi_irq,
 205                                        artpec6_pcie_msi_handler,
 206                                        IRQF_SHARED | IRQF_NO_THREAD,
 207                                        "artpec6-pcie-msi", pp);
 208                 if (ret) {
 209                         dev_err(dev, "failed to request MSI irq\n");
 210                         return ret;
 211                 }
 212         }
 213
 214         pp->root_bus_nr = -1;
 215         pp->ops = &artpec6_pcie_host_ops;
 216
 217         ret = dw_pcie_host_init(pp);
 218         if (ret) {
 219                 dev_err(dev, "failed to initialize host\n");
 220                 return ret;
 221         }
 222
 223         return 0;
 224 }
 225
 226 static int artpec6_pcie_probe(struct platform_device *pdev)
 227 {
 228         struct device *dev = &pdev->dev;
 229         struct artpec6_pcie *artpec6_pcie;
 230         struct pcie_port *pp;
 231         struct resource *dbi_base;
 232         struct resource *phy_base;
 233         int ret;
 234
 235         artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
 236         if (!artpec6_pcie)
 237                 return -ENOMEM;
 238
 239         pp = &artpec6_pcie->pp;
 240         pp->dev = dev;
 241
 242         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
 243         pp->dbi_base = devm_ioremap_resource(dev, dbi_base);
 244         if (IS_ERR(pp->dbi_base))
 245                 return PTR_ERR(pp->dbi_base);
 246
 247         phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
 248         artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
 249         if (IS_ERR(artpec6_pcie->phy_base))
 250                 return PTR_ERR(artpec6_pcie->phy_base);
 251
 252         artpec6_pcie->regmap =
 253                 syscon_regmap_lookup_by_phandle(dev->of_node,
 254                                                 "axis,syscon-pcie");
 255         if (IS_ERR(artpec6_pcie->regmap))
 256                 return PTR_ERR(artpec6_pcie->regmap);
 257
 258         ret = artpec6_add_pcie_port(pp, pdev);
 259         if (ret < 0)
 260                 return ret;
 261
 262         return 0;
 263 }
 264
 265 static const struct of_device_id artpec6_pcie_of_match[] = {
 266         { .compatible = "axis,artpec6-pcie", },
 267         {},
 268 };
 269
 270 static struct platform_driver artpec6_pcie_driver = {
 271         .probe = artpec6_pcie_probe,
 272         .driver = {
 273                 .name   = "artpec6-pcie",
 274                 .of_match_table = artpec6_pcie_of_match,
 275         },
 276 };
 277 builtin_platform_driver(artpec6_pcie_driver);