drivers/pci/host/pcie-designware.c

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/irq.h>
  15 #include <linux/irqdomain.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/msi.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci.h>
  22 #include <linux/pci_regs.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/types.h>
  25
  26 #include "pcie-designware.h"
  27
  28 /* Synopsis specific PCIE configuration registers */
  29 #define PCIE_PORT_LINK_CONTROL          0x710
  30 #define PORT_LINK_MODE_MASK             (0x3f << 16)
  31 #define PORT_LINK_MODE_1_LANES          (0x1 << 16)
  32 #define PORT_LINK_MODE_2_LANES          (0x3 << 16)
  33 #define PORT_LINK_MODE_4_LANES          (0x7 << 16)
  34 #define PORT_LINK_MODE_8_LANES          (0xf << 16)
  35
  36 #define PCIE_LINK_WIDTH_SPEED_CONTROL   0x80C
  37 #define PORT_LOGIC_SPEED_CHANGE         (0x1 << 17)
  38 #define PORT_LOGIC_LINK_WIDTH_MASK      (0x1f << 8)
  39 #define PORT_LOGIC_LINK_WIDTH_1_LANES   (0x1 << 8)
  40 #define PORT_LOGIC_LINK_WIDTH_2_LANES   (0x2 << 8)
  41 #define PORT_LOGIC_LINK_WIDTH_4_LANES   (0x4 << 8)
  42 #define PORT_LOGIC_LINK_WIDTH_8_LANES   (0x8 << 8)
  43
  44 #define PCIE_MSI_ADDR_LO                0x820
  45 #define PCIE_MSI_ADDR_HI                0x824
  46 #define PCIE_MSI_INTR0_ENABLE           0x828
  47 #define PCIE_MSI_INTR0_MASK             0x82C
  48 #define PCIE_MSI_INTR0_STATUS           0x830
  49
  50 #define PCIE_ATU_VIEWPORT               0x900
  51 #define PCIE_ATU_REGION_INBOUND         (0x1 << 31)
  52 #define PCIE_ATU_REGION_OUTBOUND        (0x0 << 31)
  53 #define PCIE_ATU_REGION_INDEX1          (0x1 << 0)
  54 #define PCIE_ATU_REGION_INDEX0          (0x0 << 0)
  55 #define PCIE_ATU_CR1                    0x904
  56 #define PCIE_ATU_TYPE_MEM               (0x0 << 0)
  57 #define PCIE_ATU_TYPE_IO                (0x2 << 0)
  58 #define PCIE_ATU_TYPE_CFG0              (0x4 << 0)
  59 #define PCIE_ATU_TYPE_CFG1              (0x5 << 0)
  60 #define PCIE_ATU_CR2                    0x908
  61 #define PCIE_ATU_ENABLE                 (0x1 << 31)
  62 #define PCIE_ATU_BAR_MODE_ENABLE        (0x1 << 30)
  63 #define PCIE_ATU_LOWER_BASE             0x90C
  64 #define PCIE_ATU_UPPER_BASE             0x910
  65 #define PCIE_ATU_LIMIT                  0x914
  66 #define PCIE_ATU_LOWER_TARGET           0x918
  67 #define PCIE_ATU_BUS(x)                 (((x) & 0xff) << 24)
  68 #define PCIE_ATU_DEV(x)                 (((x) & 0x1f) << 19)
  69 #define PCIE_ATU_FUNC(x)                (((x) & 0x7) << 16)
  70 #define PCIE_ATU_UPPER_TARGET           0x91C
  71
  72 static struct pci_ops dw_pcie_ops;
  73
  74 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
  75 {
  76         if ((uintptr_t)addr & (size - 1)) {
  77                 *val = 0;
  78                 return PCIBIOS_BAD_REGISTER_NUMBER;
  79         }
  80
  81         if (size == 4)
  82                 *val = readl(addr);
  83         else if (size == 2)
  84                 *val = readw(addr);
  85         else if (size == 1)
  86                 *val = readb(addr);
  87         else {
  88                 *val = 0;
  89                 return PCIBIOS_BAD_REGISTER_NUMBER;
  90         }
  91
  92         return PCIBIOS_SUCCESSFUL;
  93 }
  94
  95 int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
  96 {
  97         if ((uintptr_t)addr & (size - 1))
  98                 return PCIBIOS_BAD_REGISTER_NUMBER;
  99
 100         if (size == 4)
 101                 writel(val, addr);
 102         else if (size == 2)
 103                 writew(val, addr);
 104         else if (size == 1)
 105                 writeb(val, addr);
 106         else
 107                 return PCIBIOS_BAD_REGISTER_NUMBER;
 108
 109         return PCIBIOS_SUCCESSFUL;
 110 }
 111
 112 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
 113 {
 114         if (pp->ops->readl_rc)
 115                 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
 116         else
 117                 *val = readl(pp->dbi_base + reg);
 118 }
 119
 120 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
 121 {
 122         if (pp->ops->writel_rc)
 123                 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
 124         else
 125                 writel(val, pp->dbi_base + reg);
 126 }
 127
 128 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 129                                u32 *val)
 130 {
 131         if (pp->ops->rd_own_conf)
 132                 return pp->ops->rd_own_conf(pp, where, size, val);
 133
 134         return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
 135 }
 136
 137 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 138                                u32 val)
 139 {
 140         if (pp->ops->wr_own_conf)
 141                 return pp->ops->wr_own_conf(pp, where, size, val);
 142
 143         return dw_pcie_cfg_write(pp->dbi_base + where, size, val);
 144 }
 145
 146 static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
 147                 int type, u64 cpu_addr, u64 pci_addr, u32 size)
 148 {
 149         u32 val;
 150
 151         dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index,
 152                           PCIE_ATU_VIEWPORT);
 153         dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE);
 154         dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE);
 155         dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1),
 156                           PCIE_ATU_LIMIT);
 157         dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET);
 158         dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET);
 159         dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1);
 160         dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
 161
 162         /*
 163          * Make sure ATU enable takes effect before any subsequent config
 164          * and I/O accesses.
 165          */
 166         dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val);
 167 }
 168
 169 static struct irq_chip dw_msi_irq_chip = {
 170         .name = "PCI-MSI",
 171         .irq_enable = pci_msi_unmask_irq,
 172         .irq_disable = pci_msi_mask_irq,
 173         .irq_mask = pci_msi_mask_irq,
 174         .irq_unmask = pci_msi_unmask_irq,
 175 };
 176
 177 /* MSI int handler */
 178 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 179 {
 180         unsigned long val;
 181         int i, pos, irq;
 182         irqreturn_t ret = IRQ_NONE;
 183
 184         for (i = 0; i < MAX_MSI_CTRLS; i++) {
 185                 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 186                                 (u32 *)&val);
 187                 if (val) {
 188                         ret = IRQ_HANDLED;
 189                         pos = 0;
 190                         while ((pos = find_next_bit(&val, 32, pos)) != 32) {
 191                                 irq = irq_find_mapping(pp->irq_domain,
 192                                                 i * 32 + pos);
 193                                 dw_pcie_wr_own_conf(pp,
 194                                                 PCIE_MSI_INTR0_STATUS + i * 12,
 195                                                 4, 1 << pos);
 196                                 generic_handle_irq(irq);
 197                                 pos++;
 198                         }
 199                 }
 200         }
 201
 202         return ret;
 203 }
 204
 205 void dw_pcie_msi_init(struct pcie_port *pp)
 206 {
 207         u64 msi_target;
 208
 209         pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
 210         msi_target = virt_to_phys((void *)pp->msi_data);
 211
 212         /* program the msi_data */
 213         dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
 214                             (u32)(msi_target & 0xffffffff));
 215         dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
 216                             (u32)(msi_target >> 32 & 0xffffffff));
 217 }
 218
 219 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 220 {
 221         unsigned int res, bit, val;
 222
 223         res = (irq / 32) * 12;
 224         bit = irq % 32;
 225         dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
 226         val &= ~(1 << bit);
 227         dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
 228 }
 229
 230 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
 231                             unsigned int nvec, unsigned int pos)
 232 {
 233         unsigned int i;
 234
 235         for (i = 0; i < nvec; i++) {
 236                 irq_set_msi_desc_off(irq_base, i, NULL);
 237                 /* Disable corresponding interrupt on MSI controller */
 238                 if (pp->ops->msi_clear_irq)
 239                         pp->ops->msi_clear_irq(pp, pos + i);
 240                 else
 241                         dw_pcie_msi_clear_irq(pp, pos + i);
 242         }
 243
 244         bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
 245 }
 246
 247 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 248 {
 249         unsigned int res, bit, val;
 250
 251         res = (irq / 32) * 12;
 252         bit = irq % 32;
 253         dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
 254         val |= 1 << bit;
 255         dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
 256 }
 257
 258 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
 259 {
 260         int irq, pos0, i;
 261         struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc);
 262
 263         pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
 264                                        order_base_2(no_irqs));
 265         if (pos0 < 0)
 266                 goto no_valid_irq;
 267
 268         irq = irq_find_mapping(pp->irq_domain, pos0);
 269         if (!irq)
 270                 goto no_valid_irq;
 271
 272         /*
 273          * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
 274          * descs so there is no need to allocate descs here. We can therefore
 275          * assume that if irq_find_mapping above returns non-zero, then the
 276          * descs are also successfully allocated.
 277          */
 278
 279         for (i = 0; i < no_irqs; i++) {
 280                 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
 281                         clear_irq_range(pp, irq, i, pos0);
 282                         goto no_valid_irq;
 283                 }
 284                 /*Enable corresponding interrupt in MSI interrupt controller */
 285                 if (pp->ops->msi_set_irq)
 286                         pp->ops->msi_set_irq(pp, pos0 + i);
 287                 else
 288                         dw_pcie_msi_set_irq(pp, pos0 + i);
 289         }
 290
 291         *pos = pos0;
 292         desc->nvec_used = no_irqs;
 293         desc->msi_attrib.multiple = order_base_2(no_irqs);
 294
 295         return irq;
 296
 297 no_valid_irq:
 298         *pos = pos0;
 299         return -ENOSPC;
 300 }
 301
 302 static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
 303 {
 304         struct msi_msg msg;
 305         u64 msi_target;
 306
 307         if (pp->ops->get_msi_addr)
 308                 msi_target = pp->ops->get_msi_addr(pp);
 309         else
 310                 msi_target = virt_to_phys((void *)pp->msi_data);
 311
 312         msg.address_lo = (u32)(msi_target & 0xffffffff);
 313         msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
 314
 315         if (pp->ops->get_msi_data)
 316                 msg.data = pp->ops->get_msi_data(pp, pos);
 317         else
 318                 msg.data = pos;
 319
 320         pci_write_msi_msg(irq, &msg);
 321 }
 322
 323 static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
 324                         struct msi_desc *desc)
 325 {
 326         int irq, pos;
 327         struct pcie_port *pp = pdev->bus->sysdata;
 328
 329         if (desc->msi_attrib.is_msix)
 330                 return -EINVAL;
 331
 332         irq = assign_irq(1, desc, &pos);
 333         if (irq < 0)
 334                 return irq;
 335
 336         dw_msi_setup_msg(pp, irq, pos);
 337
 338         return 0;
 339 }
 340
 341 static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
 342                              int nvec, int type)
 343 {
 344 #ifdef CONFIG_PCI_MSI
 345         int irq, pos;
 346         struct msi_desc *desc;
 347         struct pcie_port *pp = pdev->bus->sysdata;
 348
 349         /* MSI-X interrupts are not supported */
 350         if (type == PCI_CAP_ID_MSIX)
 351                 return -EINVAL;
 352
 353         WARN_ON(!list_is_singular(&pdev->dev.msi_list));
 354         desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
 355
 356         irq = assign_irq(nvec, desc, &pos);
 357         if (irq < 0)
 358                 return irq;
 359
 360         dw_msi_setup_msg(pp, irq, pos);
 361
 362         return 0;
 363 #else
 364         return -EINVAL;
 365 #endif
 366 }
 367
 368 static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
 369 {
 370         struct irq_data *data = irq_get_irq_data(irq);
 371         struct msi_desc *msi = irq_data_get_msi_desc(data);
 372         struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 373
 374         clear_irq_range(pp, irq, 1, data->hwirq);
 375 }
 376
 377 static struct msi_controller dw_pcie_msi_chip = {
 378         .setup_irq = dw_msi_setup_irq,
 379         .setup_irqs = dw_msi_setup_irqs,
 380         .teardown_irq = dw_msi_teardown_irq,
 381 };
 382
 383 int dw_pcie_link_up(struct pcie_port *pp)
 384 {
 385         if (pp->ops->link_up)
 386                 return pp->ops->link_up(pp);
 387
 388         return 0;
 389 }
 390
 391 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
 392                         irq_hw_number_t hwirq)
 393 {
 394         irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
 395         irq_set_chip_data(irq, domain->host_data);
 396
 397         return 0;
 398 }
 399
 400 static const struct irq_domain_ops msi_domain_ops = {
 401         .map = dw_pcie_msi_map,
 402 };
 403
 404 int dw_pcie_host_init(struct pcie_port *pp)
 405 {
 406         struct device_node *np = pp->dev->of_node;
 407         struct platform_device *pdev = to_platform_device(pp->dev);
 408         struct pci_bus *bus, *child;
 409         struct resource *cfg_res;
 410         u32 val;
 411         int i, ret;
 412         LIST_HEAD(res);
 413         struct resource_entry *win;
 414
 415         cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
 416         if (cfg_res) {
 417                 pp->cfg0_size = resource_size(cfg_res)/2;
 418                 pp->cfg1_size = resource_size(cfg_res)/2;
 419                 pp->cfg0_base = cfg_res->start;
 420                 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
 421         } else if (!pp->va_cfg0_base) {
 422                 dev_err(pp->dev, "missing *config* reg space\n");
 423         }
 424
 425         ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
 426         if (ret)
 427                 return ret;
 428
 429         /* Get the I/O and memory ranges from DT */
 430         resource_list_for_each_entry(win, &res) {
 431                 switch (resource_type(win->res)) {
 432                 case IORESOURCE_IO:
 433                         pp->io = win->res;
 434                         pp->io->name = "I/O";
 435                         pp->io_size = resource_size(pp->io);
 436                         pp->io_bus_addr = pp->io->start - win->offset;
 437                         ret = pci_remap_iospace(pp->io, pp->io_base);
 438                         if (ret) {
 439                                 dev_warn(pp->dev, "error %d: failed to map resource %pR\n",
 440                                          ret, pp->io);
 441                                 continue;
 442                         }
 443                         break;
 444                 case IORESOURCE_MEM:
 445                         pp->mem = win->res;
 446                         pp->mem->name = "MEM";
 447                         pp->mem_size = resource_size(pp->mem);
 448                         pp->mem_bus_addr = pp->mem->start - win->offset;
 449                         break;
 450                 case 0:
 451                         pp->cfg = win->res;
 452                         pp->cfg0_size = resource_size(pp->cfg)/2;
 453                         pp->cfg1_size = resource_size(pp->cfg)/2;
 454                         pp->cfg0_base = pp->cfg->start;
 455                         pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
 456                         break;
 457                 case IORESOURCE_BUS:
 458                         pp->busn = win->res;
 459                         break;
 460                 default:
 461                         continue;
 462                 }
 463         }
 464
 465         if (!pp->dbi_base) {
 466                 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
 467                                         resource_size(pp->cfg));
 468                 if (!pp->dbi_base) {
 469                         dev_err(pp->dev, "error with ioremap\n");
 470                         return -ENOMEM;
 471                 }
 472         }
 473
 474         pp->mem_base = pp->mem->start;
 475
 476         if (!pp->va_cfg0_base) {
 477                 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
 478                                                 pp->cfg0_size);
 479                 if (!pp->va_cfg0_base) {
 480                         dev_err(pp->dev, "error with ioremap in function\n");
 481                         return -ENOMEM;
 482                 }
 483         }
 484
 485         if (!pp->va_cfg1_base) {
 486                 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
 487                                                 pp->cfg1_size);
 488                 if (!pp->va_cfg1_base) {
 489                         dev_err(pp->dev, "error with ioremap\n");
 490                         return -ENOMEM;
 491                 }
 492         }
 493
 494         ret = of_property_read_u32(np, "num-lanes", &pp->lanes);
 495         if (ret)
 496                 pp->lanes = 0;
 497
 498         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 499                 if (!pp->ops->msi_host_init) {
 500                         pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
 501                                                 MAX_MSI_IRQS, &msi_domain_ops,
 502                                                 &dw_pcie_msi_chip);
 503                         if (!pp->irq_domain) {
 504                                 dev_err(pp->dev, "irq domain init failed\n");
 505                                 return -ENXIO;
 506                         }
 507
 508                         for (i = 0; i < MAX_MSI_IRQS; i++)
 509                                 irq_create_mapping(pp->irq_domain, i);
 510                 } else {
 511                         ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
 512                         if (ret < 0)
 513                                 return ret;
 514                 }
 515         }
 516
 517         if (pp->ops->host_init)
 518                 pp->ops->host_init(pp);
 519
 520         if (!pp->ops->rd_other_conf)
 521                 dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
 522                                           PCIE_ATU_TYPE_MEM, pp->mem_base,
 523                                           pp->mem_bus_addr, pp->mem_size);
 524
 525         dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 526
 527         /* program correct class for RC */
 528         dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
 529
 530         dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
 531         val |= PORT_LOGIC_SPEED_CHANGE;
 532         dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
 533
 534         pp->root_bus_nr = pp->busn->start;
 535         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 536                 bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr,
 537                                             &dw_pcie_ops, pp, &res,
 538                                             &dw_pcie_msi_chip);
 539                 dw_pcie_msi_chip.dev = pp->dev;
 540         } else
 541                 bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
 542                                         pp, &res);
 543         if (!bus)
 544                 return -ENOMEM;
 545
 546         if (pp->ops->scan_bus)
 547                 pp->ops->scan_bus(pp);
 548
 549 #ifdef CONFIG_ARM
 550         /* support old dtbs that incorrectly describe IRQs */
 551         pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
 552 #endif
 553
 554         if (!pci_has_flag(PCI_PROBE_ONLY)) {
 555                 pci_bus_size_bridges(bus);
 556                 pci_bus_assign_resources(bus);
 557
 558                 list_for_each_entry(child, &bus->children, node)
 559                         pcie_bus_configure_settings(child);
 560         }
 561
 562         pci_bus_add_devices(bus);
 563         return 0;
 564 }
 565
 566 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 567                 u32 devfn, int where, int size, u32 *val)
 568 {
 569         int ret, type;
 570         u32 busdev, cfg_size;
 571         u64 cpu_addr;
 572         void __iomem *va_cfg_base;
 573
 574         if (pp->ops->rd_other_conf)
 575                 return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
 576
 577         busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
 578                  PCIE_ATU_FUNC(PCI_FUNC(devfn));
 579
 580         if (bus->parent->number == pp->root_bus_nr) {
 581                 type = PCIE_ATU_TYPE_CFG0;
 582                 cpu_addr = pp->cfg0_base;
 583                 cfg_size = pp->cfg0_size;
 584                 va_cfg_base = pp->va_cfg0_base;
 585         } else {
 586                 type = PCIE_ATU_TYPE_CFG1;
 587                 cpu_addr = pp->cfg1_base;
 588                 cfg_size = pp->cfg1_size;
 589                 va_cfg_base = pp->va_cfg1_base;
 590         }
 591
 592         dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
 593                                   type, cpu_addr,
 594                                   busdev, cfg_size);
 595         ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
 596         dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
 597                                   PCIE_ATU_TYPE_IO, pp->io_base,
 598                                   pp->io_bus_addr, pp->io_size);
 599
 600         return ret;
 601 }
 602
 603 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 604                 u32 devfn, int where, int size, u32 val)
 605 {
 606         int ret, type;
 607         u32 busdev, cfg_size;
 608         u64 cpu_addr;
 609         void __iomem *va_cfg_base;
 610
 611         if (pp->ops->wr_other_conf)
 612                 return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
 613
 614         busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
 615                  PCIE_ATU_FUNC(PCI_FUNC(devfn));
 616
 617         if (bus->parent->number == pp->root_bus_nr) {
 618                 type = PCIE_ATU_TYPE_CFG0;
 619                 cpu_addr = pp->cfg0_base;
 620                 cfg_size = pp->cfg0_size;
 621                 va_cfg_base = pp->va_cfg0_base;
 622         } else {
 623                 type = PCIE_ATU_TYPE_CFG1;
 624                 cpu_addr = pp->cfg1_base;
 625                 cfg_size = pp->cfg1_size;
 626                 va_cfg_base = pp->va_cfg1_base;
 627         }
 628
 629         dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
 630                                   type, cpu_addr,
 631                                   busdev, cfg_size);
 632         ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
 633         dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
 634                                   PCIE_ATU_TYPE_IO, pp->io_base,
 635                                   pp->io_bus_addr, pp->io_size);
 636
 637         return ret;
 638 }
 639
 640 static int dw_pcie_valid_config(struct pcie_port *pp,
 641                                 struct pci_bus *bus, int dev)
 642 {
 643         /* If there is no link, then there is no device */
 644         if (bus->number != pp->root_bus_nr) {
 645                 if (!dw_pcie_link_up(pp))
 646                         return 0;
 647         }
 648
 649         /* access only one slot on each root port */
 650         if (bus->number == pp->root_bus_nr && dev > 0)
 651                 return 0;
 652
 653         /*
 654          * do not read more than one device on the bus directly attached
 655          * to RC's (Virtual Bridge's) DS side.
 656          */
 657         if (bus->primary == pp->root_bus_nr && dev > 0)
 658                 return 0;
 659
 660         return 1;
 661 }
 662
 663 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 664                         int size, u32 *val)
 665 {
 666         struct pcie_port *pp = bus->sysdata;
 667
 668         if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
 669                 *val = 0xffffffff;
 670                 return PCIBIOS_DEVICE_NOT_FOUND;
 671         }
 672
 673         if (bus->number == pp->root_bus_nr)
 674                 return dw_pcie_rd_own_conf(pp, where, size, val);
 675
 676         return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
 677 }
 678
 679 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 680                         int where, int size, u32 val)
 681 {
 682         struct pcie_port *pp = bus->sysdata;
 683
 684         if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
 685                 return PCIBIOS_DEVICE_NOT_FOUND;
 686
 687         if (bus->number == pp->root_bus_nr)
 688                 return dw_pcie_wr_own_conf(pp, where, size, val);
 689
 690         return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
 691 }
 692
 693 static struct pci_ops dw_pcie_ops = {
 694         .read = dw_pcie_rd_conf,
 695         .write = dw_pcie_wr_conf,
 696 };
 697
 698 void dw_pcie_setup_rc(struct pcie_port *pp)
 699 {
 700         u32 val;
 701         u32 membase;
 702         u32 memlimit;
 703
 704         /* set the number of lanes */
 705         dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
 706         val &= ~PORT_LINK_MODE_MASK;
 707         switch (pp->lanes) {
 708         case 1:
 709                 val |= PORT_LINK_MODE_1_LANES;
 710                 break;
 711         case 2:
 712                 val |= PORT_LINK_MODE_2_LANES;
 713                 break;
 714         case 4:
 715                 val |= PORT_LINK_MODE_4_LANES;
 716                 break;
 717         case 8:
 718                 val |= PORT_LINK_MODE_8_LANES;
 719                 break;
 720         default:
 721                 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes);
 722                 return;
 723         }
 724         dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
 725
 726         /* set link width speed control register */
 727         dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
 728         val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
 729         switch (pp->lanes) {
 730         case 1:
 731                 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
 732                 break;
 733         case 2:
 734                 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
 735                 break;
 736         case 4:
 737                 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
 738                 break;
 739         case 8:
 740                 val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
 741                 break;
 742         }
 743         dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
 744
 745         /* setup RC BARs */
 746         dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
 747         dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
 748
 749         /* setup interrupt pins */
 750         dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
 751         val &= 0xffff00ff;
 752         val |= 0x00000100;
 753         dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
 754
 755         /* setup bus numbers */
 756         dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
 757         val &= 0xff000000;
 758         val |= 0x00010100;
 759         dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
 760
 761         /* setup memory base, memory limit */
 762         membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
 763         memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
 764         val = memlimit | membase;
 765         dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
 766
 767         /* setup command register */
 768         dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
 769         val &= 0xffff0000;
 770         val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 771                 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
 772         dw_pcie_writel_rc(pp, val, PCI_COMMAND);
 773 }
 774
 775 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
 776 MODULE_DESCRIPTION("Designware PCIe host controller driver");
 777 MODULE_LICENSE("GPL v2");