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[mirror_ubuntu-bionic-kernel.git] / drivers / pci / host / pcie-designware.c
1 /*
2 * Synopsys Designware PCIe host controller driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Author: Jingoo Han <jg1.han@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/platform_device.h>
24 #include <linux/types.h>
25
26 #include "pcie-designware.h"
27
28 /* Synopsis specific PCIE configuration registers */
29 #define PCIE_PORT_LINK_CONTROL 0x710
30 #define PORT_LINK_MODE_MASK (0x3f << 16)
31 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
32 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
33 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34
35 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
36 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
37 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
38 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
40 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
41
42 #define PCIE_MSI_ADDR_LO 0x820
43 #define PCIE_MSI_ADDR_HI 0x824
44 #define PCIE_MSI_INTR0_ENABLE 0x828
45 #define PCIE_MSI_INTR0_MASK 0x82C
46 #define PCIE_MSI_INTR0_STATUS 0x830
47
48 #define PCIE_ATU_VIEWPORT 0x900
49 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
50 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
51 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
52 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
53 #define PCIE_ATU_CR1 0x904
54 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
55 #define PCIE_ATU_TYPE_IO (0x2 << 0)
56 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
57 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
58 #define PCIE_ATU_CR2 0x908
59 #define PCIE_ATU_ENABLE (0x1 << 31)
60 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
61 #define PCIE_ATU_LOWER_BASE 0x90C
62 #define PCIE_ATU_UPPER_BASE 0x910
63 #define PCIE_ATU_LIMIT 0x914
64 #define PCIE_ATU_LOWER_TARGET 0x918
65 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
66 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
67 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
68 #define PCIE_ATU_UPPER_TARGET 0x91C
69
70 static struct hw_pci dw_pci;
71
72 static unsigned long global_io_offset;
73
74 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75 {
76 BUG_ON(!sys->private_data);
77
78 return sys->private_data;
79 }
80
81 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
82 {
83 *val = readl(addr);
84
85 if (size == 1)
86 *val = (*val >> (8 * (where & 3))) & 0xff;
87 else if (size == 2)
88 *val = (*val >> (8 * (where & 3))) & 0xffff;
89 else if (size != 4)
90 return PCIBIOS_BAD_REGISTER_NUMBER;
91
92 return PCIBIOS_SUCCESSFUL;
93 }
94
95 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
96 {
97 if (size == 4)
98 writel(val, addr);
99 else if (size == 2)
100 writew(val, addr + (where & 2));
101 else if (size == 1)
102 writeb(val, addr + (where & 3));
103 else
104 return PCIBIOS_BAD_REGISTER_NUMBER;
105
106 return PCIBIOS_SUCCESSFUL;
107 }
108
109 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
110 {
111 if (pp->ops->readl_rc)
112 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
113 else
114 *val = readl(pp->dbi_base + reg);
115 }
116
117 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
118 {
119 if (pp->ops->writel_rc)
120 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
121 else
122 writel(val, pp->dbi_base + reg);
123 }
124
125 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
126 u32 *val)
127 {
128 int ret;
129
130 if (pp->ops->rd_own_conf)
131 ret = pp->ops->rd_own_conf(pp, where, size, val);
132 else
133 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
134 size, val);
135
136 return ret;
137 }
138
139 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
140 u32 val)
141 {
142 int ret;
143
144 if (pp->ops->wr_own_conf)
145 ret = pp->ops->wr_own_conf(pp, where, size, val);
146 else
147 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
148 size, val);
149
150 return ret;
151 }
152
153 static struct irq_chip dw_msi_irq_chip = {
154 .name = "PCI-MSI",
155 .irq_enable = unmask_msi_irq,
156 .irq_disable = mask_msi_irq,
157 .irq_mask = mask_msi_irq,
158 .irq_unmask = unmask_msi_irq,
159 };
160
161 /* MSI int handler */
162 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
163 {
164 unsigned long val;
165 int i, pos, irq;
166 irqreturn_t ret = IRQ_NONE;
167
168 for (i = 0; i < MAX_MSI_CTRLS; i++) {
169 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
170 (u32 *)&val);
171 if (val) {
172 ret = IRQ_HANDLED;
173 pos = 0;
174 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
175 irq = irq_find_mapping(pp->irq_domain,
176 i * 32 + pos);
177 dw_pcie_wr_own_conf(pp,
178 PCIE_MSI_INTR0_STATUS + i * 12,
179 4, 1 << pos);
180 generic_handle_irq(irq);
181 pos++;
182 }
183 }
184 }
185
186 return ret;
187 }
188
189 void dw_pcie_msi_init(struct pcie_port *pp)
190 {
191 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
192
193 /* program the msi_data */
194 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
195 virt_to_phys((void *)pp->msi_data));
196 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
197 }
198
199 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
200 {
201 int flag = 1;
202
203 do {
204 pos = find_next_zero_bit(pp->msi_irq_in_use,
205 MAX_MSI_IRQS, pos);
206 /*if you have reached to the end then get out from here.*/
207 if (pos == MAX_MSI_IRQS)
208 return -ENOSPC;
209 /*
210 * Check if this position is at correct offset.nvec is always a
211 * power of two. pos0 must be nvec bit aligned.
212 */
213 if (pos % msgvec)
214 pos += msgvec - (pos % msgvec);
215 else
216 flag = 0;
217 } while (flag);
218
219 *pos0 = pos;
220 return 0;
221 }
222
223 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
224 {
225 unsigned int res, bit, val;
226
227 res = (irq / 32) * 12;
228 bit = irq % 32;
229 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
230 val &= ~(1 << bit);
231 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
232 }
233
234 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
235 unsigned int nvec, unsigned int pos)
236 {
237 unsigned int i;
238
239 for (i = 0; i < nvec; i++) {
240 irq_set_msi_desc_off(irq_base, i, NULL);
241 clear_bit(pos + i, pp->msi_irq_in_use);
242 /* Disable corresponding interrupt on MSI controller */
243 if (pp->ops->msi_clear_irq)
244 pp->ops->msi_clear_irq(pp, pos + i);
245 else
246 dw_pcie_msi_clear_irq(pp, pos + i);
247 }
248 }
249
250 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
251 {
252 unsigned int res, bit, val;
253
254 res = (irq / 32) * 12;
255 bit = irq % 32;
256 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
257 val |= 1 << bit;
258 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
259 }
260
261 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
262 {
263 int irq, pos0, pos1, i;
264 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
265
266 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
267 MAX_MSI_IRQS);
268 if (pos0 % no_irqs) {
269 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
270 goto no_valid_irq;
271 }
272 if (no_irqs > 1) {
273 pos1 = find_next_bit(pp->msi_irq_in_use,
274 MAX_MSI_IRQS, pos0);
275 /* there must be nvec number of consecutive free bits */
276 while ((pos1 - pos0) < no_irqs) {
277 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
278 goto no_valid_irq;
279 pos1 = find_next_bit(pp->msi_irq_in_use,
280 MAX_MSI_IRQS, pos0);
281 }
282 }
283
284 irq = irq_find_mapping(pp->irq_domain, pos0);
285 if (!irq)
286 goto no_valid_irq;
287
288 /*
289 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
290 * descs so there is no need to allocate descs here. We can therefore
291 * assume that if irq_find_mapping above returns non-zero, then the
292 * descs are also successfully allocated.
293 */
294
295 for (i = 0; i < no_irqs; i++) {
296 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
297 clear_irq_range(pp, irq, i, pos0);
298 goto no_valid_irq;
299 }
300 set_bit(pos0 + i, pp->msi_irq_in_use);
301 /*Enable corresponding interrupt in MSI interrupt controller */
302 if (pp->ops->msi_set_irq)
303 pp->ops->msi_set_irq(pp, pos0 + i);
304 else
305 dw_pcie_msi_set_irq(pp, pos0 + i);
306 }
307
308 *pos = pos0;
309 return irq;
310
311 no_valid_irq:
312 *pos = pos0;
313 return -ENOSPC;
314 }
315
316 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
317 struct msi_desc *desc)
318 {
319 int irq, pos;
320 struct msi_msg msg;
321 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
322
323 irq = assign_irq(1, desc, &pos);
324 if (irq < 0)
325 return irq;
326
327 if (pp->ops->get_msi_addr)
328 msg.address_lo = pp->ops->get_msi_addr(pp);
329 else
330 msg.address_lo = virt_to_phys((void *)pp->msi_data);
331 msg.address_hi = 0x0;
332
333 if (pp->ops->get_msi_data)
334 msg.data = pp->ops->get_msi_data(pp, pos);
335 else
336 msg.data = pos;
337
338 write_msi_msg(irq, &msg);
339
340 return 0;
341 }
342
343 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
344 {
345 struct irq_data *data = irq_get_irq_data(irq);
346 struct msi_desc *msi = irq_data_get_msi(data);
347 struct pcie_port *pp = sys_to_pcie(msi->dev->bus->sysdata);
348
349 clear_irq_range(pp, irq, 1, data->hwirq);
350 }
351
352 static struct msi_chip dw_pcie_msi_chip = {
353 .setup_irq = dw_msi_setup_irq,
354 .teardown_irq = dw_msi_teardown_irq,
355 };
356
357 int dw_pcie_link_up(struct pcie_port *pp)
358 {
359 if (pp->ops->link_up)
360 return pp->ops->link_up(pp);
361 else
362 return 0;
363 }
364
365 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
366 irq_hw_number_t hwirq)
367 {
368 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
369 irq_set_chip_data(irq, domain->host_data);
370 set_irq_flags(irq, IRQF_VALID);
371
372 return 0;
373 }
374
375 static const struct irq_domain_ops msi_domain_ops = {
376 .map = dw_pcie_msi_map,
377 };
378
379 int __init dw_pcie_host_init(struct pcie_port *pp)
380 {
381 struct device_node *np = pp->dev->of_node;
382 struct platform_device *pdev = to_platform_device(pp->dev);
383 struct of_pci_range range;
384 struct of_pci_range_parser parser;
385 struct resource *cfg_res;
386 u32 val, na, ns;
387 const __be32 *addrp;
388 int i, index, ret;
389
390 /* Find the address cell size and the number of cells in order to get
391 * the untranslated address.
392 */
393 of_property_read_u32(np, "#address-cells", &na);
394 ns = of_n_size_cells(np);
395
396 cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
397 if (cfg_res) {
398 pp->cfg0_size = resource_size(cfg_res)/2;
399 pp->cfg1_size = resource_size(cfg_res)/2;
400 pp->cfg0_base = cfg_res->start;
401 pp->cfg1_base = cfg_res->start + pp->cfg0_size;
402
403 /* Find the untranslated configuration space address */
404 index = of_property_match_string(np, "reg-names", "config");
405 addrp = of_get_address(np, index, NULL, NULL);
406 pp->cfg0_mod_base = of_read_number(addrp, ns);
407 pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
408 } else {
409 dev_err(pp->dev, "missing *config* reg space\n");
410 }
411
412 if (of_pci_range_parser_init(&parser, np)) {
413 dev_err(pp->dev, "missing ranges property\n");
414 return -EINVAL;
415 }
416
417 /* Get the I/O and memory ranges from DT */
418 for_each_of_pci_range(&parser, &range) {
419 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
420 if (restype == IORESOURCE_IO) {
421 of_pci_range_to_resource(&range, np, &pp->io);
422 pp->io.name = "I/O";
423 pp->io.start = max_t(resource_size_t,
424 PCIBIOS_MIN_IO,
425 range.pci_addr + global_io_offset);
426 pp->io.end = min_t(resource_size_t,
427 IO_SPACE_LIMIT,
428 range.pci_addr + range.size
429 + global_io_offset - 1);
430 pp->io_size = resource_size(&pp->io);
431 pp->io_bus_addr = range.pci_addr;
432 pp->io_base = range.cpu_addr;
433
434 /* Find the untranslated IO space address */
435 pp->io_mod_base = of_read_number(parser.range -
436 parser.np + na, ns);
437 }
438 if (restype == IORESOURCE_MEM) {
439 of_pci_range_to_resource(&range, np, &pp->mem);
440 pp->mem.name = "MEM";
441 pp->mem_size = resource_size(&pp->mem);
442 pp->mem_bus_addr = range.pci_addr;
443
444 /* Find the untranslated MEM space address */
445 pp->mem_mod_base = of_read_number(parser.range -
446 parser.np + na, ns);
447 }
448 if (restype == 0) {
449 of_pci_range_to_resource(&range, np, &pp->cfg);
450 pp->cfg0_size = resource_size(&pp->cfg)/2;
451 pp->cfg1_size = resource_size(&pp->cfg)/2;
452 pp->cfg0_base = pp->cfg.start;
453 pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
454
455 /* Find the untranslated configuration space address */
456 pp->cfg0_mod_base = of_read_number(parser.range -
457 parser.np + na, ns);
458 pp->cfg1_mod_base = pp->cfg0_mod_base +
459 pp->cfg0_size;
460 }
461 }
462
463 ret = of_pci_parse_bus_range(np, &pp->busn);
464 if (ret < 0) {
465 pp->busn.name = np->name;
466 pp->busn.start = 0;
467 pp->busn.end = 0xff;
468 pp->busn.flags = IORESOURCE_BUS;
469 dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
470 ret, &pp->busn);
471 }
472
473 if (!pp->dbi_base) {
474 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
475 resource_size(&pp->cfg));
476 if (!pp->dbi_base) {
477 dev_err(pp->dev, "error with ioremap\n");
478 return -ENOMEM;
479 }
480 }
481
482 pp->mem_base = pp->mem.start;
483
484 if (!pp->va_cfg0_base) {
485 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
486 pp->cfg0_size);
487 if (!pp->va_cfg0_base) {
488 dev_err(pp->dev, "error with ioremap in function\n");
489 return -ENOMEM;
490 }
491 }
492
493 if (!pp->va_cfg1_base) {
494 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
495 pp->cfg1_size);
496 if (!pp->va_cfg1_base) {
497 dev_err(pp->dev, "error with ioremap\n");
498 return -ENOMEM;
499 }
500 }
501
502 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
503 dev_err(pp->dev, "Failed to parse the number of lanes\n");
504 return -EINVAL;
505 }
506
507 if (IS_ENABLED(CONFIG_PCI_MSI)) {
508 if (!pp->ops->msi_host_init) {
509 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
510 MAX_MSI_IRQS, &msi_domain_ops,
511 &dw_pcie_msi_chip);
512 if (!pp->irq_domain) {
513 dev_err(pp->dev, "irq domain init failed\n");
514 return -ENXIO;
515 }
516
517 for (i = 0; i < MAX_MSI_IRQS; i++)
518 irq_create_mapping(pp->irq_domain, i);
519 } else {
520 ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
521 if (ret < 0)
522 return ret;
523 }
524 }
525
526 if (pp->ops->host_init)
527 pp->ops->host_init(pp);
528
529 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
530
531 /* program correct class for RC */
532 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
533
534 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
535 val |= PORT_LOGIC_SPEED_CHANGE;
536 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
537
538 dw_pci.nr_controllers = 1;
539 dw_pci.private_data = (void **)&pp;
540
541 pci_common_init_dev(pp->dev, &dw_pci);
542 #ifdef CONFIG_PCI_DOMAINS
543 dw_pci.domain++;
544 #endif
545
546 return 0;
547 }
548
549 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
550 {
551 /* Program viewport 0 : OUTBOUND : CFG0 */
552 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
553 PCIE_ATU_VIEWPORT);
554 dw_pcie_writel_rc(pp, pp->cfg0_mod_base, PCIE_ATU_LOWER_BASE);
555 dw_pcie_writel_rc(pp, (pp->cfg0_mod_base >> 32), PCIE_ATU_UPPER_BASE);
556 dw_pcie_writel_rc(pp, pp->cfg0_mod_base + pp->cfg0_size - 1,
557 PCIE_ATU_LIMIT);
558 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
559 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
560 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
561 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
562 }
563
564 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
565 {
566 /* Program viewport 1 : OUTBOUND : CFG1 */
567 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
568 PCIE_ATU_VIEWPORT);
569 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
570 dw_pcie_writel_rc(pp, pp->cfg1_mod_base, PCIE_ATU_LOWER_BASE);
571 dw_pcie_writel_rc(pp, (pp->cfg1_mod_base >> 32), PCIE_ATU_UPPER_BASE);
572 dw_pcie_writel_rc(pp, pp->cfg1_mod_base + pp->cfg1_size - 1,
573 PCIE_ATU_LIMIT);
574 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
575 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
576 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
577 }
578
579 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
580 {
581 /* Program viewport 0 : OUTBOUND : MEM */
582 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
583 PCIE_ATU_VIEWPORT);
584 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
585 dw_pcie_writel_rc(pp, pp->mem_mod_base, PCIE_ATU_LOWER_BASE);
586 dw_pcie_writel_rc(pp, (pp->mem_mod_base >> 32), PCIE_ATU_UPPER_BASE);
587 dw_pcie_writel_rc(pp, pp->mem_mod_base + pp->mem_size - 1,
588 PCIE_ATU_LIMIT);
589 dw_pcie_writel_rc(pp, pp->mem_bus_addr, PCIE_ATU_LOWER_TARGET);
590 dw_pcie_writel_rc(pp, upper_32_bits(pp->mem_bus_addr),
591 PCIE_ATU_UPPER_TARGET);
592 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
593 }
594
595 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
596 {
597 /* Program viewport 1 : OUTBOUND : IO */
598 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
599 PCIE_ATU_VIEWPORT);
600 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
601 dw_pcie_writel_rc(pp, pp->io_mod_base, PCIE_ATU_LOWER_BASE);
602 dw_pcie_writel_rc(pp, (pp->io_mod_base >> 32), PCIE_ATU_UPPER_BASE);
603 dw_pcie_writel_rc(pp, pp->io_mod_base + pp->io_size - 1,
604 PCIE_ATU_LIMIT);
605 dw_pcie_writel_rc(pp, pp->io_bus_addr, PCIE_ATU_LOWER_TARGET);
606 dw_pcie_writel_rc(pp, upper_32_bits(pp->io_bus_addr),
607 PCIE_ATU_UPPER_TARGET);
608 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
609 }
610
611 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
612 u32 devfn, int where, int size, u32 *val)
613 {
614 int ret = PCIBIOS_SUCCESSFUL;
615 u32 address, busdev;
616
617 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
618 PCIE_ATU_FUNC(PCI_FUNC(devfn));
619 address = where & ~0x3;
620
621 if (bus->parent->number == pp->root_bus_nr) {
622 dw_pcie_prog_viewport_cfg0(pp, busdev);
623 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
624 val);
625 dw_pcie_prog_viewport_mem_outbound(pp);
626 } else {
627 dw_pcie_prog_viewport_cfg1(pp, busdev);
628 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
629 val);
630 dw_pcie_prog_viewport_io_outbound(pp);
631 }
632
633 return ret;
634 }
635
636 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
637 u32 devfn, int where, int size, u32 val)
638 {
639 int ret = PCIBIOS_SUCCESSFUL;
640 u32 address, busdev;
641
642 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
643 PCIE_ATU_FUNC(PCI_FUNC(devfn));
644 address = where & ~0x3;
645
646 if (bus->parent->number == pp->root_bus_nr) {
647 dw_pcie_prog_viewport_cfg0(pp, busdev);
648 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
649 val);
650 dw_pcie_prog_viewport_mem_outbound(pp);
651 } else {
652 dw_pcie_prog_viewport_cfg1(pp, busdev);
653 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
654 val);
655 dw_pcie_prog_viewport_io_outbound(pp);
656 }
657
658 return ret;
659 }
660
661 static int dw_pcie_valid_config(struct pcie_port *pp,
662 struct pci_bus *bus, int dev)
663 {
664 /* If there is no link, then there is no device */
665 if (bus->number != pp->root_bus_nr) {
666 if (!dw_pcie_link_up(pp))
667 return 0;
668 }
669
670 /* access only one slot on each root port */
671 if (bus->number == pp->root_bus_nr && dev > 0)
672 return 0;
673
674 /*
675 * do not read more than one device on the bus directly attached
676 * to RC's (Virtual Bridge's) DS side.
677 */
678 if (bus->primary == pp->root_bus_nr && dev > 0)
679 return 0;
680
681 return 1;
682 }
683
684 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
685 int size, u32 *val)
686 {
687 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
688 int ret;
689
690 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
691 *val = 0xffffffff;
692 return PCIBIOS_DEVICE_NOT_FOUND;
693 }
694
695 if (bus->number != pp->root_bus_nr)
696 if (pp->ops->rd_other_conf)
697 ret = pp->ops->rd_other_conf(pp, bus, devfn,
698 where, size, val);
699 else
700 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
701 where, size, val);
702 else
703 ret = dw_pcie_rd_own_conf(pp, where, size, val);
704
705 return ret;
706 }
707
708 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
709 int where, int size, u32 val)
710 {
711 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
712 int ret;
713
714 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
715 return PCIBIOS_DEVICE_NOT_FOUND;
716
717 if (bus->number != pp->root_bus_nr)
718 if (pp->ops->wr_other_conf)
719 ret = pp->ops->wr_other_conf(pp, bus, devfn,
720 where, size, val);
721 else
722 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
723 where, size, val);
724 else
725 ret = dw_pcie_wr_own_conf(pp, where, size, val);
726
727 return ret;
728 }
729
730 static struct pci_ops dw_pcie_ops = {
731 .read = dw_pcie_rd_conf,
732 .write = dw_pcie_wr_conf,
733 };
734
735 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
736 {
737 struct pcie_port *pp;
738
739 pp = sys_to_pcie(sys);
740
741 if (global_io_offset < SZ_1M && pp->io_size > 0) {
742 sys->io_offset = global_io_offset - pp->io_bus_addr;
743 pci_ioremap_io(global_io_offset, pp->io_base);
744 global_io_offset += SZ_64K;
745 pci_add_resource_offset(&sys->resources, &pp->io,
746 sys->io_offset);
747 }
748
749 sys->mem_offset = pp->mem.start - pp->mem_bus_addr;
750 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
751 pci_add_resource(&sys->resources, &pp->busn);
752
753 return 1;
754 }
755
756 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
757 {
758 struct pci_bus *bus;
759 struct pcie_port *pp = sys_to_pcie(sys);
760
761 pp->root_bus_nr = sys->busnr;
762 bus = pci_create_root_bus(pp->dev, sys->busnr,
763 &dw_pcie_ops, sys, &sys->resources);
764 if (!bus)
765 return NULL;
766
767 pci_scan_child_bus(bus);
768
769 if (bus && pp->ops->scan_bus)
770 pp->ops->scan_bus(pp);
771
772 return bus;
773 }
774
775 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
776 {
777 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
778 int irq;
779
780 irq = of_irq_parse_and_map_pci(dev, slot, pin);
781 if (!irq)
782 irq = pp->irq;
783
784 return irq;
785 }
786
787 static void dw_pcie_add_bus(struct pci_bus *bus)
788 {
789 if (IS_ENABLED(CONFIG_PCI_MSI)) {
790 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
791
792 dw_pcie_msi_chip.dev = pp->dev;
793 bus->msi = &dw_pcie_msi_chip;
794 }
795 }
796
797 static struct hw_pci dw_pci = {
798 .setup = dw_pcie_setup,
799 .scan = dw_pcie_scan_bus,
800 .map_irq = dw_pcie_map_irq,
801 .add_bus = dw_pcie_add_bus,
802 };
803
804 void dw_pcie_setup_rc(struct pcie_port *pp)
805 {
806 u32 val;
807 u32 membase;
808 u32 memlimit;
809
810 /* set the number of lanes */
811 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
812 val &= ~PORT_LINK_MODE_MASK;
813 switch (pp->lanes) {
814 case 1:
815 val |= PORT_LINK_MODE_1_LANES;
816 break;
817 case 2:
818 val |= PORT_LINK_MODE_2_LANES;
819 break;
820 case 4:
821 val |= PORT_LINK_MODE_4_LANES;
822 break;
823 }
824 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
825
826 /* set link width speed control register */
827 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
828 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
829 switch (pp->lanes) {
830 case 1:
831 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
832 break;
833 case 2:
834 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
835 break;
836 case 4:
837 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
838 break;
839 }
840 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
841
842 /* setup RC BARs */
843 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
844 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
845
846 /* setup interrupt pins */
847 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
848 val &= 0xffff00ff;
849 val |= 0x00000100;
850 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
851
852 /* setup bus numbers */
853 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
854 val &= 0xff000000;
855 val |= 0x00010100;
856 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
857
858 /* setup memory base, memory limit */
859 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
860 memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
861 val = memlimit | membase;
862 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
863
864 /* setup command register */
865 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
866 val &= 0xffff0000;
867 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
868 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
869 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
870 }
871
872 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
873 MODULE_DESCRIPTION("Designware PCIe host controller driver");
874 MODULE_LICENSE("GPL v2");
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