2 * MediaTek PCIe host controller driver.
4 * Copyright (c) 2017 MediaTek Inc.
5 * Author: Ryder Lee <ryder.lee@mediatek.com>
6 * Honghui Zhang <honghui.zhang@mediatek.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/kernel.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/reset.h>
33 /* PCIe shared registers */
34 #define PCIE_SYS_CFG 0x00
35 #define PCIE_INT_ENABLE 0x0c
36 #define PCIE_CFG_ADDR 0x20
37 #define PCIE_CFG_DATA 0x24
39 /* PCIe per port registers */
40 #define PCIE_BAR0_SETUP 0x10
41 #define PCIE_CLASS 0x34
42 #define PCIE_LINK_STATUS 0x50
44 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
45 #define PCIE_PORT_PERST(x) BIT(1 + (x))
46 #define PCIE_PORT_LINKUP BIT(0)
47 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
49 #define PCIE_BAR_ENABLE BIT(0)
50 #define PCIE_REVISION_ID BIT(0)
51 #define PCIE_CLASS_CODE (0x60400 << 8)
52 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
53 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
54 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
55 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
56 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
57 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
58 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
59 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
61 /* MediaTek specific configuration registers */
62 #define PCIE_FTS_NUM 0x70c
63 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
64 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
66 #define PCIE_FC_CREDIT 0x73c
67 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
68 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
70 /* PCIe V2 share registers */
71 #define PCIE_SYS_CFG_V2 0x0
72 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
73 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
75 /* PCIe V2 per-port registers */
76 #define PCIE_MSI_VECTOR 0x0c0
77 #define PCIE_INT_MASK 0x420
78 #define INTX_MASK GENMASK(19, 16)
80 #define PCIE_INT_STATUS 0x424
81 #define MSI_STATUS BIT(23)
82 #define PCIE_IMSI_STATUS 0x42c
83 #define PCIE_IMSI_ADDR 0x430
84 #define MSI_MASK BIT(23)
85 #define MTK_MSI_IRQS_NUM 32
87 #define PCIE_AHB_TRANS_BASE0_L 0x438
88 #define PCIE_AHB_TRANS_BASE0_H 0x43c
89 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
90 #define PCIE_AXI_WINDOW0 0x448
91 #define WIN_ENABLE BIT(7)
93 /* PCIe V2 configuration transaction header */
94 #define PCIE_CFG_HEADER0 0x460
95 #define PCIE_CFG_HEADER1 0x464
96 #define PCIE_CFG_HEADER2 0x468
97 #define PCIE_CFG_WDATA 0x470
98 #define PCIE_APP_TLP_REQ 0x488
99 #define PCIE_CFG_RDATA 0x48c
100 #define APP_CFG_REQ BIT(0)
101 #define APP_CPL_STATUS GENMASK(7, 5)
103 #define CFG_WRRD_TYPE_0 4
107 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
108 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
109 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
110 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
111 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
112 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
113 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
114 #define CFG_HEADER_DW0(type, fmt) \
115 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
116 #define CFG_HEADER_DW1(where, size) \
117 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
118 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
119 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
120 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
122 #define PCIE_RST_CTRL 0x510
123 #define PCIE_PHY_RSTB BIT(0)
124 #define PCIE_PIPE_SRSTB BIT(1)
125 #define PCIE_MAC_SRSTB BIT(2)
126 #define PCIE_CRSTB BIT(3)
127 #define PCIE_PERSTB BIT(8)
128 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
129 #define PCIE_LINK_STATUS_V2 0x804
130 #define PCIE_PORT_LINKUP_V2 BIT(10)
132 struct mtk_pcie_port
;
135 * struct mtk_pcie_soc - differentiate between host generations
136 * @has_msi: whether this host supports MSI interrupts or not
137 * @ops: pointer to configuration access functions
138 * @startup: pointer to controller setting functions
139 * @setup_irq: pointer to initialize IRQ functions
141 struct mtk_pcie_soc
{
144 int (*startup
)(struct mtk_pcie_port
*port
);
145 int (*setup_irq
)(struct mtk_pcie_port
*port
, struct device_node
*node
);
149 * struct mtk_pcie_port - PCIe port information
150 * @base: IO mapped register base
152 * @pcie: pointer to PCIe host info
153 * @reset: pointer to port reset control
154 * @sys_ck: pointer to transaction/data link layer clock
155 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
156 * and RC initiated MMIO access
157 * @axi_ck: pointer to application layer MMIO channel operating clock
158 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
159 * when pcie_mac_ck/pcie_pipe_ck is turned off
160 * @obff_ck: pointer to OBFF functional block operating clock
161 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
162 * @phy: pointer to PHY control block
165 * @irq_domain: legacy INTx IRQ domain
166 * @msi_domain: MSI IRQ domain
167 * @msi_irq_in_use: bit map for assigned MSI IRQ
169 struct mtk_pcie_port
{
171 struct list_head list
;
172 struct mtk_pcie
*pcie
;
173 struct reset_control
*reset
;
183 struct irq_domain
*irq_domain
;
184 struct irq_domain
*msi_domain
;
185 DECLARE_BITMAP(msi_irq_in_use
, MTK_MSI_IRQS_NUM
);
189 * struct mtk_pcie - PCIe host information
190 * @dev: pointer to PCIe device
191 * @base: IO mapped register base
192 * @free_ck: free-run reference clock
195 * @mem: non-prefetchable memory resource
197 * @offset: IO / Memory offset
198 * @ports: pointer to PCIe port information
199 * @soc: pointer to SoC-dependent operations
209 struct resource busn
;
214 struct list_head ports
;
215 const struct mtk_pcie_soc
*soc
;
218 static void mtk_pcie_subsys_powerdown(struct mtk_pcie
*pcie
)
220 struct device
*dev
= pcie
->dev
;
222 clk_disable_unprepare(pcie
->free_ck
);
224 if (dev
->pm_domain
) {
225 pm_runtime_put_sync(dev
);
226 pm_runtime_disable(dev
);
230 static void mtk_pcie_port_free(struct mtk_pcie_port
*port
)
232 struct mtk_pcie
*pcie
= port
->pcie
;
233 struct device
*dev
= pcie
->dev
;
235 devm_iounmap(dev
, port
->base
);
236 list_del(&port
->list
);
237 devm_kfree(dev
, port
);
240 static void mtk_pcie_put_resources(struct mtk_pcie
*pcie
)
242 struct mtk_pcie_port
*port
, *tmp
;
244 list_for_each_entry_safe(port
, tmp
, &pcie
->ports
, list
) {
245 phy_power_off(port
->phy
);
247 clk_disable_unprepare(port
->pipe_ck
);
248 clk_disable_unprepare(port
->obff_ck
);
249 clk_disable_unprepare(port
->axi_ck
);
250 clk_disable_unprepare(port
->aux_ck
);
251 clk_disable_unprepare(port
->ahb_ck
);
252 clk_disable_unprepare(port
->sys_ck
);
253 mtk_pcie_port_free(port
);
256 mtk_pcie_subsys_powerdown(pcie
);
259 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port
*port
)
264 err
= readl_poll_timeout_atomic(port
->base
+ PCIE_APP_TLP_REQ
, val
,
265 !(val
& APP_CFG_REQ
), 10,
266 100 * USEC_PER_MSEC
);
268 return PCIBIOS_SET_FAILED
;
270 if (readl(port
->base
+ PCIE_APP_TLP_REQ
) & APP_CPL_STATUS
)
271 return PCIBIOS_SET_FAILED
;
273 return PCIBIOS_SUCCESSFUL
;
276 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port
*port
, u32 bus
, u32 devfn
,
277 int where
, int size
, u32
*val
)
281 /* Write PCIe configuration transaction header for Cfgrd */
282 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0
, CFG_RD_FMT
),
283 port
->base
+ PCIE_CFG_HEADER0
);
284 writel(CFG_HEADER_DW1(where
, size
), port
->base
+ PCIE_CFG_HEADER1
);
285 writel(CFG_HEADER_DW2(where
, PCI_FUNC(devfn
), PCI_SLOT(devfn
), bus
),
286 port
->base
+ PCIE_CFG_HEADER2
);
288 /* Trigger h/w to transmit Cfgrd TLP */
289 tmp
= readl(port
->base
+ PCIE_APP_TLP_REQ
);
291 writel(tmp
, port
->base
+ PCIE_APP_TLP_REQ
);
293 /* Check completion status */
294 if (mtk_pcie_check_cfg_cpld(port
))
295 return PCIBIOS_SET_FAILED
;
297 /* Read cpld payload of Cfgrd */
298 *val
= readl(port
->base
+ PCIE_CFG_RDATA
);
301 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
303 *val
= (*val
>> (8 * (where
& 3))) & 0xffff;
305 return PCIBIOS_SUCCESSFUL
;
308 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port
*port
, u32 bus
, u32 devfn
,
309 int where
, int size
, u32 val
)
311 /* Write PCIe configuration transaction header for Cfgwr */
312 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0
, CFG_WR_FMT
),
313 port
->base
+ PCIE_CFG_HEADER0
);
314 writel(CFG_HEADER_DW1(where
, size
), port
->base
+ PCIE_CFG_HEADER1
);
315 writel(CFG_HEADER_DW2(where
, PCI_FUNC(devfn
), PCI_SLOT(devfn
), bus
),
316 port
->base
+ PCIE_CFG_HEADER2
);
318 /* Write Cfgwr data */
319 val
= val
<< 8 * (where
& 3);
320 writel(val
, port
->base
+ PCIE_CFG_WDATA
);
322 /* Trigger h/w to transmit Cfgwr TLP */
323 val
= readl(port
->base
+ PCIE_APP_TLP_REQ
);
325 writel(val
, port
->base
+ PCIE_APP_TLP_REQ
);
327 /* Check completion status */
328 return mtk_pcie_check_cfg_cpld(port
);
331 static struct mtk_pcie_port
*mtk_pcie_find_port(struct pci_bus
*bus
,
334 struct mtk_pcie
*pcie
= bus
->sysdata
;
335 struct mtk_pcie_port
*port
;
336 struct pci_dev
*dev
= NULL
;
339 * Walk the bus hierarchy to get the devfn value
340 * of the port in the root bus.
342 while (bus
&& bus
->number
) {
348 list_for_each_entry(port
, &pcie
->ports
, list
)
349 if (port
->slot
== PCI_SLOT(devfn
))
355 static int mtk_pcie_config_read(struct pci_bus
*bus
, unsigned int devfn
,
356 int where
, int size
, u32
*val
)
358 struct mtk_pcie_port
*port
;
359 u32 bn
= bus
->number
;
362 port
= mtk_pcie_find_port(bus
, devfn
);
365 return PCIBIOS_DEVICE_NOT_FOUND
;
368 ret
= mtk_pcie_hw_rd_cfg(port
, bn
, devfn
, where
, size
, val
);
375 static int mtk_pcie_config_write(struct pci_bus
*bus
, unsigned int devfn
,
376 int where
, int size
, u32 val
)
378 struct mtk_pcie_port
*port
;
379 u32 bn
= bus
->number
;
381 port
= mtk_pcie_find_port(bus
, devfn
);
383 return PCIBIOS_DEVICE_NOT_FOUND
;
385 return mtk_pcie_hw_wr_cfg(port
, bn
, devfn
, where
, size
, val
);
388 static struct pci_ops mtk_pcie_ops_v2
= {
389 .read
= mtk_pcie_config_read
,
390 .write
= mtk_pcie_config_write
,
393 static int mtk_pcie_msi_alloc(struct mtk_pcie_port
*port
)
397 msi
= find_first_zero_bit(port
->msi_irq_in_use
, MTK_MSI_IRQS_NUM
);
398 if (msi
< MTK_MSI_IRQS_NUM
)
399 set_bit(msi
, port
->msi_irq_in_use
);
406 static void mtk_pcie_msi_free(struct mtk_pcie_port
*port
, unsigned long hwirq
)
408 clear_bit(hwirq
, port
->msi_irq_in_use
);
411 static int mtk_pcie_msi_setup_irq(struct msi_controller
*chip
,
412 struct pci_dev
*pdev
, struct msi_desc
*desc
)
414 struct mtk_pcie_port
*port
;
418 phys_addr_t msg_addr
;
420 port
= mtk_pcie_find_port(pdev
->bus
, pdev
->devfn
);
424 hwirq
= mtk_pcie_msi_alloc(port
);
428 irq
= irq_create_mapping(port
->msi_domain
, hwirq
);
430 mtk_pcie_msi_free(port
, hwirq
);
434 chip
->dev
= &pdev
->dev
;
436 irq_set_msi_desc(irq
, desc
);
438 /* MT2712/MT7622 only support 32-bit MSI addresses */
439 msg_addr
= virt_to_phys(port
->base
+ PCIE_MSI_VECTOR
);
441 msg
.address_lo
= lower_32_bits(msg_addr
);
444 pci_write_msi_msg(irq
, &msg
);
449 static void mtk_msi_teardown_irq(struct msi_controller
*chip
, unsigned int irq
)
451 struct pci_dev
*pdev
= to_pci_dev(chip
->dev
);
452 struct irq_data
*d
= irq_get_irq_data(irq
);
453 irq_hw_number_t hwirq
= irqd_to_hwirq(d
);
454 struct mtk_pcie_port
*port
;
456 port
= mtk_pcie_find_port(pdev
->bus
, pdev
->devfn
);
460 irq_dispose_mapping(irq
);
461 mtk_pcie_msi_free(port
, hwirq
);
464 static struct msi_controller mtk_pcie_msi_chip
= {
465 .setup_irq
= mtk_pcie_msi_setup_irq
,
466 .teardown_irq
= mtk_msi_teardown_irq
,
469 static struct irq_chip mtk_msi_irq_chip
= {
470 .name
= "MTK PCIe MSI",
471 .irq_enable
= pci_msi_unmask_irq
,
472 .irq_disable
= pci_msi_mask_irq
,
473 .irq_mask
= pci_msi_mask_irq
,
474 .irq_unmask
= pci_msi_unmask_irq
,
477 static int mtk_pcie_msi_map(struct irq_domain
*domain
, unsigned int irq
,
478 irq_hw_number_t hwirq
)
480 irq_set_chip_and_handler(irq
, &mtk_msi_irq_chip
, handle_simple_irq
);
481 irq_set_chip_data(irq
, domain
->host_data
);
486 static const struct irq_domain_ops msi_domain_ops
= {
487 .map
= mtk_pcie_msi_map
,
490 static void mtk_pcie_enable_msi(struct mtk_pcie_port
*port
)
493 phys_addr_t msg_addr
;
495 msg_addr
= virt_to_phys(port
->base
+ PCIE_MSI_VECTOR
);
496 val
= lower_32_bits(msg_addr
);
497 writel(val
, port
->base
+ PCIE_IMSI_ADDR
);
499 val
= readl(port
->base
+ PCIE_INT_MASK
);
501 writel(val
, port
->base
+ PCIE_INT_MASK
);
504 static int mtk_pcie_intx_map(struct irq_domain
*domain
, unsigned int irq
,
505 irq_hw_number_t hwirq
)
507 irq_set_chip_and_handler(irq
, &dummy_irq_chip
, handle_simple_irq
);
508 irq_set_chip_data(irq
, domain
->host_data
);
513 static const struct irq_domain_ops intx_domain_ops
= {
514 .map
= mtk_pcie_intx_map
,
517 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port
*port
,
518 struct device_node
*node
)
520 struct device
*dev
= port
->pcie
->dev
;
521 struct device_node
*pcie_intc_node
;
524 pcie_intc_node
= of_get_next_child(node
, NULL
);
525 if (!pcie_intc_node
) {
526 dev_err(dev
, "no PCIe Intc node found\n");
530 port
->irq_domain
= irq_domain_add_linear(pcie_intc_node
, PCI_NUM_INTX
,
531 &intx_domain_ops
, port
);
532 if (!port
->irq_domain
) {
533 dev_err(dev
, "failed to get INTx IRQ domain\n");
537 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
538 port
->msi_domain
= irq_domain_add_linear(node
, MTK_MSI_IRQS_NUM
,
541 if (!port
->msi_domain
) {
542 dev_err(dev
, "failed to create MSI IRQ domain\n");
550 static irqreturn_t
mtk_pcie_intr_handler(int irq
, void *data
)
552 struct mtk_pcie_port
*port
= (struct mtk_pcie_port
*)data
;
553 unsigned long status
;
555 u32 bit
= INTX_SHIFT
;
557 while ((status
= readl(port
->base
+ PCIE_INT_STATUS
)) & INTX_MASK
) {
558 for_each_set_bit_from(bit
, &status
, PCI_NUM_INTX
+ INTX_SHIFT
) {
560 writel(1 << bit
, port
->base
+ PCIE_INT_STATUS
);
561 virq
= irq_find_mapping(port
->irq_domain
,
563 generic_handle_irq(virq
);
567 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
568 while ((status
= readl(port
->base
+ PCIE_INT_STATUS
)) & MSI_STATUS
) {
569 unsigned long imsi_status
;
571 while ((imsi_status
= readl(port
->base
+ PCIE_IMSI_STATUS
))) {
572 for_each_set_bit(bit
, &imsi_status
, MTK_MSI_IRQS_NUM
) {
574 writel(1 << bit
, port
->base
+ PCIE_IMSI_STATUS
);
575 virq
= irq_find_mapping(port
->msi_domain
, bit
);
576 generic_handle_irq(virq
);
579 /* Clear MSI interrupt status */
580 writel(MSI_STATUS
, port
->base
+ PCIE_INT_STATUS
);
587 static int mtk_pcie_setup_irq(struct mtk_pcie_port
*port
,
588 struct device_node
*node
)
590 struct mtk_pcie
*pcie
= port
->pcie
;
591 struct device
*dev
= pcie
->dev
;
592 struct platform_device
*pdev
= to_platform_device(dev
);
595 irq
= platform_get_irq(pdev
, port
->slot
);
596 err
= devm_request_irq(dev
, irq
, mtk_pcie_intr_handler
,
597 IRQF_SHARED
, "mtk-pcie", port
);
599 dev_err(dev
, "unable to request IRQ %d\n", irq
);
603 err
= mtk_pcie_init_irq_domain(port
, node
);
605 dev_err(dev
, "failed to init PCIe IRQ domain\n");
612 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port
*port
)
614 struct mtk_pcie
*pcie
= port
->pcie
;
615 struct resource
*mem
= &pcie
->mem
;
620 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
622 val
= readl(pcie
->base
+ PCIE_SYS_CFG_V2
);
623 val
|= PCIE_CSR_LTSSM_EN(port
->slot
) |
624 PCIE_CSR_ASPM_L1_EN(port
->slot
);
625 writel(val
, pcie
->base
+ PCIE_SYS_CFG_V2
);
628 /* Assert all reset signals */
629 writel(0, port
->base
+ PCIE_RST_CTRL
);
632 * Enable PCIe link down reset, if link status changed from link up to
633 * link down, this will reset MAC control registers and configuration
636 writel(PCIE_LINKDOWN_RST_EN
, port
->base
+ PCIE_RST_CTRL
);
638 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
639 val
= readl(port
->base
+ PCIE_RST_CTRL
);
640 val
|= PCIE_PHY_RSTB
| PCIE_PERSTB
| PCIE_PIPE_SRSTB
|
641 PCIE_MAC_SRSTB
| PCIE_CRSTB
;
642 writel(val
, port
->base
+ PCIE_RST_CTRL
);
644 /* 100ms timeout value should be enough for Gen1/2 training */
645 err
= readl_poll_timeout(port
->base
+ PCIE_LINK_STATUS_V2
, val
,
646 !!(val
& PCIE_PORT_LINKUP_V2
), 20,
647 100 * USEC_PER_MSEC
);
652 val
= readl(port
->base
+ PCIE_INT_MASK
);
654 writel(val
, port
->base
+ PCIE_INT_MASK
);
656 if (IS_ENABLED(CONFIG_PCI_MSI
))
657 mtk_pcie_enable_msi(port
);
659 /* Set AHB to PCIe translation windows */
660 size
= mem
->end
- mem
->start
;
661 val
= lower_32_bits(mem
->start
) | AHB2PCIE_SIZE(fls(size
));
662 writel(val
, port
->base
+ PCIE_AHB_TRANS_BASE0_L
);
664 val
= upper_32_bits(mem
->start
);
665 writel(val
, port
->base
+ PCIE_AHB_TRANS_BASE0_H
);
667 /* Set PCIe to AXI translation memory space.*/
668 val
= fls(0xffffffff) | WIN_ENABLE
;
669 writel(val
, port
->base
+ PCIE_AXI_WINDOW0
);
674 static void __iomem
*mtk_pcie_map_bus(struct pci_bus
*bus
,
675 unsigned int devfn
, int where
)
677 struct mtk_pcie
*pcie
= bus
->sysdata
;
679 writel(PCIE_CONF_ADDR(where
, PCI_FUNC(devfn
), PCI_SLOT(devfn
),
680 bus
->number
), pcie
->base
+ PCIE_CFG_ADDR
);
682 return pcie
->base
+ PCIE_CFG_DATA
+ (where
& 3);
685 static struct pci_ops mtk_pcie_ops
= {
686 .map_bus
= mtk_pcie_map_bus
,
687 .read
= pci_generic_config_read
,
688 .write
= pci_generic_config_write
,
691 static int mtk_pcie_startup_port(struct mtk_pcie_port
*port
)
693 struct mtk_pcie
*pcie
= port
->pcie
;
694 u32 func
= PCI_FUNC(port
->slot
<< 3);
695 u32 slot
= PCI_SLOT(port
->slot
<< 3);
699 /* assert port PERST_N */
700 val
= readl(pcie
->base
+ PCIE_SYS_CFG
);
701 val
|= PCIE_PORT_PERST(port
->slot
);
702 writel(val
, pcie
->base
+ PCIE_SYS_CFG
);
704 /* de-assert port PERST_N */
705 val
= readl(pcie
->base
+ PCIE_SYS_CFG
);
706 val
&= ~PCIE_PORT_PERST(port
->slot
);
707 writel(val
, pcie
->base
+ PCIE_SYS_CFG
);
709 /* 100ms timeout value should be enough for Gen1/2 training */
710 err
= readl_poll_timeout(port
->base
+ PCIE_LINK_STATUS
, val
,
711 !!(val
& PCIE_PORT_LINKUP
), 20,
712 100 * USEC_PER_MSEC
);
716 /* enable interrupt */
717 val
= readl(pcie
->base
+ PCIE_INT_ENABLE
);
718 val
|= PCIE_PORT_INT_EN(port
->slot
);
719 writel(val
, pcie
->base
+ PCIE_INT_ENABLE
);
721 /* map to all DDR region. We need to set it before cfg operation. */
722 writel(PCIE_BAR_MAP_MAX
| PCIE_BAR_ENABLE
,
723 port
->base
+ PCIE_BAR0_SETUP
);
725 /* configure class code and revision ID */
726 writel(PCIE_CLASS_CODE
| PCIE_REVISION_ID
, port
->base
+ PCIE_CLASS
);
728 /* configure FC credit */
729 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT
, func
, slot
, 0),
730 pcie
->base
+ PCIE_CFG_ADDR
);
731 val
= readl(pcie
->base
+ PCIE_CFG_DATA
);
732 val
&= ~PCIE_FC_CREDIT_MASK
;
733 val
|= PCIE_FC_CREDIT_VAL(0x806c);
734 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT
, func
, slot
, 0),
735 pcie
->base
+ PCIE_CFG_ADDR
);
736 writel(val
, pcie
->base
+ PCIE_CFG_DATA
);
738 /* configure RC FTS number to 250 when it leaves L0s */
739 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM
, func
, slot
, 0),
740 pcie
->base
+ PCIE_CFG_ADDR
);
741 val
= readl(pcie
->base
+ PCIE_CFG_DATA
);
742 val
&= ~PCIE_FTS_NUM_MASK
;
743 val
|= PCIE_FTS_NUM_L0(0x50);
744 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM
, func
, slot
, 0),
745 pcie
->base
+ PCIE_CFG_ADDR
);
746 writel(val
, pcie
->base
+ PCIE_CFG_DATA
);
751 static void mtk_pcie_enable_port(struct mtk_pcie_port
*port
)
753 struct mtk_pcie
*pcie
= port
->pcie
;
754 struct device
*dev
= pcie
->dev
;
757 err
= clk_prepare_enable(port
->sys_ck
);
759 dev_err(dev
, "failed to enable sys_ck%d clock\n", port
->slot
);
763 err
= clk_prepare_enable(port
->ahb_ck
);
765 dev_err(dev
, "failed to enable ahb_ck%d\n", port
->slot
);
769 err
= clk_prepare_enable(port
->aux_ck
);
771 dev_err(dev
, "failed to enable aux_ck%d\n", port
->slot
);
775 err
= clk_prepare_enable(port
->axi_ck
);
777 dev_err(dev
, "failed to enable axi_ck%d\n", port
->slot
);
781 err
= clk_prepare_enable(port
->obff_ck
);
783 dev_err(dev
, "failed to enable obff_ck%d\n", port
->slot
);
787 err
= clk_prepare_enable(port
->pipe_ck
);
789 dev_err(dev
, "failed to enable pipe_ck%d\n", port
->slot
);
793 reset_control_assert(port
->reset
);
794 reset_control_deassert(port
->reset
);
796 err
= phy_init(port
->phy
);
798 dev_err(dev
, "failed to initialize port%d phy\n", port
->slot
);
802 err
= phy_power_on(port
->phy
);
804 dev_err(dev
, "failed to power on port%d phy\n", port
->slot
);
808 if (!pcie
->soc
->startup(port
))
811 dev_info(dev
, "Port%d link down\n", port
->slot
);
813 phy_power_off(port
->phy
);
817 clk_disable_unprepare(port
->pipe_ck
);
819 clk_disable_unprepare(port
->obff_ck
);
821 clk_disable_unprepare(port
->axi_ck
);
823 clk_disable_unprepare(port
->aux_ck
);
825 clk_disable_unprepare(port
->ahb_ck
);
827 clk_disable_unprepare(port
->sys_ck
);
829 mtk_pcie_port_free(port
);
832 static int mtk_pcie_parse_port(struct mtk_pcie
*pcie
,
833 struct device_node
*node
,
836 struct mtk_pcie_port
*port
;
837 struct resource
*regs
;
838 struct device
*dev
= pcie
->dev
;
839 struct platform_device
*pdev
= to_platform_device(dev
);
843 port
= devm_kzalloc(dev
, sizeof(*port
), GFP_KERNEL
);
847 err
= of_property_read_u32(node
, "num-lanes", &port
->lane
);
849 dev_err(dev
, "missing num-lanes property\n");
853 snprintf(name
, sizeof(name
), "port%d", slot
);
854 regs
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, name
);
855 port
->base
= devm_ioremap_resource(dev
, regs
);
856 if (IS_ERR(port
->base
)) {
857 dev_err(dev
, "failed to map port%d base\n", slot
);
858 return PTR_ERR(port
->base
);
861 snprintf(name
, sizeof(name
), "sys_ck%d", slot
);
862 port
->sys_ck
= devm_clk_get(dev
, name
);
863 if (IS_ERR(port
->sys_ck
)) {
864 dev_err(dev
, "failed to get sys_ck%d clock\n", slot
);
865 return PTR_ERR(port
->sys_ck
);
868 /* sys_ck might be divided into the following parts in some chips */
869 snprintf(name
, sizeof(name
), "ahb_ck%d", slot
);
870 port
->ahb_ck
= devm_clk_get(dev
, name
);
871 if (IS_ERR(port
->ahb_ck
)) {
872 if (PTR_ERR(port
->ahb_ck
) == -EPROBE_DEFER
)
873 return -EPROBE_DEFER
;
878 snprintf(name
, sizeof(name
), "axi_ck%d", slot
);
879 port
->axi_ck
= devm_clk_get(dev
, name
);
880 if (IS_ERR(port
->axi_ck
)) {
881 if (PTR_ERR(port
->axi_ck
) == -EPROBE_DEFER
)
882 return -EPROBE_DEFER
;
887 snprintf(name
, sizeof(name
), "aux_ck%d", slot
);
888 port
->aux_ck
= devm_clk_get(dev
, name
);
889 if (IS_ERR(port
->aux_ck
)) {
890 if (PTR_ERR(port
->aux_ck
) == -EPROBE_DEFER
)
891 return -EPROBE_DEFER
;
896 snprintf(name
, sizeof(name
), "obff_ck%d", slot
);
897 port
->obff_ck
= devm_clk_get(dev
, name
);
898 if (IS_ERR(port
->obff_ck
)) {
899 if (PTR_ERR(port
->obff_ck
) == -EPROBE_DEFER
)
900 return -EPROBE_DEFER
;
902 port
->obff_ck
= NULL
;
905 snprintf(name
, sizeof(name
), "pipe_ck%d", slot
);
906 port
->pipe_ck
= devm_clk_get(dev
, name
);
907 if (IS_ERR(port
->pipe_ck
)) {
908 if (PTR_ERR(port
->pipe_ck
) == -EPROBE_DEFER
)
909 return -EPROBE_DEFER
;
911 port
->pipe_ck
= NULL
;
914 snprintf(name
, sizeof(name
), "pcie-rst%d", slot
);
915 port
->reset
= devm_reset_control_get_optional_exclusive(dev
, name
);
916 if (PTR_ERR(port
->reset
) == -EPROBE_DEFER
)
917 return PTR_ERR(port
->reset
);
919 /* some platforms may use default PHY setting */
920 snprintf(name
, sizeof(name
), "pcie-phy%d", slot
);
921 port
->phy
= devm_phy_optional_get(dev
, name
);
922 if (IS_ERR(port
->phy
))
923 return PTR_ERR(port
->phy
);
928 if (pcie
->soc
->setup_irq
) {
929 err
= pcie
->soc
->setup_irq(port
, node
);
934 INIT_LIST_HEAD(&port
->list
);
935 list_add_tail(&port
->list
, &pcie
->ports
);
940 static int mtk_pcie_subsys_powerup(struct mtk_pcie
*pcie
)
942 struct device
*dev
= pcie
->dev
;
943 struct platform_device
*pdev
= to_platform_device(dev
);
944 struct resource
*regs
;
947 /* get shared registers, which are optional */
948 regs
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "subsys");
950 pcie
->base
= devm_ioremap_resource(dev
, regs
);
951 if (IS_ERR(pcie
->base
)) {
952 dev_err(dev
, "failed to map shared register\n");
953 return PTR_ERR(pcie
->base
);
957 pcie
->free_ck
= devm_clk_get(dev
, "free_ck");
958 if (IS_ERR(pcie
->free_ck
)) {
959 if (PTR_ERR(pcie
->free_ck
) == -EPROBE_DEFER
)
960 return -EPROBE_DEFER
;
962 pcie
->free_ck
= NULL
;
965 if (dev
->pm_domain
) {
966 pm_runtime_enable(dev
);
967 pm_runtime_get_sync(dev
);
970 /* enable top level clock */
971 err
= clk_prepare_enable(pcie
->free_ck
);
973 dev_err(dev
, "failed to enable free_ck\n");
980 if (dev
->pm_domain
) {
981 pm_runtime_put_sync(dev
);
982 pm_runtime_disable(dev
);
988 static int mtk_pcie_setup(struct mtk_pcie
*pcie
)
990 struct device
*dev
= pcie
->dev
;
991 struct device_node
*node
= dev
->of_node
, *child
;
992 struct of_pci_range_parser parser
;
993 struct of_pci_range range
;
995 struct mtk_pcie_port
*port
, *tmp
;
998 if (of_pci_range_parser_init(&parser
, node
)) {
999 dev_err(dev
, "missing \"ranges\" property\n");
1003 for_each_of_pci_range(&parser
, &range
) {
1004 err
= of_pci_range_to_resource(&range
, node
, &res
);
1008 switch (res
.flags
& IORESOURCE_TYPE_BITS
) {
1010 pcie
->offset
.io
= res
.start
- range
.pci_addr
;
1012 memcpy(&pcie
->pio
, &res
, sizeof(res
));
1013 pcie
->pio
.name
= node
->full_name
;
1015 pcie
->io
.start
= range
.cpu_addr
;
1016 pcie
->io
.end
= range
.cpu_addr
+ range
.size
- 1;
1017 pcie
->io
.flags
= IORESOURCE_MEM
;
1018 pcie
->io
.name
= "I/O";
1020 memcpy(&res
, &pcie
->io
, sizeof(res
));
1023 case IORESOURCE_MEM
:
1024 pcie
->offset
.mem
= res
.start
- range
.pci_addr
;
1026 memcpy(&pcie
->mem
, &res
, sizeof(res
));
1027 pcie
->mem
.name
= "non-prefetchable";
1032 err
= of_pci_parse_bus_range(node
, &pcie
->busn
);
1034 dev_err(dev
, "failed to parse bus ranges property: %d\n", err
);
1035 pcie
->busn
.name
= node
->name
;
1036 pcie
->busn
.start
= 0;
1037 pcie
->busn
.end
= 0xff;
1038 pcie
->busn
.flags
= IORESOURCE_BUS
;
1041 for_each_available_child_of_node(node
, child
) {
1044 err
= of_pci_get_devfn(child
);
1046 dev_err(dev
, "failed to parse devfn: %d\n", err
);
1050 slot
= PCI_SLOT(err
);
1052 err
= mtk_pcie_parse_port(pcie
, child
, slot
);
1057 err
= mtk_pcie_subsys_powerup(pcie
);
1061 /* enable each port, and then check link status */
1062 list_for_each_entry_safe(port
, tmp
, &pcie
->ports
, list
)
1063 mtk_pcie_enable_port(port
);
1065 /* power down PCIe subsys if slots are all empty (link down) */
1066 if (list_empty(&pcie
->ports
))
1067 mtk_pcie_subsys_powerdown(pcie
);
1072 static int mtk_pcie_request_resources(struct mtk_pcie
*pcie
)
1074 struct pci_host_bridge
*host
= pci_host_bridge_from_priv(pcie
);
1075 struct list_head
*windows
= &host
->windows
;
1076 struct device
*dev
= pcie
->dev
;
1079 pci_add_resource_offset(windows
, &pcie
->pio
, pcie
->offset
.io
);
1080 pci_add_resource_offset(windows
, &pcie
->mem
, pcie
->offset
.mem
);
1081 pci_add_resource(windows
, &pcie
->busn
);
1083 err
= devm_request_pci_bus_resources(dev
, windows
);
1087 err
= devm_pci_remap_iospace(dev
, &pcie
->pio
, pcie
->io
.start
);
1094 static int mtk_pcie_register_host(struct pci_host_bridge
*host
)
1096 struct mtk_pcie
*pcie
= pci_host_bridge_priv(host
);
1097 struct pci_bus
*child
;
1100 host
->busnr
= pcie
->busn
.start
;
1101 host
->dev
.parent
= pcie
->dev
;
1102 host
->ops
= pcie
->soc
->ops
;
1103 host
->map_irq
= of_irq_parse_and_map_pci
;
1104 host
->swizzle_irq
= pci_common_swizzle
;
1105 host
->sysdata
= pcie
;
1106 if (IS_ENABLED(CONFIG_PCI_MSI
) && pcie
->soc
->has_msi
)
1107 host
->msi
= &mtk_pcie_msi_chip
;
1109 err
= pci_scan_root_bus_bridge(host
);
1113 pci_bus_size_bridges(host
->bus
);
1114 pci_bus_assign_resources(host
->bus
);
1116 list_for_each_entry(child
, &host
->bus
->children
, node
)
1117 pcie_bus_configure_settings(child
);
1119 pci_bus_add_devices(host
->bus
);
1124 static int mtk_pcie_probe(struct platform_device
*pdev
)
1126 struct device
*dev
= &pdev
->dev
;
1127 struct mtk_pcie
*pcie
;
1128 struct pci_host_bridge
*host
;
1131 host
= devm_pci_alloc_host_bridge(dev
, sizeof(*pcie
));
1135 pcie
= pci_host_bridge_priv(host
);
1138 pcie
->soc
= of_device_get_match_data(dev
);
1139 platform_set_drvdata(pdev
, pcie
);
1140 INIT_LIST_HEAD(&pcie
->ports
);
1142 err
= mtk_pcie_setup(pcie
);
1146 err
= mtk_pcie_request_resources(pcie
);
1150 err
= mtk_pcie_register_host(host
);
1157 if (!list_empty(&pcie
->ports
))
1158 mtk_pcie_put_resources(pcie
);
1163 static const struct mtk_pcie_soc mtk_pcie_soc_v1
= {
1164 .ops
= &mtk_pcie_ops
,
1165 .startup
= mtk_pcie_startup_port
,
1168 static const struct mtk_pcie_soc mtk_pcie_soc_v2
= {
1170 .ops
= &mtk_pcie_ops_v2
,
1171 .startup
= mtk_pcie_startup_port_v2
,
1172 .setup_irq
= mtk_pcie_setup_irq
,
1175 static const struct of_device_id mtk_pcie_ids
[] = {
1176 { .compatible
= "mediatek,mt2701-pcie", .data
= &mtk_pcie_soc_v1
},
1177 { .compatible
= "mediatek,mt7623-pcie", .data
= &mtk_pcie_soc_v1
},
1178 { .compatible
= "mediatek,mt2712-pcie", .data
= &mtk_pcie_soc_v2
},
1179 { .compatible
= "mediatek,mt7622-pcie", .data
= &mtk_pcie_soc_v2
},
1183 static struct platform_driver mtk_pcie_driver
= {
1184 .probe
= mtk_pcie_probe
,
1187 .of_match_table
= mtk_pcie_ids
,
1188 .suppress_bind_attrs
= true,
1191 builtin_platform_driver(mtk_pcie_driver
);