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[mirror_ubuntu-jammy-kernel.git] / drivers / pci / host / pcie-rcar.c
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * Author: Phil Edworthy <phil.edworthy@renesas.com>
11 *
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
33
34 #define PCIECAR 0x000010
35 #define PCIECCTLR 0x000018
36 #define CONFIG_SEND_ENABLE (1 << 31)
37 #define TYPE0 (0 << 8)
38 #define TYPE1 (1 << 8)
39 #define PCIECDR 0x000020
40 #define PCIEMSR 0x000028
41 #define PCIEINTXR 0x000400
42 #define PCIEMSITXR 0x000840
43
44 /* Transfer control */
45 #define PCIETCTLR 0x02000
46 #define CFINIT 1
47 #define PCIETSTR 0x02004
48 #define DATA_LINK_ACTIVE 1
49 #define PCIEERRFR 0x02020
50 #define UNSUPPORTED_REQUEST (1 << 4)
51 #define PCIEMSIFR 0x02044
52 #define PCIEMSIALR 0x02048
53 #define MSIFE 1
54 #define PCIEMSIAUR 0x0204c
55 #define PCIEMSIIER 0x02050
56
57 /* root port address */
58 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
59
60 /* local address reg & mask */
61 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
62 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
63 #define LAM_PREFETCH (1 << 3)
64 #define LAM_64BIT (1 << 2)
65 #define LAR_ENABLE (1 << 1)
66
67 /* PCIe address reg & mask */
68 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
69 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
70 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
71 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
72 #define PAR_ENABLE (1 << 31)
73 #define IO_SPACE (1 << 8)
74
75 /* Configuration */
76 #define PCICONF(x) (0x010000 + ((x) * 0x4))
77 #define PMCAP(x) (0x010040 + ((x) * 0x4))
78 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
79 #define VCCAP(x) (0x010100 + ((x) * 0x4))
80
81 /* link layer */
82 #define IDSETR1 0x011004
83 #define TLCTLR 0x011048
84 #define MACSR 0x011054
85 #define SPCHGFIN (1 << 4)
86 #define SPCHGFAIL (1 << 6)
87 #define SPCHGSUC (1 << 7)
88 #define LINK_SPEED (0xf << 16)
89 #define LINK_SPEED_2_5GTS (1 << 16)
90 #define LINK_SPEED_5_0GTS (2 << 16)
91 #define MACCTLR 0x011058
92 #define SPEED_CHANGE (1 << 24)
93 #define SCRAMBLE_DISABLE (1 << 27)
94 #define MACS2R 0x011078
95 #define MACCGSPSETR 0x011084
96 #define SPCNGRSN (1 << 31)
97
98 /* R-Car H1 PHY */
99 #define H1_PCIEPHYADRR 0x04000c
100 #define WRITE_CMD (1 << 16)
101 #define PHY_ACK (1 << 24)
102 #define RATE_POS 12
103 #define LANE_POS 8
104 #define ADR_POS 0
105 #define H1_PCIEPHYDOUTR 0x040014
106 #define H1_PCIEPHYSR 0x040018
107
108 /* R-Car Gen2 PHY */
109 #define GEN2_PCIEPHYADDR 0x780
110 #define GEN2_PCIEPHYDATA 0x784
111 #define GEN2_PCIEPHYCTRL 0x78c
112
113 #define INT_PCI_MSI_NR 32
114
115 #define RCONF(x) (PCICONF(0)+(x))
116 #define RPMCAP(x) (PMCAP(0)+(x))
117 #define REXPCAP(x) (EXPCAP(0)+(x))
118 #define RVCCAP(x) (VCCAP(0)+(x))
119
120 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
121 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
122 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
123
124 #define RCAR_PCI_MAX_RESOURCES 4
125 #define MAX_NR_INBOUND_MAPS 6
126
127 struct rcar_msi {
128 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
129 struct irq_domain *domain;
130 struct msi_controller chip;
131 unsigned long pages;
132 struct mutex lock;
133 int irq1;
134 int irq2;
135 };
136
137 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
138 {
139 return container_of(chip, struct rcar_msi, chip);
140 }
141
142 /* Structure representing the PCIe interface */
143 struct rcar_pcie {
144 struct device *dev;
145 void __iomem *base;
146 struct list_head resources;
147 int root_bus_nr;
148 struct clk *clk;
149 struct clk *bus_clk;
150 struct rcar_msi msi;
151 };
152
153 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
154 unsigned long reg)
155 {
156 writel(val, pcie->base + reg);
157 }
158
159 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
160 unsigned long reg)
161 {
162 return readl(pcie->base + reg);
163 }
164
165 enum {
166 RCAR_PCI_ACCESS_READ,
167 RCAR_PCI_ACCESS_WRITE,
168 };
169
170 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
171 {
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
174
175 val &= ~(mask << shift);
176 val |= data << shift;
177 rcar_pci_write_reg(pcie, val, where & ~3);
178 }
179
180 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
181 {
182 int shift = 8 * (where & 3);
183 u32 val = rcar_pci_read_reg(pcie, where & ~3);
184
185 return val >> shift;
186 }
187
188 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
189 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
190 unsigned char access_type, struct pci_bus *bus,
191 unsigned int devfn, int where, u32 *data)
192 {
193 int dev, func, reg, index;
194
195 dev = PCI_SLOT(devfn);
196 func = PCI_FUNC(devfn);
197 reg = where & ~3;
198 index = reg / 4;
199
200 /*
201 * While each channel has its own memory-mapped extended config
202 * space, it's generally only accessible when in endpoint mode.
203 * When in root complex mode, the controller is unable to target
204 * itself with either type 0 or type 1 accesses, and indeed, any
205 * controller initiated target transfer to its own config space
206 * result in a completer abort.
207 *
208 * Each channel effectively only supports a single device, but as
209 * the same channel <-> device access works for any PCI_SLOT()
210 * value, we cheat a bit here and bind the controller's config
211 * space to devfn 0 in order to enable self-enumeration. In this
212 * case the regular ECAR/ECDR path is sidelined and the mangled
213 * config access itself is initiated as an internal bus transaction.
214 */
215 if (pci_is_root_bus(bus)) {
216 if (dev != 0)
217 return PCIBIOS_DEVICE_NOT_FOUND;
218
219 if (access_type == RCAR_PCI_ACCESS_READ) {
220 *data = rcar_pci_read_reg(pcie, PCICONF(index));
221 } else {
222 /* Keep an eye out for changes to the root bus number */
223 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
224 pcie->root_bus_nr = *data & 0xff;
225
226 rcar_pci_write_reg(pcie, *data, PCICONF(index));
227 }
228
229 return PCIBIOS_SUCCESSFUL;
230 }
231
232 if (pcie->root_bus_nr < 0)
233 return PCIBIOS_DEVICE_NOT_FOUND;
234
235 /* Clear errors */
236 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
237
238 /* Set the PIO address */
239 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
240 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
241
242 /* Enable the configuration access */
243 if (bus->parent->number == pcie->root_bus_nr)
244 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
245 else
246 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
247
248 /* Check for errors */
249 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
250 return PCIBIOS_DEVICE_NOT_FOUND;
251
252 /* Check for master and target aborts */
253 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
254 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
255 return PCIBIOS_DEVICE_NOT_FOUND;
256
257 if (access_type == RCAR_PCI_ACCESS_READ)
258 *data = rcar_pci_read_reg(pcie, PCIECDR);
259 else
260 rcar_pci_write_reg(pcie, *data, PCIECDR);
261
262 /* Disable the configuration access */
263 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
264
265 return PCIBIOS_SUCCESSFUL;
266 }
267
268 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
269 int where, int size, u32 *val)
270 {
271 struct rcar_pcie *pcie = bus->sysdata;
272 int ret;
273
274 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
275 bus, devfn, where, val);
276 if (ret != PCIBIOS_SUCCESSFUL) {
277 *val = 0xffffffff;
278 return ret;
279 }
280
281 if (size == 1)
282 *val = (*val >> (8 * (where & 3))) & 0xff;
283 else if (size == 2)
284 *val = (*val >> (8 * (where & 2))) & 0xffff;
285
286 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
287 bus->number, devfn, where, size, (unsigned long)*val);
288
289 return ret;
290 }
291
292 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
293 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
294 int where, int size, u32 val)
295 {
296 struct rcar_pcie *pcie = bus->sysdata;
297 int shift, ret;
298 u32 data;
299
300 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
301 bus, devfn, where, &data);
302 if (ret != PCIBIOS_SUCCESSFUL)
303 return ret;
304
305 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
306 bus->number, devfn, where, size, (unsigned long)val);
307
308 if (size == 1) {
309 shift = 8 * (where & 3);
310 data &= ~(0xff << shift);
311 data |= ((val & 0xff) << shift);
312 } else if (size == 2) {
313 shift = 8 * (where & 2);
314 data &= ~(0xffff << shift);
315 data |= ((val & 0xffff) << shift);
316 } else
317 data = val;
318
319 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
320 bus, devfn, where, &data);
321
322 return ret;
323 }
324
325 static struct pci_ops rcar_pcie_ops = {
326 .read = rcar_pcie_read_conf,
327 .write = rcar_pcie_write_conf,
328 };
329
330 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
331 struct resource *res)
332 {
333 /* Setup PCIe address space mappings for each resource */
334 resource_size_t size;
335 resource_size_t res_start;
336 u32 mask;
337
338 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
339
340 /*
341 * The PAMR mask is calculated in units of 128Bytes, which
342 * keeps things pretty simple.
343 */
344 size = resource_size(res);
345 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
346 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
347
348 if (res->flags & IORESOURCE_IO)
349 res_start = pci_pio_to_address(res->start);
350 else
351 res_start = res->start;
352
353 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
354 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
355 PCIEPALR(win));
356
357 /* First resource is for IO */
358 mask = PAR_ENABLE;
359 if (res->flags & IORESOURCE_IO)
360 mask |= IO_SPACE;
361
362 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
363 }
364
365 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
366 {
367 struct resource_entry *win;
368 int i = 0;
369
370 /* Setup PCI resources */
371 resource_list_for_each_entry(win, &pci->resources) {
372 struct resource *res = win->res;
373
374 if (!res->flags)
375 continue;
376
377 switch (resource_type(res)) {
378 case IORESOURCE_IO:
379 case IORESOURCE_MEM:
380 rcar_pcie_setup_window(i, pci, res);
381 i++;
382 break;
383 case IORESOURCE_BUS:
384 pci->root_bus_nr = res->start;
385 break;
386 default:
387 continue;
388 }
389
390 pci_add_resource(resource, res);
391 }
392
393 return 1;
394 }
395
396 static void rcar_pcie_force_speedup(struct rcar_pcie *pcie)
397 {
398 struct device *dev = pcie->dev;
399 unsigned int timeout = 1000;
400 u32 macsr;
401
402 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS)
403 return;
404
405 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) {
406 dev_err(dev, "Speed change already in progress\n");
407 return;
408 }
409
410 macsr = rcar_pci_read_reg(pcie, MACSR);
411 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS)
412 goto done;
413
414 /* Set target link speed to 5.0 GT/s */
415 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
416 PCI_EXP_LNKSTA_CLS_5_0GB);
417
418 /* Set speed change reason as intentional factor */
419 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0);
420
421 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
422 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL))
423 rcar_pci_write_reg(pcie, macsr, MACSR);
424
425 /* Start link speed change */
426 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE);
427
428 while (timeout--) {
429 macsr = rcar_pci_read_reg(pcie, MACSR);
430 if (macsr & SPCHGFIN) {
431 /* Clear the interrupt bits */
432 rcar_pci_write_reg(pcie, macsr, MACSR);
433
434 if (macsr & SPCHGFAIL)
435 dev_err(dev, "Speed change failed\n");
436
437 goto done;
438 }
439
440 msleep(1);
441 };
442
443 dev_err(dev, "Speed change timed out\n");
444
445 done:
446 dev_info(dev, "Current link speed is %s GT/s\n",
447 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5");
448 }
449
450 static int rcar_pcie_enable(struct rcar_pcie *pcie)
451 {
452 struct device *dev = pcie->dev;
453 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
454 struct pci_bus *bus, *child;
455 int ret;
456
457 /* Try setting 5 GT/s link speed */
458 rcar_pcie_force_speedup(pcie);
459
460 rcar_pcie_setup(&bridge->windows, pcie);
461
462 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
463
464 bridge->dev.parent = dev;
465 bridge->sysdata = pcie;
466 bridge->busnr = pcie->root_bus_nr;
467 bridge->ops = &rcar_pcie_ops;
468 bridge->map_irq = of_irq_parse_and_map_pci;
469 bridge->swizzle_irq = pci_common_swizzle;
470 if (IS_ENABLED(CONFIG_PCI_MSI))
471 bridge->msi = &pcie->msi.chip;
472
473 ret = pci_scan_root_bus_bridge(bridge);
474 if (ret < 0)
475 return ret;
476
477 bus = bridge->bus;
478
479 pci_bus_size_bridges(bus);
480 pci_bus_assign_resources(bus);
481
482 list_for_each_entry(child, &bus->children, node)
483 pcie_bus_configure_settings(child);
484
485 pci_bus_add_devices(bus);
486
487 return 0;
488 }
489
490 static int phy_wait_for_ack(struct rcar_pcie *pcie)
491 {
492 struct device *dev = pcie->dev;
493 unsigned int timeout = 100;
494
495 while (timeout--) {
496 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
497 return 0;
498
499 udelay(100);
500 }
501
502 dev_err(dev, "Access to PCIe phy timed out\n");
503
504 return -ETIMEDOUT;
505 }
506
507 static void phy_write_reg(struct rcar_pcie *pcie,
508 unsigned int rate, unsigned int addr,
509 unsigned int lane, unsigned int data)
510 {
511 unsigned long phyaddr;
512
513 phyaddr = WRITE_CMD |
514 ((rate & 1) << RATE_POS) |
515 ((lane & 0xf) << LANE_POS) |
516 ((addr & 0xff) << ADR_POS);
517
518 /* Set write data */
519 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
520 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
521
522 /* Ignore errors as they will be dealt with if the data link is down */
523 phy_wait_for_ack(pcie);
524
525 /* Clear command */
526 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
527 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
528
529 /* Ignore errors as they will be dealt with if the data link is down */
530 phy_wait_for_ack(pcie);
531 }
532
533 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
534 {
535 unsigned int timeout = 10;
536
537 while (timeout--) {
538 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
539 return 0;
540
541 msleep(5);
542 }
543
544 return -ETIMEDOUT;
545 }
546
547 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
548 {
549 int err;
550
551 /* Begin initialization */
552 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
553
554 /* Set mode */
555 rcar_pci_write_reg(pcie, 1, PCIEMSR);
556
557 /*
558 * Initial header for port config space is type 1, set the device
559 * class to match. Hardware takes care of propagating the IDSETR
560 * settings, so there is no need to bother with a quirk.
561 */
562 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
563
564 /*
565 * Setup Secondary Bus Number & Subordinate Bus Number, even though
566 * they aren't used, to avoid bridge being detected as broken.
567 */
568 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
569 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
570
571 /* Initialize default capabilities. */
572 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
573 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
574 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
575 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
576 PCI_HEADER_TYPE_BRIDGE);
577
578 /* Enable data link layer active state reporting */
579 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
580 PCI_EXP_LNKCAP_DLLLARC);
581
582 /* Write out the physical slot number = 0 */
583 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
584
585 /* Set the completion timer timeout to the maximum 50ms. */
586 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
587
588 /* Terminate list of capabilities (Next Capability Offset=0) */
589 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
590
591 /* Enable MSI */
592 if (IS_ENABLED(CONFIG_PCI_MSI))
593 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
594
595 /* Finish initialization - establish a PCI Express link */
596 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
597
598 /* This will timeout if we don't have a link. */
599 err = rcar_pcie_wait_for_dl(pcie);
600 if (err)
601 return err;
602
603 /* Enable INTx interrupts */
604 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
605
606 wmb();
607
608 return 0;
609 }
610
611 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
612 {
613 unsigned int timeout = 10;
614
615 /* Initialize the phy */
616 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
617 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
618 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
619 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
620 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
621 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
622 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
623 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
624 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
625 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
626 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
627 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
628
629 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
630 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
631 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
632
633 while (timeout--) {
634 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
635 return rcar_pcie_hw_init(pcie);
636
637 msleep(5);
638 }
639
640 return -ETIMEDOUT;
641 }
642
643 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
644 {
645 /*
646 * These settings come from the R-Car Series, 2nd Generation User's
647 * Manual, section 50.3.1 (2) Initialization of the physical layer.
648 */
649 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
650 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
651 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
652 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
653
654 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
655 /* The following value is for DC connection, no termination resistor */
656 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
657 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
658 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
659
660 return rcar_pcie_hw_init(pcie);
661 }
662
663 static int rcar_msi_alloc(struct rcar_msi *chip)
664 {
665 int msi;
666
667 mutex_lock(&chip->lock);
668
669 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
670 if (msi < INT_PCI_MSI_NR)
671 set_bit(msi, chip->used);
672 else
673 msi = -ENOSPC;
674
675 mutex_unlock(&chip->lock);
676
677 return msi;
678 }
679
680 static int rcar_msi_alloc_region(struct rcar_msi *chip, int no_irqs)
681 {
682 int msi;
683
684 mutex_lock(&chip->lock);
685 msi = bitmap_find_free_region(chip->used, INT_PCI_MSI_NR,
686 order_base_2(no_irqs));
687 mutex_unlock(&chip->lock);
688
689 return msi;
690 }
691
692 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
693 {
694 mutex_lock(&chip->lock);
695 clear_bit(irq, chip->used);
696 mutex_unlock(&chip->lock);
697 }
698
699 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
700 {
701 struct rcar_pcie *pcie = data;
702 struct rcar_msi *msi = &pcie->msi;
703 struct device *dev = pcie->dev;
704 unsigned long reg;
705
706 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
707
708 /* MSI & INTx share an interrupt - we only handle MSI here */
709 if (!reg)
710 return IRQ_NONE;
711
712 while (reg) {
713 unsigned int index = find_first_bit(&reg, 32);
714 unsigned int irq;
715
716 /* clear the interrupt */
717 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
718
719 irq = irq_find_mapping(msi->domain, index);
720 if (irq) {
721 if (test_bit(index, msi->used))
722 generic_handle_irq(irq);
723 else
724 dev_info(dev, "unhandled MSI\n");
725 } else {
726 /* Unknown MSI, just clear it */
727 dev_dbg(dev, "unexpected MSI\n");
728 }
729
730 /* see if there's any more pending in this vector */
731 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
732 }
733
734 return IRQ_HANDLED;
735 }
736
737 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
738 struct msi_desc *desc)
739 {
740 struct rcar_msi *msi = to_rcar_msi(chip);
741 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
742 struct msi_msg msg;
743 unsigned int irq;
744 int hwirq;
745
746 hwirq = rcar_msi_alloc(msi);
747 if (hwirq < 0)
748 return hwirq;
749
750 irq = irq_find_mapping(msi->domain, hwirq);
751 if (!irq) {
752 rcar_msi_free(msi, hwirq);
753 return -EINVAL;
754 }
755
756 irq_set_msi_desc(irq, desc);
757
758 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
759 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
760 msg.data = hwirq;
761
762 pci_write_msi_msg(irq, &msg);
763
764 return 0;
765 }
766
767 static int rcar_msi_setup_irqs(struct msi_controller *chip,
768 struct pci_dev *pdev, int nvec, int type)
769 {
770 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
771 struct rcar_msi *msi = to_rcar_msi(chip);
772 struct msi_desc *desc;
773 struct msi_msg msg;
774 unsigned int irq;
775 int hwirq;
776 int i;
777
778 /* MSI-X interrupts are not supported */
779 if (type == PCI_CAP_ID_MSIX)
780 return -EINVAL;
781
782 WARN_ON(!list_is_singular(&pdev->dev.msi_list));
783 desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
784
785 hwirq = rcar_msi_alloc_region(msi, nvec);
786 if (hwirq < 0)
787 return -ENOSPC;
788
789 irq = irq_find_mapping(msi->domain, hwirq);
790 if (!irq)
791 return -ENOSPC;
792
793 for (i = 0; i < nvec; i++) {
794 /*
795 * irq_create_mapping() called from rcar_pcie_probe() pre-
796 * allocates descs, so there is no need to allocate descs here.
797 * We can therefore assume that if irq_find_mapping() above
798 * returns non-zero, then the descs are also successfully
799 * allocated.
800 */
801 if (irq_set_msi_desc_off(irq, i, desc)) {
802 /* TODO: clear */
803 return -EINVAL;
804 }
805 }
806
807 desc->nvec_used = nvec;
808 desc->msi_attrib.multiple = order_base_2(nvec);
809
810 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
811 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
812 msg.data = hwirq;
813
814 pci_write_msi_msg(irq, &msg);
815
816 return 0;
817 }
818
819 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
820 {
821 struct rcar_msi *msi = to_rcar_msi(chip);
822 struct irq_data *d = irq_get_irq_data(irq);
823
824 rcar_msi_free(msi, d->hwirq);
825 }
826
827 static struct irq_chip rcar_msi_irq_chip = {
828 .name = "R-Car PCIe MSI",
829 .irq_enable = pci_msi_unmask_irq,
830 .irq_disable = pci_msi_mask_irq,
831 .irq_mask = pci_msi_mask_irq,
832 .irq_unmask = pci_msi_unmask_irq,
833 };
834
835 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
836 irq_hw_number_t hwirq)
837 {
838 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
839 irq_set_chip_data(irq, domain->host_data);
840
841 return 0;
842 }
843
844 static const struct irq_domain_ops msi_domain_ops = {
845 .map = rcar_msi_map,
846 };
847
848 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
849 {
850 struct device *dev = pcie->dev;
851 struct rcar_msi *msi = &pcie->msi;
852 unsigned long base;
853 int err, i;
854
855 mutex_init(&msi->lock);
856
857 msi->chip.dev = dev;
858 msi->chip.setup_irq = rcar_msi_setup_irq;
859 msi->chip.setup_irqs = rcar_msi_setup_irqs;
860 msi->chip.teardown_irq = rcar_msi_teardown_irq;
861
862 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
863 &msi_domain_ops, &msi->chip);
864 if (!msi->domain) {
865 dev_err(dev, "failed to create IRQ domain\n");
866 return -ENOMEM;
867 }
868
869 for (i = 0; i < INT_PCI_MSI_NR; i++)
870 irq_create_mapping(msi->domain, i);
871
872 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
873 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq,
874 IRQF_SHARED | IRQF_NO_THREAD,
875 rcar_msi_irq_chip.name, pcie);
876 if (err < 0) {
877 dev_err(dev, "failed to request IRQ: %d\n", err);
878 goto err;
879 }
880
881 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq,
882 IRQF_SHARED | IRQF_NO_THREAD,
883 rcar_msi_irq_chip.name, pcie);
884 if (err < 0) {
885 dev_err(dev, "failed to request IRQ: %d\n", err);
886 goto err;
887 }
888
889 /* setup MSI data target */
890 msi->pages = __get_free_pages(GFP_KERNEL, 0);
891 base = virt_to_phys((void *)msi->pages);
892
893 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
894 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
895
896 /* enable all MSI interrupts */
897 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
898
899 return 0;
900
901 err:
902 irq_domain_remove(msi->domain);
903 return err;
904 }
905
906 static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
907 {
908 struct device *dev = pcie->dev;
909 struct resource res;
910 int err, i;
911
912 err = of_address_to_resource(dev->of_node, 0, &res);
913 if (err)
914 return err;
915
916 pcie->base = devm_ioremap_resource(dev, &res);
917 if (IS_ERR(pcie->base))
918 return PTR_ERR(pcie->base);
919
920 pcie->clk = devm_clk_get(dev, "pcie");
921 if (IS_ERR(pcie->clk)) {
922 dev_err(dev, "cannot get platform clock\n");
923 return PTR_ERR(pcie->clk);
924 }
925 err = clk_prepare_enable(pcie->clk);
926 if (err)
927 return err;
928
929 pcie->bus_clk = devm_clk_get(dev, "pcie_bus");
930 if (IS_ERR(pcie->bus_clk)) {
931 dev_err(dev, "cannot get pcie bus clock\n");
932 err = PTR_ERR(pcie->bus_clk);
933 goto fail_clk;
934 }
935 err = clk_prepare_enable(pcie->bus_clk);
936 if (err)
937 goto fail_clk;
938
939 i = irq_of_parse_and_map(dev->of_node, 0);
940 if (!i) {
941 dev_err(dev, "cannot get platform resources for msi interrupt\n");
942 err = -ENOENT;
943 goto err_map_reg;
944 }
945 pcie->msi.irq1 = i;
946
947 i = irq_of_parse_and_map(dev->of_node, 1);
948 if (!i) {
949 dev_err(dev, "cannot get platform resources for msi interrupt\n");
950 err = -ENOENT;
951 goto err_map_reg;
952 }
953 pcie->msi.irq2 = i;
954
955 return 0;
956
957 err_map_reg:
958 clk_disable_unprepare(pcie->bus_clk);
959 fail_clk:
960 clk_disable_unprepare(pcie->clk);
961
962 return err;
963 }
964
965 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
966 struct of_pci_range *range,
967 int *index)
968 {
969 u64 restype = range->flags;
970 u64 cpu_addr = range->cpu_addr;
971 u64 cpu_end = range->cpu_addr + range->size;
972 u64 pci_addr = range->pci_addr;
973 u32 flags = LAM_64BIT | LAR_ENABLE;
974 u64 mask;
975 u64 size;
976 int idx = *index;
977
978 if (restype & IORESOURCE_PREFETCH)
979 flags |= LAM_PREFETCH;
980
981 /*
982 * If the size of the range is larger than the alignment of the start
983 * address, we have to use multiple entries to perform the mapping.
984 */
985 if (cpu_addr > 0) {
986 unsigned long nr_zeros = __ffs64(cpu_addr);
987 u64 alignment = 1ULL << nr_zeros;
988
989 size = min(range->size, alignment);
990 } else {
991 size = range->size;
992 }
993 /* Hardware supports max 4GiB inbound region */
994 size = min(size, 1ULL << 32);
995
996 mask = roundup_pow_of_two(size) - 1;
997 mask &= ~0xf;
998
999 while (cpu_addr < cpu_end) {
1000 /*
1001 * Set up 64-bit inbound regions as the range parser doesn't
1002 * distinguish between 32 and 64-bit types.
1003 */
1004 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
1005 PCIEPRAR(idx));
1006 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
1007 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags,
1008 PCIELAMR(idx));
1009
1010 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
1011 PCIEPRAR(idx + 1));
1012 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr),
1013 PCIELAR(idx + 1));
1014 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
1015
1016 pci_addr += size;
1017 cpu_addr += size;
1018 idx += 2;
1019
1020 if (idx > MAX_NR_INBOUND_MAPS) {
1021 dev_err(pcie->dev, "Failed to map inbound regions!\n");
1022 return -EINVAL;
1023 }
1024 }
1025 *index = idx;
1026
1027 return 0;
1028 }
1029
1030 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
1031 struct device_node *np)
1032 {
1033 struct of_pci_range range;
1034 struct of_pci_range_parser parser;
1035 int index = 0;
1036 int err;
1037
1038 if (of_pci_dma_range_parser_init(&parser, np))
1039 return -EINVAL;
1040
1041 /* Get the dma-ranges from DT */
1042 for_each_of_pci_range(&parser, &range) {
1043 u64 end = range.cpu_addr + range.size - 1;
1044
1045 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1046 range.flags, range.cpu_addr, end, range.pci_addr);
1047
1048 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
1049 if (err)
1050 return err;
1051 }
1052
1053 return 0;
1054 }
1055
1056 static const struct of_device_id rcar_pcie_of_match[] = {
1057 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
1058 { .compatible = "renesas,pcie-r8a7790",
1059 .data = rcar_pcie_hw_init_gen2 },
1060 { .compatible = "renesas,pcie-r8a7791",
1061 .data = rcar_pcie_hw_init_gen2 },
1062 { .compatible = "renesas,pcie-rcar-gen2",
1063 .data = rcar_pcie_hw_init_gen2 },
1064 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
1065 { .compatible = "renesas,pcie-rcar-gen3", .data = rcar_pcie_hw_init },
1066 {},
1067 };
1068
1069 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
1070 {
1071 int err;
1072 struct device *dev = pci->dev;
1073 struct device_node *np = dev->of_node;
1074 resource_size_t iobase;
1075 struct resource_entry *win, *tmp;
1076
1077 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources,
1078 &iobase);
1079 if (err)
1080 return err;
1081
1082 err = devm_request_pci_bus_resources(dev, &pci->resources);
1083 if (err)
1084 goto out_release_res;
1085
1086 resource_list_for_each_entry_safe(win, tmp, &pci->resources) {
1087 struct resource *res = win->res;
1088
1089 if (resource_type(res) == IORESOURCE_IO) {
1090 err = pci_remap_iospace(res, iobase);
1091 if (err) {
1092 dev_warn(dev, "error %d: failed to map resource %pR\n",
1093 err, res);
1094
1095 resource_list_destroy_entry(win);
1096 }
1097 }
1098 }
1099
1100 return 0;
1101
1102 out_release_res:
1103 pci_free_resource_list(&pci->resources);
1104 return err;
1105 }
1106
1107 static int rcar_pcie_probe(struct platform_device *pdev)
1108 {
1109 struct device *dev = &pdev->dev;
1110 struct rcar_pcie *pcie;
1111 unsigned int data;
1112 int err;
1113 int (*hw_init_fn)(struct rcar_pcie *);
1114 struct pci_host_bridge *bridge;
1115
1116 bridge = pci_alloc_host_bridge(sizeof(*pcie));
1117 if (!bridge)
1118 return -ENOMEM;
1119
1120 pcie = pci_host_bridge_priv(bridge);
1121
1122 pcie->dev = dev;
1123
1124 INIT_LIST_HEAD(&pcie->resources);
1125
1126 rcar_pcie_parse_request_of_pci_ranges(pcie);
1127
1128 err = rcar_pcie_get_resources(pcie);
1129 if (err < 0) {
1130 dev_err(dev, "failed to request resources: %d\n", err);
1131 goto err_free_resource_list;
1132 }
1133
1134 err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
1135 if (err)
1136 goto err_free_resource_list;
1137
1138 pm_runtime_enable(dev);
1139 err = pm_runtime_get_sync(dev);
1140 if (err < 0) {
1141 dev_err(dev, "pm_runtime_get_sync failed\n");
1142 goto err_pm_disable;
1143 }
1144
1145 /* Failure to get a link might just be that no cards are inserted */
1146 hw_init_fn = of_device_get_match_data(dev);
1147 err = hw_init_fn(pcie);
1148 if (err) {
1149 dev_info(dev, "PCIe link down\n");
1150 err = -ENODEV;
1151 goto err_pm_put;
1152 }
1153
1154 data = rcar_pci_read_reg(pcie, MACSR);
1155 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1156
1157 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1158 err = rcar_pcie_enable_msi(pcie);
1159 if (err < 0) {
1160 dev_err(dev,
1161 "failed to enable MSI support: %d\n",
1162 err);
1163 goto err_pm_put;
1164 }
1165 }
1166
1167 err = rcar_pcie_enable(pcie);
1168 if (err)
1169 goto err_pm_put;
1170
1171 return 0;
1172
1173 err_pm_put:
1174 pm_runtime_put(dev);
1175
1176 err_pm_disable:
1177 pm_runtime_disable(dev);
1178
1179 err_free_resource_list:
1180 pci_free_resource_list(&pcie->resources);
1181 pci_free_host_bridge(bridge);
1182
1183 return err;
1184 }
1185
1186 static struct platform_driver rcar_pcie_driver = {
1187 .driver = {
1188 .name = "rcar-pcie",
1189 .of_match_table = rcar_pcie_of_match,
1190 .suppress_bind_attrs = true,
1191 },
1192 .probe = rcar_pcie_probe,
1193 };
1194 builtin_platform_driver(rcar_pcie_driver);
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