2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
10 * Author: Phil Edworthy <phil.edworthy@renesas.com>
12 * This file is licensed under the terms of the GNU General Public
13 * License version 2. This program is licensed "as is" without any
14 * warranty of any kind, whether express or implied.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/slab.h>
34 #define DRV_NAME "rcar-pcie"
36 #define PCIECAR 0x000010
37 #define PCIECCTLR 0x000018
38 #define CONFIG_SEND_ENABLE (1 << 31)
39 #define TYPE0 (0 << 8)
40 #define TYPE1 (1 << 8)
41 #define PCIECDR 0x000020
42 #define PCIEMSR 0x000028
43 #define PCIEINTXR 0x000400
44 #define PCIEMSITXR 0x000840
46 /* Transfer control */
47 #define PCIETCTLR 0x02000
49 #define PCIETSTR 0x02004
50 #define DATA_LINK_ACTIVE 1
51 #define PCIEERRFR 0x02020
52 #define UNSUPPORTED_REQUEST (1 << 4)
53 #define PCIEMSIFR 0x02044
54 #define PCIEMSIALR 0x02048
56 #define PCIEMSIAUR 0x0204c
57 #define PCIEMSIIER 0x02050
59 /* root port address */
60 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
62 /* local address reg & mask */
63 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
64 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
65 #define LAM_PREFETCH (1 << 3)
66 #define LAM_64BIT (1 << 2)
67 #define LAR_ENABLE (1 << 1)
69 /* PCIe address reg & mask */
70 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
71 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
72 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
73 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
74 #define PAR_ENABLE (1 << 31)
75 #define IO_SPACE (1 << 8)
78 #define PCICONF(x) (0x010000 + ((x) * 0x4))
79 #define PMCAP(x) (0x010040 + ((x) * 0x4))
80 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
81 #define VCCAP(x) (0x010100 + ((x) * 0x4))
84 #define IDSETR1 0x011004
85 #define TLCTLR 0x011048
86 #define MACSR 0x011054
87 #define SPCHGFIN (1 << 4)
88 #define SPCHGFAIL (1 << 6)
89 #define SPCHGSUC (1 << 7)
90 #define LINK_SPEED (0xf << 16)
91 #define LINK_SPEED_2_5GTS (1 << 16)
92 #define LINK_SPEED_5_0GTS (2 << 16)
93 #define MACCTLR 0x011058
94 #define SPEED_CHANGE (1 << 24)
95 #define SCRAMBLE_DISABLE (1 << 27)
96 #define MACS2R 0x011078
97 #define MACCGSPSETR 0x011084
98 #define SPCNGRSN (1 << 31)
101 #define H1_PCIEPHYADRR 0x04000c
102 #define WRITE_CMD (1 << 16)
103 #define PHY_ACK (1 << 24)
107 #define H1_PCIEPHYDOUTR 0x040014
108 #define H1_PCIEPHYSR 0x040018
111 #define GEN2_PCIEPHYADDR 0x780
112 #define GEN2_PCIEPHYDATA 0x784
113 #define GEN2_PCIEPHYCTRL 0x78c
115 #define INT_PCI_MSI_NR 32
117 #define RCONF(x) (PCICONF(0)+(x))
118 #define RPMCAP(x) (PMCAP(0)+(x))
119 #define REXPCAP(x) (EXPCAP(0)+(x))
120 #define RVCCAP(x) (VCCAP(0)+(x))
122 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
123 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
124 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
126 #define RCAR_PCI_MAX_RESOURCES 4
127 #define MAX_NR_INBOUND_MAPS 6
130 DECLARE_BITMAP(used
, INT_PCI_MSI_NR
);
131 struct irq_domain
*domain
;
132 struct msi_controller chip
;
139 static inline struct rcar_msi
*to_rcar_msi(struct msi_controller
*chip
)
141 return container_of(chip
, struct rcar_msi
, chip
);
144 /* Structure representing the PCIe interface */
148 struct list_head resources
;
155 static void rcar_pci_write_reg(struct rcar_pcie
*pcie
, unsigned long val
,
158 writel(val
, pcie
->base
+ reg
);
161 static unsigned long rcar_pci_read_reg(struct rcar_pcie
*pcie
,
164 return readl(pcie
->base
+ reg
);
168 RCAR_PCI_ACCESS_READ
,
169 RCAR_PCI_ACCESS_WRITE
,
172 static void rcar_rmw32(struct rcar_pcie
*pcie
, int where
, u32 mask
, u32 data
)
174 int shift
= 8 * (where
& 3);
175 u32 val
= rcar_pci_read_reg(pcie
, where
& ~3);
177 val
&= ~(mask
<< shift
);
178 val
|= data
<< shift
;
179 rcar_pci_write_reg(pcie
, val
, where
& ~3);
182 static u32
rcar_read_conf(struct rcar_pcie
*pcie
, int where
)
184 int shift
= 8 * (where
& 3);
185 u32 val
= rcar_pci_read_reg(pcie
, where
& ~3);
190 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
191 static int rcar_pcie_config_access(struct rcar_pcie
*pcie
,
192 unsigned char access_type
, struct pci_bus
*bus
,
193 unsigned int devfn
, int where
, u32
*data
)
195 int dev
, func
, reg
, index
;
197 dev
= PCI_SLOT(devfn
);
198 func
= PCI_FUNC(devfn
);
203 * While each channel has its own memory-mapped extended config
204 * space, it's generally only accessible when in endpoint mode.
205 * When in root complex mode, the controller is unable to target
206 * itself with either type 0 or type 1 accesses, and indeed, any
207 * controller initiated target transfer to its own config space
208 * result in a completer abort.
210 * Each channel effectively only supports a single device, but as
211 * the same channel <-> device access works for any PCI_SLOT()
212 * value, we cheat a bit here and bind the controller's config
213 * space to devfn 0 in order to enable self-enumeration. In this
214 * case the regular ECAR/ECDR path is sidelined and the mangled
215 * config access itself is initiated as an internal bus transaction.
217 if (pci_is_root_bus(bus
)) {
219 return PCIBIOS_DEVICE_NOT_FOUND
;
221 if (access_type
== RCAR_PCI_ACCESS_READ
) {
222 *data
= rcar_pci_read_reg(pcie
, PCICONF(index
));
224 /* Keep an eye out for changes to the root bus number */
225 if (pci_is_root_bus(bus
) && (reg
== PCI_PRIMARY_BUS
))
226 pcie
->root_bus_nr
= *data
& 0xff;
228 rcar_pci_write_reg(pcie
, *data
, PCICONF(index
));
231 return PCIBIOS_SUCCESSFUL
;
234 if (pcie
->root_bus_nr
< 0)
235 return PCIBIOS_DEVICE_NOT_FOUND
;
238 rcar_pci_write_reg(pcie
, rcar_pci_read_reg(pcie
, PCIEERRFR
), PCIEERRFR
);
240 /* Set the PIO address */
241 rcar_pci_write_reg(pcie
, PCIE_CONF_BUS(bus
->number
) |
242 PCIE_CONF_DEV(dev
) | PCIE_CONF_FUNC(func
) | reg
, PCIECAR
);
244 /* Enable the configuration access */
245 if (bus
->parent
->number
== pcie
->root_bus_nr
)
246 rcar_pci_write_reg(pcie
, CONFIG_SEND_ENABLE
| TYPE0
, PCIECCTLR
);
248 rcar_pci_write_reg(pcie
, CONFIG_SEND_ENABLE
| TYPE1
, PCIECCTLR
);
250 /* Check for errors */
251 if (rcar_pci_read_reg(pcie
, PCIEERRFR
) & UNSUPPORTED_REQUEST
)
252 return PCIBIOS_DEVICE_NOT_FOUND
;
254 /* Check for master and target aborts */
255 if (rcar_read_conf(pcie
, RCONF(PCI_STATUS
)) &
256 (PCI_STATUS_REC_MASTER_ABORT
| PCI_STATUS_REC_TARGET_ABORT
))
257 return PCIBIOS_DEVICE_NOT_FOUND
;
259 if (access_type
== RCAR_PCI_ACCESS_READ
)
260 *data
= rcar_pci_read_reg(pcie
, PCIECDR
);
262 rcar_pci_write_reg(pcie
, *data
, PCIECDR
);
264 /* Disable the configuration access */
265 rcar_pci_write_reg(pcie
, 0, PCIECCTLR
);
267 return PCIBIOS_SUCCESSFUL
;
270 static int rcar_pcie_read_conf(struct pci_bus
*bus
, unsigned int devfn
,
271 int where
, int size
, u32
*val
)
273 struct rcar_pcie
*pcie
= bus
->sysdata
;
276 ret
= rcar_pcie_config_access(pcie
, RCAR_PCI_ACCESS_READ
,
277 bus
, devfn
, where
, val
);
278 if (ret
!= PCIBIOS_SUCCESSFUL
) {
284 *val
= (*val
>> (8 * (where
& 3))) & 0xff;
286 *val
= (*val
>> (8 * (where
& 2))) & 0xffff;
288 dev_dbg(&bus
->dev
, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
289 bus
->number
, devfn
, where
, size
, (unsigned long)*val
);
294 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
295 static int rcar_pcie_write_conf(struct pci_bus
*bus
, unsigned int devfn
,
296 int where
, int size
, u32 val
)
298 struct rcar_pcie
*pcie
= bus
->sysdata
;
302 ret
= rcar_pcie_config_access(pcie
, RCAR_PCI_ACCESS_READ
,
303 bus
, devfn
, where
, &data
);
304 if (ret
!= PCIBIOS_SUCCESSFUL
)
307 dev_dbg(&bus
->dev
, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
308 bus
->number
, devfn
, where
, size
, (unsigned long)val
);
311 shift
= 8 * (where
& 3);
312 data
&= ~(0xff << shift
);
313 data
|= ((val
& 0xff) << shift
);
314 } else if (size
== 2) {
315 shift
= 8 * (where
& 2);
316 data
&= ~(0xffff << shift
);
317 data
|= ((val
& 0xffff) << shift
);
321 ret
= rcar_pcie_config_access(pcie
, RCAR_PCI_ACCESS_WRITE
,
322 bus
, devfn
, where
, &data
);
327 static struct pci_ops rcar_pcie_ops
= {
328 .read
= rcar_pcie_read_conf
,
329 .write
= rcar_pcie_write_conf
,
332 static void rcar_pcie_setup_window(int win
, struct rcar_pcie
*pcie
,
333 struct resource
*res
)
335 /* Setup PCIe address space mappings for each resource */
336 resource_size_t size
;
337 resource_size_t res_start
;
340 rcar_pci_write_reg(pcie
, 0x00000000, PCIEPTCTLR(win
));
343 * The PAMR mask is calculated in units of 128Bytes, which
344 * keeps things pretty simple.
346 size
= resource_size(res
);
347 mask
= (roundup_pow_of_two(size
) / SZ_128
) - 1;
348 rcar_pci_write_reg(pcie
, mask
<< 7, PCIEPAMR(win
));
350 if (res
->flags
& IORESOURCE_IO
)
351 res_start
= pci_pio_to_address(res
->start
);
353 res_start
= res
->start
;
355 rcar_pci_write_reg(pcie
, upper_32_bits(res_start
), PCIEPAUR(win
));
356 rcar_pci_write_reg(pcie
, lower_32_bits(res_start
) & ~0x7F,
359 /* First resource is for IO */
361 if (res
->flags
& IORESOURCE_IO
)
364 rcar_pci_write_reg(pcie
, mask
, PCIEPTCTLR(win
));
367 static int rcar_pcie_setup(struct list_head
*resource
, struct rcar_pcie
*pci
)
369 struct resource_entry
*win
;
372 /* Setup PCI resources */
373 resource_list_for_each_entry(win
, &pci
->resources
) {
374 struct resource
*res
= win
->res
;
379 switch (resource_type(res
)) {
382 rcar_pcie_setup_window(i
, pci
, res
);
386 pci
->root_bus_nr
= res
->start
;
392 pci_add_resource(resource
, res
);
398 static void rcar_pcie_force_speedup(struct rcar_pcie
*pcie
)
400 unsigned int timeout
= 1000;
403 if ((rcar_pci_read_reg(pcie
, MACS2R
) & LINK_SPEED
) != LINK_SPEED_5_0GTS
)
406 if (rcar_pci_read_reg(pcie
, MACCTLR
) & SPEED_CHANGE
) {
407 dev_err(pcie
->dev
, "Speed change already in progress\n");
411 macsr
= rcar_pci_read_reg(pcie
, MACSR
);
412 if ((macsr
& LINK_SPEED
) == LINK_SPEED_5_0GTS
)
415 /* Set target link speed to 5.0 GT/s */
416 rcar_rmw32(pcie
, EXPCAP(12), PCI_EXP_LNKSTA_CLS
,
417 PCI_EXP_LNKSTA_CLS_5_0GB
);
419 /* Set speed change reason as intentional factor */
420 rcar_rmw32(pcie
, MACCGSPSETR
, SPCNGRSN
, 0);
422 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */
423 if (macsr
& (SPCHGFIN
| SPCHGSUC
| SPCHGFAIL
))
424 rcar_pci_write_reg(pcie
, macsr
, MACSR
);
426 /* Start link speed change */
427 rcar_rmw32(pcie
, MACCTLR
, SPEED_CHANGE
, SPEED_CHANGE
);
430 macsr
= rcar_pci_read_reg(pcie
, MACSR
);
431 if (macsr
& SPCHGFIN
) {
432 /* Clear the interrupt bits */
433 rcar_pci_write_reg(pcie
, macsr
, MACSR
);
435 if (macsr
& SPCHGFAIL
)
436 dev_err(pcie
->dev
, "Speed change failed\n");
444 dev_err(pcie
->dev
, "Speed change timed out\n");
447 dev_info(pcie
->dev
, "Current link speed is %s GT/s\n",
448 (macsr
& LINK_SPEED
) == LINK_SPEED_5_0GTS
? "5" : "2.5");
451 static int rcar_pcie_enable(struct rcar_pcie
*pcie
)
453 struct pci_bus
*bus
, *child
;
456 /* Try setting 5 GT/s link speed */
457 rcar_pcie_force_speedup(pcie
);
459 rcar_pcie_setup(&res
, pcie
);
461 pci_add_flags(PCI_REASSIGN_ALL_RSRC
| PCI_REASSIGN_ALL_BUS
);
463 if (IS_ENABLED(CONFIG_PCI_MSI
))
464 bus
= pci_scan_root_bus_msi(pcie
->dev
, pcie
->root_bus_nr
,
465 &rcar_pcie_ops
, pcie
, &res
, &pcie
->msi
.chip
);
467 bus
= pci_scan_root_bus(pcie
->dev
, pcie
->root_bus_nr
,
468 &rcar_pcie_ops
, pcie
, &res
);
471 dev_err(pcie
->dev
, "Scanning rootbus failed");
475 pci_fixup_irqs(pci_common_swizzle
, of_irq_parse_and_map_pci
);
477 pci_bus_size_bridges(bus
);
478 pci_bus_assign_resources(bus
);
480 list_for_each_entry(child
, &bus
->children
, node
)
481 pcie_bus_configure_settings(child
);
483 pci_bus_add_devices(bus
);
488 static int phy_wait_for_ack(struct rcar_pcie
*pcie
)
490 unsigned int timeout
= 100;
493 if (rcar_pci_read_reg(pcie
, H1_PCIEPHYADRR
) & PHY_ACK
)
499 dev_err(pcie
->dev
, "Access to PCIe phy timed out\n");
504 static void phy_write_reg(struct rcar_pcie
*pcie
,
505 unsigned int rate
, unsigned int addr
,
506 unsigned int lane
, unsigned int data
)
508 unsigned long phyaddr
;
510 phyaddr
= WRITE_CMD
|
511 ((rate
& 1) << RATE_POS
) |
512 ((lane
& 0xf) << LANE_POS
) |
513 ((addr
& 0xff) << ADR_POS
);
516 rcar_pci_write_reg(pcie
, data
, H1_PCIEPHYDOUTR
);
517 rcar_pci_write_reg(pcie
, phyaddr
, H1_PCIEPHYADRR
);
519 /* Ignore errors as they will be dealt with if the data link is down */
520 phy_wait_for_ack(pcie
);
523 rcar_pci_write_reg(pcie
, 0, H1_PCIEPHYDOUTR
);
524 rcar_pci_write_reg(pcie
, 0, H1_PCIEPHYADRR
);
526 /* Ignore errors as they will be dealt with if the data link is down */
527 phy_wait_for_ack(pcie
);
530 static int rcar_pcie_wait_for_dl(struct rcar_pcie
*pcie
)
532 unsigned int timeout
= 10;
535 if ((rcar_pci_read_reg(pcie
, PCIETSTR
) & DATA_LINK_ACTIVE
))
544 static int rcar_pcie_hw_init(struct rcar_pcie
*pcie
)
548 /* Begin initialization */
549 rcar_pci_write_reg(pcie
, 0, PCIETCTLR
);
552 rcar_pci_write_reg(pcie
, 1, PCIEMSR
);
555 * Initial header for port config space is type 1, set the device
556 * class to match. Hardware takes care of propagating the IDSETR
557 * settings, so there is no need to bother with a quirk.
559 rcar_pci_write_reg(pcie
, PCI_CLASS_BRIDGE_PCI
<< 16, IDSETR1
);
562 * Setup Secondary Bus Number & Subordinate Bus Number, even though
563 * they aren't used, to avoid bridge being detected as broken.
565 rcar_rmw32(pcie
, RCONF(PCI_SECONDARY_BUS
), 0xff, 1);
566 rcar_rmw32(pcie
, RCONF(PCI_SUBORDINATE_BUS
), 0xff, 1);
568 /* Initialize default capabilities. */
569 rcar_rmw32(pcie
, REXPCAP(0), 0xff, PCI_CAP_ID_EXP
);
570 rcar_rmw32(pcie
, REXPCAP(PCI_EXP_FLAGS
),
571 PCI_EXP_FLAGS_TYPE
, PCI_EXP_TYPE_ROOT_PORT
<< 4);
572 rcar_rmw32(pcie
, RCONF(PCI_HEADER_TYPE
), 0x7f,
573 PCI_HEADER_TYPE_BRIDGE
);
575 /* Enable data link layer active state reporting */
576 rcar_rmw32(pcie
, REXPCAP(PCI_EXP_LNKCAP
), PCI_EXP_LNKCAP_DLLLARC
,
577 PCI_EXP_LNKCAP_DLLLARC
);
579 /* Write out the physical slot number = 0 */
580 rcar_rmw32(pcie
, REXPCAP(PCI_EXP_SLTCAP
), PCI_EXP_SLTCAP_PSN
, 0);
582 /* Set the completion timer timeout to the maximum 50ms. */
583 rcar_rmw32(pcie
, TLCTLR
+ 1, 0x3f, 50);
585 /* Terminate list of capabilities (Next Capability Offset=0) */
586 rcar_rmw32(pcie
, RVCCAP(0), 0xfff00000, 0);
589 if (IS_ENABLED(CONFIG_PCI_MSI
))
590 rcar_pci_write_reg(pcie
, 0x801f0000, PCIEMSITXR
);
592 /* Finish initialization - establish a PCI Express link */
593 rcar_pci_write_reg(pcie
, CFINIT
, PCIETCTLR
);
595 /* This will timeout if we don't have a link. */
596 err
= rcar_pcie_wait_for_dl(pcie
);
600 /* Enable INTx interrupts */
601 rcar_rmw32(pcie
, PCIEINTXR
, 0, 0xF << 8);
608 static int rcar_pcie_hw_init_h1(struct rcar_pcie
*pcie
)
610 unsigned int timeout
= 10;
612 /* Initialize the phy */
613 phy_write_reg(pcie
, 0, 0x42, 0x1, 0x0EC34191);
614 phy_write_reg(pcie
, 1, 0x42, 0x1, 0x0EC34180);
615 phy_write_reg(pcie
, 0, 0x43, 0x1, 0x00210188);
616 phy_write_reg(pcie
, 1, 0x43, 0x1, 0x00210188);
617 phy_write_reg(pcie
, 0, 0x44, 0x1, 0x015C0014);
618 phy_write_reg(pcie
, 1, 0x44, 0x1, 0x015C0014);
619 phy_write_reg(pcie
, 1, 0x4C, 0x1, 0x786174A0);
620 phy_write_reg(pcie
, 1, 0x4D, 0x1, 0x048000BB);
621 phy_write_reg(pcie
, 0, 0x51, 0x1, 0x079EC062);
622 phy_write_reg(pcie
, 0, 0x52, 0x1, 0x20000000);
623 phy_write_reg(pcie
, 1, 0x52, 0x1, 0x20000000);
624 phy_write_reg(pcie
, 1, 0x56, 0x1, 0x00003806);
626 phy_write_reg(pcie
, 0, 0x60, 0x1, 0x004B03A5);
627 phy_write_reg(pcie
, 0, 0x64, 0x1, 0x3F0F1F0F);
628 phy_write_reg(pcie
, 0, 0x66, 0x1, 0x00008000);
631 if (rcar_pci_read_reg(pcie
, H1_PCIEPHYSR
))
632 return rcar_pcie_hw_init(pcie
);
640 static int rcar_pcie_hw_init_gen2(struct rcar_pcie
*pcie
)
643 * These settings come from the R-Car Series, 2nd Generation User's
644 * Manual, section 50.3.1 (2) Initialization of the physical layer.
646 rcar_pci_write_reg(pcie
, 0x000f0030, GEN2_PCIEPHYADDR
);
647 rcar_pci_write_reg(pcie
, 0x00381203, GEN2_PCIEPHYDATA
);
648 rcar_pci_write_reg(pcie
, 0x00000001, GEN2_PCIEPHYCTRL
);
649 rcar_pci_write_reg(pcie
, 0x00000006, GEN2_PCIEPHYCTRL
);
651 rcar_pci_write_reg(pcie
, 0x000f0054, GEN2_PCIEPHYADDR
);
652 /* The following value is for DC connection, no termination resistor */
653 rcar_pci_write_reg(pcie
, 0x13802007, GEN2_PCIEPHYDATA
);
654 rcar_pci_write_reg(pcie
, 0x00000001, GEN2_PCIEPHYCTRL
);
655 rcar_pci_write_reg(pcie
, 0x00000006, GEN2_PCIEPHYCTRL
);
657 return rcar_pcie_hw_init(pcie
);
660 static int rcar_msi_alloc(struct rcar_msi
*chip
)
664 mutex_lock(&chip
->lock
);
666 msi
= find_first_zero_bit(chip
->used
, INT_PCI_MSI_NR
);
667 if (msi
< INT_PCI_MSI_NR
)
668 set_bit(msi
, chip
->used
);
672 mutex_unlock(&chip
->lock
);
677 static int rcar_msi_alloc_region(struct rcar_msi
*chip
, int no_irqs
)
681 mutex_lock(&chip
->lock
);
682 msi
= bitmap_find_free_region(chip
->used
, INT_PCI_MSI_NR
,
683 order_base_2(no_irqs
));
684 mutex_unlock(&chip
->lock
);
689 static void rcar_msi_free(struct rcar_msi
*chip
, unsigned long irq
)
691 mutex_lock(&chip
->lock
);
692 clear_bit(irq
, chip
->used
);
693 mutex_unlock(&chip
->lock
);
696 static irqreturn_t
rcar_pcie_msi_irq(int irq
, void *data
)
698 struct rcar_pcie
*pcie
= data
;
699 struct rcar_msi
*msi
= &pcie
->msi
;
702 reg
= rcar_pci_read_reg(pcie
, PCIEMSIFR
);
704 /* MSI & INTx share an interrupt - we only handle MSI here */
709 unsigned int index
= find_first_bit(®
, 32);
712 /* clear the interrupt */
713 rcar_pci_write_reg(pcie
, 1 << index
, PCIEMSIFR
);
715 irq
= irq_find_mapping(msi
->domain
, index
);
717 if (test_bit(index
, msi
->used
))
718 generic_handle_irq(irq
);
720 dev_info(pcie
->dev
, "unhandled MSI\n");
722 /* Unknown MSI, just clear it */
723 dev_dbg(pcie
->dev
, "unexpected MSI\n");
726 /* see if there's any more pending in this vector */
727 reg
= rcar_pci_read_reg(pcie
, PCIEMSIFR
);
733 static int rcar_msi_setup_irq(struct msi_controller
*chip
, struct pci_dev
*pdev
,
734 struct msi_desc
*desc
)
736 struct rcar_msi
*msi
= to_rcar_msi(chip
);
737 struct rcar_pcie
*pcie
= container_of(chip
, struct rcar_pcie
, msi
.chip
);
742 hwirq
= rcar_msi_alloc(msi
);
746 irq
= irq_find_mapping(msi
->domain
, hwirq
);
748 rcar_msi_free(msi
, hwirq
);
752 irq_set_msi_desc(irq
, desc
);
754 msg
.address_lo
= rcar_pci_read_reg(pcie
, PCIEMSIALR
) & ~MSIFE
;
755 msg
.address_hi
= rcar_pci_read_reg(pcie
, PCIEMSIAUR
);
758 pci_write_msi_msg(irq
, &msg
);
763 static int rcar_msi_setup_irqs(struct msi_controller
*chip
,
764 struct pci_dev
*pdev
, int nvec
, int type
)
766 struct rcar_pcie
*pcie
= container_of(chip
, struct rcar_pcie
, msi
.chip
);
767 struct rcar_msi
*msi
= to_rcar_msi(chip
);
768 struct msi_desc
*desc
;
774 /* MSI-X interrupts are not supported */
775 if (type
== PCI_CAP_ID_MSIX
)
778 WARN_ON(!list_is_singular(&pdev
->dev
.msi_list
));
779 desc
= list_entry(pdev
->dev
.msi_list
.next
, struct msi_desc
, list
);
781 hwirq
= rcar_msi_alloc_region(msi
, nvec
);
785 irq
= irq_find_mapping(msi
->domain
, hwirq
);
789 for (i
= 0; i
< nvec
; i
++) {
791 * irq_create_mapping() called from rcar_pcie_probe() pre-
792 * allocates descs, so there is no need to allocate descs here.
793 * We can therefore assume that if irq_find_mapping() above
794 * returns non-zero, then the descs are also successfully
797 if (irq_set_msi_desc_off(irq
, i
, desc
)) {
803 desc
->nvec_used
= nvec
;
804 desc
->msi_attrib
.multiple
= order_base_2(nvec
);
806 msg
.address_lo
= rcar_pci_read_reg(pcie
, PCIEMSIALR
) & ~MSIFE
;
807 msg
.address_hi
= rcar_pci_read_reg(pcie
, PCIEMSIAUR
);
810 pci_write_msi_msg(irq
, &msg
);
815 static void rcar_msi_teardown_irq(struct msi_controller
*chip
, unsigned int irq
)
817 struct rcar_msi
*msi
= to_rcar_msi(chip
);
818 struct irq_data
*d
= irq_get_irq_data(irq
);
820 rcar_msi_free(msi
, d
->hwirq
);
823 static struct irq_chip rcar_msi_irq_chip
= {
824 .name
= "R-Car PCIe MSI",
825 .irq_enable
= pci_msi_unmask_irq
,
826 .irq_disable
= pci_msi_mask_irq
,
827 .irq_mask
= pci_msi_mask_irq
,
828 .irq_unmask
= pci_msi_unmask_irq
,
831 static int rcar_msi_map(struct irq_domain
*domain
, unsigned int irq
,
832 irq_hw_number_t hwirq
)
834 irq_set_chip_and_handler(irq
, &rcar_msi_irq_chip
, handle_simple_irq
);
835 irq_set_chip_data(irq
, domain
->host_data
);
840 static const struct irq_domain_ops msi_domain_ops
= {
844 static int rcar_pcie_enable_msi(struct rcar_pcie
*pcie
)
846 struct platform_device
*pdev
= to_platform_device(pcie
->dev
);
847 struct rcar_msi
*msi
= &pcie
->msi
;
851 mutex_init(&msi
->lock
);
853 msi
->chip
.dev
= pcie
->dev
;
854 msi
->chip
.setup_irq
= rcar_msi_setup_irq
;
855 msi
->chip
.setup_irqs
= rcar_msi_setup_irqs
;
856 msi
->chip
.teardown_irq
= rcar_msi_teardown_irq
;
858 msi
->domain
= irq_domain_add_linear(pcie
->dev
->of_node
, INT_PCI_MSI_NR
,
859 &msi_domain_ops
, &msi
->chip
);
861 dev_err(&pdev
->dev
, "failed to create IRQ domain\n");
865 for (i
= 0; i
< INT_PCI_MSI_NR
; i
++)
866 irq_create_mapping(msi
->domain
, i
);
868 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
869 err
= devm_request_irq(&pdev
->dev
, msi
->irq1
, rcar_pcie_msi_irq
,
870 IRQF_SHARED
| IRQF_NO_THREAD
,
871 rcar_msi_irq_chip
.name
, pcie
);
873 dev_err(&pdev
->dev
, "failed to request IRQ: %d\n", err
);
877 err
= devm_request_irq(&pdev
->dev
, msi
->irq2
, rcar_pcie_msi_irq
,
878 IRQF_SHARED
| IRQF_NO_THREAD
,
879 rcar_msi_irq_chip
.name
, pcie
);
881 dev_err(&pdev
->dev
, "failed to request IRQ: %d\n", err
);
885 /* setup MSI data target */
886 msi
->pages
= __get_free_pages(GFP_KERNEL
, 0);
887 base
= virt_to_phys((void *)msi
->pages
);
889 rcar_pci_write_reg(pcie
, base
| MSIFE
, PCIEMSIALR
);
890 rcar_pci_write_reg(pcie
, 0, PCIEMSIAUR
);
892 /* enable all MSI interrupts */
893 rcar_pci_write_reg(pcie
, 0xffffffff, PCIEMSIIER
);
898 irq_domain_remove(msi
->domain
);
902 static int rcar_pcie_get_resources(struct platform_device
*pdev
,
903 struct rcar_pcie
*pcie
)
908 err
= of_address_to_resource(pdev
->dev
.of_node
, 0, &res
);
912 pcie
->base
= devm_ioremap_resource(&pdev
->dev
, &res
);
913 if (IS_ERR(pcie
->base
))
914 return PTR_ERR(pcie
->base
);
916 pcie
->clk
= devm_clk_get(&pdev
->dev
, "pcie");
917 if (IS_ERR(pcie
->clk
)) {
918 dev_err(pcie
->dev
, "cannot get platform clock\n");
919 return PTR_ERR(pcie
->clk
);
921 err
= clk_prepare_enable(pcie
->clk
);
925 pcie
->bus_clk
= devm_clk_get(&pdev
->dev
, "pcie_bus");
926 if (IS_ERR(pcie
->bus_clk
)) {
927 dev_err(pcie
->dev
, "cannot get pcie bus clock\n");
928 err
= PTR_ERR(pcie
->bus_clk
);
931 err
= clk_prepare_enable(pcie
->bus_clk
);
935 i
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
937 dev_err(pcie
->dev
, "cannot get platform resources for msi interrupt\n");
943 i
= irq_of_parse_and_map(pdev
->dev
.of_node
, 1);
945 dev_err(pcie
->dev
, "cannot get platform resources for msi interrupt\n");
954 clk_disable_unprepare(pcie
->bus_clk
);
956 clk_disable_unprepare(pcie
->clk
);
961 static int rcar_pcie_inbound_ranges(struct rcar_pcie
*pcie
,
962 struct of_pci_range
*range
,
965 u64 restype
= range
->flags
;
966 u64 cpu_addr
= range
->cpu_addr
;
967 u64 cpu_end
= range
->cpu_addr
+ range
->size
;
968 u64 pci_addr
= range
->pci_addr
;
969 u32 flags
= LAM_64BIT
| LAR_ENABLE
;
974 if (restype
& IORESOURCE_PREFETCH
)
975 flags
|= LAM_PREFETCH
;
978 * If the size of the range is larger than the alignment of the start
979 * address, we have to use multiple entries to perform the mapping.
982 unsigned long nr_zeros
= __ffs64(cpu_addr
);
983 u64 alignment
= 1ULL << nr_zeros
;
985 size
= min(range
->size
, alignment
);
989 /* Hardware supports max 4GiB inbound region */
990 size
= min(size
, 1ULL << 32);
992 mask
= roundup_pow_of_two(size
) - 1;
995 while (cpu_addr
< cpu_end
) {
997 * Set up 64-bit inbound regions as the range parser doesn't
998 * distinguish between 32 and 64-bit types.
1000 rcar_pci_write_reg(pcie
, lower_32_bits(pci_addr
),
1002 rcar_pci_write_reg(pcie
, lower_32_bits(cpu_addr
), PCIELAR(idx
));
1003 rcar_pci_write_reg(pcie
, lower_32_bits(mask
) | flags
,
1006 rcar_pci_write_reg(pcie
, upper_32_bits(pci_addr
),
1008 rcar_pci_write_reg(pcie
, upper_32_bits(cpu_addr
),
1010 rcar_pci_write_reg(pcie
, 0, PCIELAMR(idx
+ 1));
1016 if (idx
> MAX_NR_INBOUND_MAPS
) {
1017 dev_err(pcie
->dev
, "Failed to map inbound regions!\n");
1026 static int pci_dma_range_parser_init(struct of_pci_range_parser
*parser
,
1027 struct device_node
*node
)
1029 const int na
= 3, ns
= 2;
1032 parser
->node
= node
;
1033 parser
->pna
= of_n_addr_cells(node
);
1034 parser
->np
= parser
->pna
+ na
+ ns
;
1036 parser
->range
= of_get_property(node
, "dma-ranges", &rlen
);
1040 parser
->end
= parser
->range
+ rlen
/ sizeof(__be32
);
1044 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie
*pcie
,
1045 struct device_node
*np
)
1047 struct of_pci_range range
;
1048 struct of_pci_range_parser parser
;
1052 if (pci_dma_range_parser_init(&parser
, np
))
1055 /* Get the dma-ranges from DT */
1056 for_each_of_pci_range(&parser
, &range
) {
1057 u64 end
= range
.cpu_addr
+ range
.size
- 1;
1059 dev_dbg(pcie
->dev
, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
1060 range
.flags
, range
.cpu_addr
, end
, range
.pci_addr
);
1062 err
= rcar_pcie_inbound_ranges(pcie
, &range
, &index
);
1070 static const struct of_device_id rcar_pcie_of_match
[] = {
1071 { .compatible
= "renesas,pcie-r8a7779", .data
= rcar_pcie_hw_init_h1
},
1072 { .compatible
= "renesas,pcie-rcar-gen2",
1073 .data
= rcar_pcie_hw_init_gen2
},
1074 { .compatible
= "renesas,pcie-r8a7790",
1075 .data
= rcar_pcie_hw_init_gen2
},
1076 { .compatible
= "renesas,pcie-r8a7791",
1077 .data
= rcar_pcie_hw_init_gen2
},
1078 { .compatible
= "renesas,pcie-r8a7795", .data
= rcar_pcie_hw_init
},
1082 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie
*pci
)
1085 struct device
*dev
= pci
->dev
;
1086 struct device_node
*np
= dev
->of_node
;
1087 resource_size_t iobase
;
1088 struct resource_entry
*win
, *tmp
;
1090 err
= of_pci_get_host_bridge_resources(np
, 0, 0xff, &pci
->resources
,
1095 err
= devm_request_pci_bus_resources(dev
, &pci
->resources
);
1097 goto out_release_res
;
1099 resource_list_for_each_entry_safe(win
, tmp
, &pci
->resources
) {
1100 struct resource
*res
= win
->res
;
1102 if (resource_type(res
) == IORESOURCE_IO
) {
1103 err
= pci_remap_iospace(res
, iobase
);
1105 dev_warn(dev
, "error %d: failed to map resource %pR\n",
1108 resource_list_destroy_entry(win
);
1116 pci_free_resource_list(&pci
->resources
);
1120 static int rcar_pcie_probe(struct platform_device
*pdev
)
1122 struct rcar_pcie
*pcie
;
1124 const struct of_device_id
*of_id
;
1126 int (*hw_init_fn
)(struct rcar_pcie
*);
1128 pcie
= devm_kzalloc(&pdev
->dev
, sizeof(*pcie
), GFP_KERNEL
);
1132 pcie
->dev
= &pdev
->dev
;
1133 platform_set_drvdata(pdev
, pcie
);
1135 INIT_LIST_HEAD(&pcie
->resources
);
1137 rcar_pcie_parse_request_of_pci_ranges(pcie
);
1139 err
= rcar_pcie_get_resources(pdev
, pcie
);
1141 dev_err(&pdev
->dev
, "failed to request resources: %d\n", err
);
1145 err
= rcar_pcie_parse_map_dma_ranges(pcie
, pdev
->dev
.of_node
);
1149 of_id
= of_match_device(rcar_pcie_of_match
, pcie
->dev
);
1150 if (!of_id
|| !of_id
->data
)
1152 hw_init_fn
= of_id
->data
;
1154 pm_runtime_enable(pcie
->dev
);
1155 err
= pm_runtime_get_sync(pcie
->dev
);
1157 dev_err(pcie
->dev
, "pm_runtime_get_sync failed\n");
1158 goto err_pm_disable
;
1161 /* Failure to get a link might just be that no cards are inserted */
1162 err
= hw_init_fn(pcie
);
1164 dev_info(&pdev
->dev
, "PCIe link down\n");
1169 data
= rcar_pci_read_reg(pcie
, MACSR
);
1170 dev_info(&pdev
->dev
, "PCIe x%d: link up\n", (data
>> 20) & 0x3f);
1172 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
1173 err
= rcar_pcie_enable_msi(pcie
);
1176 "failed to enable MSI support: %d\n",
1182 err
= rcar_pcie_enable(pcie
);
1189 pm_runtime_put(pcie
->dev
);
1192 pm_runtime_disable(pcie
->dev
);
1196 static struct platform_driver rcar_pcie_driver
= {
1199 .of_match_table
= rcar_pcie_of_match
,
1200 .suppress_bind_attrs
= true,
1202 .probe
= rcar_pcie_probe
,
1204 builtin_platform_driver(rcar_pcie_driver
);