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[mirror_ubuntu-jammy-kernel.git] / drivers / pci / host / pcie-xilinx-nwl.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
5 *
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 */
8
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/irqdomain.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/msi.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_irq.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqchip/chained_irq.h>
23
24 #include "../pci.h"
25
26 /* Bridge core config registers */
27 #define BRCFG_PCIE_RX0 0x00000000
28 #define BRCFG_INTERRUPT 0x00000010
29 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
30
31 /* Egress - Bridge translation registers */
32 #define E_BREG_CAPABILITIES 0x00000200
33 #define E_BREG_CONTROL 0x00000208
34 #define E_BREG_BASE_LO 0x00000210
35 #define E_BREG_BASE_HI 0x00000214
36 #define E_ECAM_CAPABILITIES 0x00000220
37 #define E_ECAM_CONTROL 0x00000228
38 #define E_ECAM_BASE_LO 0x00000230
39 #define E_ECAM_BASE_HI 0x00000234
40
41 /* Ingress - address translations */
42 #define I_MSII_CAPABILITIES 0x00000300
43 #define I_MSII_CONTROL 0x00000308
44 #define I_MSII_BASE_LO 0x00000310
45 #define I_MSII_BASE_HI 0x00000314
46
47 #define I_ISUB_CONTROL 0x000003E8
48 #define SET_ISUB_CONTROL BIT(0)
49 /* Rxed msg fifo - Interrupt status registers */
50 #define MSGF_MISC_STATUS 0x00000400
51 #define MSGF_MISC_MASK 0x00000404
52 #define MSGF_LEG_STATUS 0x00000420
53 #define MSGF_LEG_MASK 0x00000424
54 #define MSGF_MSI_STATUS_LO 0x00000440
55 #define MSGF_MSI_STATUS_HI 0x00000444
56 #define MSGF_MSI_MASK_LO 0x00000448
57 #define MSGF_MSI_MASK_HI 0x0000044C
58
59 /* Msg filter mask bits */
60 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
61 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
62 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
63 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
64 CFG_ENABLE_INT_MSG_FWD | \
65 CFG_ENABLE_ERR_MSG_FWD)
66
67 /* Misc interrupt status mask bits */
68 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
69 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
70 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
71 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
72 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
73 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
74 #define MSGF_MISC_SR_FATAL_AER BIT(16)
75 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
76 #define MSGF_MISC_SR_CORR_AER BIT(18)
77 #define MSGF_MISC_SR_UR_DETECT BIT(20)
78 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
79 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
80 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
81 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
82 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
83
84 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
85 MSGF_MISC_SR_RXMSG_OVER | \
86 MSGF_MISC_SR_SLAVE_ERR | \
87 MSGF_MISC_SR_MASTER_ERR | \
88 MSGF_MISC_SR_I_ADDR_ERR | \
89 MSGF_MISC_SR_E_ADDR_ERR | \
90 MSGF_MISC_SR_FATAL_AER | \
91 MSGF_MISC_SR_NON_FATAL_AER | \
92 MSGF_MISC_SR_CORR_AER | \
93 MSGF_MISC_SR_UR_DETECT | \
94 MSGF_MISC_SR_NON_FATAL_DEV | \
95 MSGF_MISC_SR_FATAL_DEV | \
96 MSGF_MISC_SR_LINK_DOWN | \
97 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
98 MSGF_MSIC_SR_LINK_BWIDTH)
99
100 /* Legacy interrupt status mask bits */
101 #define MSGF_LEG_SR_INTA BIT(0)
102 #define MSGF_LEG_SR_INTB BIT(1)
103 #define MSGF_LEG_SR_INTC BIT(2)
104 #define MSGF_LEG_SR_INTD BIT(3)
105 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
106 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
107
108 /* MSI interrupt status mask bits */
109 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
110 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
111
112 #define MSII_PRESENT BIT(0)
113 #define MSII_ENABLE BIT(0)
114 #define MSII_STATUS_ENABLE BIT(15)
115
116 /* Bridge config interrupt mask */
117 #define BRCFG_INTERRUPT_MASK BIT(0)
118 #define BREG_PRESENT BIT(0)
119 #define BREG_ENABLE BIT(0)
120 #define BREG_ENABLE_FORCE BIT(1)
121
122 /* E_ECAM status mask bits */
123 #define E_ECAM_PRESENT BIT(0)
124 #define E_ECAM_CR_ENABLE BIT(0)
125 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
126 #define E_ECAM_SIZE_SHIFT 16
127 #define ECAM_BUS_LOC_SHIFT 20
128 #define ECAM_DEV_LOC_SHIFT 12
129 #define NWL_ECAM_VALUE_DEFAULT 12
130
131 #define CFG_DMA_REG_BAR GENMASK(2, 0)
132
133 #define INT_PCI_MSI_NR (2 * 32)
134
135 /* Readin the PS_LINKUP */
136 #define PS_LINKUP_OFFSET 0x00000238
137 #define PCIE_PHY_LINKUP_BIT BIT(0)
138 #define PHY_RDY_LINKUP_BIT BIT(1)
139
140 /* Parameters for the waiting for link up routine */
141 #define LINK_WAIT_MAX_RETRIES 10
142 #define LINK_WAIT_USLEEP_MIN 90000
143 #define LINK_WAIT_USLEEP_MAX 100000
144
145 struct nwl_msi { /* MSI information */
146 struct irq_domain *msi_domain;
147 unsigned long *bitmap;
148 struct irq_domain *dev_domain;
149 struct mutex lock; /* protect bitmap variable */
150 int irq_msi0;
151 int irq_msi1;
152 };
153
154 struct nwl_pcie {
155 struct device *dev;
156 void __iomem *breg_base;
157 void __iomem *pcireg_base;
158 void __iomem *ecam_base;
159 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
160 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
161 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
162 u32 breg_size;
163 u32 pcie_reg_size;
164 u32 ecam_size;
165 int irq_intx;
166 int irq_misc;
167 u32 ecam_value;
168 u8 last_busno;
169 u8 root_busno;
170 struct nwl_msi msi;
171 struct irq_domain *legacy_irq_domain;
172 raw_spinlock_t leg_mask_lock;
173 };
174
175 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
176 {
177 return readl(pcie->breg_base + off);
178 }
179
180 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
181 {
182 writel(val, pcie->breg_base + off);
183 }
184
185 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
186 {
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
188 return true;
189 return false;
190 }
191
192 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
193 {
194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
195 return true;
196 return false;
197 }
198
199 static int nwl_wait_for_link(struct nwl_pcie *pcie)
200 {
201 struct device *dev = pcie->dev;
202 int retries;
203
204 /* check if the link is up or not */
205 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
206 if (nwl_phy_link_up(pcie))
207 return 0;
208 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
209 }
210
211 dev_err(dev, "PHY link never came up\n");
212 return -ETIMEDOUT;
213 }
214
215 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
216 {
217 struct nwl_pcie *pcie = bus->sysdata;
218
219 /* Check link before accessing downstream ports */
220 if (bus->number != pcie->root_busno) {
221 if (!nwl_pcie_link_up(pcie))
222 return false;
223 }
224
225 /* Only one device down on each root port */
226 if (bus->number == pcie->root_busno && devfn > 0)
227 return false;
228
229 return true;
230 }
231
232 /**
233 * nwl_pcie_map_bus - Get configuration base
234 *
235 * @bus: Bus structure of current bus
236 * @devfn: Device/function
237 * @where: Offset from base
238 *
239 * Return: Base address of the configuration space needed to be
240 * accessed.
241 */
242 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
243 int where)
244 {
245 struct nwl_pcie *pcie = bus->sysdata;
246 int relbus;
247
248 if (!nwl_pcie_valid_device(bus, devfn))
249 return NULL;
250
251 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
252 (devfn << ECAM_DEV_LOC_SHIFT);
253
254 return pcie->ecam_base + relbus + where;
255 }
256
257 /* PCIe operations */
258 static struct pci_ops nwl_pcie_ops = {
259 .map_bus = nwl_pcie_map_bus,
260 .read = pci_generic_config_read,
261 .write = pci_generic_config_write,
262 };
263
264 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
265 {
266 struct nwl_pcie *pcie = data;
267 struct device *dev = pcie->dev;
268 u32 misc_stat;
269
270 /* Checking for misc interrupts */
271 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
272 MSGF_MISC_SR_MASKALL;
273 if (!misc_stat)
274 return IRQ_NONE;
275
276 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
277 dev_err(dev, "Received Message FIFO Overflow\n");
278
279 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
280 dev_err(dev, "Slave error\n");
281
282 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
283 dev_err(dev, "Master error\n");
284
285 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
286 dev_err(dev, "In Misc Ingress address translation error\n");
287
288 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
289 dev_err(dev, "In Misc Egress address translation error\n");
290
291 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
292 dev_err(dev, "Fatal Error in AER Capability\n");
293
294 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
295 dev_err(dev, "Non-Fatal Error in AER Capability\n");
296
297 if (misc_stat & MSGF_MISC_SR_CORR_AER)
298 dev_err(dev, "Correctable Error in AER Capability\n");
299
300 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
301 dev_err(dev, "Unsupported request Detected\n");
302
303 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
304 dev_err(dev, "Non-Fatal Error Detected\n");
305
306 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
307 dev_err(dev, "Fatal Error Detected\n");
308
309 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
310 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
311
312 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
313 dev_info(dev, "Link Bandwidth Management Status bit set\n");
314
315 /* Clear misc interrupt status */
316 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
317
318 return IRQ_HANDLED;
319 }
320
321 static void nwl_pcie_leg_handler(struct irq_desc *desc)
322 {
323 struct irq_chip *chip = irq_desc_get_chip(desc);
324 struct nwl_pcie *pcie;
325 unsigned long status;
326 u32 bit;
327 u32 virq;
328
329 chained_irq_enter(chip, desc);
330 pcie = irq_desc_get_handler_data(desc);
331
332 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
333 MSGF_LEG_SR_MASKALL) != 0) {
334 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
335 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
336 if (virq)
337 generic_handle_irq(virq);
338 }
339 }
340
341 chained_irq_exit(chip, desc);
342 }
343
344 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
345 {
346 struct nwl_msi *msi;
347 unsigned long status;
348 u32 bit;
349 u32 virq;
350
351 msi = &pcie->msi;
352
353 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
354 for_each_set_bit(bit, &status, 32) {
355 nwl_bridge_writel(pcie, 1 << bit, status_reg);
356 virq = irq_find_mapping(msi->dev_domain, bit);
357 if (virq)
358 generic_handle_irq(virq);
359 }
360 }
361 }
362
363 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
364 {
365 struct irq_chip *chip = irq_desc_get_chip(desc);
366 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
367
368 chained_irq_enter(chip, desc);
369 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
370 chained_irq_exit(chip, desc);
371 }
372
373 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
374 {
375 struct irq_chip *chip = irq_desc_get_chip(desc);
376 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
377
378 chained_irq_enter(chip, desc);
379 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
380 chained_irq_exit(chip, desc);
381 }
382
383 static void nwl_mask_leg_irq(struct irq_data *data)
384 {
385 struct irq_desc *desc = irq_to_desc(data->irq);
386 struct nwl_pcie *pcie;
387 unsigned long flags;
388 u32 mask;
389 u32 val;
390
391 pcie = irq_desc_get_chip_data(desc);
392 mask = 1 << (data->hwirq - 1);
393 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
394 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
395 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
396 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
397 }
398
399 static void nwl_unmask_leg_irq(struct irq_data *data)
400 {
401 struct irq_desc *desc = irq_to_desc(data->irq);
402 struct nwl_pcie *pcie;
403 unsigned long flags;
404 u32 mask;
405 u32 val;
406
407 pcie = irq_desc_get_chip_data(desc);
408 mask = 1 << (data->hwirq - 1);
409 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
410 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
411 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
412 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
413 }
414
415 static struct irq_chip nwl_leg_irq_chip = {
416 .name = "nwl_pcie:legacy",
417 .irq_enable = nwl_unmask_leg_irq,
418 .irq_disable = nwl_mask_leg_irq,
419 .irq_mask = nwl_mask_leg_irq,
420 .irq_unmask = nwl_unmask_leg_irq,
421 };
422
423 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
424 irq_hw_number_t hwirq)
425 {
426 irq_set_chip_and_handler(irq, &nwl_leg_irq_chip, handle_level_irq);
427 irq_set_chip_data(irq, domain->host_data);
428 irq_set_status_flags(irq, IRQ_LEVEL);
429
430 return 0;
431 }
432
433 static const struct irq_domain_ops legacy_domain_ops = {
434 .map = nwl_legacy_map,
435 .xlate = pci_irqd_intx_xlate,
436 };
437
438 #ifdef CONFIG_PCI_MSI
439 static struct irq_chip nwl_msi_irq_chip = {
440 .name = "nwl_pcie:msi",
441 .irq_enable = unmask_msi_irq,
442 .irq_disable = mask_msi_irq,
443 .irq_mask = mask_msi_irq,
444 .irq_unmask = unmask_msi_irq,
445
446 };
447
448 static struct msi_domain_info nwl_msi_domain_info = {
449 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
450 MSI_FLAG_MULTI_PCI_MSI),
451 .chip = &nwl_msi_irq_chip,
452 };
453 #endif
454
455 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
456 {
457 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
458 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
459
460 msg->address_lo = lower_32_bits(msi_addr);
461 msg->address_hi = upper_32_bits(msi_addr);
462 msg->data = data->hwirq;
463 }
464
465 static int nwl_msi_set_affinity(struct irq_data *irq_data,
466 const struct cpumask *mask, bool force)
467 {
468 return -EINVAL;
469 }
470
471 static struct irq_chip nwl_irq_chip = {
472 .name = "Xilinx MSI",
473 .irq_compose_msi_msg = nwl_compose_msi_msg,
474 .irq_set_affinity = nwl_msi_set_affinity,
475 };
476
477 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
478 unsigned int nr_irqs, void *args)
479 {
480 struct nwl_pcie *pcie = domain->host_data;
481 struct nwl_msi *msi = &pcie->msi;
482 int bit;
483 int i;
484
485 mutex_lock(&msi->lock);
486 bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
487 nr_irqs, 0);
488 if (bit >= INT_PCI_MSI_NR) {
489 mutex_unlock(&msi->lock);
490 return -ENOSPC;
491 }
492
493 bitmap_set(msi->bitmap, bit, nr_irqs);
494
495 for (i = 0; i < nr_irqs; i++) {
496 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
497 domain->host_data, handle_simple_irq,
498 NULL, NULL);
499 }
500 mutex_unlock(&msi->lock);
501 return 0;
502 }
503
504 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
505 unsigned int nr_irqs)
506 {
507 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
508 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
509 struct nwl_msi *msi = &pcie->msi;
510
511 mutex_lock(&msi->lock);
512 bitmap_clear(msi->bitmap, data->hwirq, nr_irqs);
513 mutex_unlock(&msi->lock);
514 }
515
516 static const struct irq_domain_ops dev_msi_domain_ops = {
517 .alloc = nwl_irq_domain_alloc,
518 .free = nwl_irq_domain_free,
519 };
520
521 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
522 {
523 #ifdef CONFIG_PCI_MSI
524 struct device *dev = pcie->dev;
525 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
526 struct nwl_msi *msi = &pcie->msi;
527
528 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
529 &dev_msi_domain_ops, pcie);
530 if (!msi->dev_domain) {
531 dev_err(dev, "failed to create dev IRQ domain\n");
532 return -ENOMEM;
533 }
534 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
535 &nwl_msi_domain_info,
536 msi->dev_domain);
537 if (!msi->msi_domain) {
538 dev_err(dev, "failed to create msi IRQ domain\n");
539 irq_domain_remove(msi->dev_domain);
540 return -ENOMEM;
541 }
542 #endif
543 return 0;
544 }
545
546 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
547 {
548 struct device *dev = pcie->dev;
549 struct device_node *node = dev->of_node;
550 struct device_node *legacy_intc_node;
551
552 legacy_intc_node = of_get_next_child(node, NULL);
553 if (!legacy_intc_node) {
554 dev_err(dev, "No legacy intc node found\n");
555 return -EINVAL;
556 }
557
558 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
559 PCI_NUM_INTX,
560 &legacy_domain_ops,
561 pcie);
562
563 if (!pcie->legacy_irq_domain) {
564 dev_err(dev, "failed to create IRQ domain\n");
565 return -ENOMEM;
566 }
567
568 raw_spin_lock_init(&pcie->leg_mask_lock);
569 nwl_pcie_init_msi_irq_domain(pcie);
570 return 0;
571 }
572
573 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
574 {
575 struct device *dev = pcie->dev;
576 struct platform_device *pdev = to_platform_device(dev);
577 struct nwl_msi *msi = &pcie->msi;
578 unsigned long base;
579 int ret;
580 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
581
582 mutex_init(&msi->lock);
583
584 msi->bitmap = kzalloc(size, GFP_KERNEL);
585 if (!msi->bitmap)
586 return -ENOMEM;
587
588 /* Get msi_1 IRQ number */
589 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
590 if (msi->irq_msi1 < 0) {
591 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
592 ret = -EINVAL;
593 goto err;
594 }
595
596 irq_set_chained_handler_and_data(msi->irq_msi1,
597 nwl_pcie_msi_handler_high, pcie);
598
599 /* Get msi_0 IRQ number */
600 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
601 if (msi->irq_msi0 < 0) {
602 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
603 ret = -EINVAL;
604 goto err;
605 }
606
607 irq_set_chained_handler_and_data(msi->irq_msi0,
608 nwl_pcie_msi_handler_low, pcie);
609
610 /* Check for msii_present bit */
611 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
612 if (!ret) {
613 dev_err(dev, "MSI not present\n");
614 ret = -EIO;
615 goto err;
616 }
617
618 /* Enable MSII */
619 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
620 MSII_ENABLE, I_MSII_CONTROL);
621
622 /* Enable MSII status */
623 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
624 MSII_STATUS_ENABLE, I_MSII_CONTROL);
625
626 /* setup AFI/FPCI range */
627 base = pcie->phys_pcie_reg_base;
628 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
629 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
630
631 /*
632 * For high range MSI interrupts: disable, clear any pending,
633 * and enable
634 */
635 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
636
637 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
638 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
639
640 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
641
642 /*
643 * For low range MSI interrupts: disable, clear any pending,
644 * and enable
645 */
646 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
647
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
649 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
650
651 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
652
653 return 0;
654 err:
655 kfree(msi->bitmap);
656 msi->bitmap = NULL;
657 return ret;
658 }
659
660 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
661 {
662 struct device *dev = pcie->dev;
663 struct platform_device *pdev = to_platform_device(dev);
664 u32 breg_val, ecam_val, first_busno = 0;
665 int err;
666
667 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
668 if (!breg_val) {
669 dev_err(dev, "BREG is not present\n");
670 return breg_val;
671 }
672
673 /* Write bridge_off to breg base */
674 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
675 E_BREG_BASE_LO);
676 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
677 E_BREG_BASE_HI);
678
679 /* Enable BREG */
680 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
681 E_BREG_CONTROL);
682
683 /* Disable DMA channel registers */
684 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
685 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
686
687 /* Enable Ingress subtractive decode translation */
688 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
689
690 /* Enable msg filtering details */
691 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
692 BRCFG_PCIE_RX_MSG_FILTER);
693
694 err = nwl_wait_for_link(pcie);
695 if (err)
696 return err;
697
698 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
699 if (!ecam_val) {
700 dev_err(dev, "ECAM is not present\n");
701 return ecam_val;
702 }
703
704 /* Enable ECAM */
705 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
706 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
707
708 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
709 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
710 E_ECAM_CONTROL);
711
712 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
713 E_ECAM_BASE_LO);
714 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
715 E_ECAM_BASE_HI);
716
717 /* Get bus range */
718 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
719 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
720 /* Write primary, secondary and subordinate bus numbers */
721 ecam_val = first_busno;
722 ecam_val |= (first_busno + 1) << 8;
723 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
724 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
725
726 if (nwl_pcie_link_up(pcie))
727 dev_info(dev, "Link is UP\n");
728 else
729 dev_info(dev, "Link is DOWN\n");
730
731 /* Get misc IRQ number */
732 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
733 if (pcie->irq_misc < 0) {
734 dev_err(dev, "failed to get misc IRQ %d\n",
735 pcie->irq_misc);
736 return -EINVAL;
737 }
738
739 err = devm_request_irq(dev, pcie->irq_misc,
740 nwl_pcie_misc_handler, IRQF_SHARED,
741 "nwl_pcie:misc", pcie);
742 if (err) {
743 dev_err(dev, "fail to register misc IRQ#%d\n",
744 pcie->irq_misc);
745 return err;
746 }
747
748 /* Disable all misc interrupts */
749 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
750
751 /* Clear pending misc interrupts */
752 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
753 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
754
755 /* Enable all misc interrupts */
756 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
757
758
759 /* Disable all legacy interrupts */
760 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
761
762 /* Clear pending legacy interrupts */
763 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
764 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
765
766 /* Enable all legacy interrupts */
767 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
768
769 /* Enable the bridge config interrupt */
770 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
771 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
772
773 return 0;
774 }
775
776 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
777 struct platform_device *pdev)
778 {
779 struct device *dev = pcie->dev;
780 struct device_node *node = dev->of_node;
781 struct resource *res;
782 const char *type;
783
784 /* Check for device type */
785 type = of_get_property(node, "device_type", NULL);
786 if (!type || strcmp(type, "pci")) {
787 dev_err(dev, "invalid \"device_type\" %s\n", type);
788 return -EINVAL;
789 }
790
791 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
792 pcie->breg_base = devm_ioremap_resource(dev, res);
793 if (IS_ERR(pcie->breg_base))
794 return PTR_ERR(pcie->breg_base);
795 pcie->phys_breg_base = res->start;
796
797 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
798 pcie->pcireg_base = devm_ioremap_resource(dev, res);
799 if (IS_ERR(pcie->pcireg_base))
800 return PTR_ERR(pcie->pcireg_base);
801 pcie->phys_pcie_reg_base = res->start;
802
803 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
804 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
805 if (IS_ERR(pcie->ecam_base))
806 return PTR_ERR(pcie->ecam_base);
807 pcie->phys_ecam_base = res->start;
808
809 /* Get intx IRQ number */
810 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
811 if (pcie->irq_intx < 0) {
812 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
813 return pcie->irq_intx;
814 }
815
816 irq_set_chained_handler_and_data(pcie->irq_intx,
817 nwl_pcie_leg_handler, pcie);
818
819 return 0;
820 }
821
822 static const struct of_device_id nwl_pcie_of_match[] = {
823 { .compatible = "xlnx,nwl-pcie-2.11", },
824 {}
825 };
826
827 static int nwl_pcie_probe(struct platform_device *pdev)
828 {
829 struct device *dev = &pdev->dev;
830 struct nwl_pcie *pcie;
831 struct pci_bus *bus;
832 struct pci_bus *child;
833 struct pci_host_bridge *bridge;
834 int err;
835 resource_size_t iobase = 0;
836 LIST_HEAD(res);
837
838 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
839 if (!bridge)
840 return -ENODEV;
841
842 pcie = pci_host_bridge_priv(bridge);
843
844 pcie->dev = dev;
845 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
846
847 err = nwl_pcie_parse_dt(pcie, pdev);
848 if (err) {
849 dev_err(dev, "Parsing DT failed\n");
850 return err;
851 }
852
853 err = nwl_pcie_bridge_init(pcie);
854 if (err) {
855 dev_err(dev, "HW Initialization failed\n");
856 return err;
857 }
858
859 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
860 &iobase);
861 if (err) {
862 dev_err(dev, "Getting bridge resources failed\n");
863 return err;
864 }
865
866 err = devm_request_pci_bus_resources(dev, &res);
867 if (err)
868 goto error;
869
870 err = nwl_pcie_init_irq_domain(pcie);
871 if (err) {
872 dev_err(dev, "Failed creating IRQ Domain\n");
873 goto error;
874 }
875
876 list_splice_init(&res, &bridge->windows);
877 bridge->dev.parent = dev;
878 bridge->sysdata = pcie;
879 bridge->busnr = pcie->root_busno;
880 bridge->ops = &nwl_pcie_ops;
881 bridge->map_irq = of_irq_parse_and_map_pci;
882 bridge->swizzle_irq = pci_common_swizzle;
883
884 if (IS_ENABLED(CONFIG_PCI_MSI)) {
885 err = nwl_pcie_enable_msi(pcie);
886 if (err < 0) {
887 dev_err(dev, "failed to enable MSI support: %d\n", err);
888 goto error;
889 }
890 }
891
892 err = pci_scan_root_bus_bridge(bridge);
893 if (err)
894 goto error;
895
896 bus = bridge->bus;
897
898 pci_assign_unassigned_bus_resources(bus);
899 list_for_each_entry(child, &bus->children, node)
900 pcie_bus_configure_settings(child);
901 pci_bus_add_devices(bus);
902 return 0;
903
904 error:
905 pci_free_resource_list(&res);
906 return err;
907 }
908
909 static struct platform_driver nwl_pcie_driver = {
910 .driver = {
911 .name = "nwl-pcie",
912 .suppress_bind_attrs = true,
913 .of_match_table = nwl_pcie_of_match,
914 },
915 .probe = nwl_pcie_probe,
916 };
917 builtin_platform_driver(nwl_pcie_driver);
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