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[mirror_ubuntu-artful-kernel.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61 } __attribute__ ((packed));
62
63 /* offsets to the controller registers based on the above structure layout */
64 enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79 };
80
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82 {
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85 }
86
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88 {
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91 }
92
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94 {
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97 }
98
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100 {
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103 }
104
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
110
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
119
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
124
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128
129 /* Link Width Encoding */
130 #define LNK_X1 0x01
131 #define LNK_X2 0x02
132 #define LNK_X4 0x04
133 #define LNK_X8 0x08
134 #define LNK_X12 0x0C
135 #define LNK_X16 0x10
136 #define LNK_X32 0x20
137
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
144
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
156
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
168
169 /* Attention indicator and Power indicator states */
170 #define LED_ON 0x01
171 #define LED_BLINK 0x10
172 #define LED_OFF 0x11
173
174 /* Power Control Command */
175 #define POWER_ON 0
176 #define POWER_OFF 0x0400
177
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
181
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
192
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
195
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
198 {
199 struct controller *ctrl = (struct controller *)data;
200
201 /* Poll for interrupt events. regs == NULL => polling */
202 pcie_isr(0, ctrl);
203
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
207
208 start_int_poll_timer(ctrl, pciehp_poll_time);
209 }
210
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
213 {
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
216 sec = 2;
217
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
222 }
223
224 static inline int pcie_wait_cmd(struct controller *ctrl)
225 {
226 int retval = 0;
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
229 int rc;
230
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
233 if (!rc)
234 dbg("Command not completed in 1000 msec\n");
235 else if (rc < 0) {
236 retval = -EINTR;
237 info("Command was interrupted by a signal\n");
238 }
239
240 return retval;
241 }
242
243 /**
244 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
248 */
249 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
250 {
251 struct controller *ctrl = slot->ctrl;
252 int retval = 0;
253 u16 slot_status;
254 u16 slot_ctrl;
255
256 mutex_lock(&ctrl->ctrl_lock);
257
258 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
259 if (retval) {
260 err("%s: Cannot read SLOTSTATUS register\n", __func__);
261 goto out;
262 }
263
264 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
265 /* After 1 sec and CMD_COMPLETED still not set, just
266 proceed forward to issue the next command according
267 to spec. Just print out the error message */
268 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
269 __func__);
270 }
271
272 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
273 if (retval) {
274 err("%s: Cannot read SLOTCTRL register\n", __func__);
275 goto out;
276 }
277
278 slot_ctrl &= ~mask;
279 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
280
281 ctrl->cmd_busy = 1;
282 smp_mb();
283 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
284 if (retval)
285 err("%s: Cannot write to SLOTCTRL register\n", __func__);
286
287 /*
288 * Wait for command completion.
289 */
290 if (!retval)
291 retval = pcie_wait_cmd(ctrl);
292 out:
293 mutex_unlock(&ctrl->ctrl_lock);
294 return retval;
295 }
296
297 static int hpc_check_lnk_status(struct controller *ctrl)
298 {
299 u16 lnk_status;
300 int retval = 0;
301
302 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
303 if (retval) {
304 err("%s: Cannot read LNKSTATUS register\n", __func__);
305 return retval;
306 }
307
308 dbg("%s: lnk_status = %x\n", __func__, lnk_status);
309 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
310 !(lnk_status & NEG_LINK_WD)) {
311 err("%s : Link Training Error occurs \n", __func__);
312 retval = -1;
313 return retval;
314 }
315
316 return retval;
317 }
318
319 static int hpc_get_attention_status(struct slot *slot, u8 *status)
320 {
321 struct controller *ctrl = slot->ctrl;
322 u16 slot_ctrl;
323 u8 atten_led_state;
324 int retval = 0;
325
326 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
327 if (retval) {
328 err("%s: Cannot read SLOTCTRL register\n", __func__);
329 return retval;
330 }
331
332 dbg("%s: SLOTCTRL %x, value read %x\n",
333 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
334
335 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
336
337 switch (atten_led_state) {
338 case 0:
339 *status = 0xFF; /* Reserved */
340 break;
341 case 1:
342 *status = 1; /* On */
343 break;
344 case 2:
345 *status = 2; /* Blink */
346 break;
347 case 3:
348 *status = 0; /* Off */
349 break;
350 default:
351 *status = 0xFF;
352 break;
353 }
354
355 return 0;
356 }
357
358 static int hpc_get_power_status(struct slot *slot, u8 *status)
359 {
360 struct controller *ctrl = slot->ctrl;
361 u16 slot_ctrl;
362 u8 pwr_state;
363 int retval = 0;
364
365 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
366 if (retval) {
367 err("%s: Cannot read SLOTCTRL register\n", __func__);
368 return retval;
369 }
370 dbg("%s: SLOTCTRL %x value read %x\n",
371 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
372
373 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
374
375 switch (pwr_state) {
376 case 0:
377 *status = 1;
378 break;
379 case 1:
380 *status = 0;
381 break;
382 default:
383 *status = 0xFF;
384 break;
385 }
386
387 return retval;
388 }
389
390 static int hpc_get_latch_status(struct slot *slot, u8 *status)
391 {
392 struct controller *ctrl = slot->ctrl;
393 u16 slot_status;
394 int retval = 0;
395
396 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
397 if (retval) {
398 err("%s: Cannot read SLOTSTATUS register\n", __func__);
399 return retval;
400 }
401
402 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
403
404 return 0;
405 }
406
407 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
408 {
409 struct controller *ctrl = slot->ctrl;
410 u16 slot_status;
411 u8 card_state;
412 int retval = 0;
413
414 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
415 if (retval) {
416 err("%s: Cannot read SLOTSTATUS register\n", __func__);
417 return retval;
418 }
419 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
420 *status = (card_state == 1) ? 1 : 0;
421
422 return 0;
423 }
424
425 static int hpc_query_power_fault(struct slot *slot)
426 {
427 struct controller *ctrl = slot->ctrl;
428 u16 slot_status;
429 u8 pwr_fault;
430 int retval = 0;
431
432 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
433 if (retval) {
434 err("%s: Cannot check for power fault\n", __func__);
435 return retval;
436 }
437 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
438
439 return pwr_fault;
440 }
441
442 static int hpc_get_emi_status(struct slot *slot, u8 *status)
443 {
444 struct controller *ctrl = slot->ctrl;
445 u16 slot_status;
446 int retval = 0;
447
448 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
449 if (retval) {
450 err("%s : Cannot check EMI status\n", __func__);
451 return retval;
452 }
453 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
454
455 return retval;
456 }
457
458 static int hpc_toggle_emi(struct slot *slot)
459 {
460 u16 slot_cmd;
461 u16 cmd_mask;
462 int rc;
463
464 slot_cmd = EMI_CTRL;
465 cmd_mask = EMI_CTRL;
466 if (!pciehp_poll_mode) {
467 slot_cmd = slot_cmd | HP_INTR_ENABLE;
468 cmd_mask = cmd_mask | HP_INTR_ENABLE;
469 }
470
471 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
472 slot->last_emi_toggle = get_seconds();
473
474 return rc;
475 }
476
477 static int hpc_set_attention_status(struct slot *slot, u8 value)
478 {
479 struct controller *ctrl = slot->ctrl;
480 u16 slot_cmd;
481 u16 cmd_mask;
482 int rc;
483
484 cmd_mask = ATTN_LED_CTRL;
485 switch (value) {
486 case 0 : /* turn off */
487 slot_cmd = 0x00C0;
488 break;
489 case 1: /* turn on */
490 slot_cmd = 0x0040;
491 break;
492 case 2: /* turn blink */
493 slot_cmd = 0x0080;
494 break;
495 default:
496 return -1;
497 }
498 if (!pciehp_poll_mode) {
499 slot_cmd = slot_cmd | HP_INTR_ENABLE;
500 cmd_mask = cmd_mask | HP_INTR_ENABLE;
501 }
502
503 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
504 dbg("%s: SLOTCTRL %x write cmd %x\n",
505 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
506
507 return rc;
508 }
509
510 static void hpc_set_green_led_on(struct slot *slot)
511 {
512 struct controller *ctrl = slot->ctrl;
513 u16 slot_cmd;
514 u16 cmd_mask;
515
516 slot_cmd = 0x0100;
517 cmd_mask = PWR_LED_CTRL;
518 if (!pciehp_poll_mode) {
519 slot_cmd = slot_cmd | HP_INTR_ENABLE;
520 cmd_mask = cmd_mask | HP_INTR_ENABLE;
521 }
522
523 pcie_write_cmd(slot, slot_cmd, cmd_mask);
524
525 dbg("%s: SLOTCTRL %x write cmd %x\n",
526 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
527 }
528
529 static void hpc_set_green_led_off(struct slot *slot)
530 {
531 struct controller *ctrl = slot->ctrl;
532 u16 slot_cmd;
533 u16 cmd_mask;
534
535 slot_cmd = 0x0300;
536 cmd_mask = PWR_LED_CTRL;
537 if (!pciehp_poll_mode) {
538 slot_cmd = slot_cmd | HP_INTR_ENABLE;
539 cmd_mask = cmd_mask | HP_INTR_ENABLE;
540 }
541
542 pcie_write_cmd(slot, slot_cmd, cmd_mask);
543 dbg("%s: SLOTCTRL %x write cmd %x\n",
544 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
545 }
546
547 static void hpc_set_green_led_blink(struct slot *slot)
548 {
549 struct controller *ctrl = slot->ctrl;
550 u16 slot_cmd;
551 u16 cmd_mask;
552
553 slot_cmd = 0x0200;
554 cmd_mask = PWR_LED_CTRL;
555 if (!pciehp_poll_mode) {
556 slot_cmd = slot_cmd | HP_INTR_ENABLE;
557 cmd_mask = cmd_mask | HP_INTR_ENABLE;
558 }
559
560 pcie_write_cmd(slot, slot_cmd, cmd_mask);
561
562 dbg("%s: SLOTCTRL %x write cmd %x\n",
563 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
564 }
565
566 static void hpc_release_ctlr(struct controller *ctrl)
567 {
568 if (pciehp_poll_mode)
569 del_timer(&ctrl->poll_timer);
570 else
571 free_irq(ctrl->pci_dev->irq, ctrl);
572
573 /*
574 * If this is the last controller to be released, destroy the
575 * pciehp work queue
576 */
577 if (atomic_dec_and_test(&pciehp_num_controllers))
578 destroy_workqueue(pciehp_wq);
579 }
580
581 static int hpc_power_on_slot(struct slot * slot)
582 {
583 struct controller *ctrl = slot->ctrl;
584 u16 slot_cmd;
585 u16 cmd_mask;
586 u16 slot_status;
587 int retval = 0;
588
589 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
590
591 /* Clear sticky power-fault bit from previous power failures */
592 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
593 if (retval) {
594 err("%s: Cannot read SLOTSTATUS register\n", __func__);
595 return retval;
596 }
597 slot_status &= PWR_FAULT_DETECTED;
598 if (slot_status) {
599 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
600 if (retval) {
601 err("%s: Cannot write to SLOTSTATUS register\n",
602 __func__);
603 return retval;
604 }
605 }
606
607 slot_cmd = POWER_ON;
608 cmd_mask = PWR_CTRL;
609 /* Enable detection that we turned off at slot power-off time */
610 if (!pciehp_poll_mode) {
611 slot_cmd = slot_cmd |
612 PWR_FAULT_DETECT_ENABLE |
613 MRL_DETECT_ENABLE |
614 PRSN_DETECT_ENABLE |
615 HP_INTR_ENABLE;
616 cmd_mask = cmd_mask |
617 PWR_FAULT_DETECT_ENABLE |
618 MRL_DETECT_ENABLE |
619 PRSN_DETECT_ENABLE |
620 HP_INTR_ENABLE;
621 }
622
623 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
624
625 if (retval) {
626 err("%s: Write %x command failed!\n", __func__, slot_cmd);
627 return -1;
628 }
629 dbg("%s: SLOTCTRL %x write cmd %x\n",
630 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
631
632 return retval;
633 }
634
635 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
636 {
637 struct pci_dev *dev = ctrl->pci_dev;
638 int pos;
639 u32 reg;
640
641 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
642 if (!pos)
643 return 0;
644 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
645 if (reg & PCI_ERR_COR_BAD_DLLP)
646 return 0;
647 reg |= PCI_ERR_COR_BAD_DLLP;
648 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
649 return 1;
650 }
651
652 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
653 {
654 struct pci_dev *dev = ctrl->pci_dev;
655 u32 reg;
656 int pos;
657
658 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
659 if (!pos)
660 return;
661 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
662 if (!(reg & PCI_ERR_COR_BAD_DLLP))
663 return;
664 reg &= ~PCI_ERR_COR_BAD_DLLP;
665 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
666 }
667
668 static int hpc_power_off_slot(struct slot * slot)
669 {
670 struct controller *ctrl = slot->ctrl;
671 u16 slot_cmd;
672 u16 cmd_mask;
673 int retval = 0;
674 int changed;
675
676 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
677
678 /*
679 * Set Bad DLLP Mask bit in Correctable Error Mask
680 * Register. This is the workaround against Bad DLLP error
681 * that sometimes happens during turning power off the slot
682 * which conforms to PCI Express 1.0a spec.
683 */
684 changed = pcie_mask_bad_dllp(ctrl);
685
686 slot_cmd = POWER_OFF;
687 cmd_mask = PWR_CTRL;
688 /*
689 * If we get MRL or presence detect interrupts now, the isr
690 * will notice the sticky power-fault bit too and issue power
691 * indicator change commands. This will lead to an endless loop
692 * of command completions, since the power-fault bit remains on
693 * till the slot is powered on again.
694 */
695 if (!pciehp_poll_mode) {
696 slot_cmd = (slot_cmd &
697 ~PWR_FAULT_DETECT_ENABLE &
698 ~MRL_DETECT_ENABLE &
699 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
700 cmd_mask = cmd_mask |
701 PWR_FAULT_DETECT_ENABLE |
702 MRL_DETECT_ENABLE |
703 PRSN_DETECT_ENABLE |
704 HP_INTR_ENABLE;
705 }
706
707 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
708 if (retval) {
709 err("%s: Write command failed!\n", __func__);
710 retval = -1;
711 goto out;
712 }
713 dbg("%s: SLOTCTRL %x write cmd %x\n",
714 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
715
716 /*
717 * After turning power off, we must wait for at least 1 second
718 * before taking any action that relies on power having been
719 * removed from the slot/adapter.
720 */
721 msleep(1000);
722 out:
723 if (changed)
724 pcie_unmask_bad_dllp(ctrl);
725
726 return retval;
727 }
728
729 static irqreturn_t pcie_isr(int irq, void *dev_id)
730 {
731 struct controller *ctrl = (struct controller *)dev_id;
732 u16 detected, intr_loc;
733
734 /*
735 * In order to guarantee that all interrupt events are
736 * serviced, we need to re-inspect Slot Status register after
737 * clearing what is presumed to be the last pending interrupt.
738 */
739 intr_loc = 0;
740 do {
741 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
742 err("%s: Cannot read SLOTSTATUS\n", __func__);
743 return IRQ_NONE;
744 }
745
746 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
747 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
748 CMD_COMPLETED);
749 intr_loc |= detected;
750 if (!intr_loc)
751 return IRQ_NONE;
752 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
753 err("%s: Cannot write to SLOTSTATUS\n", __func__);
754 return IRQ_NONE;
755 }
756 } while (detected);
757
758 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
759
760 /* Check Command Complete Interrupt Pending */
761 if (intr_loc & CMD_COMPLETED) {
762 ctrl->cmd_busy = 0;
763 smp_mb();
764 wake_up_interruptible(&ctrl->queue);
765 }
766
767 /* Check MRL Sensor Changed */
768 if (intr_loc & MRL_SENS_CHANGED)
769 pciehp_handle_switch_change(0, ctrl);
770
771 /* Check Attention Button Pressed */
772 if (intr_loc & ATTN_BUTTN_PRESSED)
773 pciehp_handle_attention_button(0, ctrl);
774
775 /* Check Presence Detect Changed */
776 if (intr_loc & PRSN_DETECT_CHANGED)
777 pciehp_handle_presence_change(0, ctrl);
778
779 /* Check Power Fault Detected */
780 if (intr_loc & PWR_FAULT_DETECTED)
781 pciehp_handle_power_fault(0, ctrl);
782
783 return IRQ_HANDLED;
784 }
785
786 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
787 {
788 struct controller *ctrl = slot->ctrl;
789 enum pcie_link_speed lnk_speed;
790 u32 lnk_cap;
791 int retval = 0;
792
793 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
794 if (retval) {
795 err("%s: Cannot read LNKCAP register\n", __func__);
796 return retval;
797 }
798
799 switch (lnk_cap & 0x000F) {
800 case 1:
801 lnk_speed = PCIE_2PT5GB;
802 break;
803 default:
804 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
805 break;
806 }
807
808 *value = lnk_speed;
809 dbg("Max link speed = %d\n", lnk_speed);
810
811 return retval;
812 }
813
814 static int hpc_get_max_lnk_width(struct slot *slot,
815 enum pcie_link_width *value)
816 {
817 struct controller *ctrl = slot->ctrl;
818 enum pcie_link_width lnk_wdth;
819 u32 lnk_cap;
820 int retval = 0;
821
822 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
823 if (retval) {
824 err("%s: Cannot read LNKCAP register\n", __func__);
825 return retval;
826 }
827
828 switch ((lnk_cap & 0x03F0) >> 4){
829 case 0:
830 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
831 break;
832 case 1:
833 lnk_wdth = PCIE_LNK_X1;
834 break;
835 case 2:
836 lnk_wdth = PCIE_LNK_X2;
837 break;
838 case 4:
839 lnk_wdth = PCIE_LNK_X4;
840 break;
841 case 8:
842 lnk_wdth = PCIE_LNK_X8;
843 break;
844 case 12:
845 lnk_wdth = PCIE_LNK_X12;
846 break;
847 case 16:
848 lnk_wdth = PCIE_LNK_X16;
849 break;
850 case 32:
851 lnk_wdth = PCIE_LNK_X32;
852 break;
853 default:
854 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
855 break;
856 }
857
858 *value = lnk_wdth;
859 dbg("Max link width = %d\n", lnk_wdth);
860
861 return retval;
862 }
863
864 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
865 {
866 struct controller *ctrl = slot->ctrl;
867 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
868 int retval = 0;
869 u16 lnk_status;
870
871 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
872 if (retval) {
873 err("%s: Cannot read LNKSTATUS register\n", __func__);
874 return retval;
875 }
876
877 switch (lnk_status & 0x0F) {
878 case 1:
879 lnk_speed = PCIE_2PT5GB;
880 break;
881 default:
882 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
883 break;
884 }
885
886 *value = lnk_speed;
887 dbg("Current link speed = %d\n", lnk_speed);
888
889 return retval;
890 }
891
892 static int hpc_get_cur_lnk_width(struct slot *slot,
893 enum pcie_link_width *value)
894 {
895 struct controller *ctrl = slot->ctrl;
896 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
897 int retval = 0;
898 u16 lnk_status;
899
900 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
901 if (retval) {
902 err("%s: Cannot read LNKSTATUS register\n", __func__);
903 return retval;
904 }
905
906 switch ((lnk_status & 0x03F0) >> 4){
907 case 0:
908 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
909 break;
910 case 1:
911 lnk_wdth = PCIE_LNK_X1;
912 break;
913 case 2:
914 lnk_wdth = PCIE_LNK_X2;
915 break;
916 case 4:
917 lnk_wdth = PCIE_LNK_X4;
918 break;
919 case 8:
920 lnk_wdth = PCIE_LNK_X8;
921 break;
922 case 12:
923 lnk_wdth = PCIE_LNK_X12;
924 break;
925 case 16:
926 lnk_wdth = PCIE_LNK_X16;
927 break;
928 case 32:
929 lnk_wdth = PCIE_LNK_X32;
930 break;
931 default:
932 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
933 break;
934 }
935
936 *value = lnk_wdth;
937 dbg("Current link width = %d\n", lnk_wdth);
938
939 return retval;
940 }
941
942 static struct hpc_ops pciehp_hpc_ops = {
943 .power_on_slot = hpc_power_on_slot,
944 .power_off_slot = hpc_power_off_slot,
945 .set_attention_status = hpc_set_attention_status,
946 .get_power_status = hpc_get_power_status,
947 .get_attention_status = hpc_get_attention_status,
948 .get_latch_status = hpc_get_latch_status,
949 .get_adapter_status = hpc_get_adapter_status,
950 .get_emi_status = hpc_get_emi_status,
951 .toggle_emi = hpc_toggle_emi,
952
953 .get_max_bus_speed = hpc_get_max_lnk_speed,
954 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
955 .get_max_lnk_width = hpc_get_max_lnk_width,
956 .get_cur_lnk_width = hpc_get_cur_lnk_width,
957
958 .query_power_fault = hpc_query_power_fault,
959 .green_led_on = hpc_set_green_led_on,
960 .green_led_off = hpc_set_green_led_off,
961 .green_led_blink = hpc_set_green_led_blink,
962
963 .release_ctlr = hpc_release_ctlr,
964 .check_lnk_status = hpc_check_lnk_status,
965 };
966
967 #ifdef CONFIG_ACPI
968 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
969 {
970 acpi_status status;
971 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
972 struct pci_dev *pdev = dev;
973 struct pci_bus *parent;
974 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
975
976 /*
977 * Per PCI firmware specification, we should run the ACPI _OSC
978 * method to get control of hotplug hardware before using it.
979 * If an _OSC is missing, we look for an OSHP to do the same thing.
980 * To handle different BIOS behavior, we look for _OSC and OSHP
981 * within the scope of the hotplug controller and its parents, upto
982 * the host bridge under which this controller exists.
983 */
984 while (!handle) {
985 /*
986 * This hotplug controller was not listed in the ACPI name
987 * space at all. Try to get acpi handle of parent pci bus.
988 */
989 if (!pdev || !pdev->bus->parent)
990 break;
991 parent = pdev->bus->parent;
992 dbg("Could not find %s in acpi namespace, trying parent\n",
993 pci_name(pdev));
994 if (!parent->self)
995 /* Parent must be a host bridge */
996 handle = acpi_get_pci_rootbridge_handle(
997 pci_domain_nr(parent),
998 parent->number);
999 else
1000 handle = DEVICE_ACPI_HANDLE(
1001 &(parent->self->dev));
1002 pdev = parent->self;
1003 }
1004
1005 while (handle) {
1006 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1007 dbg("Trying to get hotplug control for %s \n",
1008 (char *)string.pointer);
1009 status = pci_osc_control_set(handle,
1010 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1011 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1012 if (status == AE_NOT_FOUND)
1013 status = acpi_run_oshp(handle);
1014 if (ACPI_SUCCESS(status)) {
1015 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1016 pci_name(dev), (char *)string.pointer);
1017 kfree(string.pointer);
1018 return 0;
1019 }
1020 if (acpi_root_bridge(handle))
1021 break;
1022 chandle = handle;
1023 status = acpi_get_parent(chandle, &handle);
1024 if (ACPI_FAILURE(status))
1025 break;
1026 }
1027
1028 err("Cannot get control of hotplug hardware for pci %s\n",
1029 pci_name(dev));
1030
1031 kfree(string.pointer);
1032 return -1;
1033 }
1034 #endif
1035
1036 static int pcie_init_hardware_part1(struct controller *ctrl,
1037 struct pcie_device *dev)
1038 {
1039 int rc;
1040 u16 temp_word;
1041 u32 slot_cap;
1042 u16 slot_status;
1043
1044 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1045 if (rc) {
1046 err("%s: Cannot read SLOTCAP register\n", __func__);
1047 return -1;
1048 }
1049
1050 /* Mask Hot-plug Interrupt Enable */
1051 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1052 if (rc) {
1053 err("%s: Cannot read SLOTCTRL register\n", __func__);
1054 return -1;
1055 }
1056
1057 dbg("%s: SLOTCTRL %x value read %x\n",
1058 __func__, ctrl->cap_base + SLOTCTRL, temp_word);
1059 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1060 0x00;
1061
1062 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1063 if (rc) {
1064 err("%s: Cannot write to SLOTCTRL register\n", __func__);
1065 return -1;
1066 }
1067
1068 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1069 if (rc) {
1070 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1071 return -1;
1072 }
1073
1074 temp_word = 0x1F; /* Clear all events */
1075 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1076 if (rc) {
1077 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1078 return -1;
1079 }
1080 return 0;
1081 }
1082
1083 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1084 {
1085 int rc;
1086 u16 temp_word;
1087 u16 intr_enable = 0;
1088 u32 slot_cap;
1089 u16 slot_status;
1090
1091 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1092 if (rc) {
1093 err("%s: Cannot read SLOTCTRL register\n", __func__);
1094 goto abort;
1095 }
1096
1097 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1098
1099 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1100 if (rc) {
1101 err("%s: Cannot read SLOTCAP register\n", __func__);
1102 goto abort;
1103 }
1104
1105 if (ATTN_BUTTN(slot_cap))
1106 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1107
1108 if (POWER_CTRL(slot_cap))
1109 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1110
1111 if (MRL_SENS(slot_cap))
1112 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1113
1114 temp_word = (temp_word & ~intr_enable) | intr_enable;
1115
1116 if (pciehp_poll_mode) {
1117 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1118 } else {
1119 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1120 }
1121
1122 /*
1123 * Unmask Hot-plug Interrupt Enable for the interrupt
1124 * notification mechanism case.
1125 */
1126 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1127 if (rc) {
1128 err("%s: Cannot write to SLOTCTRL register\n", __func__);
1129 goto abort;
1130 }
1131 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1132 if (rc) {
1133 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1134 goto abort_disable_intr;
1135 }
1136
1137 temp_word = 0x1F; /* Clear all events */
1138 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1139 if (rc) {
1140 err("%s: Cannot write to SLOTSTATUS register\n", __func__);
1141 goto abort_disable_intr;
1142 }
1143
1144 if (pciehp_force) {
1145 dbg("Bypassing BIOS check for pciehp use on %s\n",
1146 pci_name(ctrl->pci_dev));
1147 } else {
1148 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1149 if (rc)
1150 goto abort_disable_intr;
1151 }
1152
1153 return 0;
1154
1155 /* We end up here for the many possible ways to fail this API. */
1156 abort_disable_intr:
1157 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1158 if (!rc) {
1159 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1160 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1161 }
1162 if (rc)
1163 err("%s : disabling interrupts failed\n", __func__);
1164 abort:
1165 return -1;
1166 }
1167
1168 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1169 {
1170 int rc;
1171 u16 cap_reg;
1172 u32 slot_cap;
1173 int cap_base;
1174 u16 slot_status, slot_ctrl;
1175 struct pci_dev *pdev;
1176
1177 pdev = dev->port;
1178 ctrl->pci_dev = pdev; /* save pci_dev in context */
1179
1180 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1181 __func__, pdev->vendor, pdev->device);
1182
1183 cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1184 if (cap_base == 0) {
1185 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
1186 goto abort;
1187 }
1188
1189 ctrl->cap_base = cap_base;
1190
1191 dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
1192
1193 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1194 if (rc) {
1195 err("%s: Cannot read CAPREG register\n", __func__);
1196 goto abort;
1197 }
1198 dbg("%s: CAPREG offset %x cap_reg %x\n",
1199 __func__, ctrl->cap_base + CAPREG, cap_reg);
1200
1201 if (((cap_reg & SLOT_IMPL) == 0) ||
1202 (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1203 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1204 dbg("%s : This is not a root port or the port is not "
1205 "connected to a slot\n", __func__);
1206 goto abort;
1207 }
1208
1209 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1210 if (rc) {
1211 err("%s: Cannot read SLOTCAP register\n", __func__);
1212 goto abort;
1213 }
1214 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1215 __func__, ctrl->cap_base + SLOTCAP, slot_cap);
1216
1217 if (!(slot_cap & HP_CAP)) {
1218 dbg("%s : This slot is not hot-plug capable\n", __func__);
1219 goto abort;
1220 }
1221 /* For debugging purpose */
1222 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1223 if (rc) {
1224 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1225 goto abort;
1226 }
1227 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1228 __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
1229
1230 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1231 if (rc) {
1232 err("%s: Cannot read SLOTCTRL register\n", __func__);
1233 goto abort;
1234 }
1235 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1236 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1237
1238 for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1239 if (pci_resource_len(pdev, rc) > 0)
1240 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1241 (unsigned long long)pci_resource_start(pdev, rc),
1242 (unsigned long long)pci_resource_len(pdev, rc));
1243
1244 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1245 pdev->vendor, pdev->device,
1246 pdev->subsystem_vendor, pdev->subsystem_device);
1247
1248 mutex_init(&ctrl->crit_sect);
1249 mutex_init(&ctrl->ctrl_lock);
1250
1251 /* setup wait queue */
1252 init_waitqueue_head(&ctrl->queue);
1253
1254 /* return PCI Controller Info */
1255 ctrl->slot_device_offset = 0;
1256 ctrl->num_slots = 1;
1257 ctrl->first_slot = slot_cap >> 19;
1258 ctrl->ctrlcap = slot_cap & 0x0000007f;
1259
1260 rc = pcie_init_hardware_part1(ctrl, dev);
1261 if (rc)
1262 goto abort;
1263
1264 if (pciehp_poll_mode) {
1265 /* Install interrupt polling timer. Start with 10 sec delay */
1266 init_timer(&ctrl->poll_timer);
1267 start_int_poll_timer(ctrl, 10);
1268 } else {
1269 /* Installs the interrupt handler */
1270 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1271 MY_NAME, (void *)ctrl);
1272 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1273 __func__, ctrl->pci_dev->irq,
1274 atomic_read(&pciehp_num_controllers), rc);
1275 if (rc) {
1276 err("Can't get irq %d for the hotplug controller\n",
1277 ctrl->pci_dev->irq);
1278 goto abort;
1279 }
1280 }
1281 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1282 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1283
1284 /*
1285 * If this is the first controller to be initialized,
1286 * initialize the pciehp work queue
1287 */
1288 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1289 pciehp_wq = create_singlethread_workqueue("pciehpd");
1290 if (!pciehp_wq) {
1291 rc = -ENOMEM;
1292 goto abort_free_irq;
1293 }
1294 }
1295
1296 rc = pcie_init_hardware_part2(ctrl, dev);
1297 if (rc == 0) {
1298 ctrl->hpc_ops = &pciehp_hpc_ops;
1299 return 0;
1300 }
1301 abort_free_irq:
1302 if (pciehp_poll_mode)
1303 del_timer_sync(&ctrl->poll_timer);
1304 else
1305 free_irq(ctrl->pci_dev->irq, ctrl);
1306 abort:
1307 return -1;
1308 }
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