drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  45 {
  46         return ctrl->pcie->port;
  47 }
  48
  49 static irqreturn_t pcie_isr(int irq, void *dev_id);
  50 static void start_int_poll_timer(struct controller *ctrl, int sec);
  51
  52 /* This is the interrupt polling timeout function. */
  53 static void int_poll_timeout(unsigned long data)
  54 {
  55         struct controller *ctrl = (struct controller *)data;
  56
  57         /* Poll for interrupt events.  regs == NULL => polling */
  58         pcie_isr(0, ctrl);
  59
  60         init_timer(&ctrl->poll_timer);
  61         if (!pciehp_poll_time)
  62                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  63
  64         start_int_poll_timer(ctrl, pciehp_poll_time);
  65 }
  66
  67 /* This function starts the interrupt polling timer. */
  68 static void start_int_poll_timer(struct controller *ctrl, int sec)
  69 {
  70         /* Clamp to sane value */
  71         if ((sec <= 0) || (sec > 60))
  72                 sec = 2;
  73
  74         ctrl->poll_timer.function = &int_poll_timeout;
  75         ctrl->poll_timer.data = (unsigned long)ctrl;
  76         ctrl->poll_timer.expires = jiffies + sec * HZ;
  77         add_timer(&ctrl->poll_timer);
  78 }
  79
  80 static inline int pciehp_request_irq(struct controller *ctrl)
  81 {
  82         int retval, irq = ctrl->pcie->irq;
  83
  84         /* Install interrupt polling timer. Start with 10 sec delay */
  85         if (pciehp_poll_mode) {
  86                 init_timer(&ctrl->poll_timer);
  87                 start_int_poll_timer(ctrl, 10);
  88                 return 0;
  89         }
  90
  91         /* Installs the interrupt handler */
  92         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  93         if (retval)
  94                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  95                          irq);
  96         return retval;
  97 }
  98
  99 static inline void pciehp_free_irq(struct controller *ctrl)
 100 {
 101         if (pciehp_poll_mode)
 102                 del_timer_sync(&ctrl->poll_timer);
 103         else
 104                 free_irq(ctrl->pcie->irq, ctrl);
 105 }
 106
 107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
 108 {
 109         struct pci_dev *pdev = ctrl_dev(ctrl);
 110         u16 slot_status;
 111
 112         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 113         if (slot_status & PCI_EXP_SLTSTA_CC) {
 114                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 115                                            PCI_EXP_SLTSTA_CC);
 116                 return 1;
 117         }
 118         while (timeout > 0) {
 119                 msleep(10);
 120                 timeout -= 10;
 121                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 122                 if (slot_status & PCI_EXP_SLTSTA_CC) {
 123                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 124                                                    PCI_EXP_SLTSTA_CC);
 125                         return 1;
 126                 }
 127         }
 128         return 0;       /* timeout */
 129 }
 130
 131 static void pcie_wait_cmd(struct controller *ctrl)
 132 {
 133         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 134         unsigned long duration = msecs_to_jiffies(msecs);
 135         unsigned long cmd_timeout = ctrl->cmd_started + duration;
 136         unsigned long now, timeout;
 137         int rc;
 138
 139         /*
 140          * If the controller does not generate notifications for command
 141          * completions, we never need to wait between writes.
 142          */
 143         if (NO_CMD_CMPL(ctrl))
 144                 return;
 145
 146         if (!ctrl->cmd_busy)
 147                 return;
 148
 149         /*
 150          * Even if the command has already timed out, we want to call
 151          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 152          */
 153         now = jiffies;
 154         if (time_before_eq(cmd_timeout, now))
 155                 timeout = 1;
 156         else
 157                 timeout = cmd_timeout - now;
 158
 159         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 160             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 161                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162         else
 163                 rc = pcie_poll_cmd(ctrl, timeout);
 164
 165         /*
 166          * Controllers with errata like Intel CF118 don't generate
 167          * completion notifications unless the power/indicator/interlock
 168          * control bits are changed.  On such controllers, we'll emit this
 169          * timeout message when we wait for completion of commands that
 170          * don't change those bits, e.g., commands that merely enable
 171          * interrupts.
 172          */
 173         if (!rc)
 174                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 175                           ctrl->slot_ctrl,
 176                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 177 }
 178
 179 /**
 180  * pcie_write_cmd - Issue controller command
 181  * @ctrl: controller to which the command is issued
 182  * @cmd:  command value written to slot control register
 183  * @mask: bitmask of slot control register to be modified
 184  */
 185 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 186 {
 187         struct pci_dev *pdev = ctrl_dev(ctrl);
 188         u16 slot_ctrl;
 189
 190         mutex_lock(&ctrl->ctrl_lock);
 191
 192         /* Wait for any previous command that might still be in progress */
 193         pcie_wait_cmd(ctrl);
 194
 195         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 196         slot_ctrl &= ~mask;
 197         slot_ctrl |= (cmd & mask);
 198         ctrl->cmd_busy = 1;
 199         smp_mb();
 200         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 201         ctrl->cmd_started = jiffies;
 202         ctrl->slot_ctrl = slot_ctrl;
 203
 204         mutex_unlock(&ctrl->ctrl_lock);
 205 }
 206
 207 bool pciehp_check_link_active(struct controller *ctrl)
 208 {
 209         struct pci_dev *pdev = ctrl_dev(ctrl);
 210         u16 lnk_status;
 211         bool ret;
 212
 213         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 214         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 215
 216         if (ret)
 217                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 218
 219         return ret;
 220 }
 221
 222 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 223 {
 224         int timeout = 1000;
 225
 226         if (pciehp_check_link_active(ctrl) == active)
 227                 return;
 228         while (timeout > 0) {
 229                 msleep(10);
 230                 timeout -= 10;
 231                 if (pciehp_check_link_active(ctrl) == active)
 232                         return;
 233         }
 234         ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 235                         active ? "set" : "cleared");
 236 }
 237
 238 static void pcie_wait_link_active(struct controller *ctrl)
 239 {
 240         __pcie_wait_link_active(ctrl, true);
 241 }
 242
 243 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 244 {
 245         u32 l;
 246         int count = 0;
 247         int delay = 1000, step = 20;
 248         bool found = false;
 249
 250         do {
 251                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 252                 count++;
 253
 254                 if (found)
 255                         break;
 256
 257                 msleep(step);
 258                 delay -= step;
 259         } while (delay > 0);
 260
 261         if (count > 1 && pciehp_debug)
 262                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 263                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 264                         PCI_FUNC(devfn), count, step, l);
 265
 266         return found;
 267 }
 268
 269 int pciehp_check_link_status(struct controller *ctrl)
 270 {
 271         struct pci_dev *pdev = ctrl_dev(ctrl);
 272         bool found;
 273         u16 lnk_status;
 274
 275         /*
 276          * Data Link Layer Link Active Reporting must be capable for
 277          * hot-plug capable downstream port. But old controller might
 278          * not implement it. In this case, we wait for 1000 ms.
 279         */
 280         if (ctrl->link_active_reporting)
 281                 pcie_wait_link_active(ctrl);
 282         else
 283                 msleep(1000);
 284
 285         /* wait 100ms before read pci conf, and try in 1s */
 286         msleep(100);
 287         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 288                                         PCI_DEVFN(0, 0));
 289
 290         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 291         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 292         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 293             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 294                 ctrl_err(ctrl, "Link Training Error occurs\n");
 295                 return -1;
 296         }
 297
 298         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 299
 300         if (!found)
 301                 return -1;
 302
 303         return 0;
 304 }
 305
 306 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 307 {
 308         struct pci_dev *pdev = ctrl_dev(ctrl);
 309         u16 lnk_ctrl;
 310
 311         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 312
 313         if (enable)
 314                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 315         else
 316                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 317
 318         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 319         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 320         return 0;
 321 }
 322
 323 static int pciehp_link_enable(struct controller *ctrl)
 324 {
 325         return __pciehp_link_set(ctrl, true);
 326 }
 327
 328 void pciehp_get_attention_status(struct slot *slot, u8 *status)
 329 {
 330         struct controller *ctrl = slot->ctrl;
 331         struct pci_dev *pdev = ctrl_dev(ctrl);
 332         u16 slot_ctrl;
 333
 334         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 335         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 336                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 337
 338         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 339         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 340                 *status = 1;    /* On */
 341                 break;
 342         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 343                 *status = 2;    /* Blink */
 344                 break;
 345         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 346                 *status = 0;    /* Off */
 347                 break;
 348         default:
 349                 *status = 0xFF;
 350                 break;
 351         }
 352 }
 353
 354 void pciehp_get_power_status(struct slot *slot, u8 *status)
 355 {
 356         struct controller *ctrl = slot->ctrl;
 357         struct pci_dev *pdev = ctrl_dev(ctrl);
 358         u16 slot_ctrl;
 359
 360         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 361         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 362                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 363
 364         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 365         case PCI_EXP_SLTCTL_PWR_ON:
 366                 *status = 1;    /* On */
 367                 break;
 368         case PCI_EXP_SLTCTL_PWR_OFF:
 369                 *status = 0;    /* Off */
 370                 break;
 371         default:
 372                 *status = 0xFF;
 373                 break;
 374         }
 375 }
 376
 377 void pciehp_get_latch_status(struct slot *slot, u8 *status)
 378 {
 379         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 380         u16 slot_status;
 381
 382         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 383         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 384 }
 385
 386 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 387 {
 388         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 389         u16 slot_status;
 390
 391         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 392         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 393 }
 394
 395 int pciehp_query_power_fault(struct slot *slot)
 396 {
 397         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 398         u16 slot_status;
 399
 400         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 401         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 402 }
 403
 404 void pciehp_set_attention_status(struct slot *slot, u8 value)
 405 {
 406         struct controller *ctrl = slot->ctrl;
 407         u16 slot_cmd;
 408
 409         if (!ATTN_LED(ctrl))
 410                 return;
 411
 412         switch (value) {
 413         case 0:         /* turn off */
 414                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 415                 break;
 416         case 1:         /* turn on */
 417                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 418                 break;
 419         case 2:         /* turn blink */
 420                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 421                 break;
 422         default:
 423                 return;
 424         }
 425         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 426                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 427         pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 428 }
 429
 430 void pciehp_green_led_on(struct slot *slot)
 431 {
 432         struct controller *ctrl = slot->ctrl;
 433
 434         if (!PWR_LED(ctrl))
 435                 return;
 436
 437         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
 438         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 439                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 440                  PCI_EXP_SLTCTL_PWR_IND_ON);
 441 }
 442
 443 void pciehp_green_led_off(struct slot *slot)
 444 {
 445         struct controller *ctrl = slot->ctrl;
 446
 447         if (!PWR_LED(ctrl))
 448                 return;
 449
 450         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
 451         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 452                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 453                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 454 }
 455
 456 void pciehp_green_led_blink(struct slot *slot)
 457 {
 458         struct controller *ctrl = slot->ctrl;
 459
 460         if (!PWR_LED(ctrl))
 461                 return;
 462
 463         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
 464         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 465                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 466                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 467 }
 468
 469 int pciehp_power_on_slot(struct slot *slot)
 470 {
 471         struct controller *ctrl = slot->ctrl;
 472         struct pci_dev *pdev = ctrl_dev(ctrl);
 473         u16 slot_status;
 474         int retval;
 475
 476         /* Clear sticky power-fault bit from previous power failures */
 477         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 478         if (slot_status & PCI_EXP_SLTSTA_PFD)
 479                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 480                                            PCI_EXP_SLTSTA_PFD);
 481         ctrl->power_fault_detected = 0;
 482
 483         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 484         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 485                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 486                  PCI_EXP_SLTCTL_PWR_ON);
 487
 488         retval = pciehp_link_enable(ctrl);
 489         if (retval)
 490                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 491
 492         return retval;
 493 }
 494
 495 void pciehp_power_off_slot(struct slot *slot)
 496 {
 497         struct controller *ctrl = slot->ctrl;
 498
 499         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 500         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 501                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 502                  PCI_EXP_SLTCTL_PWR_OFF);
 503 }
 504
 505 static irqreturn_t pcie_isr(int irq, void *dev_id)
 506 {
 507         struct controller *ctrl = (struct controller *)dev_id;
 508         struct pci_dev *pdev = ctrl_dev(ctrl);
 509         struct slot *slot = ctrl->slot;
 510         u16 detected, intr_loc;
 511
 512         /*
 513          * In order to guarantee that all interrupt events are
 514          * serviced, we need to re-inspect Slot Status register after
 515          * clearing what is presumed to be the last pending interrupt.
 516          */
 517         intr_loc = 0;
 518         do {
 519                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
 520
 521                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 522                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 523                              PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 524                 detected &= ~intr_loc;
 525                 intr_loc |= detected;
 526                 if (!intr_loc)
 527                         return IRQ_NONE;
 528                 if (detected)
 529                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 530                                                    intr_loc);
 531         } while (detected);
 532
 533         ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
 534
 535         /* Check Command Complete Interrupt Pending */
 536         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 537                 ctrl->cmd_busy = 0;
 538                 smp_mb();
 539                 wake_up(&ctrl->queue);
 540         }
 541
 542         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 543                 return IRQ_HANDLED;
 544
 545         /* Check MRL Sensor Changed */
 546         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 547                 pciehp_handle_switch_change(slot);
 548
 549         /* Check Attention Button Pressed */
 550         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 551                 pciehp_handle_attention_button(slot);
 552
 553         /* Check Presence Detect Changed */
 554         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 555                 pciehp_handle_presence_change(slot);
 556
 557         /* Check Power Fault Detected */
 558         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 559                 ctrl->power_fault_detected = 1;
 560                 pciehp_handle_power_fault(slot);
 561         }
 562
 563         if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
 564                 pciehp_handle_linkstate_change(slot);
 565
 566         return IRQ_HANDLED;
 567 }
 568
 569 void pcie_enable_notification(struct controller *ctrl)
 570 {
 571         u16 cmd, mask;
 572
 573         /*
 574          * TBD: Power fault detected software notification support.
 575          *
 576          * Power fault detected software notification is not enabled
 577          * now, because it caused power fault detected interrupt storm
 578          * on some machines. On those machines, power fault detected
 579          * bit in the slot status register was set again immediately
 580          * when it is cleared in the interrupt service routine, and
 581          * next power fault detected interrupt was notified again.
 582          */
 583
 584         /*
 585          * Always enable link events: thus link-up and link-down shall
 586          * always be treated as hotplug and unplug respectively. Enable
 587          * presence detect only if Attention Button is not present.
 588          */
 589         cmd = PCI_EXP_SLTCTL_DLLSCE;
 590         if (ATTN_BUTTN(ctrl))
 591                 cmd |= PCI_EXP_SLTCTL_ABPE;
 592         else
 593                 cmd |= PCI_EXP_SLTCTL_PDCE;
 594         if (MRL_SENS(ctrl))
 595                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 596         if (!pciehp_poll_mode)
 597                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 598
 599         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 600                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 601                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 602                 PCI_EXP_SLTCTL_DLLSCE);
 603
 604         pcie_write_cmd(ctrl, cmd, mask);
 605 }
 606
 607 static void pcie_disable_notification(struct controller *ctrl)
 608 {
 609         u16 mask;
 610
 611         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 612                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 613                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 614                 PCI_EXP_SLTCTL_DLLSCE);
 615         pcie_write_cmd(ctrl, 0, mask);
 616 }
 617
 618 /*
 619  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 620  * bus reset of the bridge, but at the same time we want to ensure that it is
 621  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 622  * disable link state notification and presence detection change notification
 623  * momentarily, if we see that they could interfere. Also, clear any spurious
 624  * events after.
 625  */
 626 int pciehp_reset_slot(struct slot *slot, int probe)
 627 {
 628         struct controller *ctrl = slot->ctrl;
 629         struct pci_dev *pdev = ctrl_dev(ctrl);
 630         u16 stat_mask = 0, ctrl_mask = 0;
 631
 632         if (probe)
 633                 return 0;
 634
 635         if (!ATTN_BUTTN(ctrl)) {
 636                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 637                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 638         }
 639         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 640         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 641
 642         pcie_write_cmd(ctrl, 0, ctrl_mask);
 643         if (pciehp_poll_mode)
 644                 del_timer_sync(&ctrl->poll_timer);
 645
 646         pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 647
 648         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 649         pcie_write_cmd(ctrl, ctrl_mask, ctrl_mask);
 650         if (pciehp_poll_mode)
 651                 int_poll_timeout(ctrl->poll_timer.data);
 652
 653         return 0;
 654 }
 655
 656 int pcie_init_notification(struct controller *ctrl)
 657 {
 658         if (pciehp_request_irq(ctrl))
 659                 return -1;
 660         pcie_enable_notification(ctrl);
 661         ctrl->notification_enabled = 1;
 662         return 0;
 663 }
 664
 665 static void pcie_shutdown_notification(struct controller *ctrl)
 666 {
 667         if (ctrl->notification_enabled) {
 668                 pcie_disable_notification(ctrl);
 669                 pciehp_free_irq(ctrl);
 670                 ctrl->notification_enabled = 0;
 671         }
 672 }
 673
 674 static int pcie_init_slot(struct controller *ctrl)
 675 {
 676         struct slot *slot;
 677
 678         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 679         if (!slot)
 680                 return -ENOMEM;
 681
 682         slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
 683         if (!slot->wq)
 684                 goto abort;
 685
 686         slot->ctrl = ctrl;
 687         mutex_init(&slot->lock);
 688         mutex_init(&slot->hotplug_lock);
 689         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 690         ctrl->slot = slot;
 691         return 0;
 692 abort:
 693         kfree(slot);
 694         return -ENOMEM;
 695 }
 696
 697 static void pcie_cleanup_slot(struct controller *ctrl)
 698 {
 699         struct slot *slot = ctrl->slot;
 700         cancel_delayed_work(&slot->work);
 701         destroy_workqueue(slot->wq);
 702         kfree(slot);
 703 }
 704
 705 static inline void dbg_ctrl(struct controller *ctrl)
 706 {
 707         int i;
 708         u16 reg16;
 709         struct pci_dev *pdev = ctrl->pcie->port;
 710
 711         if (!pciehp_debug)
 712                 return;
 713
 714         ctrl_info(ctrl, "Hotplug Controller:\n");
 715         ctrl_info(ctrl, "  Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
 716                   pci_name(pdev), pdev->irq);
 717         ctrl_info(ctrl, "  Vendor ID            : 0x%04x\n", pdev->vendor);
 718         ctrl_info(ctrl, "  Device ID            : 0x%04x\n", pdev->device);
 719         ctrl_info(ctrl, "  Subsystem ID         : 0x%04x\n",
 720                   pdev->subsystem_device);
 721         ctrl_info(ctrl, "  Subsystem Vendor ID  : 0x%04x\n",
 722                   pdev->subsystem_vendor);
 723         ctrl_info(ctrl, "  PCIe Cap offset      : 0x%02x\n",
 724                   pci_pcie_cap(pdev));
 725         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 726                 if (!pci_resource_len(pdev, i))
 727                         continue;
 728                 ctrl_info(ctrl, "  PCI resource [%d]     : %pR\n",
 729                           i, &pdev->resource[i]);
 730         }
 731         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 732         ctrl_info(ctrl, "  Physical Slot Number : %d\n", PSN(ctrl));
 733         ctrl_info(ctrl, "  Attention Button     : %3s\n",
 734                   ATTN_BUTTN(ctrl) ? "yes" : "no");
 735         ctrl_info(ctrl, "  Power Controller     : %3s\n",
 736                   POWER_CTRL(ctrl) ? "yes" : "no");
 737         ctrl_info(ctrl, "  MRL Sensor           : %3s\n",
 738                   MRL_SENS(ctrl)   ? "yes" : "no");
 739         ctrl_info(ctrl, "  Attention Indicator  : %3s\n",
 740                   ATTN_LED(ctrl)   ? "yes" : "no");
 741         ctrl_info(ctrl, "  Power Indicator      : %3s\n",
 742                   PWR_LED(ctrl)    ? "yes" : "no");
 743         ctrl_info(ctrl, "  Hot-Plug Surprise    : %3s\n",
 744                   HP_SUPR_RM(ctrl) ? "yes" : "no");
 745         ctrl_info(ctrl, "  EMI Present          : %3s\n",
 746                   EMI(ctrl)        ? "yes" : "no");
 747         ctrl_info(ctrl, "  Command Completed    : %3s\n",
 748                   NO_CMD_CMPL(ctrl) ? "no" : "yes");
 749         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 750         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 751         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 752         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 753 }
 754
 755 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 756
 757 struct controller *pcie_init(struct pcie_device *dev)
 758 {
 759         struct controller *ctrl;
 760         u32 slot_cap, link_cap;
 761         struct pci_dev *pdev = dev->port;
 762
 763         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 764         if (!ctrl) {
 765                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 766                 goto abort;
 767         }
 768         ctrl->pcie = dev;
 769         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 770         ctrl->slot_cap = slot_cap;
 771         mutex_init(&ctrl->ctrl_lock);
 772         init_waitqueue_head(&ctrl->queue);
 773         dbg_ctrl(ctrl);
 774
 775         /* Check if Data Link Layer Link Active Reporting is implemented */
 776         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 777         if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
 778                 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
 779                 ctrl->link_active_reporting = 1;
 780         }
 781
 782         /* Clear all remaining event bits in Slot Status register */
 783         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 784                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 785                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 786                 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 787
 788         /* Disable software notification */
 789         pcie_disable_notification(ctrl);
 790
 791         ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
 792                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 793                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 794                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 795                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 796                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 797                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 798                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 799                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 800                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 801
 802         if (pcie_init_slot(ctrl))
 803                 goto abort_ctrl;
 804
 805         return ctrl;
 806
 807 abort_ctrl:
 808         kfree(ctrl);
 809 abort:
 810         return NULL;
 811 }
 812
 813 void pciehp_release_ctrl(struct controller *ctrl)
 814 {
 815         pcie_shutdown_notification(ctrl);
 816         pcie_cleanup_slot(ctrl);
 817         kfree(ctrl);
 818 }