drivers/pci/hotplug/pciehp_hpc.c

   1 /*
   2  * PCI Express PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/types.h>
  33 #include <linux/signal.h>
  34 #include <linux/jiffies.h>
  35 #include <linux/timer.h>
  36 #include <linux/pci.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/time.h>
  39 #include <linux/slab.h>
  40
  41 #include "../pci.h"
  42 #include "pciehp.h"
  43
  44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
  45 {
  46         return ctrl->pcie->port;
  47 }
  48
  49 static irqreturn_t pcie_isr(int irq, void *dev_id);
  50 static void start_int_poll_timer(struct controller *ctrl, int sec);
  51
  52 /* This is the interrupt polling timeout function. */
  53 static void int_poll_timeout(unsigned long data)
  54 {
  55         struct controller *ctrl = (struct controller *)data;
  56
  57         /* Poll for interrupt events.  regs == NULL => polling */
  58         pcie_isr(0, ctrl);
  59
  60         init_timer(&ctrl->poll_timer);
  61         if (!pciehp_poll_time)
  62                 pciehp_poll_time = 2; /* default polling interval is 2 sec */
  63
  64         start_int_poll_timer(ctrl, pciehp_poll_time);
  65 }
  66
  67 /* This function starts the interrupt polling timer. */
  68 static void start_int_poll_timer(struct controller *ctrl, int sec)
  69 {
  70         /* Clamp to sane value */
  71         if ((sec <= 0) || (sec > 60))
  72                 sec = 2;
  73
  74         ctrl->poll_timer.function = &int_poll_timeout;
  75         ctrl->poll_timer.data = (unsigned long)ctrl;
  76         ctrl->poll_timer.expires = jiffies + sec * HZ;
  77         add_timer(&ctrl->poll_timer);
  78 }
  79
  80 static inline int pciehp_request_irq(struct controller *ctrl)
  81 {
  82         int retval, irq = ctrl->pcie->irq;
  83
  84         /* Install interrupt polling timer. Start with 10 sec delay */
  85         if (pciehp_poll_mode) {
  86                 init_timer(&ctrl->poll_timer);
  87                 start_int_poll_timer(ctrl, 10);
  88                 return 0;
  89         }
  90
  91         /* Installs the interrupt handler */
  92         retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
  93         if (retval)
  94                 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
  95                          irq);
  96         return retval;
  97 }
  98
  99 static inline void pciehp_free_irq(struct controller *ctrl)
 100 {
 101         if (pciehp_poll_mode)
 102                 del_timer_sync(&ctrl->poll_timer);
 103         else
 104                 free_irq(ctrl->pcie->irq, ctrl);
 105 }
 106
 107 static int pcie_poll_cmd(struct controller *ctrl, int timeout)
 108 {
 109         struct pci_dev *pdev = ctrl_dev(ctrl);
 110         u16 slot_status;
 111
 112         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 113         if (slot_status & PCI_EXP_SLTSTA_CC) {
 114                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 115                                            PCI_EXP_SLTSTA_CC);
 116                 return 1;
 117         }
 118         while (timeout > 0) {
 119                 msleep(10);
 120                 timeout -= 10;
 121                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 122                 if (slot_status & PCI_EXP_SLTSTA_CC) {
 123                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 124                                                    PCI_EXP_SLTSTA_CC);
 125                         return 1;
 126                 }
 127         }
 128         return 0;       /* timeout */
 129 }
 130
 131 static void pcie_wait_cmd(struct controller *ctrl)
 132 {
 133         unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
 134         unsigned long duration = msecs_to_jiffies(msecs);
 135         unsigned long cmd_timeout = ctrl->cmd_started + duration;
 136         unsigned long now, timeout;
 137         int rc;
 138
 139         /*
 140          * If the controller does not generate notifications for command
 141          * completions, we never need to wait between writes.
 142          */
 143         if (NO_CMD_CMPL(ctrl))
 144                 return;
 145
 146         if (!ctrl->cmd_busy)
 147                 return;
 148
 149         /*
 150          * Even if the command has already timed out, we want to call
 151          * pcie_poll_cmd() so it can clear PCI_EXP_SLTSTA_CC.
 152          */
 153         now = jiffies;
 154         if (time_before_eq(cmd_timeout, now))
 155                 timeout = 1;
 156         else
 157                 timeout = cmd_timeout - now;
 158
 159         if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE &&
 160             ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE)
 161                 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
 162         else
 163                 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout));
 164
 165         /*
 166          * Controllers with errata like Intel CF118 don't generate
 167          * completion notifications unless the power/indicator/interlock
 168          * control bits are changed.  On such controllers, we'll emit this
 169          * timeout message when we wait for completion of commands that
 170          * don't change those bits, e.g., commands that merely enable
 171          * interrupts.
 172          */
 173         if (!rc)
 174                 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n",
 175                           ctrl->slot_ctrl,
 176                           jiffies_to_msecs(jiffies - ctrl->cmd_started));
 177 }
 178
 179 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd,
 180                               u16 mask, bool wait)
 181 {
 182         struct pci_dev *pdev = ctrl_dev(ctrl);
 183         u16 slot_ctrl;
 184
 185         mutex_lock(&ctrl->ctrl_lock);
 186
 187         /*
 188          * Always wait for any previous command that might still be in progress
 189          */
 190         pcie_wait_cmd(ctrl);
 191
 192         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 193         slot_ctrl &= ~mask;
 194         slot_ctrl |= (cmd & mask);
 195         ctrl->cmd_busy = 1;
 196         smp_mb();
 197         pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
 198         ctrl->cmd_started = jiffies;
 199         ctrl->slot_ctrl = slot_ctrl;
 200
 201         /*
 202          * Optionally wait for the hardware to be ready for a new command,
 203          * indicating completion of the above issued command.
 204          */
 205         if (wait)
 206                 pcie_wait_cmd(ctrl);
 207
 208         mutex_unlock(&ctrl->ctrl_lock);
 209 }
 210
 211 /**
 212  * pcie_write_cmd - Issue controller command
 213  * @ctrl: controller to which the command is issued
 214  * @cmd:  command value written to slot control register
 215  * @mask: bitmask of slot control register to be modified
 216  */
 217 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
 218 {
 219         pcie_do_write_cmd(ctrl, cmd, mask, true);
 220 }
 221
 222 /* Same as above without waiting for the hardware to latch */
 223 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask)
 224 {
 225         pcie_do_write_cmd(ctrl, cmd, mask, false);
 226 }
 227
 228 bool pciehp_check_link_active(struct controller *ctrl)
 229 {
 230         struct pci_dev *pdev = ctrl_dev(ctrl);
 231         u16 lnk_status;
 232         bool ret;
 233
 234         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 235         ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
 236
 237         if (ret)
 238                 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 239
 240         return ret;
 241 }
 242
 243 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
 244 {
 245         int timeout = 1000;
 246
 247         if (pciehp_check_link_active(ctrl) == active)
 248                 return;
 249         while (timeout > 0) {
 250                 msleep(10);
 251                 timeout -= 10;
 252                 if (pciehp_check_link_active(ctrl) == active)
 253                         return;
 254         }
 255         ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
 256                         active ? "set" : "cleared");
 257 }
 258
 259 static void pcie_wait_link_active(struct controller *ctrl)
 260 {
 261         __pcie_wait_link_active(ctrl, true);
 262 }
 263
 264 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
 265 {
 266         u32 l;
 267         int count = 0;
 268         int delay = 1000, step = 20;
 269         bool found = false;
 270
 271         do {
 272                 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
 273                 count++;
 274
 275                 if (found)
 276                         break;
 277
 278                 msleep(step);
 279                 delay -= step;
 280         } while (delay > 0);
 281
 282         if (count > 1 && pciehp_debug)
 283                 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
 284                         pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
 285                         PCI_FUNC(devfn), count, step, l);
 286
 287         return found;
 288 }
 289
 290 int pciehp_check_link_status(struct controller *ctrl)
 291 {
 292         struct pci_dev *pdev = ctrl_dev(ctrl);
 293         bool found;
 294         u16 lnk_status;
 295
 296         /*
 297          * Data Link Layer Link Active Reporting must be capable for
 298          * hot-plug capable downstream port. But old controller might
 299          * not implement it. In this case, we wait for 1000 ms.
 300         */
 301         if (ctrl->link_active_reporting)
 302                 pcie_wait_link_active(ctrl);
 303         else
 304                 msleep(1000);
 305
 306         /* wait 100ms before read pci conf, and try in 1s */
 307         msleep(100);
 308         found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
 309                                         PCI_DEVFN(0, 0));
 310
 311         pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
 312         ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
 313         if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
 314             !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
 315                 ctrl_err(ctrl, "link training error: status %#06x\n",
 316                          lnk_status);
 317                 return -1;
 318         }
 319
 320         pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
 321
 322         if (!found)
 323                 return -1;
 324
 325         return 0;
 326 }
 327
 328 static int __pciehp_link_set(struct controller *ctrl, bool enable)
 329 {
 330         struct pci_dev *pdev = ctrl_dev(ctrl);
 331         u16 lnk_ctrl;
 332
 333         pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
 334
 335         if (enable)
 336                 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
 337         else
 338                 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
 339
 340         pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
 341         ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
 342         return 0;
 343 }
 344
 345 static int pciehp_link_enable(struct controller *ctrl)
 346 {
 347         return __pciehp_link_set(ctrl, true);
 348 }
 349
 350 void pciehp_get_attention_status(struct slot *slot, u8 *status)
 351 {
 352         struct controller *ctrl = slot->ctrl;
 353         struct pci_dev *pdev = ctrl_dev(ctrl);
 354         u16 slot_ctrl;
 355
 356         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 357         ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
 358                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 359
 360         switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
 361         case PCI_EXP_SLTCTL_ATTN_IND_ON:
 362                 *status = 1;    /* On */
 363                 break;
 364         case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
 365                 *status = 2;    /* Blink */
 366                 break;
 367         case PCI_EXP_SLTCTL_ATTN_IND_OFF:
 368                 *status = 0;    /* Off */
 369                 break;
 370         default:
 371                 *status = 0xFF;
 372                 break;
 373         }
 374 }
 375
 376 void pciehp_get_power_status(struct slot *slot, u8 *status)
 377 {
 378         struct controller *ctrl = slot->ctrl;
 379         struct pci_dev *pdev = ctrl_dev(ctrl);
 380         u16 slot_ctrl;
 381
 382         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 383         ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
 384                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
 385
 386         switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
 387         case PCI_EXP_SLTCTL_PWR_ON:
 388                 *status = 1;    /* On */
 389                 break;
 390         case PCI_EXP_SLTCTL_PWR_OFF:
 391                 *status = 0;    /* Off */
 392                 break;
 393         default:
 394                 *status = 0xFF;
 395                 break;
 396         }
 397 }
 398
 399 void pciehp_get_latch_status(struct slot *slot, u8 *status)
 400 {
 401         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 402         u16 slot_status;
 403
 404         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 405         *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
 406 }
 407
 408 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
 409 {
 410         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 411         u16 slot_status;
 412
 413         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 414         *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
 415 }
 416
 417 int pciehp_query_power_fault(struct slot *slot)
 418 {
 419         struct pci_dev *pdev = ctrl_dev(slot->ctrl);
 420         u16 slot_status;
 421
 422         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 423         return !!(slot_status & PCI_EXP_SLTSTA_PFD);
 424 }
 425
 426 void pciehp_set_attention_status(struct slot *slot, u8 value)
 427 {
 428         struct controller *ctrl = slot->ctrl;
 429         u16 slot_cmd;
 430
 431         if (!ATTN_LED(ctrl))
 432                 return;
 433
 434         switch (value) {
 435         case 0:         /* turn off */
 436                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
 437                 break;
 438         case 1:         /* turn on */
 439                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
 440                 break;
 441         case 2:         /* turn blink */
 442                 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
 443                 break;
 444         default:
 445                 return;
 446         }
 447         pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
 448         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 449                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
 450 }
 451
 452 void pciehp_green_led_on(struct slot *slot)
 453 {
 454         struct controller *ctrl = slot->ctrl;
 455
 456         if (!PWR_LED(ctrl))
 457                 return;
 458
 459         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
 460                               PCI_EXP_SLTCTL_PIC);
 461         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 462                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 463                  PCI_EXP_SLTCTL_PWR_IND_ON);
 464 }
 465
 466 void pciehp_green_led_off(struct slot *slot)
 467 {
 468         struct controller *ctrl = slot->ctrl;
 469
 470         if (!PWR_LED(ctrl))
 471                 return;
 472
 473         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
 474                               PCI_EXP_SLTCTL_PIC);
 475         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 476                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 477                  PCI_EXP_SLTCTL_PWR_IND_OFF);
 478 }
 479
 480 void pciehp_green_led_blink(struct slot *slot)
 481 {
 482         struct controller *ctrl = slot->ctrl;
 483
 484         if (!PWR_LED(ctrl))
 485                 return;
 486
 487         pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
 488                               PCI_EXP_SLTCTL_PIC);
 489         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 490                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 491                  PCI_EXP_SLTCTL_PWR_IND_BLINK);
 492 }
 493
 494 int pciehp_power_on_slot(struct slot *slot)
 495 {
 496         struct controller *ctrl = slot->ctrl;
 497         struct pci_dev *pdev = ctrl_dev(ctrl);
 498         u16 slot_status;
 499         int retval;
 500
 501         /* Clear sticky power-fault bit from previous power failures */
 502         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
 503         if (slot_status & PCI_EXP_SLTSTA_PFD)
 504                 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 505                                            PCI_EXP_SLTSTA_PFD);
 506         ctrl->power_fault_detected = 0;
 507
 508         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
 509         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 510                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 511                  PCI_EXP_SLTCTL_PWR_ON);
 512
 513         retval = pciehp_link_enable(ctrl);
 514         if (retval)
 515                 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
 516
 517         return retval;
 518 }
 519
 520 void pciehp_power_off_slot(struct slot *slot)
 521 {
 522         struct controller *ctrl = slot->ctrl;
 523
 524         pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
 525         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 526                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
 527                  PCI_EXP_SLTCTL_PWR_OFF);
 528 }
 529
 530 static irqreturn_t pcie_isr(int irq, void *dev_id)
 531 {
 532         struct controller *ctrl = (struct controller *)dev_id;
 533         struct pci_dev *pdev = ctrl_dev(ctrl);
 534         struct pci_bus *subordinate = pdev->subordinate;
 535         struct pci_dev *dev;
 536         struct slot *slot = ctrl->slot;
 537         u16 detected, intr_loc;
 538
 539         /*
 540          * In order to guarantee that all interrupt events are
 541          * serviced, we need to re-inspect Slot Status register after
 542          * clearing what is presumed to be the last pending interrupt.
 543          */
 544         intr_loc = 0;
 545         do {
 546                 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
 547
 548                 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 549                              PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 550                              PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 551                 detected &= ~intr_loc;
 552                 intr_loc |= detected;
 553                 if (!intr_loc)
 554                         return IRQ_NONE;
 555                 if (detected)
 556                         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 557                                                    intr_loc);
 558         } while (detected);
 559
 560         ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", intr_loc);
 561
 562         /* Check Command Complete Interrupt Pending */
 563         if (intr_loc & PCI_EXP_SLTSTA_CC) {
 564                 ctrl->cmd_busy = 0;
 565                 smp_mb();
 566                 wake_up(&ctrl->queue);
 567         }
 568
 569         if (subordinate) {
 570                 list_for_each_entry(dev, &subordinate->devices, bus_list) {
 571                         if (dev->ignore_hotplug) {
 572                                 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n",
 573                                          intr_loc, pci_name(dev));
 574                                 return IRQ_HANDLED;
 575                         }
 576                 }
 577         }
 578
 579         if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
 580                 return IRQ_HANDLED;
 581
 582         /* Check MRL Sensor Changed */
 583         if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
 584                 pciehp_handle_switch_change(slot);
 585
 586         /* Check Attention Button Pressed */
 587         if (intr_loc & PCI_EXP_SLTSTA_ABP)
 588                 pciehp_handle_attention_button(slot);
 589
 590         /* Check Presence Detect Changed */
 591         if (intr_loc & PCI_EXP_SLTSTA_PDC)
 592                 pciehp_handle_presence_change(slot);
 593
 594         /* Check Power Fault Detected */
 595         if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
 596                 ctrl->power_fault_detected = 1;
 597                 pciehp_handle_power_fault(slot);
 598         }
 599
 600         if (intr_loc & PCI_EXP_SLTSTA_DLLSC)
 601                 pciehp_handle_linkstate_change(slot);
 602
 603         return IRQ_HANDLED;
 604 }
 605
 606 void pcie_enable_notification(struct controller *ctrl)
 607 {
 608         u16 cmd, mask;
 609
 610         /*
 611          * TBD: Power fault detected software notification support.
 612          *
 613          * Power fault detected software notification is not enabled
 614          * now, because it caused power fault detected interrupt storm
 615          * on some machines. On those machines, power fault detected
 616          * bit in the slot status register was set again immediately
 617          * when it is cleared in the interrupt service routine, and
 618          * next power fault detected interrupt was notified again.
 619          */
 620
 621         /*
 622          * Always enable link events: thus link-up and link-down shall
 623          * always be treated as hotplug and unplug respectively. Enable
 624          * presence detect only if Attention Button is not present.
 625          */
 626         cmd = PCI_EXP_SLTCTL_DLLSCE;
 627         if (ATTN_BUTTN(ctrl))
 628                 cmd |= PCI_EXP_SLTCTL_ABPE;
 629         else
 630                 cmd |= PCI_EXP_SLTCTL_PDCE;
 631         if (MRL_SENS(ctrl))
 632                 cmd |= PCI_EXP_SLTCTL_MRLSCE;
 633         if (!pciehp_poll_mode)
 634                 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
 635
 636         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 637                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 638                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 639                 PCI_EXP_SLTCTL_DLLSCE);
 640
 641         pcie_write_cmd_nowait(ctrl, cmd, mask);
 642         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 643                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
 644 }
 645
 646 static void pcie_disable_notification(struct controller *ctrl)
 647 {
 648         u16 mask;
 649
 650         mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
 651                 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
 652                 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
 653                 PCI_EXP_SLTCTL_DLLSCE);
 654         pcie_write_cmd(ctrl, 0, mask);
 655         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 656                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 657 }
 658
 659 /*
 660  * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
 661  * bus reset of the bridge, but at the same time we want to ensure that it is
 662  * not seen as a hot-unplug, followed by the hot-plug of the device. Thus,
 663  * disable link state notification and presence detection change notification
 664  * momentarily, if we see that they could interfere. Also, clear any spurious
 665  * events after.
 666  */
 667 int pciehp_reset_slot(struct slot *slot, int probe)
 668 {
 669         struct controller *ctrl = slot->ctrl;
 670         struct pci_dev *pdev = ctrl_dev(ctrl);
 671         u16 stat_mask = 0, ctrl_mask = 0;
 672
 673         if (probe)
 674                 return 0;
 675
 676         if (!ATTN_BUTTN(ctrl)) {
 677                 ctrl_mask |= PCI_EXP_SLTCTL_PDCE;
 678                 stat_mask |= PCI_EXP_SLTSTA_PDC;
 679         }
 680         ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
 681         stat_mask |= PCI_EXP_SLTSTA_DLLSC;
 682
 683         pcie_write_cmd(ctrl, 0, ctrl_mask);
 684         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 685                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
 686         if (pciehp_poll_mode)
 687                 del_timer_sync(&ctrl->poll_timer);
 688
 689         pci_reset_bridge_secondary_bus(ctrl->pcie->port);
 690
 691         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
 692         pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
 693         ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
 694                  pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
 695         if (pciehp_poll_mode)
 696                 int_poll_timeout(ctrl->poll_timer.data);
 697
 698         return 0;
 699 }
 700
 701 int pcie_init_notification(struct controller *ctrl)
 702 {
 703         if (pciehp_request_irq(ctrl))
 704                 return -1;
 705         pcie_enable_notification(ctrl);
 706         ctrl->notification_enabled = 1;
 707         return 0;
 708 }
 709
 710 static void pcie_shutdown_notification(struct controller *ctrl)
 711 {
 712         if (ctrl->notification_enabled) {
 713                 pcie_disable_notification(ctrl);
 714                 pciehp_free_irq(ctrl);
 715                 ctrl->notification_enabled = 0;
 716         }
 717 }
 718
 719 static int pcie_init_slot(struct controller *ctrl)
 720 {
 721         struct slot *slot;
 722
 723         slot = kzalloc(sizeof(*slot), GFP_KERNEL);
 724         if (!slot)
 725                 return -ENOMEM;
 726
 727         slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
 728         if (!slot->wq)
 729                 goto abort;
 730
 731         slot->ctrl = ctrl;
 732         mutex_init(&slot->lock);
 733         mutex_init(&slot->hotplug_lock);
 734         INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
 735         ctrl->slot = slot;
 736         return 0;
 737 abort:
 738         kfree(slot);
 739         return -ENOMEM;
 740 }
 741
 742 static void pcie_cleanup_slot(struct controller *ctrl)
 743 {
 744         struct slot *slot = ctrl->slot;
 745         cancel_delayed_work(&slot->work);
 746         destroy_workqueue(slot->wq);
 747         kfree(slot);
 748 }
 749
 750 static inline void dbg_ctrl(struct controller *ctrl)
 751 {
 752         struct pci_dev *pdev = ctrl->pcie->port;
 753         u16 reg16;
 754
 755         if (!pciehp_debug)
 756                 return;
 757
 758         ctrl_info(ctrl, "Slot Capabilities      : 0x%08x\n", ctrl->slot_cap);
 759         pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &reg16);
 760         ctrl_info(ctrl, "Slot Status            : 0x%04x\n", reg16);
 761         pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &reg16);
 762         ctrl_info(ctrl, "Slot Control           : 0x%04x\n", reg16);
 763 }
 764
 765 #define FLAG(x, y)      (((x) & (y)) ? '+' : '-')
 766
 767 struct controller *pcie_init(struct pcie_device *dev)
 768 {
 769         struct controller *ctrl;
 770         u32 slot_cap, link_cap;
 771         struct pci_dev *pdev = dev->port;
 772
 773         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
 774         if (!ctrl) {
 775                 dev_err(&dev->device, "%s: Out of memory\n", __func__);
 776                 goto abort;
 777         }
 778         ctrl->pcie = dev;
 779         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 780         ctrl->slot_cap = slot_cap;
 781         mutex_init(&ctrl->ctrl_lock);
 782         init_waitqueue_head(&ctrl->queue);
 783         dbg_ctrl(ctrl);
 784
 785         /* Check if Data Link Layer Link Active Reporting is implemented */
 786         pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
 787         if (link_cap & PCI_EXP_LNKCAP_DLLLARC)
 788                 ctrl->link_active_reporting = 1;
 789
 790         /* Clear all remaining event bits in Slot Status register */
 791         pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
 792                 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
 793                 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
 794                 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC);
 795
 796         ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c\n",
 797                 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
 798                 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
 799                 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
 800                 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
 801                 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
 802                 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
 803                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPC),
 804                 FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
 805                 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
 806                 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
 807                 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
 808
 809         if (pcie_init_slot(ctrl))
 810                 goto abort_ctrl;
 811
 812         return ctrl;
 813
 814 abort_ctrl:
 815         kfree(ctrl);
 816 abort:
 817         return NULL;
 818 }
 819
 820 void pciehp_release_ctrl(struct controller *ctrl)
 821 {
 822         pcie_shutdown_notification(ctrl);
 823         pcie_cleanup_slot(ctrl);
 824         kfree(ctrl);
 825 }