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pciehp: remove trailing whitespace form pciehp_pci.c
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / hotplug / pciehp_hpc.c
1 /*
2 * PCI Express PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39
40 #include "../pci.h"
41 #include "pciehp.h"
42
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
44
45 struct ctrl_reg {
46 u8 cap_id;
47 u8 nxt_ptr;
48 u16 cap_reg;
49 u32 dev_cap;
50 u16 dev_ctrl;
51 u16 dev_status;
52 u32 lnk_cap;
53 u16 lnk_ctrl;
54 u16 lnk_status;
55 u32 slot_cap;
56 u16 slot_ctrl;
57 u16 slot_status;
58 u16 root_ctrl;
59 u16 rsvp;
60 u32 root_status;
61 } __attribute__ ((packed));
62
63 /* offsets to the controller registers based on the above structure layout */
64 enum ctrl_offsets {
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
79 };
80
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
82 {
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
85 }
86
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
88 {
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
91 }
92
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
94 {
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
97 }
98
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
100 {
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
103 }
104
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
110
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
119
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
124
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
128
129 /* Link Width Encoding */
130 #define LNK_X1 0x01
131 #define LNK_X2 0x02
132 #define LNK_X4 0x04
133 #define LNK_X8 0x08
134 #define LNK_X12 0x0C
135 #define LNK_X16 0x10
136 #define LNK_X32 0x20
137
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
144
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
156
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
168
169 /* Attention indicator and Power indicator states */
170 #define LED_ON 0x01
171 #define LED_BLINK 0x10
172 #define LED_OFF 0x11
173
174 /* Power Control Command */
175 #define POWER_ON 0
176 #define POWER_OFF 0x0400
177
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
181
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
192
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
195
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
198 {
199 struct controller *ctrl = (struct controller *)data;
200
201 /* Poll for interrupt events. regs == NULL => polling */
202 pcie_isr(0, ctrl);
203
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
207
208 start_int_poll_timer(ctrl, pciehp_poll_time);
209 }
210
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
213 {
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
216 sec = 2;
217
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
222 }
223
224 static inline int pcie_wait_cmd(struct controller *ctrl)
225 {
226 int retval = 0;
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
229 int rc;
230
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
233 if (!rc)
234 dbg("Command not completed in 1000 msec\n");
235 else if (rc < 0) {
236 retval = -EINTR;
237 info("Command was interrupted by a signal\n");
238 }
239
240 return retval;
241 }
242
243 /**
244 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
248 */
249 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
250 {
251 struct controller *ctrl = slot->ctrl;
252 int retval = 0;
253 u16 slot_status;
254 u16 slot_ctrl;
255 unsigned long flags;
256
257 mutex_lock(&ctrl->ctrl_lock);
258
259 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
260 if (retval) {
261 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
262 goto out;
263 }
264
265 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
266 /* After 1 sec and CMD_COMPLETED still not set, just
267 proceed forward to issue the next command according
268 to spec. Just print out the error message */
269 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
270 __FUNCTION__);
271 }
272
273 spin_lock_irqsave(&ctrl->lock, flags);
274 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
275 if (retval) {
276 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
277 goto out_spin_unlock;
278 }
279
280 slot_ctrl &= ~mask;
281 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
282
283 ctrl->cmd_busy = 1;
284 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
285 if (retval)
286 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
287
288 out_spin_unlock:
289 spin_unlock_irqrestore(&ctrl->lock, flags);
290
291 /*
292 * Wait for command completion.
293 */
294 if (!retval)
295 retval = pcie_wait_cmd(ctrl);
296 out:
297 mutex_unlock(&ctrl->ctrl_lock);
298 return retval;
299 }
300
301 static int hpc_check_lnk_status(struct controller *ctrl)
302 {
303 u16 lnk_status;
304 int retval = 0;
305
306 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
307 if (retval) {
308 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
309 return retval;
310 }
311
312 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
313 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
314 !(lnk_status & NEG_LINK_WD)) {
315 err("%s : Link Training Error occurs \n", __FUNCTION__);
316 retval = -1;
317 return retval;
318 }
319
320 return retval;
321 }
322
323
324 static int hpc_get_attention_status(struct slot *slot, u8 *status)
325 {
326 struct controller *ctrl = slot->ctrl;
327 u16 slot_ctrl;
328 u8 atten_led_state;
329 int retval = 0;
330
331 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
332 if (retval) {
333 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
334 return retval;
335 }
336
337 dbg("%s: SLOTCTRL %x, value read %x\n",
338 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
339
340 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
341
342 switch (atten_led_state) {
343 case 0:
344 *status = 0xFF; /* Reserved */
345 break;
346 case 1:
347 *status = 1; /* On */
348 break;
349 case 2:
350 *status = 2; /* Blink */
351 break;
352 case 3:
353 *status = 0; /* Off */
354 break;
355 default:
356 *status = 0xFF;
357 break;
358 }
359
360 return 0;
361 }
362
363 static int hpc_get_power_status(struct slot *slot, u8 *status)
364 {
365 struct controller *ctrl = slot->ctrl;
366 u16 slot_ctrl;
367 u8 pwr_state;
368 int retval = 0;
369
370 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
371 if (retval) {
372 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
373 return retval;
374 }
375 dbg("%s: SLOTCTRL %x value read %x\n",
376 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
377
378 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
379
380 switch (pwr_state) {
381 case 0:
382 *status = 1;
383 break;
384 case 1:
385 *status = 0;
386 break;
387 default:
388 *status = 0xFF;
389 break;
390 }
391
392 return retval;
393 }
394
395
396 static int hpc_get_latch_status(struct slot *slot, u8 *status)
397 {
398 struct controller *ctrl = slot->ctrl;
399 u16 slot_status;
400 int retval = 0;
401
402 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
403 if (retval) {
404 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
405 return retval;
406 }
407
408 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
409
410 return 0;
411 }
412
413 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
414 {
415 struct controller *ctrl = slot->ctrl;
416 u16 slot_status;
417 u8 card_state;
418 int retval = 0;
419
420 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
421 if (retval) {
422 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
423 return retval;
424 }
425 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
426 *status = (card_state == 1) ? 1 : 0;
427
428 return 0;
429 }
430
431 static int hpc_query_power_fault(struct slot *slot)
432 {
433 struct controller *ctrl = slot->ctrl;
434 u16 slot_status;
435 u8 pwr_fault;
436 int retval = 0;
437
438 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
439 if (retval) {
440 err("%s: Cannot check for power fault\n", __FUNCTION__);
441 return retval;
442 }
443 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
444
445 return pwr_fault;
446 }
447
448 static int hpc_get_emi_status(struct slot *slot, u8 *status)
449 {
450 struct controller *ctrl = slot->ctrl;
451 u16 slot_status;
452 int retval = 0;
453
454 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
455 if (retval) {
456 err("%s : Cannot check EMI status\n", __FUNCTION__);
457 return retval;
458 }
459 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
460
461 return retval;
462 }
463
464 static int hpc_toggle_emi(struct slot *slot)
465 {
466 u16 slot_cmd;
467 u16 cmd_mask;
468 int rc;
469
470 slot_cmd = EMI_CTRL;
471 cmd_mask = EMI_CTRL;
472 if (!pciehp_poll_mode) {
473 slot_cmd = slot_cmd | HP_INTR_ENABLE;
474 cmd_mask = cmd_mask | HP_INTR_ENABLE;
475 }
476
477 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
478 slot->last_emi_toggle = get_seconds();
479
480 return rc;
481 }
482
483 static int hpc_set_attention_status(struct slot *slot, u8 value)
484 {
485 struct controller *ctrl = slot->ctrl;
486 u16 slot_cmd;
487 u16 cmd_mask;
488 int rc;
489
490 cmd_mask = ATTN_LED_CTRL;
491 switch (value) {
492 case 0 : /* turn off */
493 slot_cmd = 0x00C0;
494 break;
495 case 1: /* turn on */
496 slot_cmd = 0x0040;
497 break;
498 case 2: /* turn blink */
499 slot_cmd = 0x0080;
500 break;
501 default:
502 return -1;
503 }
504 if (!pciehp_poll_mode) {
505 slot_cmd = slot_cmd | HP_INTR_ENABLE;
506 cmd_mask = cmd_mask | HP_INTR_ENABLE;
507 }
508
509 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
510 dbg("%s: SLOTCTRL %x write cmd %x\n",
511 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
512
513 return rc;
514 }
515
516
517 static void hpc_set_green_led_on(struct slot *slot)
518 {
519 struct controller *ctrl = slot->ctrl;
520 u16 slot_cmd;
521 u16 cmd_mask;
522
523 slot_cmd = 0x0100;
524 cmd_mask = PWR_LED_CTRL;
525 if (!pciehp_poll_mode) {
526 slot_cmd = slot_cmd | HP_INTR_ENABLE;
527 cmd_mask = cmd_mask | HP_INTR_ENABLE;
528 }
529
530 pcie_write_cmd(slot, slot_cmd, cmd_mask);
531
532 dbg("%s: SLOTCTRL %x write cmd %x\n",
533 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
534 }
535
536 static void hpc_set_green_led_off(struct slot *slot)
537 {
538 struct controller *ctrl = slot->ctrl;
539 u16 slot_cmd;
540 u16 cmd_mask;
541
542 slot_cmd = 0x0300;
543 cmd_mask = PWR_LED_CTRL;
544 if (!pciehp_poll_mode) {
545 slot_cmd = slot_cmd | HP_INTR_ENABLE;
546 cmd_mask = cmd_mask | HP_INTR_ENABLE;
547 }
548
549 pcie_write_cmd(slot, slot_cmd, cmd_mask);
550 dbg("%s: SLOTCTRL %x write cmd %x\n",
551 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
552 }
553
554 static void hpc_set_green_led_blink(struct slot *slot)
555 {
556 struct controller *ctrl = slot->ctrl;
557 u16 slot_cmd;
558 u16 cmd_mask;
559
560 slot_cmd = 0x0200;
561 cmd_mask = PWR_LED_CTRL;
562 if (!pciehp_poll_mode) {
563 slot_cmd = slot_cmd | HP_INTR_ENABLE;
564 cmd_mask = cmd_mask | HP_INTR_ENABLE;
565 }
566
567 pcie_write_cmd(slot, slot_cmd, cmd_mask);
568
569 dbg("%s: SLOTCTRL %x write cmd %x\n",
570 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
571 }
572
573 static void hpc_release_ctlr(struct controller *ctrl)
574 {
575 if (pciehp_poll_mode)
576 del_timer(&ctrl->poll_timer);
577 else
578 free_irq(ctrl->pci_dev->irq, ctrl);
579
580 /*
581 * If this is the last controller to be released, destroy the
582 * pciehp work queue
583 */
584 if (atomic_dec_and_test(&pciehp_num_controllers))
585 destroy_workqueue(pciehp_wq);
586 }
587
588 static int hpc_power_on_slot(struct slot * slot)
589 {
590 struct controller *ctrl = slot->ctrl;
591 u16 slot_cmd;
592 u16 cmd_mask;
593 u16 slot_status;
594 int retval = 0;
595
596 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
597
598 /* Clear sticky power-fault bit from previous power failures */
599 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
600 if (retval) {
601 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
602 return retval;
603 }
604 slot_status &= PWR_FAULT_DETECTED;
605 if (slot_status) {
606 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
607 if (retval) {
608 err("%s: Cannot write to SLOTSTATUS register\n",
609 __FUNCTION__);
610 return retval;
611 }
612 }
613
614 slot_cmd = POWER_ON;
615 cmd_mask = PWR_CTRL;
616 /* Enable detection that we turned off at slot power-off time */
617 if (!pciehp_poll_mode) {
618 slot_cmd = slot_cmd |
619 PWR_FAULT_DETECT_ENABLE |
620 MRL_DETECT_ENABLE |
621 PRSN_DETECT_ENABLE |
622 HP_INTR_ENABLE;
623 cmd_mask = cmd_mask |
624 PWR_FAULT_DETECT_ENABLE |
625 MRL_DETECT_ENABLE |
626 PRSN_DETECT_ENABLE |
627 HP_INTR_ENABLE;
628 }
629
630 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
631
632 if (retval) {
633 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
634 return -1;
635 }
636 dbg("%s: SLOTCTRL %x write cmd %x\n",
637 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
638
639 return retval;
640 }
641
642 static int hpc_power_off_slot(struct slot * slot)
643 {
644 struct controller *ctrl = slot->ctrl;
645 u16 slot_cmd;
646 u16 cmd_mask;
647 int retval = 0;
648
649 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
650
651 slot_cmd = POWER_OFF;
652 cmd_mask = PWR_CTRL;
653 /*
654 * If we get MRL or presence detect interrupts now, the isr
655 * will notice the sticky power-fault bit too and issue power
656 * indicator change commands. This will lead to an endless loop
657 * of command completions, since the power-fault bit remains on
658 * till the slot is powered on again.
659 */
660 if (!pciehp_poll_mode) {
661 slot_cmd = (slot_cmd &
662 ~PWR_FAULT_DETECT_ENABLE &
663 ~MRL_DETECT_ENABLE &
664 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
665 cmd_mask = cmd_mask |
666 PWR_FAULT_DETECT_ENABLE |
667 MRL_DETECT_ENABLE |
668 PRSN_DETECT_ENABLE |
669 HP_INTR_ENABLE;
670 }
671
672 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
673 if (retval) {
674 err("%s: Write command failed!\n", __FUNCTION__);
675 return -1;
676 }
677 dbg("%s: SLOTCTRL %x write cmd %x\n",
678 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
679
680 return retval;
681 }
682
683 static irqreturn_t pcie_isr(int irq, void *dev_id)
684 {
685 struct controller *ctrl = (struct controller *)dev_id;
686 u16 slot_status, intr_detect, intr_loc;
687 u16 temp_word;
688 int hp_slot = 0; /* only 1 slot per PCI Express port */
689 int rc = 0;
690 unsigned long flags;
691
692 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
693 if (rc) {
694 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
695 return IRQ_NONE;
696 }
697
698 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
699 PRSN_DETECT_CHANGED | CMD_COMPLETED );
700
701 intr_loc = slot_status & intr_detect;
702
703 /* Check to see if it was our interrupt */
704 if ( !intr_loc )
705 return IRQ_NONE;
706
707 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
708 /* Mask Hot-plug Interrupt Enable */
709 if (!pciehp_poll_mode) {
710 spin_lock_irqsave(&ctrl->lock, flags);
711 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
712 if (rc) {
713 err("%s: Cannot read SLOT_CTRL register\n",
714 __FUNCTION__);
715 spin_unlock_irqrestore(&ctrl->lock, flags);
716 return IRQ_NONE;
717 }
718
719 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
720 __FUNCTION__, temp_word);
721 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
722 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
723 if (rc) {
724 err("%s: Cannot write to SLOTCTRL register\n",
725 __FUNCTION__);
726 spin_unlock_irqrestore(&ctrl->lock, flags);
727 return IRQ_NONE;
728 }
729 spin_unlock_irqrestore(&ctrl->lock, flags);
730
731 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
732 if (rc) {
733 err("%s: Cannot read SLOT_STATUS register\n",
734 __FUNCTION__);
735 return IRQ_NONE;
736 }
737 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
738 __FUNCTION__, slot_status);
739
740 /* Clear command complete interrupt caused by this write */
741 temp_word = 0x1f;
742 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
743 if (rc) {
744 err("%s: Cannot write to SLOTSTATUS register\n",
745 __FUNCTION__);
746 return IRQ_NONE;
747 }
748 }
749
750 if (intr_loc & CMD_COMPLETED) {
751 /*
752 * Command Complete Interrupt Pending
753 */
754 ctrl->cmd_busy = 0;
755 wake_up_interruptible(&ctrl->queue);
756 }
757
758 if (intr_loc & MRL_SENS_CHANGED)
759 pciehp_handle_switch_change(hp_slot, ctrl);
760
761 if (intr_loc & ATTN_BUTTN_PRESSED)
762 pciehp_handle_attention_button(hp_slot, ctrl);
763
764 if (intr_loc & PRSN_DETECT_CHANGED)
765 pciehp_handle_presence_change(hp_slot, ctrl);
766
767 if (intr_loc & PWR_FAULT_DETECTED)
768 pciehp_handle_power_fault(hp_slot, ctrl);
769
770 /* Clear all events after serving them */
771 temp_word = 0x1F;
772 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
773 if (rc) {
774 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
775 return IRQ_NONE;
776 }
777 /* Unmask Hot-plug Interrupt Enable */
778 if (!pciehp_poll_mode) {
779 spin_lock_irqsave(&ctrl->lock, flags);
780 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
781 if (rc) {
782 err("%s: Cannot read SLOTCTRL register\n",
783 __FUNCTION__);
784 spin_unlock_irqrestore(&ctrl->lock, flags);
785 return IRQ_NONE;
786 }
787
788 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
789 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
790
791 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
792 if (rc) {
793 err("%s: Cannot write to SLOTCTRL register\n",
794 __FUNCTION__);
795 spin_unlock_irqrestore(&ctrl->lock, flags);
796 return IRQ_NONE;
797 }
798 spin_unlock_irqrestore(&ctrl->lock, flags);
799
800 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
801 if (rc) {
802 err("%s: Cannot read SLOT_STATUS register\n",
803 __FUNCTION__);
804 return IRQ_NONE;
805 }
806
807 /* Clear command complete interrupt caused by this write */
808 temp_word = 0x1F;
809 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
810 if (rc) {
811 err("%s: Cannot write to SLOTSTATUS failed\n",
812 __FUNCTION__);
813 return IRQ_NONE;
814 }
815 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
816 __FUNCTION__, temp_word);
817 }
818
819 return IRQ_HANDLED;
820 }
821
822 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
823 {
824 struct controller *ctrl = slot->ctrl;
825 enum pcie_link_speed lnk_speed;
826 u32 lnk_cap;
827 int retval = 0;
828
829 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
830 if (retval) {
831 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
832 return retval;
833 }
834
835 switch (lnk_cap & 0x000F) {
836 case 1:
837 lnk_speed = PCIE_2PT5GB;
838 break;
839 default:
840 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
841 break;
842 }
843
844 *value = lnk_speed;
845 dbg("Max link speed = %d\n", lnk_speed);
846
847 return retval;
848 }
849
850 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
851 {
852 struct controller *ctrl = slot->ctrl;
853 enum pcie_link_width lnk_wdth;
854 u32 lnk_cap;
855 int retval = 0;
856
857 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
858 if (retval) {
859 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
860 return retval;
861 }
862
863 switch ((lnk_cap & 0x03F0) >> 4){
864 case 0:
865 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
866 break;
867 case 1:
868 lnk_wdth = PCIE_LNK_X1;
869 break;
870 case 2:
871 lnk_wdth = PCIE_LNK_X2;
872 break;
873 case 4:
874 lnk_wdth = PCIE_LNK_X4;
875 break;
876 case 8:
877 lnk_wdth = PCIE_LNK_X8;
878 break;
879 case 12:
880 lnk_wdth = PCIE_LNK_X12;
881 break;
882 case 16:
883 lnk_wdth = PCIE_LNK_X16;
884 break;
885 case 32:
886 lnk_wdth = PCIE_LNK_X32;
887 break;
888 default:
889 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
890 break;
891 }
892
893 *value = lnk_wdth;
894 dbg("Max link width = %d\n", lnk_wdth);
895
896 return retval;
897 }
898
899 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
900 {
901 struct controller *ctrl = slot->ctrl;
902 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
903 int retval = 0;
904 u16 lnk_status;
905
906 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
907 if (retval) {
908 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
909 return retval;
910 }
911
912 switch (lnk_status & 0x0F) {
913 case 1:
914 lnk_speed = PCIE_2PT5GB;
915 break;
916 default:
917 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
918 break;
919 }
920
921 *value = lnk_speed;
922 dbg("Current link speed = %d\n", lnk_speed);
923
924 return retval;
925 }
926
927 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
928 {
929 struct controller *ctrl = slot->ctrl;
930 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
931 int retval = 0;
932 u16 lnk_status;
933
934 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
935 if (retval) {
936 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
937 return retval;
938 }
939
940 switch ((lnk_status & 0x03F0) >> 4){
941 case 0:
942 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
943 break;
944 case 1:
945 lnk_wdth = PCIE_LNK_X1;
946 break;
947 case 2:
948 lnk_wdth = PCIE_LNK_X2;
949 break;
950 case 4:
951 lnk_wdth = PCIE_LNK_X4;
952 break;
953 case 8:
954 lnk_wdth = PCIE_LNK_X8;
955 break;
956 case 12:
957 lnk_wdth = PCIE_LNK_X12;
958 break;
959 case 16:
960 lnk_wdth = PCIE_LNK_X16;
961 break;
962 case 32:
963 lnk_wdth = PCIE_LNK_X32;
964 break;
965 default:
966 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
967 break;
968 }
969
970 *value = lnk_wdth;
971 dbg("Current link width = %d\n", lnk_wdth);
972
973 return retval;
974 }
975
976 static struct hpc_ops pciehp_hpc_ops = {
977 .power_on_slot = hpc_power_on_slot,
978 .power_off_slot = hpc_power_off_slot,
979 .set_attention_status = hpc_set_attention_status,
980 .get_power_status = hpc_get_power_status,
981 .get_attention_status = hpc_get_attention_status,
982 .get_latch_status = hpc_get_latch_status,
983 .get_adapter_status = hpc_get_adapter_status,
984 .get_emi_status = hpc_get_emi_status,
985 .toggle_emi = hpc_toggle_emi,
986
987 .get_max_bus_speed = hpc_get_max_lnk_speed,
988 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
989 .get_max_lnk_width = hpc_get_max_lnk_width,
990 .get_cur_lnk_width = hpc_get_cur_lnk_width,
991
992 .query_power_fault = hpc_query_power_fault,
993 .green_led_on = hpc_set_green_led_on,
994 .green_led_off = hpc_set_green_led_off,
995 .green_led_blink = hpc_set_green_led_blink,
996
997 .release_ctlr = hpc_release_ctlr,
998 .check_lnk_status = hpc_check_lnk_status,
999 };
1000
1001 #ifdef CONFIG_ACPI
1002 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1003 {
1004 acpi_status status;
1005 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1006 struct pci_dev *pdev = dev;
1007 struct pci_bus *parent;
1008 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1009
1010 /*
1011 * Per PCI firmware specification, we should run the ACPI _OSC
1012 * method to get control of hotplug hardware before using it.
1013 * If an _OSC is missing, we look for an OSHP to do the same thing.
1014 * To handle different BIOS behavior, we look for _OSC and OSHP
1015 * within the scope of the hotplug controller and its parents, upto
1016 * the host bridge under which this controller exists.
1017 */
1018 while (!handle) {
1019 /*
1020 * This hotplug controller was not listed in the ACPI name
1021 * space at all. Try to get acpi handle of parent pci bus.
1022 */
1023 if (!pdev || !pdev->bus->parent)
1024 break;
1025 parent = pdev->bus->parent;
1026 dbg("Could not find %s in acpi namespace, trying parent\n",
1027 pci_name(pdev));
1028 if (!parent->self)
1029 /* Parent must be a host bridge */
1030 handle = acpi_get_pci_rootbridge_handle(
1031 pci_domain_nr(parent),
1032 parent->number);
1033 else
1034 handle = DEVICE_ACPI_HANDLE(
1035 &(parent->self->dev));
1036 pdev = parent->self;
1037 }
1038
1039 while (handle) {
1040 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1041 dbg("Trying to get hotplug control for %s \n",
1042 (char *)string.pointer);
1043 status = pci_osc_control_set(handle,
1044 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1045 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1046 if (status == AE_NOT_FOUND)
1047 status = acpi_run_oshp(handle);
1048 if (ACPI_SUCCESS(status)) {
1049 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1050 pci_name(dev), (char *)string.pointer);
1051 kfree(string.pointer);
1052 return 0;
1053 }
1054 if (acpi_root_bridge(handle))
1055 break;
1056 chandle = handle;
1057 status = acpi_get_parent(chandle, &handle);
1058 if (ACPI_FAILURE(status))
1059 break;
1060 }
1061
1062 err("Cannot get control of hotplug hardware for pci %s\n",
1063 pci_name(dev));
1064
1065 kfree(string.pointer);
1066 return -1;
1067 }
1068 #endif
1069
1070
1071
1072 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1073 {
1074 int rc;
1075 u16 temp_word;
1076 u16 cap_reg;
1077 u16 intr_enable = 0;
1078 u32 slot_cap;
1079 int cap_base;
1080 u16 slot_status, slot_ctrl;
1081 struct pci_dev *pdev;
1082
1083 pdev = dev->port;
1084 ctrl->pci_dev = pdev; /* save pci_dev in context */
1085
1086 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1087 __FUNCTION__, pdev->vendor, pdev->device);
1088
1089 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1090 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1091 goto abort_free_ctlr;
1092 }
1093
1094 ctrl->cap_base = cap_base;
1095
1096 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1097
1098 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1099 if (rc) {
1100 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1101 goto abort_free_ctlr;
1102 }
1103 dbg("%s: CAPREG offset %x cap_reg %x\n",
1104 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1105
1106 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1107 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1108 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1109 goto abort_free_ctlr;
1110 }
1111
1112 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1113 if (rc) {
1114 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1115 goto abort_free_ctlr;
1116 }
1117 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1118 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1119
1120 if (!(slot_cap & HP_CAP)) {
1121 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1122 goto abort_free_ctlr;
1123 }
1124 /* For debugging purpose */
1125 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1126 if (rc) {
1127 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1128 goto abort_free_ctlr;
1129 }
1130 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1131 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1132
1133 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1134 if (rc) {
1135 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1136 goto abort_free_ctlr;
1137 }
1138 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1139 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1140
1141 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1142 if (pci_resource_len(pdev, rc) > 0)
1143 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1144 (unsigned long long)pci_resource_start(pdev, rc),
1145 (unsigned long long)pci_resource_len(pdev, rc));
1146
1147 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1148 pdev->subsystem_vendor, pdev->subsystem_device);
1149
1150 mutex_init(&ctrl->crit_sect);
1151 mutex_init(&ctrl->ctrl_lock);
1152 spin_lock_init(&ctrl->lock);
1153
1154 /* setup wait queue */
1155 init_waitqueue_head(&ctrl->queue);
1156
1157 /* return PCI Controller Info */
1158 ctrl->slot_device_offset = 0;
1159 ctrl->num_slots = 1;
1160 ctrl->first_slot = slot_cap >> 19;
1161 ctrl->ctrlcap = slot_cap & 0x0000007f;
1162
1163 /* Mask Hot-plug Interrupt Enable */
1164 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1165 if (rc) {
1166 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1167 goto abort_free_ctlr;
1168 }
1169
1170 dbg("%s: SLOTCTRL %x value read %x\n",
1171 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1172 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1173
1174 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1175 if (rc) {
1176 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1177 goto abort_free_ctlr;
1178 }
1179
1180 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1181 if (rc) {
1182 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1183 goto abort_free_ctlr;
1184 }
1185
1186 temp_word = 0x1F; /* Clear all events */
1187 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1188 if (rc) {
1189 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1190 goto abort_free_ctlr;
1191 }
1192
1193 if (pciehp_poll_mode) {
1194 /* Install interrupt polling timer. Start with 10 sec delay */
1195 init_timer(&ctrl->poll_timer);
1196 start_int_poll_timer(ctrl, 10);
1197 } else {
1198 /* Installs the interrupt handler */
1199 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1200 MY_NAME, (void *)ctrl);
1201 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1202 __FUNCTION__, ctrl->pci_dev->irq,
1203 atomic_read(&pciehp_num_controllers), rc);
1204 if (rc) {
1205 err("Can't get irq %d for the hotplug controller\n",
1206 ctrl->pci_dev->irq);
1207 goto abort_free_ctlr;
1208 }
1209 }
1210 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1211 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1212
1213 /*
1214 * If this is the first controller to be initialized,
1215 * initialize the pciehp work queue
1216 */
1217 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1218 pciehp_wq = create_singlethread_workqueue("pciehpd");
1219 if (!pciehp_wq) {
1220 rc = -ENOMEM;
1221 goto abort_free_irq;
1222 }
1223 }
1224
1225 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1226 if (rc) {
1227 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1228 goto abort_free_irq;
1229 }
1230
1231 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1232
1233 if (ATTN_BUTTN(slot_cap))
1234 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1235
1236 if (POWER_CTRL(slot_cap))
1237 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1238
1239 if (MRL_SENS(slot_cap))
1240 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1241
1242 temp_word = (temp_word & ~intr_enable) | intr_enable;
1243
1244 if (pciehp_poll_mode) {
1245 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1246 } else {
1247 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1248 }
1249
1250 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1251 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1252 if (rc) {
1253 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1254 goto abort_free_irq;
1255 }
1256 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1257 if (rc) {
1258 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1259 goto abort_disable_intr;
1260 }
1261
1262 temp_word = 0x1F; /* Clear all events */
1263 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1264 if (rc) {
1265 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1266 goto abort_disable_intr;
1267 }
1268
1269 if (pciehp_force) {
1270 dbg("Bypassing BIOS check for pciehp use on %s\n",
1271 pci_name(ctrl->pci_dev));
1272 } else {
1273 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1274 if (rc)
1275 goto abort_disable_intr;
1276 }
1277
1278 ctrl->hpc_ops = &pciehp_hpc_ops;
1279
1280 return 0;
1281
1282 /* We end up here for the many possible ways to fail this API. */
1283 abort_disable_intr:
1284 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1285 if (!rc) {
1286 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1287 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1288 }
1289 if (rc)
1290 err("%s : disabling interrupts failed\n", __FUNCTION__);
1291
1292 abort_free_irq:
1293 if (pciehp_poll_mode)
1294 del_timer_sync(&ctrl->poll_timer);
1295 else
1296 free_irq(ctrl->pci_dev->irq, ctrl);
1297
1298 abort_free_ctlr:
1299 return -1;
1300 }
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