2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline int pciehp_readw(struct controller
*ctrl
, int reg
, u16
*value
)
46 struct pci_dev
*dev
= ctrl
->pcie
->port
;
47 return pci_read_config_word(dev
, pci_pcie_cap(dev
) + reg
, value
);
50 static inline int pciehp_readl(struct controller
*ctrl
, int reg
, u32
*value
)
52 struct pci_dev
*dev
= ctrl
->pcie
->port
;
53 return pci_read_config_dword(dev
, pci_pcie_cap(dev
) + reg
, value
);
56 static inline int pciehp_writew(struct controller
*ctrl
, int reg
, u16 value
)
58 struct pci_dev
*dev
= ctrl
->pcie
->port
;
59 return pci_write_config_word(dev
, pci_pcie_cap(dev
) + reg
, value
);
62 static inline int pciehp_writel(struct controller
*ctrl
, int reg
, u32 value
)
64 struct pci_dev
*dev
= ctrl
->pcie
->port
;
65 return pci_write_config_dword(dev
, pci_pcie_cap(dev
) + reg
, value
);
68 /* Power Control Command */
70 #define POWER_OFF PCI_EXP_SLTCTL_PCC
72 static irqreturn_t
pcie_isr(int irq
, void *dev_id
);
73 static void start_int_poll_timer(struct controller
*ctrl
, int sec
);
75 /* This is the interrupt polling timeout function. */
76 static void int_poll_timeout(unsigned long data
)
78 struct controller
*ctrl
= (struct controller
*)data
;
80 /* Poll for interrupt events. regs == NULL => polling */
83 init_timer(&ctrl
->poll_timer
);
84 if (!pciehp_poll_time
)
85 pciehp_poll_time
= 2; /* default polling interval is 2 sec */
87 start_int_poll_timer(ctrl
, pciehp_poll_time
);
90 /* This function starts the interrupt polling timer. */
91 static void start_int_poll_timer(struct controller
*ctrl
, int sec
)
93 /* Clamp to sane value */
94 if ((sec
<= 0) || (sec
> 60))
97 ctrl
->poll_timer
.function
= &int_poll_timeout
;
98 ctrl
->poll_timer
.data
= (unsigned long)ctrl
;
99 ctrl
->poll_timer
.expires
= jiffies
+ sec
* HZ
;
100 add_timer(&ctrl
->poll_timer
);
103 static inline int pciehp_request_irq(struct controller
*ctrl
)
105 int retval
, irq
= ctrl
->pcie
->irq
;
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode
) {
109 init_timer(&ctrl
->poll_timer
);
110 start_int_poll_timer(ctrl
, 10);
114 /* Installs the interrupt handler */
115 retval
= request_irq(irq
, pcie_isr
, IRQF_SHARED
, MY_NAME
, ctrl
);
117 ctrl_err(ctrl
, "Cannot get irq %d for the hotplug controller\n",
122 static inline void pciehp_free_irq(struct controller
*ctrl
)
124 if (pciehp_poll_mode
)
125 del_timer_sync(&ctrl
->poll_timer
);
127 free_irq(ctrl
->pcie
->irq
, ctrl
);
130 static int pcie_poll_cmd(struct controller
*ctrl
)
133 int err
, timeout
= 1000;
135 err
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
136 if (!err
&& (slot_status
& PCI_EXP_SLTSTA_CC
)) {
137 pciehp_writew(ctrl
, PCI_EXP_SLTSTA
, PCI_EXP_SLTSTA_CC
);
140 while (timeout
> 0) {
143 err
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
144 if (!err
&& (slot_status
& PCI_EXP_SLTSTA_CC
)) {
145 pciehp_writew(ctrl
, PCI_EXP_SLTSTA
, PCI_EXP_SLTSTA_CC
);
149 return 0; /* timeout */
152 static void pcie_wait_cmd(struct controller
*ctrl
, int poll
)
154 unsigned int msecs
= pciehp_poll_mode
? 2500 : 1000;
155 unsigned long timeout
= msecs_to_jiffies(msecs
);
159 rc
= pcie_poll_cmd(ctrl
);
161 rc
= wait_event_timeout(ctrl
->queue
, !ctrl
->cmd_busy
, timeout
);
163 ctrl_dbg(ctrl
, "Command not completed in 1000 msec\n");
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
172 static int pcie_write_cmd(struct controller
*ctrl
, u16 cmd
, u16 mask
)
178 mutex_lock(&ctrl
->ctrl_lock
);
180 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
182 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
187 if (slot_status
& PCI_EXP_SLTSTA_CC
) {
188 if (!ctrl
->no_cmd_complete
) {
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
194 ctrl_dbg(ctrl
, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl
)) {
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
201 ctrl_dbg(ctrl
, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl
->no_cmd_complete
= 0;
205 ctrl_dbg(ctrl
, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
210 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTCTL
, &slot_ctrl
);
212 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
217 slot_ctrl
|= (cmd
& mask
);
220 retval
= pciehp_writew(ctrl
, PCI_EXP_SLTCTL
, slot_ctrl
);
222 ctrl_err(ctrl
, "Cannot write to SLOTCTRL register\n");
225 * Wait for command completion.
227 if (!retval
&& !ctrl
->no_cmd_complete
) {
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
234 if (!(slot_ctrl
& PCI_EXP_SLTCTL_HPIE
) ||
235 !(slot_ctrl
& PCI_EXP_SLTCTL_CCIE
))
237 pcie_wait_cmd(ctrl
, poll
);
240 mutex_unlock(&ctrl
->ctrl_lock
);
244 static inline int check_link_active(struct controller
*ctrl
)
248 if (pciehp_readw(ctrl
, PCI_EXP_LNKSTA
, &link_status
))
250 return !!(link_status
& PCI_EXP_LNKSTA_DLLLA
);
253 static void pcie_wait_link_active(struct controller
*ctrl
)
257 if (check_link_active(ctrl
))
259 while (timeout
> 0) {
262 if (check_link_active(ctrl
))
265 ctrl_dbg(ctrl
, "Data Link Layer Link Active not set in 1000 msec\n");
268 int pciehp_check_link_status(struct controller
*ctrl
)
274 * Data Link Layer Link Active Reporting must be capable for
275 * hot-plug capable downstream port. But old controller might
276 * not implement it. In this case, we wait for 1000 ms.
278 if (ctrl
->link_active_reporting
)
279 pcie_wait_link_active(ctrl
);
284 * Need to wait for 1000 ms after Data Link Layer Link Active
285 * (DLLLA) bit reads 1b before sending configuration request.
286 * We need it before checking Link Training (LT) bit becuase
287 * LT is still set even after DLLLA bit is set on some platform.
291 retval
= pciehp_readw(ctrl
, PCI_EXP_LNKSTA
, &lnk_status
);
293 ctrl_err(ctrl
, "Cannot read LNKSTATUS register\n");
297 ctrl_dbg(ctrl
, "%s: lnk_status = %x\n", __func__
, lnk_status
);
298 if ((lnk_status
& PCI_EXP_LNKSTA_LT
) ||
299 !(lnk_status
& PCI_EXP_LNKSTA_NLW
)) {
300 ctrl_err(ctrl
, "Link Training Error occurs \n");
306 * If the port supports Link speeds greater than 5.0 GT/s, we
307 * must wait for 100 ms after Link training completes before
308 * sending configuration request.
310 if (ctrl
->pcie
->port
->subordinate
->max_bus_speed
> PCIE_SPEED_5_0GT
)
313 pcie_update_link_speed(ctrl
->pcie
->port
->subordinate
, lnk_status
);
318 int pciehp_get_attention_status(struct slot
*slot
, u8
*status
)
320 struct controller
*ctrl
= slot
->ctrl
;
325 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTCTL
, &slot_ctrl
);
327 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
331 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x, value read %x\n", __func__
,
332 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_ctrl
);
334 atten_led_state
= (slot_ctrl
& PCI_EXP_SLTCTL_AIC
) >> 6;
336 switch (atten_led_state
) {
338 *status
= 0xFF; /* Reserved */
341 *status
= 1; /* On */
344 *status
= 2; /* Blink */
347 *status
= 0; /* Off */
357 int pciehp_get_power_status(struct slot
*slot
, u8
*status
)
359 struct controller
*ctrl
= slot
->ctrl
;
364 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTCTL
, &slot_ctrl
);
366 ctrl_err(ctrl
, "%s: Cannot read SLOTCTRL register\n", __func__
);
369 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x value read %x\n", __func__
,
370 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_ctrl
);
372 pwr_state
= (slot_ctrl
& PCI_EXP_SLTCTL_PCC
) >> 10;
389 int pciehp_get_latch_status(struct slot
*slot
, u8
*status
)
391 struct controller
*ctrl
= slot
->ctrl
;
395 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
397 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
401 *status
= !!(slot_status
& PCI_EXP_SLTSTA_MRLSS
);
405 int pciehp_get_adapter_status(struct slot
*slot
, u8
*status
)
407 struct controller
*ctrl
= slot
->ctrl
;
411 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
413 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
417 *status
= !!(slot_status
& PCI_EXP_SLTSTA_PDS
);
421 int pciehp_query_power_fault(struct slot
*slot
)
423 struct controller
*ctrl
= slot
->ctrl
;
427 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
429 ctrl_err(ctrl
, "Cannot check for power fault\n");
432 return !!(slot_status
& PCI_EXP_SLTSTA_PFD
);
435 int pciehp_set_attention_status(struct slot
*slot
, u8 value
)
437 struct controller
*ctrl
= slot
->ctrl
;
441 cmd_mask
= PCI_EXP_SLTCTL_AIC
;
443 case 0 : /* turn off */
446 case 1: /* turn on */
449 case 2: /* turn blink */
455 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
456 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
457 return pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
460 void pciehp_green_led_on(struct slot
*slot
)
462 struct controller
*ctrl
= slot
->ctrl
;
467 cmd_mask
= PCI_EXP_SLTCTL_PIC
;
468 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
469 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
470 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
473 void pciehp_green_led_off(struct slot
*slot
)
475 struct controller
*ctrl
= slot
->ctrl
;
480 cmd_mask
= PCI_EXP_SLTCTL_PIC
;
481 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
482 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
483 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
486 void pciehp_green_led_blink(struct slot
*slot
)
488 struct controller
*ctrl
= slot
->ctrl
;
493 cmd_mask
= PCI_EXP_SLTCTL_PIC
;
494 pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
495 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
496 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
499 int pciehp_power_on_slot(struct slot
* slot
)
501 struct controller
*ctrl
= slot
->ctrl
;
507 /* Clear sticky power-fault bit from previous power failures */
508 retval
= pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &slot_status
);
510 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS register\n",
514 slot_status
&= PCI_EXP_SLTSTA_PFD
;
516 retval
= pciehp_writew(ctrl
, PCI_EXP_SLTSTA
, slot_status
);
519 "%s: Cannot write to SLOTSTATUS register\n",
524 ctrl
->power_fault_detected
= 0;
527 cmd_mask
= PCI_EXP_SLTCTL_PCC
;
528 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
530 ctrl_err(ctrl
, "Write %x command failed!\n", slot_cmd
);
533 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
534 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
539 int pciehp_power_off_slot(struct slot
* slot
)
541 struct controller
*ctrl
= slot
->ctrl
;
546 slot_cmd
= POWER_OFF
;
547 cmd_mask
= PCI_EXP_SLTCTL_PCC
;
548 retval
= pcie_write_cmd(ctrl
, slot_cmd
, cmd_mask
);
550 ctrl_err(ctrl
, "Write command failed!\n");
553 ctrl_dbg(ctrl
, "%s: SLOTCTRL %x write cmd %x\n", __func__
,
554 pci_pcie_cap(ctrl
->pcie
->port
) + PCI_EXP_SLTCTL
, slot_cmd
);
558 static irqreturn_t
pcie_isr(int irq
, void *dev_id
)
560 struct controller
*ctrl
= (struct controller
*)dev_id
;
561 struct slot
*slot
= ctrl
->slot
;
562 u16 detected
, intr_loc
;
565 * In order to guarantee that all interrupt events are
566 * serviced, we need to re-inspect Slot Status register after
567 * clearing what is presumed to be the last pending interrupt.
571 if (pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, &detected
)) {
572 ctrl_err(ctrl
, "%s: Cannot read SLOTSTATUS\n",
577 detected
&= (PCI_EXP_SLTSTA_ABP
| PCI_EXP_SLTSTA_PFD
|
578 PCI_EXP_SLTSTA_MRLSC
| PCI_EXP_SLTSTA_PDC
|
580 detected
&= ~intr_loc
;
581 intr_loc
|= detected
;
584 if (detected
&& pciehp_writew(ctrl
, PCI_EXP_SLTSTA
, intr_loc
)) {
585 ctrl_err(ctrl
, "%s: Cannot write to SLOTSTATUS\n",
591 ctrl_dbg(ctrl
, "%s: intr_loc %x\n", __func__
, intr_loc
);
593 /* Check Command Complete Interrupt Pending */
594 if (intr_loc
& PCI_EXP_SLTSTA_CC
) {
597 wake_up(&ctrl
->queue
);
600 if (!(intr_loc
& ~PCI_EXP_SLTSTA_CC
))
603 /* Check MRL Sensor Changed */
604 if (intr_loc
& PCI_EXP_SLTSTA_MRLSC
)
605 pciehp_handle_switch_change(slot
);
607 /* Check Attention Button Pressed */
608 if (intr_loc
& PCI_EXP_SLTSTA_ABP
)
609 pciehp_handle_attention_button(slot
);
611 /* Check Presence Detect Changed */
612 if (intr_loc
& PCI_EXP_SLTSTA_PDC
)
613 pciehp_handle_presence_change(slot
);
615 /* Check Power Fault Detected */
616 if ((intr_loc
& PCI_EXP_SLTSTA_PFD
) && !ctrl
->power_fault_detected
) {
617 ctrl
->power_fault_detected
= 1;
618 pciehp_handle_power_fault(slot
);
623 int pciehp_get_max_lnk_width(struct slot
*slot
,
624 enum pcie_link_width
*value
)
626 struct controller
*ctrl
= slot
->ctrl
;
627 enum pcie_link_width lnk_wdth
;
631 retval
= pciehp_readl(ctrl
, PCI_EXP_LNKCAP
, &lnk_cap
);
633 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
637 switch ((lnk_cap
& PCI_EXP_LNKSTA_NLW
) >> 4){
639 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
642 lnk_wdth
= PCIE_LNK_X1
;
645 lnk_wdth
= PCIE_LNK_X2
;
648 lnk_wdth
= PCIE_LNK_X4
;
651 lnk_wdth
= PCIE_LNK_X8
;
654 lnk_wdth
= PCIE_LNK_X12
;
657 lnk_wdth
= PCIE_LNK_X16
;
660 lnk_wdth
= PCIE_LNK_X32
;
663 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
668 ctrl_dbg(ctrl
, "Max link width = %d\n", lnk_wdth
);
673 int pciehp_get_cur_lnk_width(struct slot
*slot
,
674 enum pcie_link_width
*value
)
676 struct controller
*ctrl
= slot
->ctrl
;
677 enum pcie_link_width lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
681 retval
= pciehp_readw(ctrl
, PCI_EXP_LNKSTA
, &lnk_status
);
683 ctrl_err(ctrl
, "%s: Cannot read LNKSTATUS register\n",
688 switch ((lnk_status
& PCI_EXP_LNKSTA_NLW
) >> 4){
690 lnk_wdth
= PCIE_LNK_WIDTH_RESRV
;
693 lnk_wdth
= PCIE_LNK_X1
;
696 lnk_wdth
= PCIE_LNK_X2
;
699 lnk_wdth
= PCIE_LNK_X4
;
702 lnk_wdth
= PCIE_LNK_X8
;
705 lnk_wdth
= PCIE_LNK_X12
;
708 lnk_wdth
= PCIE_LNK_X16
;
711 lnk_wdth
= PCIE_LNK_X32
;
714 lnk_wdth
= PCIE_LNK_WIDTH_UNKNOWN
;
719 ctrl_dbg(ctrl
, "Current link width = %d\n", lnk_wdth
);
724 int pcie_enable_notification(struct controller
*ctrl
)
729 * TBD: Power fault detected software notification support.
731 * Power fault detected software notification is not enabled
732 * now, because it caused power fault detected interrupt storm
733 * on some machines. On those machines, power fault detected
734 * bit in the slot status register was set again immediately
735 * when it is cleared in the interrupt service routine, and
736 * next power fault detected interrupt was notified again.
738 cmd
= PCI_EXP_SLTCTL_PDCE
;
739 if (ATTN_BUTTN(ctrl
))
740 cmd
|= PCI_EXP_SLTCTL_ABPE
;
742 cmd
|= PCI_EXP_SLTCTL_MRLSCE
;
743 if (!pciehp_poll_mode
)
744 cmd
|= PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
;
746 mask
= (PCI_EXP_SLTCTL_PDCE
| PCI_EXP_SLTCTL_ABPE
|
747 PCI_EXP_SLTCTL_MRLSCE
| PCI_EXP_SLTCTL_PFDE
|
748 PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
);
750 if (pcie_write_cmd(ctrl
, cmd
, mask
)) {
751 ctrl_err(ctrl
, "Cannot enable software notification\n");
757 static void pcie_disable_notification(struct controller
*ctrl
)
760 mask
= (PCI_EXP_SLTCTL_PDCE
| PCI_EXP_SLTCTL_ABPE
|
761 PCI_EXP_SLTCTL_MRLSCE
| PCI_EXP_SLTCTL_PFDE
|
762 PCI_EXP_SLTCTL_HPIE
| PCI_EXP_SLTCTL_CCIE
|
763 PCI_EXP_SLTCTL_DLLSCE
);
764 if (pcie_write_cmd(ctrl
, 0, mask
))
765 ctrl_warn(ctrl
, "Cannot disable software notification\n");
768 int pcie_init_notification(struct controller
*ctrl
)
770 if (pciehp_request_irq(ctrl
))
772 if (pcie_enable_notification(ctrl
)) {
773 pciehp_free_irq(ctrl
);
776 ctrl
->notification_enabled
= 1;
780 static void pcie_shutdown_notification(struct controller
*ctrl
)
782 if (ctrl
->notification_enabled
) {
783 pcie_disable_notification(ctrl
);
784 pciehp_free_irq(ctrl
);
785 ctrl
->notification_enabled
= 0;
789 static int pcie_init_slot(struct controller
*ctrl
)
793 slot
= kzalloc(sizeof(*slot
), GFP_KERNEL
);
798 mutex_init(&slot
->lock
);
799 INIT_DELAYED_WORK(&slot
->work
, pciehp_queue_pushbutton_work
);
804 static void pcie_cleanup_slot(struct controller
*ctrl
)
806 struct slot
*slot
= ctrl
->slot
;
807 cancel_delayed_work(&slot
->work
);
808 flush_workqueue(pciehp_wq
);
809 flush_workqueue(pciehp_ordered_wq
);
813 static inline void dbg_ctrl(struct controller
*ctrl
)
817 struct pci_dev
*pdev
= ctrl
->pcie
->port
;
822 ctrl_info(ctrl
, "Hotplug Controller:\n");
823 ctrl_info(ctrl
, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
824 pci_name(pdev
), pdev
->irq
);
825 ctrl_info(ctrl
, " Vendor ID : 0x%04x\n", pdev
->vendor
);
826 ctrl_info(ctrl
, " Device ID : 0x%04x\n", pdev
->device
);
827 ctrl_info(ctrl
, " Subsystem ID : 0x%04x\n",
828 pdev
->subsystem_device
);
829 ctrl_info(ctrl
, " Subsystem Vendor ID : 0x%04x\n",
830 pdev
->subsystem_vendor
);
831 ctrl_info(ctrl
, " PCIe Cap offset : 0x%02x\n",
833 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
834 if (!pci_resource_len(pdev
, i
))
836 ctrl_info(ctrl
, " PCI resource [%d] : %pR\n",
837 i
, &pdev
->resource
[i
]);
839 ctrl_info(ctrl
, "Slot Capabilities : 0x%08x\n", ctrl
->slot_cap
);
840 ctrl_info(ctrl
, " Physical Slot Number : %d\n", PSN(ctrl
));
841 ctrl_info(ctrl
, " Attention Button : %3s\n",
842 ATTN_BUTTN(ctrl
) ? "yes" : "no");
843 ctrl_info(ctrl
, " Power Controller : %3s\n",
844 POWER_CTRL(ctrl
) ? "yes" : "no");
845 ctrl_info(ctrl
, " MRL Sensor : %3s\n",
846 MRL_SENS(ctrl
) ? "yes" : "no");
847 ctrl_info(ctrl
, " Attention Indicator : %3s\n",
848 ATTN_LED(ctrl
) ? "yes" : "no");
849 ctrl_info(ctrl
, " Power Indicator : %3s\n",
850 PWR_LED(ctrl
) ? "yes" : "no");
851 ctrl_info(ctrl
, " Hot-Plug Surprise : %3s\n",
852 HP_SUPR_RM(ctrl
) ? "yes" : "no");
853 ctrl_info(ctrl
, " EMI Present : %3s\n",
854 EMI(ctrl
) ? "yes" : "no");
855 ctrl_info(ctrl
, " Command Completed : %3s\n",
856 NO_CMD_CMPL(ctrl
) ? "no" : "yes");
857 pciehp_readw(ctrl
, PCI_EXP_SLTSTA
, ®16
);
858 ctrl_info(ctrl
, "Slot Status : 0x%04x\n", reg16
);
859 pciehp_readw(ctrl
, PCI_EXP_SLTCTL
, ®16
);
860 ctrl_info(ctrl
, "Slot Control : 0x%04x\n", reg16
);
863 struct controller
*pcie_init(struct pcie_device
*dev
)
865 struct controller
*ctrl
;
866 u32 slot_cap
, link_cap
;
867 struct pci_dev
*pdev
= dev
->port
;
869 ctrl
= kzalloc(sizeof(*ctrl
), GFP_KERNEL
);
871 dev_err(&dev
->device
, "%s: Out of memory\n", __func__
);
875 if (!pci_pcie_cap(pdev
)) {
876 ctrl_err(ctrl
, "Cannot find PCI Express capability\n");
879 if (pciehp_readl(ctrl
, PCI_EXP_SLTCAP
, &slot_cap
)) {
880 ctrl_err(ctrl
, "Cannot read SLOTCAP register\n");
884 ctrl
->slot_cap
= slot_cap
;
885 mutex_init(&ctrl
->ctrl_lock
);
886 init_waitqueue_head(&ctrl
->queue
);
889 * Controller doesn't notify of command completion if the "No
890 * Command Completed Support" bit is set in Slot Capability
891 * register or the controller supports none of power
892 * controller, attention led, power led and EMI.
894 if (NO_CMD_CMPL(ctrl
) ||
895 !(POWER_CTRL(ctrl
) | ATTN_LED(ctrl
) | PWR_LED(ctrl
) | EMI(ctrl
)))
896 ctrl
->no_cmd_complete
= 1;
898 /* Check if Data Link Layer Link Active Reporting is implemented */
899 if (pciehp_readl(ctrl
, PCI_EXP_LNKCAP
, &link_cap
)) {
900 ctrl_err(ctrl
, "%s: Cannot read LNKCAP register\n", __func__
);
903 if (link_cap
& PCI_EXP_LNKCAP_DLLLARC
) {
904 ctrl_dbg(ctrl
, "Link Active Reporting supported\n");
905 ctrl
->link_active_reporting
= 1;
908 /* Clear all remaining event bits in Slot Status register */
909 if (pciehp_writew(ctrl
, PCI_EXP_SLTSTA
, 0x1f))
912 /* Disable sotfware notification */
913 pcie_disable_notification(ctrl
);
915 ctrl_info(ctrl
, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
916 pdev
->vendor
, pdev
->device
, pdev
->subsystem_vendor
,
917 pdev
->subsystem_device
);
919 if (pcie_init_slot(ctrl
))
930 void pciehp_release_ctrl(struct controller
*ctrl
)
932 pcie_shutdown_notification(ctrl
);
933 pcie_cleanup_slot(ctrl
);