drivers/pci/hotplug/pciehprm_nonacpi.c

   1 /*
   2  * PCIEHPRM NONACPI: PHP Resource Manager for Non-ACPI/Legacy platform
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  27  *
  28  */
  29
  30 #include <linux/config.h>
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/types.h>
  34 #include <linux/sched.h>
  35 #include <linux/pci.h>
  36 #include <linux/init.h>
  37 #include <linux/slab.h>
  38 #include <asm/uaccess.h>
  39 #include "pciehp.h"
  40 #include "pciehprm.h"
  41 #include "pciehprm_nonacpi.h"
  42
  43
  44 void pciehprm_cleanup(void)
  45 {
  46         return;
  47 }
  48
  49 int pciehprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
  50 {
  51
  52         *sun = (u8) (ctrl->first_slot);
  53         return 0;
  54 }
  55
  56 int pciehprm_set_hpp(
  57         struct controller *ctrl,
  58         struct pci_func *func,
  59         u8      card_type)
  60 {
  61         u32 rc;
  62         u8 temp_byte;
  63         struct pci_bus lpci_bus, *pci_bus;
  64         unsigned int    devfn;
  65         memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
  66         pci_bus = &lpci_bus;
  67         pci_bus->number = func->bus;
  68         devfn = PCI_DEVFN(func->device, func->function);
  69
  70         temp_byte = 0x40;       /* hard coded value for LT */
  71         if (card_type == PCI_HEADER_TYPE_BRIDGE) {
  72                 /* set subordinate Latency Timer */
  73                 rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
  74
  75                 if (rc) {
  76                         dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__,
  77                                 func->bus, func->device, func->function);
  78                         return rc;
  79                 }
  80         }
  81
  82         /* set base Latency Timer */
  83         rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
  84
  85         if (rc) {
  86                 dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  87                 return rc;
  88         }
  89
  90         /* set Cache Line size */
  91         temp_byte = 0x08;       /* hard coded value for CLS */
  92
  93         rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
  94
  95         if (rc) {
  96                 dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  97         }
  98
  99         /* set enable_perr */
 100         /* set enable_serr */
 101
 102         return rc;
 103 }
 104
 105 void pciehprm_enable_card(
 106         struct controller *ctrl,
 107         struct pci_func *func,
 108         u8 card_type)
 109 {
 110         u16 command, bcommand;
 111         struct pci_bus lpci_bus, *pci_bus;
 112         unsigned int devfn;
 113         int rc;
 114
 115         memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
 116         pci_bus = &lpci_bus;
 117         pci_bus->number = func->bus;
 118         devfn = PCI_DEVFN(func->device, func->function);
 119
 120         rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
 121
 122         command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
 123                 | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 124                 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
 125
 126         rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
 127
 128         if (card_type == PCI_HEADER_TYPE_BRIDGE) {
 129
 130                 rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
 131
 132                 bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
 133                         | PCI_BRIDGE_CTL_NO_ISA;
 134
 135                 rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
 136         }
 137 }
 138
 139 static int legacy_pciehprm_init_pci(void)
 140 {
 141         return 0;
 142 }
 143
 144 int pciehprm_init(enum php_ctlr_type ctrl_type)
 145 {
 146         int retval;
 147
 148         switch (ctrl_type) {
 149         case PCI:
 150                 retval = legacy_pciehprm_init_pci();
 151                 break;
 152         default:
 153                 retval = -ENODEV;
 154                 break;
 155         }
 156
 157         return retval;
 158 }