drivers/pci/hotplug/shpchp.h

   1 /*
   2  * Standard Hot Plug Controller Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27  *
  28  */
  29 #ifndef _SHPCHP_H
  30 #define _SHPCHP_H
  31
  32 #include <linux/types.h>
  33 #include <linux/pci.h>
  34 #include <linux/delay.h>
  35 #include <linux/sched.h>        /* signal_pending(), struct timer_list */
  36 #include <linux/mutex.h>
  37
  38 #include "pci_hotplug.h"
  39
  40 #if !defined(MODULE)
  41         #define MY_NAME "shpchp"
  42 #else
  43         #define MY_NAME THIS_MODULE->name
  44 #endif
  45
  46 extern int shpchp_poll_mode;
  47 extern int shpchp_poll_time;
  48 extern int shpchp_debug;
  49
  50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
  51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
  52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
  53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
  54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
  55
  56 struct slot {
  57         u8 bus;
  58         u8 device;
  59         u16 status;
  60         u32 number;
  61         u8 is_a_board;
  62         u8 state;
  63         u8 presence_save;
  64         u8 pwr_save;
  65         struct timer_list task_event;
  66         u8 hp_slot;
  67         struct controller *ctrl;
  68         struct hpc_ops *hpc_ops;
  69         struct hotplug_slot *hotplug_slot;
  70         struct list_head        slot_list;
  71 };
  72
  73 struct event_info {
  74         u32 event_type;
  75         u8 hp_slot;
  76 };
  77
  78 struct controller {
  79         struct list_head ctrl_list;
  80         struct mutex crit_sect;         /* critical section mutex */
  81         struct mutex cmd_lock;          /* command lock */
  82         struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
  83         int num_slots;                  /* Number of slots on ctlr */
  84         int slot_num_inc;               /* 1 or -1 */
  85         struct pci_dev *pci_dev;
  86         struct pci_bus *pci_bus;
  87         struct event_info event_queue[10];
  88         struct list_head slot_list;
  89         struct hpc_ops *hpc_ops;
  90         wait_queue_head_t queue;        /* sleep & wake process */
  91         u8 next_event;
  92         u8 bus;
  93         u8 device;
  94         u8 function;
  95         u8 slot_device_offset;
  96         u8 add_support;
  97         u32 pcix_misc2_reg;     /* for amd pogo errata */
  98         enum pci_bus_speed speed;
  99         u32 first_slot;         /* First physical slot number */
 100         u8 slot_bus;            /* Bus where the slots handled by this controller sit */
 101         u32 cap_offset;
 102         unsigned long mmio_base;
 103         unsigned long mmio_size;
 104         volatile int cmd_busy;
 105 };
 106
 107 struct hotplug_params {
 108         u8      cache_line_size;
 109         u8      latency_timer;
 110         u8      enable_serr;
 111         u8      enable_perr;
 112 };
 113
 114 /* Define AMD SHPC ID  */
 115 #define PCI_DEVICE_ID_AMD_GOLAM_7450    0x7450
 116 #define PCI_DEVICE_ID_AMD_POGO_7458     0x7458
 117
 118 /* AMD PCIX bridge registers */
 119
 120 #define PCIX_MEM_BASE_LIMIT_OFFSET      0x1C
 121 #define PCIX_MISCII_OFFSET              0x48
 122 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET  0x80
 123
 124 /* AMD PCIX_MISCII masks and offsets */
 125 #define PERRNONFATALENABLE_MASK         0x00040000
 126 #define PERRFATALENABLE_MASK            0x00080000
 127 #define PERRFLOODENABLE_MASK            0x00100000
 128 #define SERRNONFATALENABLE_MASK         0x00200000
 129 #define SERRFATALENABLE_MASK            0x00400000
 130
 131 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
 132 #define PERR_OBSERVED_MASK              0x00000001
 133
 134 /* AMD PCIX_MEM_BASE_LIMIT masks */
 135 #define RSE_MASK                        0x40000000
 136
 137 #define INT_BUTTON_IGNORE               0
 138 #define INT_PRESENCE_ON                 1
 139 #define INT_PRESENCE_OFF                2
 140 #define INT_SWITCH_CLOSE                3
 141 #define INT_SWITCH_OPEN                 4
 142 #define INT_POWER_FAULT                 5
 143 #define INT_POWER_FAULT_CLEAR           6
 144 #define INT_BUTTON_PRESS                7
 145 #define INT_BUTTON_RELEASE              8
 146 #define INT_BUTTON_CANCEL               9
 147
 148 #define STATIC_STATE                    0
 149 #define BLINKINGON_STATE                1
 150 #define BLINKINGOFF_STATE               2
 151 #define POWERON_STATE                   3
 152 #define POWEROFF_STATE                  4
 153
 154 #define PCI_TO_PCI_BRIDGE_CLASS         0x00060400
 155
 156 /* Error messages */
 157 #define INTERLOCK_OPEN                  0x00000002
 158 #define ADD_NOT_SUPPORTED               0x00000003
 159 #define CARD_FUNCTIONING                0x00000005
 160 #define ADAPTER_NOT_SAME                0x00000006
 161 #define NO_ADAPTER_PRESENT              0x00000009
 162 #define NOT_ENOUGH_RESOURCES            0x0000000B
 163 #define DEVICE_TYPE_NOT_SUPPORTED       0x0000000C
 164 #define WRONG_BUS_FREQUENCY             0x0000000D
 165 #define POWER_FAILURE                   0x0000000E
 166
 167 #define REMOVE_NOT_SUPPORTED            0x00000003
 168
 169 #define DISABLE_CARD                    1
 170
 171 /*
 172  * error Messages
 173  */
 174 #define msg_initialization_err  "Initialization failure, error=%d\n"
 175 #define msg_button_on           "PCI slot #%d - powering on due to button press.\n"
 176 #define msg_button_off          "PCI slot #%d - powering off due to button press.\n"
 177 #define msg_button_cancel       "PCI slot #%d - action canceled due to button press.\n"
 178
 179 /* sysfs functions for the hotplug controller info */
 180 extern void shpchp_create_ctrl_files    (struct controller *ctrl);
 181
 182 /* controller functions */
 183 extern int      shpchp_event_start_thread(void);
 184 extern void     shpchp_event_stop_thread(void);
 185 extern int      shpchp_enable_slot(struct slot *slot);
 186 extern int      shpchp_disable_slot(struct slot *slot);
 187
 188 extern u8       shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
 189 extern u8       shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
 190 extern u8       shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
 191 extern u8       shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
 192
 193 /* pci functions */
 194 extern int      shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
 195 extern int      shpchp_configure_device(struct slot *p_slot);
 196 extern int      shpchp_unconfigure_device(struct slot *p_slot);
 197 extern void     get_hp_hw_control_from_firmware(struct pci_dev *dev);
 198 extern void     get_hp_params_from_firmware(struct pci_dev *dev,
 199                 struct hotplug_params *hpp);
 200 extern int      shpchprm_get_physical_slot_number(struct controller *ctrl,
 201                 u32 *sun, u8 busnum, u8 devnum);
 202 extern void     shpchp_remove_ctrl_files(struct controller *ctrl);
 203
 204
 205 /* Global variables */
 206 extern struct list_head shpchp_ctrl_list;
 207
 208 struct ctrl_reg {
 209         volatile u32 base_offset;
 210         volatile u32 slot_avail1;
 211         volatile u32 slot_avail2;
 212         volatile u32 slot_config;
 213         volatile u16 sec_bus_config;
 214         volatile u8  msi_ctrl;
 215         volatile u8  prog_interface;
 216         volatile u16 cmd;
 217         volatile u16 cmd_status;
 218         volatile u32 intr_loc;
 219         volatile u32 serr_loc;
 220         volatile u32 serr_intr_enable;
 221         volatile u32 slot1;
 222         volatile u32 slot2;
 223         volatile u32 slot3;
 224         volatile u32 slot4;
 225         volatile u32 slot5;
 226         volatile u32 slot6;
 227         volatile u32 slot7;
 228         volatile u32 slot8;
 229         volatile u32 slot9;
 230         volatile u32 slot10;
 231         volatile u32 slot11;
 232         volatile u32 slot12;
 233 } __attribute__ ((packed));
 234
 235 /* offsets to the controller registers based on the above structure layout */
 236 enum ctrl_offsets {
 237         BASE_OFFSET =   offsetof(struct ctrl_reg, base_offset),
 238         SLOT_AVAIL1 =   offsetof(struct ctrl_reg, slot_avail1),
 239         SLOT_AVAIL2     =       offsetof(struct ctrl_reg, slot_avail2),
 240         SLOT_CONFIG =   offsetof(struct ctrl_reg, slot_config),
 241         SEC_BUS_CONFIG =        offsetof(struct ctrl_reg, sec_bus_config),
 242         MSI_CTRL        =       offsetof(struct ctrl_reg, msi_ctrl),
 243         PROG_INTERFACE =        offsetof(struct ctrl_reg, prog_interface),
 244         CMD             =       offsetof(struct ctrl_reg, cmd),
 245         CMD_STATUS      =       offsetof(struct ctrl_reg, cmd_status),
 246         INTR_LOC        =       offsetof(struct ctrl_reg, intr_loc),
 247         SERR_LOC        =       offsetof(struct ctrl_reg, serr_loc),
 248         SERR_INTR_ENABLE =      offsetof(struct ctrl_reg, serr_intr_enable),
 249         SLOT1 =         offsetof(struct ctrl_reg, slot1),
 250         SLOT2 =         offsetof(struct ctrl_reg, slot2),
 251         SLOT3 =         offsetof(struct ctrl_reg, slot3),
 252         SLOT4 =         offsetof(struct ctrl_reg, slot4),
 253         SLOT5 =         offsetof(struct ctrl_reg, slot5),
 254         SLOT6 =         offsetof(struct ctrl_reg, slot6),
 255         SLOT7 =         offsetof(struct ctrl_reg, slot7),
 256         SLOT8 =         offsetof(struct ctrl_reg, slot8),
 257         SLOT9 =         offsetof(struct ctrl_reg, slot9),
 258         SLOT10 =        offsetof(struct ctrl_reg, slot10),
 259         SLOT11 =        offsetof(struct ctrl_reg, slot11),
 260         SLOT12 =        offsetof(struct ctrl_reg, slot12),
 261 };
 262 typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
 263 struct php_ctlr_state_s {
 264         struct php_ctlr_state_s *pnext;
 265         struct pci_dev *pci_dev;
 266         unsigned int irq;
 267         unsigned long flags;    /* spinlock's */
 268         u32 slot_device_offset;
 269         u32 num_slots;
 270         struct timer_list       int_poll_timer; /* Added for poll event */
 271         php_intr_callback_t attention_button_callback;
 272         php_intr_callback_t switch_change_callback;
 273         php_intr_callback_t presence_change_callback;
 274         php_intr_callback_t power_fault_callback;
 275         void *callback_instance_id;
 276         void __iomem *creg;                     /* Ptr to controller register space */
 277 };
 278 /* Inline functions */
 279
 280
 281 /* Inline functions to check the sanity of a pointer that is passed to us */
 282 static inline int slot_paranoia_check (struct slot *slot, const char *function)
 283 {
 284         if (!slot) {
 285                 dbg("%s - slot == NULL", function);
 286                 return -1;
 287         }
 288         if (!slot->hotplug_slot) {
 289                 dbg("%s - slot->hotplug_slot == NULL!", function);
 290                 return -1;
 291         }
 292         return 0;
 293 }
 294
 295 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
 296 {
 297         struct slot *slot;
 298
 299         if (!hotplug_slot) {
 300                 dbg("%s - hotplug_slot == NULL\n", function);
 301                 return NULL;
 302         }
 303
 304         slot = (struct slot *)hotplug_slot->private;
 305         if (slot_paranoia_check (slot, function))
 306                 return NULL;
 307         return slot;
 308 }
 309
 310 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
 311 {
 312         struct slot *slot;
 313
 314         if (!ctrl)
 315                 return NULL;
 316
 317         list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
 318                 if (slot->device == device)
 319                         return slot;
 320         }
 321
 322         err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
 323
 324         return NULL;
 325 }
 326
 327 static inline int wait_for_ctrl_irq (struct controller *ctrl)
 328 {
 329     DECLARE_WAITQUEUE(wait, current);
 330         int retval = 0;
 331
 332         add_wait_queue(&ctrl->queue, &wait);
 333
 334         if (!shpchp_poll_mode) {
 335                 /* Sleep for up to 1 second */
 336                 msleep_interruptible(1000);
 337         } else {
 338                 /* Sleep for up to 2 seconds */
 339                 msleep_interruptible(2000);
 340         }
 341         remove_wait_queue(&ctrl->queue, &wait);
 342         if (signal_pending(current))
 343                 retval =  -EINTR;
 344
 345         return retval;
 346 }
 347
 348 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
 349 {
 350         u32 pcix_misc2_temp;
 351
 352         /* save MiscII register */
 353         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
 354
 355         p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
 356
 357         /* clear SERR/PERR enable bits */
 358         pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 359         pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 360         pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 361         pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 362         pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 363         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 364 }
 365
 366 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
 367 {
 368         u32 pcix_misc2_temp;
 369         u32 pcix_bridge_errors_reg;
 370         u32 pcix_mem_base_reg;
 371         u8  perr_set;
 372         u8  rse_set;
 373
 374         /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
 375         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
 376         perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
 377         if (perr_set) {
 378                 dbg ("%s  W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
 379
 380                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
 381         }
 382
 383         /* write-one-to-clear Memory_Base_Limit[ RSE ] */
 384         pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
 385         rse_set = pcix_mem_base_reg & RSE_MASK;
 386         if (rse_set) {
 387                 dbg ("%s  W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
 388
 389                 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
 390         }
 391         /* restore MiscII register */
 392         pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
 393
 394         if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
 395                 pcix_misc2_temp |= SERRFATALENABLE_MASK;
 396         else
 397                 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
 398
 399         if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
 400                 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
 401         else
 402                 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
 403
 404         if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
 405                 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
 406         else
 407                 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
 408
 409         if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
 410                 pcix_misc2_temp |= PERRFATALENABLE_MASK;
 411         else
 412                 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
 413
 414         if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
 415                 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
 416         else
 417                 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
 418         pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
 419 }
 420
 421 enum php_ctlr_type {
 422         PCI,
 423         ISA,
 424         ACPI
 425 };
 426
 427 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
 428
 429 int shpc_get_ctlr_slot_config( struct controller *ctrl,
 430                 int *num_ctlr_slots,
 431                 int *first_device_num,
 432                 int *physical_slot_num,
 433                 int *updown,
 434                 int *flags);
 435
 436 struct hpc_ops {
 437         int     (*power_on_slot )               (struct slot *slot);
 438         int     (*slot_enable )                 (struct slot *slot);
 439         int     (*slot_disable )                (struct slot *slot);
 440         int     (*set_bus_speed_mode)   (struct slot *slot, enum pci_bus_speed speed);
 441         int     (*get_power_status)             (struct slot *slot, u8 *status);
 442         int     (*get_attention_status) (struct slot *slot, u8 *status);
 443         int     (*set_attention_status) (struct slot *slot, u8 status);
 444         int     (*get_latch_status)             (struct slot *slot, u8 *status);
 445         int     (*get_adapter_status)   (struct slot *slot, u8 *status);
 446
 447         int     (*get_max_bus_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 448         int     (*get_cur_bus_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 449         int     (*get_adapter_speed)    (struct slot *slot, enum pci_bus_speed *speed);
 450         int     (*get_mode1_ECC_cap)    (struct slot *slot, u8 *mode);
 451         int     (*get_prog_int)                 (struct slot *slot, u8 *prog_int);
 452
 453         int     (*query_power_fault)    (struct slot *slot);
 454         void    (*green_led_on)         (struct slot *slot);
 455         void    (*green_led_off)        (struct slot *slot);
 456         void    (*green_led_blink)      (struct slot *slot);
 457         void    (*release_ctlr)         (struct controller *ctrl);
 458         int (*check_cmd_status)         (struct controller *ctrl);
 459 };
 460
 461 #endif                          /* _SHPCHP_H */