1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
31 static int pci_msi_enable
= 1;
32 int pci_msi_ignore_mask
;
34 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
36 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
37 static int pci_msi_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
39 struct irq_domain
*domain
;
41 domain
= dev_get_msi_domain(&dev
->dev
);
42 if (domain
&& irq_domain_is_hierarchy(domain
))
43 return msi_domain_alloc_irqs(domain
, &dev
->dev
, nvec
);
45 return arch_setup_msi_irqs(dev
, nvec
, type
);
48 static void pci_msi_teardown_msi_irqs(struct pci_dev
*dev
)
50 struct irq_domain
*domain
;
52 domain
= dev_get_msi_domain(&dev
->dev
);
53 if (domain
&& irq_domain_is_hierarchy(domain
))
54 msi_domain_free_irqs(domain
, &dev
->dev
);
56 arch_teardown_msi_irqs(dev
);
59 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
60 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
65 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
70 void __weak
arch_teardown_msi_irq(unsigned int irq
)
74 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
76 struct msi_desc
*entry
;
80 * If an architecture wants to support multiple MSI, it needs to
81 * override arch_setup_msi_irqs()
83 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
86 for_each_pci_msi_entry(entry
, dev
) {
87 ret
= arch_setup_msi_irq(dev
, entry
);
97 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
100 struct msi_desc
*entry
;
102 for_each_pci_msi_entry(entry
, dev
)
104 for (i
= 0; i
< entry
->nvec_used
; i
++)
105 arch_teardown_msi_irq(entry
->irq
+ i
);
107 #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
109 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
111 struct msi_desc
*entry
;
114 if (dev
->msix_enabled
) {
115 for_each_pci_msi_entry(entry
, dev
) {
116 if (irq
== entry
->irq
)
119 } else if (dev
->msi_enabled
) {
120 entry
= irq_get_msi_desc(irq
);
124 __pci_write_msi_msg(entry
, &entry
->msg
);
127 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
129 return default_restore_msi_irqs(dev
);
133 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
134 * mask all MSI interrupts by clearing the MSI enable bit does not work
135 * reliably as devices without an INTx disable bit will then generate a
136 * level IRQ which will never be cleared.
138 static inline __attribute_const__ u32
msi_multi_mask(struct msi_desc
*desc
)
140 /* Don't shift by >= width of type */
141 if (desc
->msi_attrib
.multi_cap
>= 5)
143 return (1 << (1 << desc
->msi_attrib
.multi_cap
)) - 1;
146 static noinline
void pci_msi_update_mask(struct msi_desc
*desc
, u32 clear
, u32 set
)
148 raw_spinlock_t
*lock
= &desc
->dev
->msi_lock
;
151 if (!desc
->msi_attrib
.can_mask
)
154 raw_spin_lock_irqsave(lock
, flags
);
155 desc
->msi_mask
&= ~clear
;
156 desc
->msi_mask
|= set
;
157 pci_write_config_dword(msi_desc_to_pci_dev(desc
), desc
->mask_pos
,
159 raw_spin_unlock_irqrestore(lock
, flags
);
162 static inline void pci_msi_mask(struct msi_desc
*desc
, u32 mask
)
164 pci_msi_update_mask(desc
, 0, mask
);
167 static inline void pci_msi_unmask(struct msi_desc
*desc
, u32 mask
)
169 pci_msi_update_mask(desc
, mask
, 0);
172 static inline void __iomem
*pci_msix_desc_addr(struct msi_desc
*desc
)
174 return desc
->mask_base
+ desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
178 * This internal function does not flush PCI writes to the device. All
179 * users must ensure that they read from the device before either assuming
180 * that the device state is up to date, or returning out of this file.
181 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
183 static void pci_msix_write_vector_ctrl(struct msi_desc
*desc
, u32 ctrl
)
185 void __iomem
*desc_addr
= pci_msix_desc_addr(desc
);
187 if (desc
->msi_attrib
.can_mask
)
188 writel(ctrl
, desc_addr
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
191 static inline void pci_msix_mask(struct msi_desc
*desc
)
193 desc
->msix_ctrl
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
194 pci_msix_write_vector_ctrl(desc
, desc
->msix_ctrl
);
195 /* Flush write to device */
196 readl(desc
->mask_base
);
199 static inline void pci_msix_unmask(struct msi_desc
*desc
)
201 desc
->msix_ctrl
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
202 pci_msix_write_vector_ctrl(desc
, desc
->msix_ctrl
);
205 static void __pci_msi_mask_desc(struct msi_desc
*desc
, u32 mask
)
207 if (desc
->msi_attrib
.is_msix
)
210 pci_msi_mask(desc
, mask
);
213 static void __pci_msi_unmask_desc(struct msi_desc
*desc
, u32 mask
)
215 if (desc
->msi_attrib
.is_msix
)
216 pci_msix_unmask(desc
);
218 pci_msi_unmask(desc
, mask
);
222 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
223 * @data: pointer to irqdata associated to that interrupt
225 void pci_msi_mask_irq(struct irq_data
*data
)
227 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
229 __pci_msi_mask_desc(desc
, BIT(data
->irq
- desc
->irq
));
231 EXPORT_SYMBOL_GPL(pci_msi_mask_irq
);
234 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
235 * @data: pointer to irqdata associated to that interrupt
237 void pci_msi_unmask_irq(struct irq_data
*data
)
239 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
241 __pci_msi_unmask_desc(desc
, BIT(data
->irq
- desc
->irq
));
243 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq
);
245 void default_restore_msi_irqs(struct pci_dev
*dev
)
247 struct msi_desc
*entry
;
249 for_each_pci_msi_entry(entry
, dev
)
250 default_restore_msi_irq(dev
, entry
->irq
);
253 void __pci_read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
255 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
257 BUG_ON(dev
->current_state
!= PCI_D0
);
259 if (entry
->msi_attrib
.is_msix
) {
260 void __iomem
*base
= pci_msix_desc_addr(entry
);
262 if (WARN_ON_ONCE(entry
->msi_attrib
.is_virtual
))
265 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
266 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
267 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
269 int pos
= dev
->msi_cap
;
272 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
274 if (entry
->msi_attrib
.is_64
) {
275 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
277 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
280 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
286 void __pci_write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
288 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
290 if (dev
->current_state
!= PCI_D0
|| pci_dev_is_disconnected(dev
)) {
291 /* Don't touch the hardware now */
292 } else if (entry
->msi_attrib
.is_msix
) {
293 void __iomem
*base
= pci_msix_desc_addr(entry
);
294 u32 ctrl
= entry
->msix_ctrl
;
295 bool unmasked
= !(ctrl
& PCI_MSIX_ENTRY_CTRL_MASKBIT
);
297 if (entry
->msi_attrib
.is_virtual
)
301 * The specification mandates that the entry is masked
302 * when the message is modified:
304 * "If software changes the Address or Data value of an
305 * entry while the entry is unmasked, the result is
309 pci_msix_write_vector_ctrl(entry
, ctrl
| PCI_MSIX_ENTRY_CTRL_MASKBIT
);
311 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
312 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
313 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
316 pci_msix_write_vector_ctrl(entry
, ctrl
);
318 /* Ensure that the writes are visible in the device */
319 readl(base
+ PCI_MSIX_ENTRY_DATA
);
321 int pos
= dev
->msi_cap
;
324 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
325 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
326 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
327 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
329 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
331 if (entry
->msi_attrib
.is_64
) {
332 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
334 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
337 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
340 /* Ensure that the writes are visible in the device */
341 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
347 if (entry
->write_msi_msg
)
348 entry
->write_msi_msg(entry
, entry
->write_msi_msg_data
);
352 void pci_write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
354 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
356 __pci_write_msi_msg(entry
, msg
);
358 EXPORT_SYMBOL_GPL(pci_write_msi_msg
);
360 static void free_msi_irqs(struct pci_dev
*dev
)
362 struct list_head
*msi_list
= dev_to_msi_list(&dev
->dev
);
363 struct msi_desc
*entry
, *tmp
;
366 for_each_pci_msi_entry(entry
, dev
)
368 for (i
= 0; i
< entry
->nvec_used
; i
++)
369 BUG_ON(irq_has_action(entry
->irq
+ i
));
371 pci_msi_teardown_msi_irqs(dev
);
373 list_for_each_entry_safe(entry
, tmp
, msi_list
, list
) {
374 if (entry
->msi_attrib
.is_msix
) {
375 if (list_is_last(&entry
->list
, msi_list
))
376 iounmap(entry
->mask_base
);
379 list_del(&entry
->list
);
380 free_msi_entry(entry
);
383 if (dev
->msi_irq_groups
) {
384 msi_destroy_sysfs(&dev
->dev
, dev
->msi_irq_groups
);
385 dev
->msi_irq_groups
= NULL
;
389 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
391 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
392 pci_intx(dev
, enable
);
395 static void pci_msi_set_enable(struct pci_dev
*dev
, int enable
)
399 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
400 control
&= ~PCI_MSI_FLAGS_ENABLE
;
402 control
|= PCI_MSI_FLAGS_ENABLE
;
403 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
406 static void __pci_restore_msi_state(struct pci_dev
*dev
)
409 struct msi_desc
*entry
;
411 if (!dev
->msi_enabled
)
414 entry
= irq_get_msi_desc(dev
->irq
);
416 pci_intx_for_msi(dev
, 0);
417 pci_msi_set_enable(dev
, 0);
418 arch_restore_msi_irqs(dev
);
420 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
421 pci_msi_update_mask(entry
, 0, 0);
422 control
&= ~PCI_MSI_FLAGS_QSIZE
;
423 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
424 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
427 static void pci_msix_clear_and_set_ctrl(struct pci_dev
*dev
, u16 clear
, u16 set
)
431 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
434 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, ctrl
);
437 static void __pci_restore_msix_state(struct pci_dev
*dev
)
439 struct msi_desc
*entry
;
441 if (!dev
->msix_enabled
)
443 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
445 /* route the table */
446 pci_intx_for_msi(dev
, 0);
447 pci_msix_clear_and_set_ctrl(dev
, 0,
448 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
450 arch_restore_msi_irqs(dev
);
451 for_each_pci_msi_entry(entry
, dev
)
452 pci_msix_write_vector_ctrl(entry
, entry
->msix_ctrl
);
454 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
457 void pci_restore_msi_state(struct pci_dev
*dev
)
459 __pci_restore_msi_state(dev
);
460 __pci_restore_msix_state(dev
);
462 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
464 static struct msi_desc
*
465 msi_setup_entry(struct pci_dev
*dev
, int nvec
, struct irq_affinity
*affd
)
467 struct irq_affinity_desc
*masks
= NULL
;
468 struct msi_desc
*entry
;
472 masks
= irq_create_affinity_masks(nvec
, affd
);
474 /* MSI Entry Initialization */
475 entry
= alloc_msi_entry(&dev
->dev
, nvec
, masks
);
479 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
481 entry
->msi_attrib
.is_msix
= 0;
482 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
483 entry
->msi_attrib
.is_virtual
= 0;
484 entry
->msi_attrib
.entry_nr
= 0;
485 entry
->msi_attrib
.can_mask
= !pci_msi_ignore_mask
&&
486 !!(control
& PCI_MSI_FLAGS_MASKBIT
);
487 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
488 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
489 entry
->msi_attrib
.multiple
= ilog2(__roundup_pow_of_two(nvec
));
491 if (control
& PCI_MSI_FLAGS_64BIT
)
492 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
494 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
496 /* Save the initial mask status */
497 if (entry
->msi_attrib
.can_mask
)
498 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->msi_mask
);
505 static int msi_verify_entries(struct pci_dev
*dev
)
507 struct msi_desc
*entry
;
509 if (!dev
->no_64bit_msi
)
512 for_each_pci_msi_entry(entry
, dev
) {
513 if (entry
->msg
.address_hi
) {
514 pci_err(dev
, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
515 entry
->msg
.address_hi
, entry
->msg
.address_lo
);
523 * msi_capability_init - configure device's MSI capability structure
524 * @dev: pointer to the pci_dev data structure of MSI device function
525 * @nvec: number of interrupts to allocate
526 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
528 * Setup the MSI capability structure of the device with the requested
529 * number of interrupts. A return value of zero indicates the successful
530 * setup of an entry with the new MSI IRQ. A negative return value indicates
531 * an error, and a positive return value indicates the number of interrupts
532 * which could have been allocated.
534 static int msi_capability_init(struct pci_dev
*dev
, int nvec
,
535 struct irq_affinity
*affd
)
537 const struct attribute_group
**groups
;
538 struct msi_desc
*entry
;
541 pci_msi_set_enable(dev
, 0); /* Disable MSI during set up */
543 entry
= msi_setup_entry(dev
, nvec
, affd
);
547 /* All MSIs are unmasked by default; mask them all */
548 pci_msi_mask(entry
, msi_multi_mask(entry
));
550 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
552 /* Configure MSI capability structure */
553 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
557 ret
= msi_verify_entries(dev
);
561 groups
= msi_populate_sysfs(&dev
->dev
);
562 if (IS_ERR(groups
)) {
563 ret
= PTR_ERR(groups
);
567 dev
->msi_irq_groups
= groups
;
569 /* Set MSI enabled bits */
570 pci_intx_for_msi(dev
, 0);
571 pci_msi_set_enable(dev
, 1);
572 dev
->msi_enabled
= 1;
574 pcibios_free_irq(dev
);
575 dev
->irq
= entry
->irq
;
579 pci_msi_unmask(entry
, msi_multi_mask(entry
));
584 static void __iomem
*msix_map_region(struct pci_dev
*dev
,
585 unsigned int nr_entries
)
587 resource_size_t phys_addr
;
592 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
594 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
595 flags
= pci_resource_flags(dev
, bir
);
596 if (!flags
|| (flags
& IORESOURCE_UNSET
))
599 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
600 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
602 return ioremap(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
605 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
606 struct msix_entry
*entries
, int nvec
,
607 struct irq_affinity
*affd
)
609 struct irq_affinity_desc
*curmsk
, *masks
= NULL
;
610 struct msi_desc
*entry
;
613 int vec_count
= pci_msix_vec_count(dev
);
616 masks
= irq_create_affinity_masks(nvec
, affd
);
618 for (i
= 0, curmsk
= masks
; i
< nvec
; i
++) {
619 entry
= alloc_msi_entry(&dev
->dev
, 1, curmsk
);
625 /* No enough memory. Don't try again */
630 entry
->msi_attrib
.is_msix
= 1;
631 entry
->msi_attrib
.is_64
= 1;
634 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
636 entry
->msi_attrib
.entry_nr
= i
;
638 entry
->msi_attrib
.is_virtual
=
639 entry
->msi_attrib
.entry_nr
>= vec_count
;
641 entry
->msi_attrib
.can_mask
= !pci_msi_ignore_mask
&&
642 !entry
->msi_attrib
.is_virtual
;
644 entry
->msi_attrib
.default_irq
= dev
->irq
;
645 entry
->mask_base
= base
;
647 if (entry
->msi_attrib
.can_mask
) {
648 addr
= pci_msix_desc_addr(entry
);
649 entry
->msix_ctrl
= readl(addr
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
652 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
662 static void msix_update_entries(struct pci_dev
*dev
, struct msix_entry
*entries
)
664 struct msi_desc
*entry
;
666 for_each_pci_msi_entry(entry
, dev
) {
668 entries
->vector
= entry
->irq
;
674 static void msix_mask_all(void __iomem
*base
, int tsize
)
676 u32 ctrl
= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
679 if (pci_msi_ignore_mask
)
682 for (i
= 0; i
< tsize
; i
++, base
+= PCI_MSIX_ENTRY_SIZE
)
683 writel(ctrl
, base
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
687 * msix_capability_init - configure device's MSI-X capability
688 * @dev: pointer to the pci_dev data structure of MSI-X device function
689 * @entries: pointer to an array of struct msix_entry entries
690 * @nvec: number of @entries
691 * @affd: Optional pointer to enable automatic affinity assignment
693 * Setup the MSI-X capability structure of device function with a
694 * single MSI-X IRQ. A return of zero indicates the successful setup of
695 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
697 static int msix_capability_init(struct pci_dev
*dev
, struct msix_entry
*entries
,
698 int nvec
, struct irq_affinity
*affd
)
700 const struct attribute_group
**groups
;
706 * Some devices require MSI-X to be enabled before the MSI-X
707 * registers can be accessed. Mask all the vectors to prevent
708 * interrupts coming in before they're fully set up.
710 pci_msix_clear_and_set_ctrl(dev
, 0, PCI_MSIX_FLAGS_MASKALL
|
711 PCI_MSIX_FLAGS_ENABLE
);
713 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
714 /* Request & Map MSI-X table region */
715 tsize
= msix_table_size(control
);
716 base
= msix_map_region(dev
, tsize
);
722 /* Ensure that all table entries are masked. */
723 msix_mask_all(base
, tsize
);
725 ret
= msix_setup_entries(dev
, base
, entries
, nvec
, affd
);
729 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
733 /* Check if all MSI entries honor device restrictions */
734 ret
= msi_verify_entries(dev
);
738 msix_update_entries(dev
, entries
);
740 groups
= msi_populate_sysfs(&dev
->dev
);
741 if (IS_ERR(groups
)) {
742 ret
= PTR_ERR(groups
);
746 dev
->msi_irq_groups
= groups
;
748 /* Set MSI-X enabled bits and unmask the function */
749 pci_intx_for_msi(dev
, 0);
750 dev
->msix_enabled
= 1;
751 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
753 pcibios_free_irq(dev
);
759 * If we had some success, report the number of IRQs
760 * we succeeded in setting up.
762 struct msi_desc
*entry
;
765 for_each_pci_msi_entry(entry
, dev
) {
777 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
783 * pci_msi_supported - check whether MSI may be enabled on a device
784 * @dev: pointer to the pci_dev data structure of MSI device function
785 * @nvec: how many MSIs have been requested?
787 * Look at global flags, the device itself, and its parent buses
788 * to determine if MSI/-X are supported for the device. If MSI/-X is
789 * supported return 1, else return 0.
791 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
795 /* MSI must be globally enabled and supported by the device */
799 if (!dev
|| dev
->no_msi
)
803 * You can't ask to have 0 or less MSIs configured.
805 * b) the list manipulation code assumes nvec >= 1.
811 * Any bridge which does NOT route MSI transactions from its
812 * secondary bus to its primary bus must set NO_MSI flag on
813 * the secondary pci_bus.
815 * The NO_MSI flag can either be set directly by:
816 * - arch-specific PCI host bus controller drivers (deprecated)
817 * - quirks for specific PCI bridges
819 * or indirectly by platform-specific PCI host bridge drivers by
820 * advertising the 'msi_domain' property, which results in
821 * the NO_MSI flag when no MSI domain is found for this bridge
824 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
825 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
832 * pci_msi_vec_count - Return the number of MSI vectors a device can send
833 * @dev: device to report about
835 * This function returns the number of MSI vectors a device requested via
836 * Multiple Message Capable register. It returns a negative errno if the
837 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
838 * and returns a power of two, up to a maximum of 2^5 (32), according to the
841 int pci_msi_vec_count(struct pci_dev
*dev
)
849 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
850 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
854 EXPORT_SYMBOL(pci_msi_vec_count
);
856 static void pci_msi_shutdown(struct pci_dev
*dev
)
858 struct msi_desc
*desc
;
860 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
863 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
864 desc
= first_pci_msi_entry(dev
);
866 pci_msi_set_enable(dev
, 0);
867 pci_intx_for_msi(dev
, 1);
868 dev
->msi_enabled
= 0;
870 /* Return the device with MSI unmasked as initial states */
871 pci_msi_unmask(desc
, msi_multi_mask(desc
));
873 /* Restore dev->irq to its default pin-assertion IRQ */
874 dev
->irq
= desc
->msi_attrib
.default_irq
;
875 pcibios_alloc_irq(dev
);
878 void pci_disable_msi(struct pci_dev
*dev
)
880 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
883 pci_msi_shutdown(dev
);
886 EXPORT_SYMBOL(pci_disable_msi
);
889 * pci_msix_vec_count - return the number of device's MSI-X table entries
890 * @dev: pointer to the pci_dev data structure of MSI-X device function
891 * This function returns the number of device's MSI-X table entries and
892 * therefore the number of MSI-X vectors device is capable of sending.
893 * It returns a negative errno if the device is not capable of sending MSI-X
896 int pci_msix_vec_count(struct pci_dev
*dev
)
903 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
904 return msix_table_size(control
);
906 EXPORT_SYMBOL(pci_msix_vec_count
);
908 static int __pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
,
909 int nvec
, struct irq_affinity
*affd
, int flags
)
914 if (!pci_msi_supported(dev
, nvec
) || dev
->current_state
!= PCI_D0
)
917 nr_entries
= pci_msix_vec_count(dev
);
920 if (nvec
> nr_entries
&& !(flags
& PCI_IRQ_VIRTUAL
))
924 /* Check for any invalid entries */
925 for (i
= 0; i
< nvec
; i
++) {
926 if (entries
[i
].entry
>= nr_entries
)
927 return -EINVAL
; /* invalid entry */
928 for (j
= i
+ 1; j
< nvec
; j
++) {
929 if (entries
[i
].entry
== entries
[j
].entry
)
930 return -EINVAL
; /* duplicate entry */
935 /* Check whether driver already requested for MSI IRQ */
936 if (dev
->msi_enabled
) {
937 pci_info(dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
940 return msix_capability_init(dev
, entries
, nvec
, affd
);
943 static void pci_msix_shutdown(struct pci_dev
*dev
)
945 struct msi_desc
*entry
;
947 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
950 if (pci_dev_is_disconnected(dev
)) {
951 dev
->msix_enabled
= 0;
955 /* Return the device with MSI-X masked as initial states */
956 for_each_pci_msi_entry(entry
, dev
)
957 pci_msix_mask(entry
);
959 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
960 pci_intx_for_msi(dev
, 1);
961 dev
->msix_enabled
= 0;
962 pcibios_alloc_irq(dev
);
965 void pci_disable_msix(struct pci_dev
*dev
)
967 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
970 pci_msix_shutdown(dev
);
973 EXPORT_SYMBOL(pci_disable_msix
);
975 void pci_no_msi(void)
981 * pci_msi_enabled - is MSI enabled?
983 * Returns true if MSI has not been disabled by the command-line option
986 int pci_msi_enabled(void)
988 return pci_msi_enable
;
990 EXPORT_SYMBOL(pci_msi_enabled
);
992 static int __pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
,
993 struct irq_affinity
*affd
)
998 if (!pci_msi_supported(dev
, minvec
) || dev
->current_state
!= PCI_D0
)
1001 /* Check whether driver already requested MSI-X IRQs */
1002 if (dev
->msix_enabled
) {
1003 pci_info(dev
, "can't enable MSI (MSI-X already enabled)\n");
1007 if (maxvec
< minvec
)
1010 if (WARN_ON_ONCE(dev
->msi_enabled
))
1013 nvec
= pci_msi_vec_count(dev
);
1024 nvec
= irq_calc_affinity_vectors(minvec
, nvec
, affd
);
1029 rc
= msi_capability_init(dev
, nvec
, affd
);
1042 /* deprecated, don't use */
1043 int pci_enable_msi(struct pci_dev
*dev
)
1045 int rc
= __pci_enable_msi_range(dev
, 1, 1, NULL
);
1050 EXPORT_SYMBOL(pci_enable_msi
);
1052 static int __pci_enable_msix_range(struct pci_dev
*dev
,
1053 struct msix_entry
*entries
, int minvec
,
1054 int maxvec
, struct irq_affinity
*affd
,
1057 int rc
, nvec
= maxvec
;
1059 if (maxvec
< minvec
)
1062 if (WARN_ON_ONCE(dev
->msix_enabled
))
1067 nvec
= irq_calc_affinity_vectors(minvec
, nvec
, affd
);
1072 rc
= __pci_enable_msix(dev
, entries
, nvec
, affd
, flags
);
1086 * pci_enable_msix_range - configure device's MSI-X capability structure
1087 * @dev: pointer to the pci_dev data structure of MSI-X device function
1088 * @entries: pointer to an array of MSI-X entries
1089 * @minvec: minimum number of MSI-X IRQs requested
1090 * @maxvec: maximum number of MSI-X IRQs requested
1092 * Setup the MSI-X capability structure of device function with a maximum
1093 * possible number of interrupts in the range between @minvec and @maxvec
1094 * upon its software driver call to request for MSI-X mode enabled on its
1095 * hardware device function. It returns a negative errno if an error occurs.
1096 * If it succeeds, it returns the actual number of interrupts allocated and
1097 * indicates the successful configuration of MSI-X capability structure
1098 * with new allocated MSI-X interrupts.
1100 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1101 int minvec
, int maxvec
)
1103 return __pci_enable_msix_range(dev
, entries
, minvec
, maxvec
, NULL
, 0);
1105 EXPORT_SYMBOL(pci_enable_msix_range
);
1108 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1109 * @dev: PCI device to operate on
1110 * @min_vecs: minimum number of vectors required (must be >= 1)
1111 * @max_vecs: maximum (desired) number of vectors
1112 * @flags: flags or quirks for the allocation
1113 * @affd: optional description of the affinity requirements
1115 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1116 * vectors if available, and fall back to a single legacy vector
1117 * if neither is available. Return the number of vectors allocated,
1118 * (which might be smaller than @max_vecs) if successful, or a negative
1119 * error code on error. If less than @min_vecs interrupt vectors are
1120 * available for @dev the function will fail with -ENOSPC.
1122 * To get the Linux IRQ number used for a vector that can be passed to
1123 * request_irq() use the pci_irq_vector() helper.
1125 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1126 unsigned int max_vecs
, unsigned int flags
,
1127 struct irq_affinity
*affd
)
1129 struct irq_affinity msi_default_affd
= {0};
1130 int nvecs
= -ENOSPC
;
1132 if (flags
& PCI_IRQ_AFFINITY
) {
1134 affd
= &msi_default_affd
;
1140 if (flags
& PCI_IRQ_MSIX
) {
1141 nvecs
= __pci_enable_msix_range(dev
, NULL
, min_vecs
, max_vecs
,
1147 if (flags
& PCI_IRQ_MSI
) {
1148 nvecs
= __pci_enable_msi_range(dev
, min_vecs
, max_vecs
, affd
);
1153 /* use legacy IRQ if allowed */
1154 if (flags
& PCI_IRQ_LEGACY
) {
1155 if (min_vecs
== 1 && dev
->irq
) {
1157 * Invoke the affinity spreading logic to ensure that
1158 * the device driver can adjust queue configuration
1159 * for the single interrupt case.
1162 irq_create_affinity_masks(1, affd
);
1170 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity
);
1173 * pci_free_irq_vectors - free previously allocated IRQs for a device
1174 * @dev: PCI device to operate on
1176 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1178 void pci_free_irq_vectors(struct pci_dev
*dev
)
1180 pci_disable_msix(dev
);
1181 pci_disable_msi(dev
);
1183 EXPORT_SYMBOL(pci_free_irq_vectors
);
1186 * pci_irq_vector - return Linux IRQ number of a device vector
1187 * @dev: PCI device to operate on
1188 * @nr: device-relative interrupt vector index (0-based).
1190 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1192 if (dev
->msix_enabled
) {
1193 struct msi_desc
*entry
;
1196 for_each_pci_msi_entry(entry
, dev
) {
1205 if (dev
->msi_enabled
) {
1206 struct msi_desc
*entry
= first_pci_msi_entry(dev
);
1208 if (WARN_ON_ONCE(nr
>= entry
->nvec_used
))
1211 if (WARN_ON_ONCE(nr
> 0))
1215 return dev
->irq
+ nr
;
1217 EXPORT_SYMBOL(pci_irq_vector
);
1220 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1221 * @dev: PCI device to operate on
1222 * @nr: device-relative interrupt vector index (0-based).
1224 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*dev
, int nr
)
1226 if (dev
->msix_enabled
) {
1227 struct msi_desc
*entry
;
1230 for_each_pci_msi_entry(entry
, dev
) {
1232 return &entry
->affinity
->mask
;
1237 } else if (dev
->msi_enabled
) {
1238 struct msi_desc
*entry
= first_pci_msi_entry(dev
);
1240 if (WARN_ON_ONCE(!entry
|| !entry
->affinity
||
1241 nr
>= entry
->nvec_used
))
1244 return &entry
->affinity
[nr
].mask
;
1246 return cpu_possible_mask
;
1249 EXPORT_SYMBOL(pci_irq_get_affinity
);
1251 struct pci_dev
*msi_desc_to_pci_dev(struct msi_desc
*desc
)
1253 return to_pci_dev(desc
->dev
);
1255 EXPORT_SYMBOL(msi_desc_to_pci_dev
);
1257 void *msi_desc_to_pci_sysdata(struct msi_desc
*desc
)
1259 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1261 return dev
->bus
->sysdata
;
1263 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata
);
1265 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1267 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1268 * @irq_data: Pointer to interrupt data of the MSI interrupt
1269 * @msg: Pointer to the message
1271 void pci_msi_domain_write_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
1273 struct msi_desc
*desc
= irq_data_get_msi_desc(irq_data
);
1276 * For MSI-X desc->irq is always equal to irq_data->irq. For
1277 * MSI only the first interrupt of MULTI MSI passes the test.
1279 if (desc
->irq
== irq_data
->irq
)
1280 __pci_write_msi_msg(desc
, msg
);
1284 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1285 * @desc: Pointer to the MSI descriptor
1287 * The ID number is only used within the irqdomain.
1289 static irq_hw_number_t
pci_msi_domain_calc_hwirq(struct msi_desc
*desc
)
1291 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1293 return (irq_hw_number_t
)desc
->msi_attrib
.entry_nr
|
1294 pci_dev_id(dev
) << 11 |
1295 (pci_domain_nr(dev
->bus
) & 0xFFFFFFFF) << 27;
1298 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc
*desc
)
1300 return !desc
->msi_attrib
.is_msix
&& desc
->nvec_used
> 1;
1304 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1306 * @domain: The interrupt domain to check
1307 * @info: The domain info for verification
1308 * @dev: The device to check
1311 * 0 if the functionality is supported
1312 * 1 if Multi MSI is requested, but the domain does not support it
1313 * -ENOTSUPP otherwise
1315 int pci_msi_domain_check_cap(struct irq_domain
*domain
,
1316 struct msi_domain_info
*info
, struct device
*dev
)
1318 struct msi_desc
*desc
= first_pci_msi_entry(to_pci_dev(dev
));
1320 /* Special handling to support __pci_enable_msi_range() */
1321 if (pci_msi_desc_is_multi_msi(desc
) &&
1322 !(info
->flags
& MSI_FLAG_MULTI_PCI_MSI
))
1324 else if (desc
->msi_attrib
.is_msix
&& !(info
->flags
& MSI_FLAG_PCI_MSIX
))
1330 static int pci_msi_domain_handle_error(struct irq_domain
*domain
,
1331 struct msi_desc
*desc
, int error
)
1333 /* Special handling to support __pci_enable_msi_range() */
1334 if (pci_msi_desc_is_multi_msi(desc
) && error
== -ENOSPC
)
1340 static void pci_msi_domain_set_desc(msi_alloc_info_t
*arg
,
1341 struct msi_desc
*desc
)
1344 arg
->hwirq
= pci_msi_domain_calc_hwirq(desc
);
1347 static struct msi_domain_ops pci_msi_domain_ops_default
= {
1348 .set_desc
= pci_msi_domain_set_desc
,
1349 .msi_check
= pci_msi_domain_check_cap
,
1350 .handle_error
= pci_msi_domain_handle_error
,
1353 static void pci_msi_domain_update_dom_ops(struct msi_domain_info
*info
)
1355 struct msi_domain_ops
*ops
= info
->ops
;
1358 info
->ops
= &pci_msi_domain_ops_default
;
1360 if (ops
->set_desc
== NULL
)
1361 ops
->set_desc
= pci_msi_domain_set_desc
;
1362 if (ops
->msi_check
== NULL
)
1363 ops
->msi_check
= pci_msi_domain_check_cap
;
1364 if (ops
->handle_error
== NULL
)
1365 ops
->handle_error
= pci_msi_domain_handle_error
;
1369 static void pci_msi_domain_update_chip_ops(struct msi_domain_info
*info
)
1371 struct irq_chip
*chip
= info
->chip
;
1374 if (!chip
->irq_write_msi_msg
)
1375 chip
->irq_write_msi_msg
= pci_msi_domain_write_msg
;
1376 if (!chip
->irq_mask
)
1377 chip
->irq_mask
= pci_msi_mask_irq
;
1378 if (!chip
->irq_unmask
)
1379 chip
->irq_unmask
= pci_msi_unmask_irq
;
1383 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1384 * @fwnode: Optional fwnode of the interrupt controller
1385 * @info: MSI domain info
1386 * @parent: Parent irq domain
1388 * Updates the domain and chip ops and creates a MSI interrupt domain.
1391 * A domain pointer or NULL in case of failure.
1393 struct irq_domain
*pci_msi_create_irq_domain(struct fwnode_handle
*fwnode
,
1394 struct msi_domain_info
*info
,
1395 struct irq_domain
*parent
)
1397 struct irq_domain
*domain
;
1399 if (WARN_ON(info
->flags
& MSI_FLAG_LEVEL_CAPABLE
))
1400 info
->flags
&= ~MSI_FLAG_LEVEL_CAPABLE
;
1402 if (info
->flags
& MSI_FLAG_USE_DEF_DOM_OPS
)
1403 pci_msi_domain_update_dom_ops(info
);
1404 if (info
->flags
& MSI_FLAG_USE_DEF_CHIP_OPS
)
1405 pci_msi_domain_update_chip_ops(info
);
1407 info
->flags
|= MSI_FLAG_ACTIVATE_EARLY
;
1408 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE
))
1409 info
->flags
|= MSI_FLAG_MUST_REACTIVATE
;
1411 /* PCI-MSI is oneshot-safe */
1412 info
->chip
->flags
|= IRQCHIP_ONESHOT_SAFE
;
1414 domain
= msi_create_irq_domain(fwnode
, info
, parent
);
1418 irq_domain_update_bus_token(domain
, DOMAIN_BUS_PCI_MSI
);
1421 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain
);
1424 * Users of the generic MSI infrastructure expect a device to have a single ID,
1425 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1426 * DMA phantom functions tend to still emit MSIs from the real function number,
1427 * so we ignore those and only consider topological aliases where either the
1428 * alias device or RID appears on a different bus number. We also make the
1429 * reasonable assumption that bridges are walked in an upstream direction (so
1430 * the last one seen wins), and the much braver assumption that the most likely
1431 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1432 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1433 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1434 * for taking ownership all we can really do is close our eyes and hope...
1436 static int get_msi_id_cb(struct pci_dev
*pdev
, u16 alias
, void *data
)
1439 u8 bus
= PCI_BUS_NUM(*pa
);
1441 if (pdev
->bus
->number
!= bus
|| PCI_BUS_NUM(alias
) != bus
)
1448 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1449 * @domain: The interrupt domain
1450 * @pdev: The PCI device.
1452 * The RID for a device is formed from the alias, with a firmware
1453 * supplied mapping applied
1457 u32
pci_msi_domain_get_msi_rid(struct irq_domain
*domain
, struct pci_dev
*pdev
)
1459 struct device_node
*of_node
;
1460 u32 rid
= pci_dev_id(pdev
);
1462 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1464 of_node
= irq_domain_get_of_node(domain
);
1465 rid
= of_node
? of_msi_map_id(&pdev
->dev
, of_node
, rid
) :
1466 iort_msi_map_id(&pdev
->dev
, rid
);
1472 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1473 * @pdev: The PCI device
1475 * Use the firmware data to find a device-specific MSI domain
1476 * (i.e. not one that is set as a default).
1478 * Returns: The corresponding MSI domain or NULL if none has been found.
1480 struct irq_domain
*pci_msi_get_device_domain(struct pci_dev
*pdev
)
1482 struct irq_domain
*dom
;
1483 u32 rid
= pci_dev_id(pdev
);
1485 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1486 dom
= of_msi_map_get_device_domain(&pdev
->dev
, rid
, DOMAIN_BUS_PCI_MSI
);
1488 dom
= iort_get_device_domain(&pdev
->dev
, rid
,
1489 DOMAIN_BUS_PCI_MSI
);
1494 * pci_dev_has_special_msi_domain - Check whether the device is handled by
1495 * a non-standard PCI-MSI domain
1496 * @pdev: The PCI device to check.
1498 * Returns: True if the device irqdomain or the bus irqdomain is
1499 * non-standard PCI/MSI.
1501 bool pci_dev_has_special_msi_domain(struct pci_dev
*pdev
)
1503 struct irq_domain
*dom
= dev_get_msi_domain(&pdev
->dev
);
1506 dom
= dev_get_msi_domain(&pdev
->bus
->dev
);
1511 return dom
->bus_token
!= DOMAIN_BUS_PCI_MSI
;
1514 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1515 #endif /* CONFIG_PCI_MSI */
1517 void pci_msi_init(struct pci_dev
*dev
)
1522 * Disable the MSI hardware to avoid screaming interrupts
1523 * during boot. This is the power on reset default so
1524 * usually this should be a noop.
1526 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1530 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &ctrl
);
1531 if (ctrl
& PCI_MSI_FLAGS_ENABLE
)
1532 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
,
1533 ctrl
& ~PCI_MSI_FLAGS_ENABLE
);
1535 if (!(ctrl
& PCI_MSI_FLAGS_64BIT
))
1536 dev
->no_64bit_msi
= 1;
1539 void pci_msix_init(struct pci_dev
*dev
)
1543 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1547 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
1548 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
)
1549 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
,
1550 ctrl
& ~PCI_MSIX_FLAGS_ENABLE
);