1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
31 static int pci_msi_enable
= 1;
32 int pci_msi_ignore_mask
;
34 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
36 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
37 static int pci_msi_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
39 struct irq_domain
*domain
;
41 domain
= dev_get_msi_domain(&dev
->dev
);
42 if (domain
&& irq_domain_is_hierarchy(domain
))
43 return msi_domain_alloc_irqs(domain
, &dev
->dev
, nvec
);
45 return arch_setup_msi_irqs(dev
, nvec
, type
);
48 static void pci_msi_teardown_msi_irqs(struct pci_dev
*dev
)
50 struct irq_domain
*domain
;
52 domain
= dev_get_msi_domain(&dev
->dev
);
53 if (domain
&& irq_domain_is_hierarchy(domain
))
54 msi_domain_free_irqs(domain
, &dev
->dev
);
56 arch_teardown_msi_irqs(dev
);
59 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
60 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
65 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
70 void __weak
arch_teardown_msi_irq(unsigned int irq
)
74 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
76 struct msi_desc
*entry
;
80 * If an architecture wants to support multiple MSI, it needs to
81 * override arch_setup_msi_irqs()
83 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
86 for_each_pci_msi_entry(entry
, dev
) {
87 ret
= arch_setup_msi_irq(dev
, entry
);
97 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
100 struct msi_desc
*entry
;
102 for_each_pci_msi_entry(entry
, dev
)
104 for (i
= 0; i
< entry
->nvec_used
; i
++)
105 arch_teardown_msi_irq(entry
->irq
+ i
);
107 #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
109 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
111 struct msi_desc
*entry
;
114 if (dev
->msix_enabled
) {
115 for_each_pci_msi_entry(entry
, dev
) {
116 if (irq
== entry
->irq
)
119 } else if (dev
->msi_enabled
) {
120 entry
= irq_get_msi_desc(irq
);
124 __pci_write_msi_msg(entry
, &entry
->msg
);
127 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
129 return default_restore_msi_irqs(dev
);
133 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
134 * mask all MSI interrupts by clearing the MSI enable bit does not work
135 * reliably as devices without an INTx disable bit will then generate a
136 * level IRQ which will never be cleared.
138 static inline __attribute_const__ u32
msi_multi_mask(struct msi_desc
*desc
)
140 /* Don't shift by >= width of type */
141 if (desc
->msi_attrib
.multi_cap
>= 5)
143 return (1 << (1 << desc
->msi_attrib
.multi_cap
)) - 1;
146 static noinline
void pci_msi_update_mask(struct msi_desc
*desc
, u32 clear
, u32 set
)
148 raw_spinlock_t
*lock
= &desc
->dev
->msi_lock
;
151 raw_spin_lock_irqsave(lock
, flags
);
152 desc
->msi_mask
&= ~clear
;
153 desc
->msi_mask
|= set
;
154 pci_write_config_dword(msi_desc_to_pci_dev(desc
), desc
->mask_pos
,
156 raw_spin_unlock_irqrestore(lock
, flags
);
159 static inline void pci_msi_mask(struct msi_desc
*desc
, u32 mask
)
161 pci_msi_update_mask(desc
, 0, mask
);
164 static inline void pci_msi_unmask(struct msi_desc
*desc
, u32 mask
)
166 pci_msi_update_mask(desc
, mask
, 0);
169 static inline void __iomem
*pci_msix_desc_addr(struct msi_desc
*desc
)
171 return desc
->mask_base
+ desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
175 * This internal function does not flush PCI writes to the device. All
176 * users must ensure that they read from the device before either assuming
177 * that the device state is up to date, or returning out of this file.
178 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
180 static void pci_msix_write_vector_ctrl(struct msi_desc
*desc
, u32 ctrl
)
182 void __iomem
*desc_addr
= pci_msix_desc_addr(desc
);
184 writel(ctrl
, desc_addr
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
187 static inline void pci_msix_mask(struct msi_desc
*desc
)
189 desc
->msix_ctrl
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
190 pci_msix_write_vector_ctrl(desc
, desc
->msix_ctrl
);
191 /* Flush write to device */
192 readl(desc
->mask_base
);
195 static inline void pci_msix_unmask(struct msi_desc
*desc
)
197 desc
->msix_ctrl
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
198 pci_msix_write_vector_ctrl(desc
, desc
->msix_ctrl
);
201 static void __pci_msi_mask_desc(struct msi_desc
*desc
, u32 mask
)
203 if (pci_msi_ignore_mask
|| desc
->msi_attrib
.is_virtual
)
206 if (desc
->msi_attrib
.is_msix
)
208 else if (desc
->msi_attrib
.maskbit
)
209 pci_msi_mask(desc
, mask
);
212 static void __pci_msi_unmask_desc(struct msi_desc
*desc
, u32 mask
)
214 if (pci_msi_ignore_mask
|| desc
->msi_attrib
.is_virtual
)
217 if (desc
->msi_attrib
.is_msix
)
218 pci_msix_unmask(desc
);
219 else if (desc
->msi_attrib
.maskbit
)
220 pci_msi_unmask(desc
, mask
);
224 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
225 * @data: pointer to irqdata associated to that interrupt
227 void pci_msi_mask_irq(struct irq_data
*data
)
229 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
231 __pci_msi_mask_desc(desc
, BIT(data
->irq
- desc
->irq
));
233 EXPORT_SYMBOL_GPL(pci_msi_mask_irq
);
236 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
237 * @data: pointer to irqdata associated to that interrupt
239 void pci_msi_unmask_irq(struct irq_data
*data
)
241 struct msi_desc
*desc
= irq_data_get_msi_desc(data
);
243 __pci_msi_unmask_desc(desc
, BIT(data
->irq
- desc
->irq
));
245 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq
);
247 void default_restore_msi_irqs(struct pci_dev
*dev
)
249 struct msi_desc
*entry
;
251 for_each_pci_msi_entry(entry
, dev
)
252 default_restore_msi_irq(dev
, entry
->irq
);
255 void __pci_read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
257 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
259 BUG_ON(dev
->current_state
!= PCI_D0
);
261 if (entry
->msi_attrib
.is_msix
) {
262 void __iomem
*base
= pci_msix_desc_addr(entry
);
264 if (WARN_ON_ONCE(entry
->msi_attrib
.is_virtual
))
267 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
268 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
269 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
271 int pos
= dev
->msi_cap
;
274 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
276 if (entry
->msi_attrib
.is_64
) {
277 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
279 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
282 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
288 void __pci_write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
290 struct pci_dev
*dev
= msi_desc_to_pci_dev(entry
);
292 if (dev
->current_state
!= PCI_D0
|| pci_dev_is_disconnected(dev
)) {
293 /* Don't touch the hardware now */
294 } else if (entry
->msi_attrib
.is_msix
) {
295 void __iomem
*base
= pci_msix_desc_addr(entry
);
296 u32 ctrl
= entry
->msix_ctrl
;
297 bool unmasked
= !(ctrl
& PCI_MSIX_ENTRY_CTRL_MASKBIT
);
299 if (entry
->msi_attrib
.is_virtual
)
303 * The specification mandates that the entry is masked
304 * when the message is modified:
306 * "If software changes the Address or Data value of an
307 * entry while the entry is unmasked, the result is
311 pci_msix_write_vector_ctrl(entry
, ctrl
| PCI_MSIX_ENTRY_CTRL_MASKBIT
);
313 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
314 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
315 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
318 pci_msix_write_vector_ctrl(entry
, ctrl
);
320 /* Ensure that the writes are visible in the device */
321 readl(base
+ PCI_MSIX_ENTRY_DATA
);
323 int pos
= dev
->msi_cap
;
326 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
327 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
328 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
329 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
331 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
333 if (entry
->msi_attrib
.is_64
) {
334 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
336 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
339 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
342 /* Ensure that the writes are visible in the device */
343 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
349 if (entry
->write_msi_msg
)
350 entry
->write_msi_msg(entry
, entry
->write_msi_msg_data
);
354 void pci_write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
356 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
358 __pci_write_msi_msg(entry
, msg
);
360 EXPORT_SYMBOL_GPL(pci_write_msi_msg
);
362 static void free_msi_irqs(struct pci_dev
*dev
)
364 struct list_head
*msi_list
= dev_to_msi_list(&dev
->dev
);
365 struct msi_desc
*entry
, *tmp
;
368 for_each_pci_msi_entry(entry
, dev
)
370 for (i
= 0; i
< entry
->nvec_used
; i
++)
371 BUG_ON(irq_has_action(entry
->irq
+ i
));
373 pci_msi_teardown_msi_irqs(dev
);
375 list_for_each_entry_safe(entry
, tmp
, msi_list
, list
) {
376 if (entry
->msi_attrib
.is_msix
) {
377 if (list_is_last(&entry
->list
, msi_list
))
378 iounmap(entry
->mask_base
);
381 list_del(&entry
->list
);
382 free_msi_entry(entry
);
385 if (dev
->msi_irq_groups
) {
386 msi_destroy_sysfs(&dev
->dev
, dev
->msi_irq_groups
);
387 dev
->msi_irq_groups
= NULL
;
391 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
393 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
394 pci_intx(dev
, enable
);
397 static void pci_msi_set_enable(struct pci_dev
*dev
, int enable
)
401 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
402 control
&= ~PCI_MSI_FLAGS_ENABLE
;
404 control
|= PCI_MSI_FLAGS_ENABLE
;
405 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
408 static void __pci_restore_msi_state(struct pci_dev
*dev
)
411 struct msi_desc
*entry
;
413 if (!dev
->msi_enabled
)
416 entry
= irq_get_msi_desc(dev
->irq
);
418 pci_intx_for_msi(dev
, 0);
419 pci_msi_set_enable(dev
, 0);
420 arch_restore_msi_irqs(dev
);
422 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
423 pci_msi_update_mask(entry
, 0, 0);
424 control
&= ~PCI_MSI_FLAGS_QSIZE
;
425 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
426 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
429 static void pci_msix_clear_and_set_ctrl(struct pci_dev
*dev
, u16 clear
, u16 set
)
433 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
436 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, ctrl
);
439 static void __pci_restore_msix_state(struct pci_dev
*dev
)
441 struct msi_desc
*entry
;
443 if (!dev
->msix_enabled
)
445 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
447 /* route the table */
448 pci_intx_for_msi(dev
, 0);
449 pci_msix_clear_and_set_ctrl(dev
, 0,
450 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
452 arch_restore_msi_irqs(dev
);
453 for_each_pci_msi_entry(entry
, dev
)
454 pci_msix_write_vector_ctrl(entry
, entry
->msix_ctrl
);
456 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
459 void pci_restore_msi_state(struct pci_dev
*dev
)
461 __pci_restore_msi_state(dev
);
462 __pci_restore_msix_state(dev
);
464 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
466 static struct msi_desc
*
467 msi_setup_entry(struct pci_dev
*dev
, int nvec
, struct irq_affinity
*affd
)
469 struct irq_affinity_desc
*masks
= NULL
;
470 struct msi_desc
*entry
;
474 masks
= irq_create_affinity_masks(nvec
, affd
);
476 /* MSI Entry Initialization */
477 entry
= alloc_msi_entry(&dev
->dev
, nvec
, masks
);
481 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
483 entry
->msi_attrib
.is_msix
= 0;
484 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
485 entry
->msi_attrib
.is_virtual
= 0;
486 entry
->msi_attrib
.entry_nr
= 0;
487 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
488 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
489 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
490 entry
->msi_attrib
.multiple
= ilog2(__roundup_pow_of_two(nvec
));
492 if (control
& PCI_MSI_FLAGS_64BIT
)
493 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
495 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
497 /* Save the initial mask status */
498 if (entry
->msi_attrib
.maskbit
)
499 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->msi_mask
);
506 static int msi_verify_entries(struct pci_dev
*dev
)
508 struct msi_desc
*entry
;
510 if (!dev
->no_64bit_msi
)
513 for_each_pci_msi_entry(entry
, dev
) {
514 if (entry
->msg
.address_hi
) {
515 pci_err(dev
, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
516 entry
->msg
.address_hi
, entry
->msg
.address_lo
);
524 * msi_capability_init - configure device's MSI capability structure
525 * @dev: pointer to the pci_dev data structure of MSI device function
526 * @nvec: number of interrupts to allocate
527 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
529 * Setup the MSI capability structure of the device with the requested
530 * number of interrupts. A return value of zero indicates the successful
531 * setup of an entry with the new MSI IRQ. A negative return value indicates
532 * an error, and a positive return value indicates the number of interrupts
533 * which could have been allocated.
535 static int msi_capability_init(struct pci_dev
*dev
, int nvec
,
536 struct irq_affinity
*affd
)
538 struct msi_desc
*entry
;
541 pci_msi_set_enable(dev
, 0); /* Disable MSI during set up */
543 entry
= msi_setup_entry(dev
, nvec
, affd
);
547 /* All MSIs are unmasked by default; mask them all */
548 pci_msi_mask(entry
, msi_multi_mask(entry
));
550 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
552 /* Configure MSI capability structure */
553 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
557 ret
= msi_verify_entries(dev
);
561 dev
->msi_irq_groups
= msi_populate_sysfs(&dev
->dev
);
562 if (IS_ERR(dev
->msi_irq_groups
)) {
563 ret
= PTR_ERR(dev
->msi_irq_groups
);
567 /* Set MSI enabled bits */
568 pci_intx_for_msi(dev
, 0);
569 pci_msi_set_enable(dev
, 1);
570 dev
->msi_enabled
= 1;
572 pcibios_free_irq(dev
);
573 dev
->irq
= entry
->irq
;
577 pci_msi_unmask(entry
, msi_multi_mask(entry
));
582 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
584 resource_size_t phys_addr
;
589 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
591 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
592 flags
= pci_resource_flags(dev
, bir
);
593 if (!flags
|| (flags
& IORESOURCE_UNSET
))
596 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
597 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
599 return ioremap(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
602 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
603 struct msix_entry
*entries
, int nvec
,
604 struct irq_affinity
*affd
)
606 struct irq_affinity_desc
*curmsk
, *masks
= NULL
;
607 struct msi_desc
*entry
;
610 int vec_count
= pci_msix_vec_count(dev
);
613 masks
= irq_create_affinity_masks(nvec
, affd
);
615 for (i
= 0, curmsk
= masks
; i
< nvec
; i
++) {
616 entry
= alloc_msi_entry(&dev
->dev
, 1, curmsk
);
622 /* No enough memory. Don't try again */
627 entry
->msi_attrib
.is_msix
= 1;
628 entry
->msi_attrib
.is_64
= 1;
631 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
633 entry
->msi_attrib
.entry_nr
= i
;
635 entry
->msi_attrib
.is_virtual
=
636 entry
->msi_attrib
.entry_nr
>= vec_count
;
638 entry
->msi_attrib
.default_irq
= dev
->irq
;
639 entry
->mask_base
= base
;
641 if (!entry
->msi_attrib
.is_virtual
) {
642 addr
= pci_msix_desc_addr(entry
);
643 entry
->msix_ctrl
= readl(addr
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
646 list_add_tail(&entry
->list
, dev_to_msi_list(&dev
->dev
));
656 static void msix_update_entries(struct pci_dev
*dev
, struct msix_entry
*entries
)
658 struct msi_desc
*entry
;
660 for_each_pci_msi_entry(entry
, dev
) {
662 entries
->vector
= entry
->irq
;
668 static void msix_mask_all(void __iomem
*base
, int tsize
)
670 u32 ctrl
= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
673 if (pci_msi_ignore_mask
)
676 for (i
= 0; i
< tsize
; i
++, base
+= PCI_MSIX_ENTRY_SIZE
)
677 writel(ctrl
, base
+ PCI_MSIX_ENTRY_VECTOR_CTRL
);
681 * msix_capability_init - configure device's MSI-X capability
682 * @dev: pointer to the pci_dev data structure of MSI-X device function
683 * @entries: pointer to an array of struct msix_entry entries
684 * @nvec: number of @entries
685 * @affd: Optional pointer to enable automatic affinity assignment
687 * Setup the MSI-X capability structure of device function with a
688 * single MSI-X IRQ. A return of zero indicates the successful setup of
689 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
691 static int msix_capability_init(struct pci_dev
*dev
, struct msix_entry
*entries
,
692 int nvec
, struct irq_affinity
*affd
)
699 * Some devices require MSI-X to be enabled before the MSI-X
700 * registers can be accessed. Mask all the vectors to prevent
701 * interrupts coming in before they're fully set up.
703 pci_msix_clear_and_set_ctrl(dev
, 0, PCI_MSIX_FLAGS_MASKALL
|
704 PCI_MSIX_FLAGS_ENABLE
);
706 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
707 /* Request & Map MSI-X table region */
708 tsize
= msix_table_size(control
);
709 base
= msix_map_region(dev
, tsize
);
715 /* Ensure that all table entries are masked. */
716 msix_mask_all(base
, tsize
);
718 ret
= msix_setup_entries(dev
, base
, entries
, nvec
, affd
);
722 ret
= pci_msi_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
726 /* Check if all MSI entries honor device restrictions */
727 ret
= msi_verify_entries(dev
);
731 msix_update_entries(dev
, entries
);
733 dev
->msi_irq_groups
= msi_populate_sysfs(&dev
->dev
);
734 if (IS_ERR(dev
->msi_irq_groups
)) {
735 ret
= PTR_ERR(dev
->msi_irq_groups
);
739 /* Set MSI-X enabled bits and unmask the function */
740 pci_intx_for_msi(dev
, 0);
741 dev
->msix_enabled
= 1;
742 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
744 pcibios_free_irq(dev
);
750 * If we had some success, report the number of IRQs
751 * we succeeded in setting up.
753 struct msi_desc
*entry
;
756 for_each_pci_msi_entry(entry
, dev
) {
768 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
774 * pci_msi_supported - check whether MSI may be enabled on a device
775 * @dev: pointer to the pci_dev data structure of MSI device function
776 * @nvec: how many MSIs have been requested?
778 * Look at global flags, the device itself, and its parent buses
779 * to determine if MSI/-X are supported for the device. If MSI/-X is
780 * supported return 1, else return 0.
782 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
786 /* MSI must be globally enabled and supported by the device */
790 if (!dev
|| dev
->no_msi
)
794 * You can't ask to have 0 or less MSIs configured.
796 * b) the list manipulation code assumes nvec >= 1.
802 * Any bridge which does NOT route MSI transactions from its
803 * secondary bus to its primary bus must set NO_MSI flag on
804 * the secondary pci_bus.
806 * The NO_MSI flag can either be set directly by:
807 * - arch-specific PCI host bus controller drivers (deprecated)
808 * - quirks for specific PCI bridges
810 * or indirectly by platform-specific PCI host bridge drivers by
811 * advertising the 'msi_domain' property, which results in
812 * the NO_MSI flag when no MSI domain is found for this bridge
815 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
816 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
823 * pci_msi_vec_count - Return the number of MSI vectors a device can send
824 * @dev: device to report about
826 * This function returns the number of MSI vectors a device requested via
827 * Multiple Message Capable register. It returns a negative errno if the
828 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
829 * and returns a power of two, up to a maximum of 2^5 (32), according to the
832 int pci_msi_vec_count(struct pci_dev
*dev
)
840 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
841 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
845 EXPORT_SYMBOL(pci_msi_vec_count
);
847 static void pci_msi_shutdown(struct pci_dev
*dev
)
849 struct msi_desc
*desc
;
851 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
854 BUG_ON(list_empty(dev_to_msi_list(&dev
->dev
)));
855 desc
= first_pci_msi_entry(dev
);
857 pci_msi_set_enable(dev
, 0);
858 pci_intx_for_msi(dev
, 1);
859 dev
->msi_enabled
= 0;
861 /* Return the device with MSI unmasked as initial states */
862 pci_msi_unmask(desc
, msi_multi_mask(desc
));
864 /* Restore dev->irq to its default pin-assertion IRQ */
865 dev
->irq
= desc
->msi_attrib
.default_irq
;
866 pcibios_alloc_irq(dev
);
869 void pci_disable_msi(struct pci_dev
*dev
)
871 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
874 pci_msi_shutdown(dev
);
877 EXPORT_SYMBOL(pci_disable_msi
);
880 * pci_msix_vec_count - return the number of device's MSI-X table entries
881 * @dev: pointer to the pci_dev data structure of MSI-X device function
882 * This function returns the number of device's MSI-X table entries and
883 * therefore the number of MSI-X vectors device is capable of sending.
884 * It returns a negative errno if the device is not capable of sending MSI-X
887 int pci_msix_vec_count(struct pci_dev
*dev
)
894 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
895 return msix_table_size(control
);
897 EXPORT_SYMBOL(pci_msix_vec_count
);
899 static int __pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
,
900 int nvec
, struct irq_affinity
*affd
, int flags
)
905 if (!pci_msi_supported(dev
, nvec
) || dev
->current_state
!= PCI_D0
)
908 nr_entries
= pci_msix_vec_count(dev
);
911 if (nvec
> nr_entries
&& !(flags
& PCI_IRQ_VIRTUAL
))
915 /* Check for any invalid entries */
916 for (i
= 0; i
< nvec
; i
++) {
917 if (entries
[i
].entry
>= nr_entries
)
918 return -EINVAL
; /* invalid entry */
919 for (j
= i
+ 1; j
< nvec
; j
++) {
920 if (entries
[i
].entry
== entries
[j
].entry
)
921 return -EINVAL
; /* duplicate entry */
926 /* Check whether driver already requested for MSI IRQ */
927 if (dev
->msi_enabled
) {
928 pci_info(dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
931 return msix_capability_init(dev
, entries
, nvec
, affd
);
934 static void pci_msix_shutdown(struct pci_dev
*dev
)
936 struct msi_desc
*entry
;
938 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
941 if (pci_dev_is_disconnected(dev
)) {
942 dev
->msix_enabled
= 0;
946 /* Return the device with MSI-X masked as initial states */
947 for_each_pci_msi_entry(entry
, dev
)
948 pci_msix_mask(entry
);
950 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
951 pci_intx_for_msi(dev
, 1);
952 dev
->msix_enabled
= 0;
953 pcibios_alloc_irq(dev
);
956 void pci_disable_msix(struct pci_dev
*dev
)
958 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
961 pci_msix_shutdown(dev
);
964 EXPORT_SYMBOL(pci_disable_msix
);
966 void pci_no_msi(void)
972 * pci_msi_enabled - is MSI enabled?
974 * Returns true if MSI has not been disabled by the command-line option
977 int pci_msi_enabled(void)
979 return pci_msi_enable
;
981 EXPORT_SYMBOL(pci_msi_enabled
);
983 static int __pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
,
984 struct irq_affinity
*affd
)
989 if (!pci_msi_supported(dev
, minvec
) || dev
->current_state
!= PCI_D0
)
992 /* Check whether driver already requested MSI-X IRQs */
993 if (dev
->msix_enabled
) {
994 pci_info(dev
, "can't enable MSI (MSI-X already enabled)\n");
1001 if (WARN_ON_ONCE(dev
->msi_enabled
))
1004 nvec
= pci_msi_vec_count(dev
);
1015 nvec
= irq_calc_affinity_vectors(minvec
, nvec
, affd
);
1020 rc
= msi_capability_init(dev
, nvec
, affd
);
1033 /* deprecated, don't use */
1034 int pci_enable_msi(struct pci_dev
*dev
)
1036 int rc
= __pci_enable_msi_range(dev
, 1, 1, NULL
);
1041 EXPORT_SYMBOL(pci_enable_msi
);
1043 static int __pci_enable_msix_range(struct pci_dev
*dev
,
1044 struct msix_entry
*entries
, int minvec
,
1045 int maxvec
, struct irq_affinity
*affd
,
1048 int rc
, nvec
= maxvec
;
1050 if (maxvec
< minvec
)
1053 if (WARN_ON_ONCE(dev
->msix_enabled
))
1058 nvec
= irq_calc_affinity_vectors(minvec
, nvec
, affd
);
1063 rc
= __pci_enable_msix(dev
, entries
, nvec
, affd
, flags
);
1077 * pci_enable_msix_range - configure device's MSI-X capability structure
1078 * @dev: pointer to the pci_dev data structure of MSI-X device function
1079 * @entries: pointer to an array of MSI-X entries
1080 * @minvec: minimum number of MSI-X IRQs requested
1081 * @maxvec: maximum number of MSI-X IRQs requested
1083 * Setup the MSI-X capability structure of device function with a maximum
1084 * possible number of interrupts in the range between @minvec and @maxvec
1085 * upon its software driver call to request for MSI-X mode enabled on its
1086 * hardware device function. It returns a negative errno if an error occurs.
1087 * If it succeeds, it returns the actual number of interrupts allocated and
1088 * indicates the successful configuration of MSI-X capability structure
1089 * with new allocated MSI-X interrupts.
1091 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1092 int minvec
, int maxvec
)
1094 return __pci_enable_msix_range(dev
, entries
, minvec
, maxvec
, NULL
, 0);
1096 EXPORT_SYMBOL(pci_enable_msix_range
);
1099 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1100 * @dev: PCI device to operate on
1101 * @min_vecs: minimum number of vectors required (must be >= 1)
1102 * @max_vecs: maximum (desired) number of vectors
1103 * @flags: flags or quirks for the allocation
1104 * @affd: optional description of the affinity requirements
1106 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1107 * vectors if available, and fall back to a single legacy vector
1108 * if neither is available. Return the number of vectors allocated,
1109 * (which might be smaller than @max_vecs) if successful, or a negative
1110 * error code on error. If less than @min_vecs interrupt vectors are
1111 * available for @dev the function will fail with -ENOSPC.
1113 * To get the Linux IRQ number used for a vector that can be passed to
1114 * request_irq() use the pci_irq_vector() helper.
1116 int pci_alloc_irq_vectors_affinity(struct pci_dev
*dev
, unsigned int min_vecs
,
1117 unsigned int max_vecs
, unsigned int flags
,
1118 struct irq_affinity
*affd
)
1120 struct irq_affinity msi_default_affd
= {0};
1121 int nvecs
= -ENOSPC
;
1123 if (flags
& PCI_IRQ_AFFINITY
) {
1125 affd
= &msi_default_affd
;
1131 if (flags
& PCI_IRQ_MSIX
) {
1132 nvecs
= __pci_enable_msix_range(dev
, NULL
, min_vecs
, max_vecs
,
1138 if (flags
& PCI_IRQ_MSI
) {
1139 nvecs
= __pci_enable_msi_range(dev
, min_vecs
, max_vecs
, affd
);
1144 /* use legacy IRQ if allowed */
1145 if (flags
& PCI_IRQ_LEGACY
) {
1146 if (min_vecs
== 1 && dev
->irq
) {
1148 * Invoke the affinity spreading logic to ensure that
1149 * the device driver can adjust queue configuration
1150 * for the single interrupt case.
1153 irq_create_affinity_masks(1, affd
);
1161 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity
);
1164 * pci_free_irq_vectors - free previously allocated IRQs for a device
1165 * @dev: PCI device to operate on
1167 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1169 void pci_free_irq_vectors(struct pci_dev
*dev
)
1171 pci_disable_msix(dev
);
1172 pci_disable_msi(dev
);
1174 EXPORT_SYMBOL(pci_free_irq_vectors
);
1177 * pci_irq_vector - return Linux IRQ number of a device vector
1178 * @dev: PCI device to operate on
1179 * @nr: device-relative interrupt vector index (0-based).
1181 int pci_irq_vector(struct pci_dev
*dev
, unsigned int nr
)
1183 if (dev
->msix_enabled
) {
1184 struct msi_desc
*entry
;
1187 for_each_pci_msi_entry(entry
, dev
) {
1196 if (dev
->msi_enabled
) {
1197 struct msi_desc
*entry
= first_pci_msi_entry(dev
);
1199 if (WARN_ON_ONCE(nr
>= entry
->nvec_used
))
1202 if (WARN_ON_ONCE(nr
> 0))
1206 return dev
->irq
+ nr
;
1208 EXPORT_SYMBOL(pci_irq_vector
);
1211 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1212 * @dev: PCI device to operate on
1213 * @nr: device-relative interrupt vector index (0-based).
1215 const struct cpumask
*pci_irq_get_affinity(struct pci_dev
*dev
, int nr
)
1217 if (dev
->msix_enabled
) {
1218 struct msi_desc
*entry
;
1221 for_each_pci_msi_entry(entry
, dev
) {
1223 return &entry
->affinity
->mask
;
1228 } else if (dev
->msi_enabled
) {
1229 struct msi_desc
*entry
= first_pci_msi_entry(dev
);
1231 if (WARN_ON_ONCE(!entry
|| !entry
->affinity
||
1232 nr
>= entry
->nvec_used
))
1235 return &entry
->affinity
[nr
].mask
;
1237 return cpu_possible_mask
;
1240 EXPORT_SYMBOL(pci_irq_get_affinity
);
1242 struct pci_dev
*msi_desc_to_pci_dev(struct msi_desc
*desc
)
1244 return to_pci_dev(desc
->dev
);
1246 EXPORT_SYMBOL(msi_desc_to_pci_dev
);
1248 void *msi_desc_to_pci_sysdata(struct msi_desc
*desc
)
1250 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1252 return dev
->bus
->sysdata
;
1254 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata
);
1256 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1258 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1259 * @irq_data: Pointer to interrupt data of the MSI interrupt
1260 * @msg: Pointer to the message
1262 void pci_msi_domain_write_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
1264 struct msi_desc
*desc
= irq_data_get_msi_desc(irq_data
);
1267 * For MSI-X desc->irq is always equal to irq_data->irq. For
1268 * MSI only the first interrupt of MULTI MSI passes the test.
1270 if (desc
->irq
== irq_data
->irq
)
1271 __pci_write_msi_msg(desc
, msg
);
1275 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1276 * @desc: Pointer to the MSI descriptor
1278 * The ID number is only used within the irqdomain.
1280 static irq_hw_number_t
pci_msi_domain_calc_hwirq(struct msi_desc
*desc
)
1282 struct pci_dev
*dev
= msi_desc_to_pci_dev(desc
);
1284 return (irq_hw_number_t
)desc
->msi_attrib
.entry_nr
|
1285 pci_dev_id(dev
) << 11 |
1286 (pci_domain_nr(dev
->bus
) & 0xFFFFFFFF) << 27;
1289 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc
*desc
)
1291 return !desc
->msi_attrib
.is_msix
&& desc
->nvec_used
> 1;
1295 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1297 * @domain: The interrupt domain to check
1298 * @info: The domain info for verification
1299 * @dev: The device to check
1302 * 0 if the functionality is supported
1303 * 1 if Multi MSI is requested, but the domain does not support it
1304 * -ENOTSUPP otherwise
1306 int pci_msi_domain_check_cap(struct irq_domain
*domain
,
1307 struct msi_domain_info
*info
, struct device
*dev
)
1309 struct msi_desc
*desc
= first_pci_msi_entry(to_pci_dev(dev
));
1311 /* Special handling to support __pci_enable_msi_range() */
1312 if (pci_msi_desc_is_multi_msi(desc
) &&
1313 !(info
->flags
& MSI_FLAG_MULTI_PCI_MSI
))
1315 else if (desc
->msi_attrib
.is_msix
&& !(info
->flags
& MSI_FLAG_PCI_MSIX
))
1321 static int pci_msi_domain_handle_error(struct irq_domain
*domain
,
1322 struct msi_desc
*desc
, int error
)
1324 /* Special handling to support __pci_enable_msi_range() */
1325 if (pci_msi_desc_is_multi_msi(desc
) && error
== -ENOSPC
)
1331 static void pci_msi_domain_set_desc(msi_alloc_info_t
*arg
,
1332 struct msi_desc
*desc
)
1335 arg
->hwirq
= pci_msi_domain_calc_hwirq(desc
);
1338 static struct msi_domain_ops pci_msi_domain_ops_default
= {
1339 .set_desc
= pci_msi_domain_set_desc
,
1340 .msi_check
= pci_msi_domain_check_cap
,
1341 .handle_error
= pci_msi_domain_handle_error
,
1344 static void pci_msi_domain_update_dom_ops(struct msi_domain_info
*info
)
1346 struct msi_domain_ops
*ops
= info
->ops
;
1349 info
->ops
= &pci_msi_domain_ops_default
;
1351 if (ops
->set_desc
== NULL
)
1352 ops
->set_desc
= pci_msi_domain_set_desc
;
1353 if (ops
->msi_check
== NULL
)
1354 ops
->msi_check
= pci_msi_domain_check_cap
;
1355 if (ops
->handle_error
== NULL
)
1356 ops
->handle_error
= pci_msi_domain_handle_error
;
1360 static void pci_msi_domain_update_chip_ops(struct msi_domain_info
*info
)
1362 struct irq_chip
*chip
= info
->chip
;
1365 if (!chip
->irq_write_msi_msg
)
1366 chip
->irq_write_msi_msg
= pci_msi_domain_write_msg
;
1367 if (!chip
->irq_mask
)
1368 chip
->irq_mask
= pci_msi_mask_irq
;
1369 if (!chip
->irq_unmask
)
1370 chip
->irq_unmask
= pci_msi_unmask_irq
;
1374 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1375 * @fwnode: Optional fwnode of the interrupt controller
1376 * @info: MSI domain info
1377 * @parent: Parent irq domain
1379 * Updates the domain and chip ops and creates a MSI interrupt domain.
1382 * A domain pointer or NULL in case of failure.
1384 struct irq_domain
*pci_msi_create_irq_domain(struct fwnode_handle
*fwnode
,
1385 struct msi_domain_info
*info
,
1386 struct irq_domain
*parent
)
1388 struct irq_domain
*domain
;
1390 if (WARN_ON(info
->flags
& MSI_FLAG_LEVEL_CAPABLE
))
1391 info
->flags
&= ~MSI_FLAG_LEVEL_CAPABLE
;
1393 if (info
->flags
& MSI_FLAG_USE_DEF_DOM_OPS
)
1394 pci_msi_domain_update_dom_ops(info
);
1395 if (info
->flags
& MSI_FLAG_USE_DEF_CHIP_OPS
)
1396 pci_msi_domain_update_chip_ops(info
);
1398 info
->flags
|= MSI_FLAG_ACTIVATE_EARLY
;
1399 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE
))
1400 info
->flags
|= MSI_FLAG_MUST_REACTIVATE
;
1402 /* PCI-MSI is oneshot-safe */
1403 info
->chip
->flags
|= IRQCHIP_ONESHOT_SAFE
;
1405 domain
= msi_create_irq_domain(fwnode
, info
, parent
);
1409 irq_domain_update_bus_token(domain
, DOMAIN_BUS_PCI_MSI
);
1412 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain
);
1415 * Users of the generic MSI infrastructure expect a device to have a single ID,
1416 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1417 * DMA phantom functions tend to still emit MSIs from the real function number,
1418 * so we ignore those and only consider topological aliases where either the
1419 * alias device or RID appears on a different bus number. We also make the
1420 * reasonable assumption that bridges are walked in an upstream direction (so
1421 * the last one seen wins), and the much braver assumption that the most likely
1422 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1423 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1424 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1425 * for taking ownership all we can really do is close our eyes and hope...
1427 static int get_msi_id_cb(struct pci_dev
*pdev
, u16 alias
, void *data
)
1430 u8 bus
= PCI_BUS_NUM(*pa
);
1432 if (pdev
->bus
->number
!= bus
|| PCI_BUS_NUM(alias
) != bus
)
1439 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1440 * @domain: The interrupt domain
1441 * @pdev: The PCI device.
1443 * The RID for a device is formed from the alias, with a firmware
1444 * supplied mapping applied
1448 u32
pci_msi_domain_get_msi_rid(struct irq_domain
*domain
, struct pci_dev
*pdev
)
1450 struct device_node
*of_node
;
1451 u32 rid
= pci_dev_id(pdev
);
1453 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1455 of_node
= irq_domain_get_of_node(domain
);
1456 rid
= of_node
? of_msi_map_id(&pdev
->dev
, of_node
, rid
) :
1457 iort_msi_map_id(&pdev
->dev
, rid
);
1463 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1464 * @pdev: The PCI device
1466 * Use the firmware data to find a device-specific MSI domain
1467 * (i.e. not one that is set as a default).
1469 * Returns: The corresponding MSI domain or NULL if none has been found.
1471 struct irq_domain
*pci_msi_get_device_domain(struct pci_dev
*pdev
)
1473 struct irq_domain
*dom
;
1474 u32 rid
= pci_dev_id(pdev
);
1476 pci_for_each_dma_alias(pdev
, get_msi_id_cb
, &rid
);
1477 dom
= of_msi_map_get_device_domain(&pdev
->dev
, rid
, DOMAIN_BUS_PCI_MSI
);
1479 dom
= iort_get_device_domain(&pdev
->dev
, rid
,
1480 DOMAIN_BUS_PCI_MSI
);
1485 * pci_dev_has_special_msi_domain - Check whether the device is handled by
1486 * a non-standard PCI-MSI domain
1487 * @pdev: The PCI device to check.
1489 * Returns: True if the device irqdomain or the bus irqdomain is
1490 * non-standard PCI/MSI.
1492 bool pci_dev_has_special_msi_domain(struct pci_dev
*pdev
)
1494 struct irq_domain
*dom
= dev_get_msi_domain(&pdev
->dev
);
1497 dom
= dev_get_msi_domain(&pdev
->bus
->dev
);
1502 return dom
->bus_token
!= DOMAIN_BUS_PCI_MSI
;
1505 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1506 #endif /* CONFIG_PCI_MSI */
1508 void pci_msi_init(struct pci_dev
*dev
)
1513 * Disable the MSI hardware to avoid screaming interrupts
1514 * during boot. This is the power on reset default so
1515 * usually this should be a noop.
1517 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1521 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &ctrl
);
1522 if (ctrl
& PCI_MSI_FLAGS_ENABLE
)
1523 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
,
1524 ctrl
& ~PCI_MSI_FLAGS_ENABLE
);
1526 if (!(ctrl
& PCI_MSI_FLAGS_64BIT
))
1527 dev
->no_64bit_msi
= 1;
1530 void pci_msix_init(struct pci_dev
*dev
)
1534 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1538 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
1539 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
)
1540 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
,
1541 ctrl
& ~PCI_MSIX_FLAGS_ENABLE
);