3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/export.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
25 static int pci_msi_enable
= 1;
27 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
32 int __weak
arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
34 struct msi_chip
*chip
= dev
->bus
->msi
;
37 if (!chip
|| !chip
->setup_irq
)
40 err
= chip
->setup_irq(chip
, dev
, desc
);
44 irq_set_chip_data(desc
->irq
, chip
);
49 void __weak
arch_teardown_msi_irq(unsigned int irq
)
51 struct msi_chip
*chip
= irq_get_chip_data(irq
);
53 if (!chip
|| !chip
->teardown_irq
)
56 chip
->teardown_irq(chip
, irq
);
59 int __weak
arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
61 struct msi_desc
*entry
;
65 * If an architecture wants to support multiple MSI, it needs to
66 * override arch_setup_msi_irqs()
68 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
71 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
72 ret
= arch_setup_msi_irq(dev
, entry
);
83 * We have a default implementation available as a separate non-weak
84 * function, as it is used by the Xen x86 PCI code
86 void default_teardown_msi_irqs(struct pci_dev
*dev
)
88 struct msi_desc
*entry
;
90 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
95 nvec
= entry
->nvec_used
;
97 nvec
= 1 << entry
->msi_attrib
.multiple
;
98 for (i
= 0; i
< nvec
; i
++)
99 arch_teardown_msi_irq(entry
->irq
+ i
);
103 void __weak
arch_teardown_msi_irqs(struct pci_dev
*dev
)
105 return default_teardown_msi_irqs(dev
);
108 static void default_restore_msi_irq(struct pci_dev
*dev
, int irq
)
110 struct msi_desc
*entry
;
113 if (dev
->msix_enabled
) {
114 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
115 if (irq
== entry
->irq
)
118 } else if (dev
->msi_enabled
) {
119 entry
= irq_get_msi_desc(irq
);
123 __write_msi_msg(entry
, &entry
->msg
);
126 void __weak
arch_restore_msi_irqs(struct pci_dev
*dev
)
128 return default_restore_msi_irqs(dev
);
131 static void msi_set_enable(struct pci_dev
*dev
, int enable
)
135 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
136 control
&= ~PCI_MSI_FLAGS_ENABLE
;
138 control
|= PCI_MSI_FLAGS_ENABLE
;
139 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
142 static void msix_clear_and_set_ctrl(struct pci_dev
*dev
, u16 clear
, u16 set
)
146 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
149 pci_write_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, ctrl
);
152 static inline __attribute_const__ u32
msi_mask(unsigned x
)
154 /* Don't shift by >= width of type */
157 return (1 << (1 << x
)) - 1;
161 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
162 * mask all MSI interrupts by clearing the MSI enable bit does not work
163 * reliably as devices without an INTx disable bit will then generate a
164 * level IRQ which will never be cleared.
166 u32
default_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
168 u32 mask_bits
= desc
->masked
;
170 if (!desc
->msi_attrib
.maskbit
)
175 pci_write_config_dword(desc
->dev
, desc
->mask_pos
, mask_bits
);
180 __weak u32
arch_msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
182 return default_msi_mask_irq(desc
, mask
, flag
);
185 static void msi_mask_irq(struct msi_desc
*desc
, u32 mask
, u32 flag
)
187 desc
->masked
= arch_msi_mask_irq(desc
, mask
, flag
);
191 * This internal function does not flush PCI writes to the device.
192 * All users must ensure that they read from the device before either
193 * assuming that the device state is up to date, or returning out of this
194 * file. This saves a few milliseconds when initialising devices with lots
195 * of MSI-X interrupts.
197 u32
default_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
199 u32 mask_bits
= desc
->masked
;
200 unsigned offset
= desc
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
+
201 PCI_MSIX_ENTRY_VECTOR_CTRL
;
202 mask_bits
&= ~PCI_MSIX_ENTRY_CTRL_MASKBIT
;
204 mask_bits
|= PCI_MSIX_ENTRY_CTRL_MASKBIT
;
205 writel(mask_bits
, desc
->mask_base
+ offset
);
210 __weak u32
arch_msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
212 return default_msix_mask_irq(desc
, flag
);
215 static void msix_mask_irq(struct msi_desc
*desc
, u32 flag
)
217 desc
->masked
= arch_msix_mask_irq(desc
, flag
);
220 static void msi_set_mask_bit(struct irq_data
*data
, u32 flag
)
222 struct msi_desc
*desc
= irq_data_get_msi(data
);
224 if (desc
->msi_attrib
.is_msix
) {
225 msix_mask_irq(desc
, flag
);
226 readl(desc
->mask_base
); /* Flush write to device */
228 unsigned offset
= data
->irq
- desc
->irq
;
229 msi_mask_irq(desc
, 1 << offset
, flag
<< offset
);
233 void mask_msi_irq(struct irq_data
*data
)
235 msi_set_mask_bit(data
, 1);
238 void unmask_msi_irq(struct irq_data
*data
)
240 msi_set_mask_bit(data
, 0);
243 void default_restore_msi_irqs(struct pci_dev
*dev
)
245 struct msi_desc
*entry
;
247 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
248 default_restore_msi_irq(dev
, entry
->irq
);
252 void __read_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
254 BUG_ON(entry
->dev
->current_state
!= PCI_D0
);
256 if (entry
->msi_attrib
.is_msix
) {
257 void __iomem
*base
= entry
->mask_base
+
258 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
260 msg
->address_lo
= readl(base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
261 msg
->address_hi
= readl(base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
262 msg
->data
= readl(base
+ PCI_MSIX_ENTRY_DATA
);
264 struct pci_dev
*dev
= entry
->dev
;
265 int pos
= dev
->msi_cap
;
268 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
270 if (entry
->msi_attrib
.is_64
) {
271 pci_read_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
273 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_64
, &data
);
276 pci_read_config_word(dev
, pos
+ PCI_MSI_DATA_32
, &data
);
282 void read_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
284 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
286 __read_msi_msg(entry
, msg
);
289 void __get_cached_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
291 /* Assert that the cache is valid, assuming that
292 * valid messages are not all-zeroes. */
293 BUG_ON(!(entry
->msg
.address_hi
| entry
->msg
.address_lo
|
299 void get_cached_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
301 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
303 __get_cached_msi_msg(entry
, msg
);
305 EXPORT_SYMBOL_GPL(get_cached_msi_msg
);
307 void __write_msi_msg(struct msi_desc
*entry
, struct msi_msg
*msg
)
309 if (entry
->dev
->current_state
!= PCI_D0
) {
310 /* Don't touch the hardware now */
311 } else if (entry
->msi_attrib
.is_msix
) {
313 base
= entry
->mask_base
+
314 entry
->msi_attrib
.entry_nr
* PCI_MSIX_ENTRY_SIZE
;
316 writel(msg
->address_lo
, base
+ PCI_MSIX_ENTRY_LOWER_ADDR
);
317 writel(msg
->address_hi
, base
+ PCI_MSIX_ENTRY_UPPER_ADDR
);
318 writel(msg
->data
, base
+ PCI_MSIX_ENTRY_DATA
);
320 struct pci_dev
*dev
= entry
->dev
;
321 int pos
= dev
->msi_cap
;
324 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &msgctl
);
325 msgctl
&= ~PCI_MSI_FLAGS_QSIZE
;
326 msgctl
|= entry
->msi_attrib
.multiple
<< 4;
327 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, msgctl
);
329 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_LO
,
331 if (entry
->msi_attrib
.is_64
) {
332 pci_write_config_dword(dev
, pos
+ PCI_MSI_ADDRESS_HI
,
334 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_64
,
337 pci_write_config_word(dev
, pos
+ PCI_MSI_DATA_32
,
344 void write_msi_msg(unsigned int irq
, struct msi_msg
*msg
)
346 struct msi_desc
*entry
= irq_get_msi_desc(irq
);
348 __write_msi_msg(entry
, msg
);
350 EXPORT_SYMBOL_GPL(write_msi_msg
);
352 static void free_msi_irqs(struct pci_dev
*dev
)
354 struct msi_desc
*entry
, *tmp
;
355 struct attribute
**msi_attrs
;
356 struct device_attribute
*dev_attr
;
359 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
363 if (entry
->nvec_used
)
364 nvec
= entry
->nvec_used
;
366 nvec
= 1 << entry
->msi_attrib
.multiple
;
367 for (i
= 0; i
< nvec
; i
++)
368 BUG_ON(irq_has_action(entry
->irq
+ i
));
371 arch_teardown_msi_irqs(dev
);
373 list_for_each_entry_safe(entry
, tmp
, &dev
->msi_list
, list
) {
374 if (entry
->msi_attrib
.is_msix
) {
375 if (list_is_last(&entry
->list
, &dev
->msi_list
))
376 iounmap(entry
->mask_base
);
379 list_del(&entry
->list
);
383 if (dev
->msi_irq_groups
) {
384 sysfs_remove_groups(&dev
->dev
.kobj
, dev
->msi_irq_groups
);
385 msi_attrs
= dev
->msi_irq_groups
[0]->attrs
;
386 while (msi_attrs
[count
]) {
387 dev_attr
= container_of(msi_attrs
[count
],
388 struct device_attribute
, attr
);
389 kfree(dev_attr
->attr
.name
);
394 kfree(dev
->msi_irq_groups
[0]);
395 kfree(dev
->msi_irq_groups
);
396 dev
->msi_irq_groups
= NULL
;
400 static struct msi_desc
*alloc_msi_entry(struct pci_dev
*dev
)
402 struct msi_desc
*desc
= kzalloc(sizeof(*desc
), GFP_KERNEL
);
406 INIT_LIST_HEAD(&desc
->list
);
412 static void pci_intx_for_msi(struct pci_dev
*dev
, int enable
)
414 if (!(dev
->dev_flags
& PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG
))
415 pci_intx(dev
, enable
);
418 static void __pci_restore_msi_state(struct pci_dev
*dev
)
421 struct msi_desc
*entry
;
423 if (!dev
->msi_enabled
)
426 entry
= irq_get_msi_desc(dev
->irq
);
428 pci_intx_for_msi(dev
, 0);
429 msi_set_enable(dev
, 0);
430 arch_restore_msi_irqs(dev
);
432 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
433 msi_mask_irq(entry
, msi_mask(entry
->msi_attrib
.multi_cap
),
435 control
&= ~PCI_MSI_FLAGS_QSIZE
;
436 control
|= (entry
->msi_attrib
.multiple
<< 4) | PCI_MSI_FLAGS_ENABLE
;
437 pci_write_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, control
);
440 static void __pci_restore_msix_state(struct pci_dev
*dev
)
442 struct msi_desc
*entry
;
444 if (!dev
->msix_enabled
)
446 BUG_ON(list_empty(&dev
->msi_list
));
448 /* route the table */
449 pci_intx_for_msi(dev
, 0);
450 msix_clear_and_set_ctrl(dev
, 0,
451 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
453 arch_restore_msi_irqs(dev
);
454 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
455 msix_mask_irq(entry
, entry
->masked
);
458 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
461 void pci_restore_msi_state(struct pci_dev
*dev
)
463 __pci_restore_msi_state(dev
);
464 __pci_restore_msix_state(dev
);
466 EXPORT_SYMBOL_GPL(pci_restore_msi_state
);
468 static ssize_t
msi_mode_show(struct device
*dev
, struct device_attribute
*attr
,
471 struct msi_desc
*entry
;
475 retval
= kstrtoul(attr
->attr
.name
, 10, &irq
);
479 entry
= irq_get_msi_desc(irq
);
481 return sprintf(buf
, "%s\n",
482 entry
->msi_attrib
.is_msix
? "msix" : "msi");
487 static int populate_msi_sysfs(struct pci_dev
*pdev
)
489 struct attribute
**msi_attrs
;
490 struct attribute
*msi_attr
;
491 struct device_attribute
*msi_dev_attr
;
492 struct attribute_group
*msi_irq_group
;
493 const struct attribute_group
**msi_irq_groups
;
494 struct msi_desc
*entry
;
499 /* Determine how many msi entries we have */
500 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
506 /* Dynamically create the MSI attributes for the PCI device */
507 msi_attrs
= kzalloc(sizeof(void *) * (num_msi
+ 1), GFP_KERNEL
);
510 list_for_each_entry(entry
, &pdev
->msi_list
, list
) {
511 msi_dev_attr
= kzalloc(sizeof(*msi_dev_attr
), GFP_KERNEL
);
514 msi_attrs
[count
] = &msi_dev_attr
->attr
;
516 sysfs_attr_init(&msi_dev_attr
->attr
);
517 msi_dev_attr
->attr
.name
= kasprintf(GFP_KERNEL
, "%d",
519 if (!msi_dev_attr
->attr
.name
)
521 msi_dev_attr
->attr
.mode
= S_IRUGO
;
522 msi_dev_attr
->show
= msi_mode_show
;
526 msi_irq_group
= kzalloc(sizeof(*msi_irq_group
), GFP_KERNEL
);
529 msi_irq_group
->name
= "msi_irqs";
530 msi_irq_group
->attrs
= msi_attrs
;
532 msi_irq_groups
= kzalloc(sizeof(void *) * 2, GFP_KERNEL
);
534 goto error_irq_group
;
535 msi_irq_groups
[0] = msi_irq_group
;
537 ret
= sysfs_create_groups(&pdev
->dev
.kobj
, msi_irq_groups
);
539 goto error_irq_groups
;
540 pdev
->msi_irq_groups
= msi_irq_groups
;
545 kfree(msi_irq_groups
);
547 kfree(msi_irq_group
);
550 msi_attr
= msi_attrs
[count
];
552 msi_dev_attr
= container_of(msi_attr
, struct device_attribute
, attr
);
553 kfree(msi_attr
->name
);
556 msi_attr
= msi_attrs
[count
];
562 static struct msi_desc
*msi_setup_entry(struct pci_dev
*dev
)
565 struct msi_desc
*entry
;
567 /* MSI Entry Initialization */
568 entry
= alloc_msi_entry(dev
);
572 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &control
);
574 entry
->msi_attrib
.is_msix
= 0;
575 entry
->msi_attrib
.is_64
= !!(control
& PCI_MSI_FLAGS_64BIT
);
576 entry
->msi_attrib
.entry_nr
= 0;
577 entry
->msi_attrib
.maskbit
= !!(control
& PCI_MSI_FLAGS_MASKBIT
);
578 entry
->msi_attrib
.default_irq
= dev
->irq
; /* Save IOAPIC IRQ */
579 entry
->msi_attrib
.multi_cap
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
581 if (control
& PCI_MSI_FLAGS_64BIT
)
582 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_64
;
584 entry
->mask_pos
= dev
->msi_cap
+ PCI_MSI_MASK_32
;
586 /* Save the initial mask status */
587 if (entry
->msi_attrib
.maskbit
)
588 pci_read_config_dword(dev
, entry
->mask_pos
, &entry
->masked
);
593 static int msi_verify_entries(struct pci_dev
*dev
)
595 struct msi_desc
*entry
;
597 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
598 if (!dev
->no_64bit_msi
|| !entry
->msg
.address_hi
)
600 dev_err(&dev
->dev
, "Device has broken 64-bit MSI but arch"
601 " tried to assign one above 4G\n");
608 * msi_capability_init - configure device's MSI capability structure
609 * @dev: pointer to the pci_dev data structure of MSI device function
610 * @nvec: number of interrupts to allocate
612 * Setup the MSI capability structure of the device with the requested
613 * number of interrupts. A return value of zero indicates the successful
614 * setup of an entry with the new MSI irq. A negative return value indicates
615 * an error, and a positive return value indicates the number of interrupts
616 * which could have been allocated.
618 static int msi_capability_init(struct pci_dev
*dev
, int nvec
)
620 struct msi_desc
*entry
;
624 msi_set_enable(dev
, 0); /* Disable MSI during set up */
626 entry
= msi_setup_entry(dev
);
630 /* All MSIs are unmasked by default, Mask them all */
631 mask
= msi_mask(entry
->msi_attrib
.multi_cap
);
632 msi_mask_irq(entry
, mask
, mask
);
634 list_add_tail(&entry
->list
, &dev
->msi_list
);
636 /* Configure MSI capability structure */
637 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSI
);
639 msi_mask_irq(entry
, mask
, ~mask
);
644 ret
= msi_verify_entries(dev
);
646 msi_mask_irq(entry
, mask
, ~mask
);
651 ret
= populate_msi_sysfs(dev
);
653 msi_mask_irq(entry
, mask
, ~mask
);
658 /* Set MSI enabled bits */
659 pci_intx_for_msi(dev
, 0);
660 msi_set_enable(dev
, 1);
661 dev
->msi_enabled
= 1;
663 dev
->irq
= entry
->irq
;
667 static void __iomem
*msix_map_region(struct pci_dev
*dev
, unsigned nr_entries
)
669 resource_size_t phys_addr
;
673 pci_read_config_dword(dev
, dev
->msix_cap
+ PCI_MSIX_TABLE
,
675 bir
= (u8
)(table_offset
& PCI_MSIX_TABLE_BIR
);
676 table_offset
&= PCI_MSIX_TABLE_OFFSET
;
677 phys_addr
= pci_resource_start(dev
, bir
) + table_offset
;
679 return ioremap_nocache(phys_addr
, nr_entries
* PCI_MSIX_ENTRY_SIZE
);
682 static int msix_setup_entries(struct pci_dev
*dev
, void __iomem
*base
,
683 struct msix_entry
*entries
, int nvec
)
685 struct msi_desc
*entry
;
688 for (i
= 0; i
< nvec
; i
++) {
689 entry
= alloc_msi_entry(dev
);
695 /* No enough memory. Don't try again */
699 entry
->msi_attrib
.is_msix
= 1;
700 entry
->msi_attrib
.is_64
= 1;
701 entry
->msi_attrib
.entry_nr
= entries
[i
].entry
;
702 entry
->msi_attrib
.default_irq
= dev
->irq
;
703 entry
->mask_base
= base
;
705 list_add_tail(&entry
->list
, &dev
->msi_list
);
711 static void msix_program_entries(struct pci_dev
*dev
,
712 struct msix_entry
*entries
)
714 struct msi_desc
*entry
;
717 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
718 int offset
= entries
[i
].entry
* PCI_MSIX_ENTRY_SIZE
+
719 PCI_MSIX_ENTRY_VECTOR_CTRL
;
721 entries
[i
].vector
= entry
->irq
;
722 irq_set_msi_desc(entry
->irq
, entry
);
723 entry
->masked
= readl(entry
->mask_base
+ offset
);
724 msix_mask_irq(entry
, 1);
730 * msix_capability_init - configure device's MSI-X capability
731 * @dev: pointer to the pci_dev data structure of MSI-X device function
732 * @entries: pointer to an array of struct msix_entry entries
733 * @nvec: number of @entries
735 * Setup the MSI-X capability structure of device function with a
736 * single MSI-X irq. A return of zero indicates the successful setup of
737 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
739 static int msix_capability_init(struct pci_dev
*dev
,
740 struct msix_entry
*entries
, int nvec
)
746 /* Ensure MSI-X is disabled while it is set up */
747 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
749 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
750 /* Request & Map MSI-X table region */
751 base
= msix_map_region(dev
, msix_table_size(control
));
755 ret
= msix_setup_entries(dev
, base
, entries
, nvec
);
759 ret
= arch_setup_msi_irqs(dev
, nvec
, PCI_CAP_ID_MSIX
);
763 /* Check if all MSI entries honor device restrictions */
764 ret
= msi_verify_entries(dev
);
769 * Some devices require MSI-X to be enabled before we can touch the
770 * MSI-X registers. We need to mask all the vectors to prevent
771 * interrupts coming in before they're fully set up.
773 msix_clear_and_set_ctrl(dev
, 0,
774 PCI_MSIX_FLAGS_MASKALL
| PCI_MSIX_FLAGS_ENABLE
);
776 msix_program_entries(dev
, entries
);
778 ret
= populate_msi_sysfs(dev
);
782 /* Set MSI-X enabled bits and unmask the function */
783 pci_intx_for_msi(dev
, 0);
784 dev
->msix_enabled
= 1;
786 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_MASKALL
, 0);
793 * If we had some success, report the number of irqs
794 * we succeeded in setting up.
796 struct msi_desc
*entry
;
799 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
814 * pci_msi_supported - check whether MSI may be enabled on a device
815 * @dev: pointer to the pci_dev data structure of MSI device function
816 * @nvec: how many MSIs have been requested ?
818 * Look at global flags, the device itself, and its parent buses
819 * to determine if MSI/-X are supported for the device. If MSI/-X is
820 * supported return 1, else return 0.
822 static int pci_msi_supported(struct pci_dev
*dev
, int nvec
)
826 /* MSI must be globally enabled and supported by the device */
830 if (!dev
|| dev
->no_msi
|| dev
->current_state
!= PCI_D0
)
834 * You can't ask to have 0 or less MSIs configured.
836 * b) the list manipulation code assumes nvec >= 1.
842 * Any bridge which does NOT route MSI transactions from its
843 * secondary bus to its primary bus must set NO_MSI flag on
844 * the secondary pci_bus.
845 * We expect only arch-specific PCI host bus controller driver
846 * or quirks for specific PCI bridges to be setting NO_MSI.
848 for (bus
= dev
->bus
; bus
; bus
= bus
->parent
)
849 if (bus
->bus_flags
& PCI_BUS_FLAGS_NO_MSI
)
856 * pci_msi_vec_count - Return the number of MSI vectors a device can send
857 * @dev: device to report about
859 * This function returns the number of MSI vectors a device requested via
860 * Multiple Message Capable register. It returns a negative errno if the
861 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
862 * and returns a power of two, up to a maximum of 2^5 (32), according to the
865 int pci_msi_vec_count(struct pci_dev
*dev
)
873 pci_read_config_word(dev
, dev
->msi_cap
+ PCI_MSI_FLAGS
, &msgctl
);
874 ret
= 1 << ((msgctl
& PCI_MSI_FLAGS_QMASK
) >> 1);
878 EXPORT_SYMBOL(pci_msi_vec_count
);
880 void pci_msi_shutdown(struct pci_dev
*dev
)
882 struct msi_desc
*desc
;
885 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
888 BUG_ON(list_empty(&dev
->msi_list
));
889 desc
= list_first_entry(&dev
->msi_list
, struct msi_desc
, list
);
891 msi_set_enable(dev
, 0);
892 pci_intx_for_msi(dev
, 1);
893 dev
->msi_enabled
= 0;
895 /* Return the device with MSI unmasked as initial states */
896 mask
= msi_mask(desc
->msi_attrib
.multi_cap
);
897 /* Keep cached state to be restored */
898 arch_msi_mask_irq(desc
, mask
, ~mask
);
900 /* Restore dev->irq to its default pin-assertion irq */
901 dev
->irq
= desc
->msi_attrib
.default_irq
;
904 void pci_disable_msi(struct pci_dev
*dev
)
906 if (!pci_msi_enable
|| !dev
|| !dev
->msi_enabled
)
909 pci_msi_shutdown(dev
);
912 EXPORT_SYMBOL(pci_disable_msi
);
915 * pci_msix_vec_count - return the number of device's MSI-X table entries
916 * @dev: pointer to the pci_dev data structure of MSI-X device function
917 * This function returns the number of device's MSI-X table entries and
918 * therefore the number of MSI-X vectors device is capable of sending.
919 * It returns a negative errno if the device is not capable of sending MSI-X
922 int pci_msix_vec_count(struct pci_dev
*dev
)
929 pci_read_config_word(dev
, dev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
930 return msix_table_size(control
);
932 EXPORT_SYMBOL(pci_msix_vec_count
);
935 * pci_enable_msix - configure device's MSI-X capability structure
936 * @dev: pointer to the pci_dev data structure of MSI-X device function
937 * @entries: pointer to an array of MSI-X entries
938 * @nvec: number of MSI-X irqs requested for allocation by device driver
940 * Setup the MSI-X capability structure of device function with the number
941 * of requested irqs upon its software driver call to request for
942 * MSI-X mode enabled on its hardware device function. A return of zero
943 * indicates the successful configuration of MSI-X capability structure
944 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
945 * Or a return of > 0 indicates that driver request is exceeding the number
946 * of irqs or MSI-X vectors available. Driver should use the returned value to
947 * re-send its request.
949 int pci_enable_msix(struct pci_dev
*dev
, struct msix_entry
*entries
, int nvec
)
954 if (!pci_msi_supported(dev
, nvec
))
960 nr_entries
= pci_msix_vec_count(dev
);
963 if (nvec
> nr_entries
)
966 /* Check for any invalid entries */
967 for (i
= 0; i
< nvec
; i
++) {
968 if (entries
[i
].entry
>= nr_entries
)
969 return -EINVAL
; /* invalid entry */
970 for (j
= i
+ 1; j
< nvec
; j
++) {
971 if (entries
[i
].entry
== entries
[j
].entry
)
972 return -EINVAL
; /* duplicate entry */
975 WARN_ON(!!dev
->msix_enabled
);
977 /* Check whether driver already requested for MSI irq */
978 if (dev
->msi_enabled
) {
979 dev_info(&dev
->dev
, "can't enable MSI-X (MSI IRQ already assigned)\n");
982 return msix_capability_init(dev
, entries
, nvec
);
984 EXPORT_SYMBOL(pci_enable_msix
);
986 void pci_msix_shutdown(struct pci_dev
*dev
)
988 struct msi_desc
*entry
;
990 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
993 /* Return the device with MSI-X masked as initial states */
994 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
995 /* Keep cached states to be restored */
996 arch_msix_mask_irq(entry
, 1);
999 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1000 pci_intx_for_msi(dev
, 1);
1001 dev
->msix_enabled
= 0;
1004 void pci_disable_msix(struct pci_dev
*dev
)
1006 if (!pci_msi_enable
|| !dev
|| !dev
->msix_enabled
)
1009 pci_msix_shutdown(dev
);
1012 EXPORT_SYMBOL(pci_disable_msix
);
1014 void pci_no_msi(void)
1020 * pci_msi_enabled - is MSI enabled?
1022 * Returns true if MSI has not been disabled by the command-line option
1025 int pci_msi_enabled(void)
1027 return pci_msi_enable
;
1029 EXPORT_SYMBOL(pci_msi_enabled
);
1031 void pci_msi_init_pci_dev(struct pci_dev
*dev
)
1033 INIT_LIST_HEAD(&dev
->msi_list
);
1035 /* Disable the msi hardware to avoid screaming interrupts
1036 * during boot. This is the power on reset default so
1037 * usually this should be a noop.
1039 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1041 msi_set_enable(dev
, 0);
1043 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1045 msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1049 * pci_enable_msi_range - configure device's MSI capability structure
1050 * @dev: device to configure
1051 * @minvec: minimal number of interrupts to configure
1052 * @maxvec: maximum number of interrupts to configure
1054 * This function tries to allocate a maximum possible number of interrupts in a
1055 * range between @minvec and @maxvec. It returns a negative errno if an error
1056 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1057 * and updates the @dev's irq member to the lowest new interrupt number;
1058 * the other interrupt numbers allocated to this device are consecutive.
1060 int pci_enable_msi_range(struct pci_dev
*dev
, int minvec
, int maxvec
)
1065 if (!pci_msi_supported(dev
, minvec
))
1068 WARN_ON(!!dev
->msi_enabled
);
1070 /* Check whether driver already requested MSI-X irqs */
1071 if (dev
->msix_enabled
) {
1073 "can't enable MSI (MSI-X already enabled)\n");
1077 if (maxvec
< minvec
)
1080 nvec
= pci_msi_vec_count(dev
);
1083 else if (nvec
< minvec
)
1085 else if (nvec
> maxvec
)
1089 rc
= msi_capability_init(dev
, nvec
);
1092 } else if (rc
> 0) {
1101 EXPORT_SYMBOL(pci_enable_msi_range
);
1104 * pci_enable_msix_range - configure device's MSI-X capability structure
1105 * @dev: pointer to the pci_dev data structure of MSI-X device function
1106 * @entries: pointer to an array of MSI-X entries
1107 * @minvec: minimum number of MSI-X irqs requested
1108 * @maxvec: maximum number of MSI-X irqs requested
1110 * Setup the MSI-X capability structure of device function with a maximum
1111 * possible number of interrupts in the range between @minvec and @maxvec
1112 * upon its software driver call to request for MSI-X mode enabled on its
1113 * hardware device function. It returns a negative errno if an error occurs.
1114 * If it succeeds, it returns the actual number of interrupts allocated and
1115 * indicates the successful configuration of MSI-X capability structure
1116 * with new allocated MSI-X interrupts.
1118 int pci_enable_msix_range(struct pci_dev
*dev
, struct msix_entry
*entries
,
1119 int minvec
, int maxvec
)
1124 if (maxvec
< minvec
)
1128 rc
= pci_enable_msix(dev
, entries
, nvec
);
1131 } else if (rc
> 0) {
1140 EXPORT_SYMBOL(pci_enable_msix_range
);