1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
36 DEFINE_MUTEX(pci_slot_mutex
);
38 const char *pci_power_names
[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names
);
43 int isa_dma_bridge_buggy
;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
47 EXPORT_SYMBOL(pci_pci_problems
);
49 unsigned int pci_pm_d3hot_delay
;
51 static void pci_pme_list_scan(struct work_struct
*work
);
53 static LIST_HEAD(pci_pme_list
);
54 static DEFINE_MUTEX(pci_pme_list_mutex
);
55 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
57 struct pci_pme_device
{
58 struct list_head list
;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
66 unsigned int delay
= dev
->d3hot_delay
;
68 if (delay
< pci_pm_d3hot_delay
)
69 delay
= pci_pm_d3hot_delay
;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported
= 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
83 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
87 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
88 /* hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
91 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
92 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
93 * pci=hpmemsize=nnM overrides both
95 unsigned long pci_hotplug_mmio_size
= DEFAULT_HOTPLUG_MMIO_SIZE
;
96 unsigned long pci_hotplug_mmio_pref_size
= DEFAULT_HOTPLUG_MMIO_PREF_SIZE
;
98 #define DEFAULT_HOTPLUG_BUS_SIZE 1
99 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
102 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
103 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
104 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
105 #elif defined CONFIG_PCIE_BUS_SAFE
106 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_SAFE
;
107 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
108 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
109 #elif defined CONFIG_PCIE_BUS_PEER2PEER
110 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PEER2PEER
;
112 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
116 * The default CLS is used if arch didn't set CLS explicitly and not
117 * all pci devices agree on the same value. Arch can override either
118 * the dfl or actual value as it sees fit. Don't forget this is
119 * measured in 32-bit words, not bytes.
121 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
122 u8 pci_cache_line_size
;
125 * If we set up a device for bus mastering, we need to check the latency
126 * timer as certain BIOSes forget to set it properly.
128 unsigned int pcibios_max_latency
= 255;
130 /* If set, the PCIe ARI capability will not be used. */
131 static bool pcie_ari_disabled
;
133 /* If set, the PCIe ATS capability will not be used. */
134 static bool pcie_ats_disabled
;
136 /* If set, the PCI config space of each device is printed during boot. */
139 bool pci_ats_disabled(void)
141 return pcie_ats_disabled
;
143 EXPORT_SYMBOL_GPL(pci_ats_disabled
);
145 /* Disable bridge_d3 for all PCIe ports */
146 static bool pci_bridge_d3_disable
;
147 /* Force bridge_d3 for all PCIe ports */
148 static bool pci_bridge_d3_force
;
150 static int __init
pcie_port_pm_setup(char *str
)
152 if (!strcmp(str
, "off"))
153 pci_bridge_d3_disable
= true;
154 else if (!strcmp(str
, "force"))
155 pci_bridge_d3_force
= true;
158 __setup("pcie_port_pm=", pcie_port_pm_setup
);
160 /* Time to wait after a reset for device to become responsive */
161 #define PCIE_RESET_READY_POLL_MS 60000
164 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
165 * @bus: pointer to PCI bus structure to search
167 * Given a PCI bus, returns the highest PCI bus number present in the set
168 * including the given PCI bus and its list of child PCI buses.
170 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
173 unsigned char max
, n
;
175 max
= bus
->busn_res
.end
;
176 list_for_each_entry(tmp
, &bus
->children
, node
) {
177 n
= pci_bus_max_busnr(tmp
);
183 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
186 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
187 * @pdev: the PCI device
189 * Returns error bits set in PCI_STATUS and clears them.
191 int pci_status_get_and_clear_errors(struct pci_dev
*pdev
)
196 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
197 if (ret
!= PCIBIOS_SUCCESSFUL
)
200 status
&= PCI_STATUS_ERROR_BITS
;
202 pci_write_config_word(pdev
, PCI_STATUS
, status
);
206 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors
);
208 #ifdef CONFIG_HAS_IOMEM
209 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
211 struct resource
*res
= &pdev
->resource
[bar
];
214 * Make sure the BAR is actually a memory resource, not an IO resource
216 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
217 pci_warn(pdev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
220 return ioremap(res
->start
, resource_size(res
));
222 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
224 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
227 * Make sure the BAR is actually a memory resource, not an IO resource
229 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
233 return ioremap_wc(pci_resource_start(pdev
, bar
),
234 pci_resource_len(pdev
, bar
));
236 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
240 * pci_dev_str_match_path - test if a path string matches a device
241 * @dev: the PCI device to test
242 * @path: string to match the device against
243 * @endptr: pointer to the string after the match
245 * Test if a string (typically from a kernel parameter) formatted as a
246 * path of device/function addresses matches a PCI device. The string must
249 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
251 * A path for a device can be obtained using 'lspci -t'. Using a path
252 * is more robust against bus renumbering than using only a single bus,
253 * device and function address.
255 * Returns 1 if the string matches the device, 0 if it does not and
256 * a negative error code if it fails to parse the string.
258 static int pci_dev_str_match_path(struct pci_dev
*dev
, const char *path
,
262 int seg
, bus
, slot
, func
;
266 *endptr
= strchrnul(path
, ';');
268 wpath
= kmemdup_nul(path
, *endptr
- path
, GFP_KERNEL
);
273 p
= strrchr(wpath
, '/');
276 ret
= sscanf(p
, "/%x.%x%c", &slot
, &func
, &end
);
282 if (dev
->devfn
!= PCI_DEVFN(slot
, func
)) {
288 * Note: we don't need to get a reference to the upstream
289 * bridge because we hold a reference to the top level
290 * device which should hold a reference to the bridge,
293 dev
= pci_upstream_bridge(dev
);
302 ret
= sscanf(wpath
, "%x:%x:%x.%x%c", &seg
, &bus
, &slot
,
306 ret
= sscanf(wpath
, "%x:%x.%x%c", &bus
, &slot
, &func
, &end
);
313 ret
= (seg
== pci_domain_nr(dev
->bus
) &&
314 bus
== dev
->bus
->number
&&
315 dev
->devfn
== PCI_DEVFN(slot
, func
));
323 * pci_dev_str_match - test if a string matches a device
324 * @dev: the PCI device to test
325 * @p: string to match the device against
326 * @endptr: pointer to the string after the match
328 * Test if a string (typically from a kernel parameter) matches a specified
329 * PCI device. The string may be of one of the following formats:
331 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
332 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
334 * The first format specifies a PCI bus/device/function address which
335 * may change if new hardware is inserted, if motherboard firmware changes,
336 * or due to changes caused in kernel parameters. If the domain is
337 * left unspecified, it is taken to be 0. In order to be robust against
338 * bus renumbering issues, a path of PCI device/function numbers may be used
339 * to address the specific device. The path for a device can be determined
340 * through the use of 'lspci -t'.
342 * The second format matches devices using IDs in the configuration
343 * space which may match multiple devices in the system. A value of 0
344 * for any field will match all devices. (Note: this differs from
345 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
346 * legacy reasons and convenience so users don't have to specify
347 * FFFFFFFFs on the command line.)
349 * Returns 1 if the string matches the device, 0 if it does not and
350 * a negative error code if the string cannot be parsed.
352 static int pci_dev_str_match(struct pci_dev
*dev
, const char *p
,
357 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
359 if (strncmp(p
, "pci:", 4) == 0) {
360 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
362 ret
= sscanf(p
, "%hx:%hx:%hx:%hx%n", &vendor
, &device
,
363 &subsystem_vendor
, &subsystem_device
, &count
);
365 ret
= sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
);
369 subsystem_vendor
= 0;
370 subsystem_device
= 0;
375 if ((!vendor
|| vendor
== dev
->vendor
) &&
376 (!device
|| device
== dev
->device
) &&
377 (!subsystem_vendor
||
378 subsystem_vendor
== dev
->subsystem_vendor
) &&
379 (!subsystem_device
||
380 subsystem_device
== dev
->subsystem_device
))
384 * PCI Bus, Device, Function IDs are specified
385 * (optionally, may include a path of devfns following it)
387 ret
= pci_dev_str_match_path(dev
, p
, &p
);
402 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
403 u8 pos
, int cap
, int *ttl
)
408 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
414 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
426 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
429 int ttl
= PCI_FIND_CAP_TTL
;
431 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
434 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
436 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
437 pos
+ PCI_CAP_LIST_NEXT
, cap
);
439 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
441 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
442 unsigned int devfn
, u8 hdr_type
)
446 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
447 if (!(status
& PCI_STATUS_CAP_LIST
))
451 case PCI_HEADER_TYPE_NORMAL
:
452 case PCI_HEADER_TYPE_BRIDGE
:
453 return PCI_CAPABILITY_LIST
;
454 case PCI_HEADER_TYPE_CARDBUS
:
455 return PCI_CB_CAPABILITY_LIST
;
462 * pci_find_capability - query for devices' capabilities
463 * @dev: PCI device to query
464 * @cap: capability code
466 * Tell if a device supports a given PCI capability.
467 * Returns the address of the requested capability structure within the
468 * device's PCI configuration space or 0 in case the device does not
469 * support it. Possible values for @cap include:
471 * %PCI_CAP_ID_PM Power Management
472 * %PCI_CAP_ID_AGP Accelerated Graphics Port
473 * %PCI_CAP_ID_VPD Vital Product Data
474 * %PCI_CAP_ID_SLOTID Slot Identification
475 * %PCI_CAP_ID_MSI Message Signalled Interrupts
476 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
477 * %PCI_CAP_ID_PCIX PCI-X
478 * %PCI_CAP_ID_EXP PCI Express
480 int pci_find_capability(struct pci_dev
*dev
, int cap
)
484 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
486 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
490 EXPORT_SYMBOL(pci_find_capability
);
493 * pci_bus_find_capability - query for devices' capabilities
494 * @bus: the PCI bus to query
495 * @devfn: PCI device to query
496 * @cap: capability code
498 * Like pci_find_capability() but works for PCI devices that do not have a
499 * pci_dev structure set up yet.
501 * Returns the address of the requested capability structure within the
502 * device's PCI configuration space or 0 in case the device does not
505 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
510 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
512 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
514 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
518 EXPORT_SYMBOL(pci_bus_find_capability
);
521 * pci_find_next_ext_capability - Find an extended capability
522 * @dev: PCI device to query
523 * @start: address at which to start looking (0 to start at beginning of list)
524 * @cap: capability code
526 * Returns the address of the next matching extended capability structure
527 * within the device's PCI configuration space or 0 if the device does
528 * not support it. Some capabilities can occur several times, e.g., the
529 * vendor-specific capability, and this provides a way to find them all.
531 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
535 int pos
= PCI_CFG_SPACE_SIZE
;
537 /* minimum 8 bytes per capability */
538 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
540 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
546 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
550 * If we have no capabilities, this is indicated by cap ID,
551 * cap version and next pointer all being 0.
557 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
560 pos
= PCI_EXT_CAP_NEXT(header
);
561 if (pos
< PCI_CFG_SPACE_SIZE
)
564 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
570 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
573 * pci_find_ext_capability - Find an extended capability
574 * @dev: PCI device to query
575 * @cap: capability code
577 * Returns the address of the requested extended capability structure
578 * within the device's PCI configuration space or 0 if the device does
579 * not support it. Possible values for @cap include:
581 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
582 * %PCI_EXT_CAP_ID_VC Virtual Channel
583 * %PCI_EXT_CAP_ID_DSN Device Serial Number
584 * %PCI_EXT_CAP_ID_PWR Power Budgeting
586 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
588 return pci_find_next_ext_capability(dev
, 0, cap
);
590 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
593 * pci_get_dsn - Read and return the 8-byte Device Serial Number
594 * @dev: PCI device to query
596 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
599 * Returns the DSN, or zero if the capability does not exist.
601 u64
pci_get_dsn(struct pci_dev
*dev
)
607 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_DSN
);
612 * The Device Serial Number is two dwords offset 4 bytes from the
613 * capability position. The specification says that the first dword is
614 * the lower half, and the second dword is the upper half.
617 pci_read_config_dword(dev
, pos
, &dword
);
619 pci_read_config_dword(dev
, pos
+ 4, &dword
);
620 dsn
|= ((u64
)dword
) << 32;
624 EXPORT_SYMBOL_GPL(pci_get_dsn
);
626 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
628 int rc
, ttl
= PCI_FIND_CAP_TTL
;
631 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
632 mask
= HT_3BIT_CAP_MASK
;
634 mask
= HT_5BIT_CAP_MASK
;
636 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
637 PCI_CAP_ID_HT
, &ttl
);
639 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
640 if (rc
!= PCIBIOS_SUCCESSFUL
)
643 if ((cap
& mask
) == ht_cap
)
646 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
647 pos
+ PCI_CAP_LIST_NEXT
,
648 PCI_CAP_ID_HT
, &ttl
);
654 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
655 * @dev: PCI device to query
656 * @pos: Position from which to continue searching
657 * @ht_cap: Hypertransport capability code
659 * To be used in conjunction with pci_find_ht_capability() to search for
660 * all capabilities matching @ht_cap. @pos should always be a value returned
661 * from pci_find_ht_capability().
663 * NB. To be 100% safe against broken PCI devices, the caller should take
664 * steps to avoid an infinite loop.
666 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
668 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
670 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
673 * pci_find_ht_capability - query a device's Hypertransport capabilities
674 * @dev: PCI device to query
675 * @ht_cap: Hypertransport capability code
677 * Tell if a device supports a given Hypertransport capability.
678 * Returns an address within the device's PCI configuration space
679 * or 0 in case the device does not support the request capability.
680 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
681 * which has a Hypertransport capability matching @ht_cap.
683 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
687 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
689 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
693 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
696 * pci_find_parent_resource - return resource region of parent bus of given
698 * @dev: PCI device structure contains resources to be searched
699 * @res: child resource record for which parent is sought
701 * For given resource region of given device, return the resource region of
702 * parent bus the given region is contained in.
704 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
705 struct resource
*res
)
707 const struct pci_bus
*bus
= dev
->bus
;
711 pci_bus_for_each_resource(bus
, r
, i
) {
714 if (resource_contains(r
, res
)) {
717 * If the window is prefetchable but the BAR is
718 * not, the allocator made a mistake.
720 if (r
->flags
& IORESOURCE_PREFETCH
&&
721 !(res
->flags
& IORESOURCE_PREFETCH
))
725 * If we're below a transparent bridge, there may
726 * be both a positively-decoded aperture and a
727 * subtractively-decoded region that contain the BAR.
728 * We want the positively-decoded one, so this depends
729 * on pci_bus_for_each_resource() giving us those
737 EXPORT_SYMBOL(pci_find_parent_resource
);
740 * pci_find_resource - Return matching PCI device resource
741 * @dev: PCI device to query
742 * @res: Resource to look for
744 * Goes over standard PCI resources (BARs) and checks if the given resource
745 * is partially or fully contained in any of them. In that case the
746 * matching resource is returned, %NULL otherwise.
748 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
752 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
753 struct resource
*r
= &dev
->resource
[i
];
755 if (r
->start
&& resource_contains(r
, res
))
761 EXPORT_SYMBOL(pci_find_resource
);
764 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
765 * @dev: the PCI device to operate on
766 * @pos: config space offset of status word
767 * @mask: mask of bit(s) to care about in status word
769 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
771 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
775 /* Wait for Transaction Pending bit clean */
776 for (i
= 0; i
< 4; i
++) {
779 msleep((1 << (i
- 1)) * 100);
781 pci_read_config_word(dev
, pos
, &status
);
782 if (!(status
& mask
))
789 static int pci_acs_enable
;
792 * pci_request_acs - ask for ACS to be enabled if supported
794 void pci_request_acs(void)
799 static const char *disable_acs_redir_param
;
802 * pci_disable_acs_redir - disable ACS redirect capabilities
803 * @dev: the PCI device
805 * For only devices specified in the disable_acs_redir parameter.
807 static void pci_disable_acs_redir(struct pci_dev
*dev
)
814 if (!disable_acs_redir_param
)
817 p
= disable_acs_redir_param
;
819 ret
= pci_dev_str_match(dev
, p
, &p
);
821 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
822 disable_acs_redir_param
);
825 } else if (ret
== 1) {
830 if (*p
!= ';' && *p
!= ',') {
831 /* End of param or invalid format */
840 if (!pci_dev_specific_disable_acs_redir(dev
))
845 pci_warn(dev
, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
849 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
851 /* P2P Request & Completion Redirect */
852 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
854 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
856 pci_info(dev
, "disabled ACS redirect\n");
860 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
861 * @dev: the PCI device
863 static void pci_std_enable_acs(struct pci_dev
*dev
)
873 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
874 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
876 /* Source Validation */
877 ctrl
|= (cap
& PCI_ACS_SV
);
879 /* P2P Request Redirect */
880 ctrl
|= (cap
& PCI_ACS_RR
);
882 /* P2P Completion Redirect */
883 ctrl
|= (cap
& PCI_ACS_CR
);
885 /* Upstream Forwarding */
886 ctrl
|= (cap
& PCI_ACS_UF
);
888 /* Enable Translation Blocking for external devices */
889 if (dev
->external_facing
|| dev
->untrusted
)
890 ctrl
|= (cap
& PCI_ACS_TB
);
892 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
896 * pci_enable_acs - enable ACS if hardware support it
897 * @dev: the PCI device
899 static void pci_enable_acs(struct pci_dev
*dev
)
902 goto disable_acs_redir
;
904 if (!pci_dev_specific_enable_acs(dev
))
905 goto disable_acs_redir
;
907 pci_std_enable_acs(dev
);
911 * Note: pci_disable_acs_redir() must be called even if ACS was not
912 * enabled by the kernel because it may have been enabled by
913 * platform firmware. So if we are told to disable it, we should
914 * always disable it after setting the kernel's default
917 pci_disable_acs_redir(dev
);
921 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
922 * @dev: PCI device to have its BARs restored
924 * Restore the BAR values for a given device, so as to make it
925 * accessible by its driver.
927 static void pci_restore_bars(struct pci_dev
*dev
)
931 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
932 pci_update_resource(dev
, i
);
935 static const struct pci_platform_pm_ops
*pci_platform_pm
;
937 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
939 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
940 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
942 pci_platform_pm
= ops
;
946 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
948 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
951 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
954 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
957 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
959 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
962 static inline void platform_pci_refresh_power_state(struct pci_dev
*dev
)
964 if (pci_platform_pm
&& pci_platform_pm
->refresh_state
)
965 pci_platform_pm
->refresh_state(dev
);
968 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
970 return pci_platform_pm
?
971 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
974 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
976 return pci_platform_pm
?
977 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
980 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
982 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
985 static inline bool platform_pci_bridge_d3(struct pci_dev
*dev
)
987 if (pci_platform_pm
&& pci_platform_pm
->bridge_d3
)
988 return pci_platform_pm
->bridge_d3(dev
);
993 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
995 * @dev: PCI device to handle.
996 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
999 * -EINVAL if the requested state is invalid.
1000 * -EIO if device does not support PCI PM or its PM capabilities register has a
1001 * wrong version, or device doesn't support the requested state.
1002 * 0 if device already is in the requested state.
1003 * 0 if device's power state has been successfully changed.
1005 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1008 bool need_restore
= false;
1010 /* Check if we're already there */
1011 if (dev
->current_state
== state
)
1017 if (state
< PCI_D0
|| state
> PCI_D3hot
)
1021 * Validate transition: We can enter D0 from any state, but if
1022 * we're already in a low-power state, we can only go deeper. E.g.,
1023 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1024 * we'd have to go from D3 to D0, then to D1.
1026 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
1027 && dev
->current_state
> state
) {
1028 pci_err(dev
, "invalid power transition (from %s to %s)\n",
1029 pci_power_name(dev
->current_state
),
1030 pci_power_name(state
));
1034 /* Check if this device supports the desired state */
1035 if ((state
== PCI_D1
&& !dev
->d1_support
)
1036 || (state
== PCI_D2
&& !dev
->d2_support
))
1039 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1040 if (pmcsr
== (u16
) ~0) {
1041 pci_err(dev
, "can't change power state from %s to %s (config space inaccessible)\n",
1042 pci_power_name(dev
->current_state
),
1043 pci_power_name(state
));
1048 * If we're (effectively) in D3, force entire word to 0.
1049 * This doesn't affect PME_Status, disables PME_En, and
1050 * sets PowerState to 0.
1052 switch (dev
->current_state
) {
1056 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
1061 case PCI_UNKNOWN
: /* Boot-up */
1062 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
1063 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
1064 need_restore
= true;
1065 /* Fall-through - force to D0 */
1071 /* Enter specified state */
1072 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1075 * Mandatory power management transition delays; see PCI PM 1.1
1078 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
1079 pci_dev_d3_sleep(dev
);
1080 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
1081 udelay(PCI_PM_D2_DELAY
);
1083 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1084 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1085 if (dev
->current_state
!= state
)
1086 pci_info_ratelimited(dev
, "refused to change power state from %s to %s\n",
1087 pci_power_name(dev
->current_state
),
1088 pci_power_name(state
));
1091 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1092 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1093 * from D3hot to D0 _may_ perform an internal reset, thereby
1094 * going to "D0 Uninitialized" rather than "D0 Initialized".
1095 * For example, at least some versions of the 3c905B and the
1096 * 3c556B exhibit this behaviour.
1098 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1099 * devices in a D3hot state at boot. Consequently, we need to
1100 * restore at least the BARs so that the device will be
1101 * accessible to its driver.
1104 pci_restore_bars(dev
);
1107 pcie_aspm_pm_state_change(dev
->bus
->self
);
1113 * pci_update_current_state - Read power state of given device and cache it
1114 * @dev: PCI device to handle.
1115 * @state: State to cache in case the device doesn't have the PM capability
1117 * The power state is read from the PMCSR register, which however is
1118 * inaccessible in D3cold. The platform firmware is therefore queried first
1119 * to detect accessibility of the register. In case the platform firmware
1120 * reports an incorrect state or the device isn't power manageable by the
1121 * platform at all, we try to detect D3cold by testing accessibility of the
1122 * vendor ID in config space.
1124 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
1126 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
1127 !pci_device_is_present(dev
)) {
1128 dev
->current_state
= PCI_D3cold
;
1129 } else if (dev
->pm_cap
) {
1132 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1133 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1135 dev
->current_state
= state
;
1140 * pci_refresh_power_state - Refresh the given device's power state data
1141 * @dev: Target PCI device.
1143 * Ask the platform to refresh the devices power state information and invoke
1144 * pci_update_current_state() to update its current PCI power state.
1146 void pci_refresh_power_state(struct pci_dev
*dev
)
1148 if (platform_pci_power_manageable(dev
))
1149 platform_pci_refresh_power_state(dev
);
1151 pci_update_current_state(dev
, dev
->current_state
);
1155 * pci_platform_power_transition - Use platform to change device power state
1156 * @dev: PCI device to handle.
1157 * @state: State to put the device into.
1159 int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
1163 if (platform_pci_power_manageable(dev
)) {
1164 error
= platform_pci_set_power_state(dev
, state
);
1166 pci_update_current_state(dev
, state
);
1170 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
1171 dev
->current_state
= PCI_D0
;
1175 EXPORT_SYMBOL_GPL(pci_platform_power_transition
);
1178 * pci_wakeup - Wake up a PCI device
1179 * @pci_dev: Device to handle.
1180 * @ign: ignored parameter
1182 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
1184 pci_wakeup_event(pci_dev
);
1185 pm_request_resume(&pci_dev
->dev
);
1190 * pci_wakeup_bus - Walk given bus and wake up devices on it
1191 * @bus: Top bus of the subtree to walk.
1193 void pci_wakeup_bus(struct pci_bus
*bus
)
1196 pci_walk_bus(bus
, pci_wakeup
, NULL
);
1199 static int pci_dev_wait(struct pci_dev
*dev
, char *reset_type
, int timeout
)
1205 * After reset, the device should not silently discard config
1206 * requests, but it may still indicate that it needs more time by
1207 * responding to them with CRS completions. The Root Port will
1208 * generally synthesize ~0 data to complete the read (except when
1209 * CRS SV is enabled and the read was for the Vendor ID; in that
1210 * case it synthesizes 0x0001 data).
1212 * Wait for the device to return a non-CRS completion. Read the
1213 * Command register instead of Vendor ID so we don't have to
1214 * contend with the CRS SV value.
1216 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1218 if (delay
> timeout
) {
1219 pci_warn(dev
, "not ready %dms after %s; giving up\n",
1220 delay
- 1, reset_type
);
1225 pci_info(dev
, "not ready %dms after %s; waiting\n",
1226 delay
- 1, reset_type
);
1230 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1234 pci_info(dev
, "ready %dms after %s\n", delay
- 1,
1241 * pci_power_up - Put the given device into D0
1242 * @dev: PCI device to power up
1244 int pci_power_up(struct pci_dev
*dev
)
1246 pci_platform_power_transition(dev
, PCI_D0
);
1249 * Mandatory power management transition delays are handled in
1250 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1251 * corresponding bridge.
1253 if (dev
->runtime_d3cold
) {
1255 * When powering on a bridge from D3cold, the whole hierarchy
1256 * may be powered on into D0uninitialized state, resume them to
1257 * give them a chance to suspend again
1259 pci_wakeup_bus(dev
->subordinate
);
1262 return pci_raw_set_power_state(dev
, PCI_D0
);
1266 * __pci_dev_set_current_state - Set current state of a PCI device
1267 * @dev: Device to handle
1268 * @data: pointer to state to be set
1270 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
1272 pci_power_t state
= *(pci_power_t
*)data
;
1274 dev
->current_state
= state
;
1279 * pci_bus_set_current_state - Walk given bus and set current state of devices
1280 * @bus: Top bus of the subtree to walk.
1281 * @state: state to be set
1283 void pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
1286 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
1290 * pci_set_power_state - Set the power state of a PCI device
1291 * @dev: PCI device to handle.
1292 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1294 * Transition a device to a new power state, using the platform firmware and/or
1295 * the device's PCI PM registers.
1298 * -EINVAL if the requested state is invalid.
1299 * -EIO if device does not support PCI PM or its PM capabilities register has a
1300 * wrong version, or device doesn't support the requested state.
1301 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1302 * 0 if device already is in the requested state.
1303 * 0 if the transition is to D3 but D3 is not supported.
1304 * 0 if device's power state has been successfully changed.
1306 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1310 /* Bound the state we're entering */
1311 if (state
> PCI_D3cold
)
1313 else if (state
< PCI_D0
)
1315 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
1318 * If the device or the parent bridge do not support PCI
1319 * PM, ignore the request if we're doing anything other
1320 * than putting it into D0 (which would only happen on
1325 /* Check if we're already there */
1326 if (dev
->current_state
== state
)
1329 if (state
== PCI_D0
)
1330 return pci_power_up(dev
);
1333 * This device is quirked not to be put into D3, so don't put it in
1336 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
1340 * To put device in D3cold, we put device into D3hot in native
1341 * way, then put device into D3cold with platform ops
1343 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
1346 if (pci_platform_power_transition(dev
, state
))
1349 /* Powering off a bridge may power off the whole hierarchy */
1350 if (state
== PCI_D3cold
)
1351 pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
1355 EXPORT_SYMBOL(pci_set_power_state
);
1358 * pci_choose_state - Choose the power state of a PCI device
1359 * @dev: PCI device to be suspended
1360 * @state: target sleep state for the whole system. This is the value
1361 * that is passed to suspend() function.
1363 * Returns PCI power state suitable for given device and given system
1366 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
1373 ret
= platform_pci_choose_state(dev
);
1374 if (ret
!= PCI_POWER_ERROR
)
1377 switch (state
.event
) {
1380 case PM_EVENT_FREEZE
:
1381 case PM_EVENT_PRETHAW
:
1382 /* REVISIT both freeze and pre-thaw "should" use D0 */
1383 case PM_EVENT_SUSPEND
:
1384 case PM_EVENT_HIBERNATE
:
1387 pci_info(dev
, "unrecognized suspend event %d\n",
1393 EXPORT_SYMBOL(pci_choose_state
);
1395 #define PCI_EXP_SAVE_REGS 7
1397 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
1398 u16 cap
, bool extended
)
1400 struct pci_cap_saved_state
*tmp
;
1402 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
1403 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
1409 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
1411 return _pci_find_saved_cap(dev
, cap
, false);
1414 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1416 return _pci_find_saved_cap(dev
, cap
, true);
1419 static int pci_save_pcie_state(struct pci_dev
*dev
)
1422 struct pci_cap_saved_state
*save_state
;
1425 if (!pci_is_pcie(dev
))
1428 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1430 pci_err(dev
, "buffer not found in %s\n", __func__
);
1434 cap
= (u16
*)&save_state
->cap
.data
[0];
1435 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1436 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1437 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1438 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1439 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1440 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1441 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1446 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1449 struct pci_cap_saved_state
*save_state
;
1452 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1456 cap
= (u16
*)&save_state
->cap
.data
[0];
1457 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1458 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1459 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1460 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1461 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1462 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1463 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1466 static int pci_save_pcix_state(struct pci_dev
*dev
)
1469 struct pci_cap_saved_state
*save_state
;
1471 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1475 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1477 pci_err(dev
, "buffer not found in %s\n", __func__
);
1481 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1482 (u16
*)save_state
->cap
.data
);
1487 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1490 struct pci_cap_saved_state
*save_state
;
1493 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1494 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1495 if (!save_state
|| !pos
)
1497 cap
= (u16
*)&save_state
->cap
.data
[0];
1499 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1502 static void pci_save_ltr_state(struct pci_dev
*dev
)
1505 struct pci_cap_saved_state
*save_state
;
1508 if (!pci_is_pcie(dev
))
1511 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1515 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1517 pci_err(dev
, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1521 cap
= (u16
*)&save_state
->cap
.data
[0];
1522 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, cap
++);
1523 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, cap
++);
1526 static void pci_restore_ltr_state(struct pci_dev
*dev
)
1528 struct pci_cap_saved_state
*save_state
;
1532 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1533 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1534 if (!save_state
|| !ltr
)
1537 cap
= (u16
*)&save_state
->cap
.data
[0];
1538 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, *cap
++);
1539 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, *cap
++);
1543 * pci_save_state - save the PCI configuration space of a device before
1545 * @dev: PCI device that we're dealing with
1547 int pci_save_state(struct pci_dev
*dev
)
1550 /* XXX: 100% dword access ok here? */
1551 for (i
= 0; i
< 16; i
++) {
1552 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1553 pci_dbg(dev
, "saving config space at offset %#x (reading %#x)\n",
1554 i
* 4, dev
->saved_config_space
[i
]);
1556 dev
->state_saved
= true;
1558 i
= pci_save_pcie_state(dev
);
1562 i
= pci_save_pcix_state(dev
);
1566 pci_save_ltr_state(dev
);
1567 pci_save_dpc_state(dev
);
1568 pci_save_aer_state(dev
);
1569 return pci_save_vc_state(dev
);
1571 EXPORT_SYMBOL(pci_save_state
);
1573 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1574 u32 saved_val
, int retry
, bool force
)
1578 pci_read_config_dword(pdev
, offset
, &val
);
1579 if (!force
&& val
== saved_val
)
1583 pci_dbg(pdev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1584 offset
, val
, saved_val
);
1585 pci_write_config_dword(pdev
, offset
, saved_val
);
1589 pci_read_config_dword(pdev
, offset
, &val
);
1590 if (val
== saved_val
)
1597 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1598 int start
, int end
, int retry
,
1603 for (index
= end
; index
>= start
; index
--)
1604 pci_restore_config_dword(pdev
, 4 * index
,
1605 pdev
->saved_config_space
[index
],
1609 static void pci_restore_config_space(struct pci_dev
*pdev
)
1611 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1612 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1613 /* Restore BARs before the command register. */
1614 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1615 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1616 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1617 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1620 * Force rewriting of prefetch registers to avoid S3 resume
1621 * issues on Intel PCI bridges that occur when these
1622 * registers are not explicitly written.
1624 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1625 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1627 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1631 static void pci_restore_rebar_state(struct pci_dev
*pdev
)
1633 unsigned int pos
, nbars
, i
;
1636 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
1640 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1641 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
1642 PCI_REBAR_CTRL_NBAR_SHIFT
;
1644 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
1645 struct resource
*res
;
1648 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1649 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
1650 res
= pdev
->resource
+ bar_idx
;
1651 size
= ilog2(resource_size(res
)) - 20;
1652 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
1653 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
1654 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
1659 * pci_restore_state - Restore the saved state of a PCI device
1660 * @dev: PCI device that we're dealing with
1662 void pci_restore_state(struct pci_dev
*dev
)
1664 if (!dev
->state_saved
)
1668 * Restore max latencies (in the LTR capability) before enabling
1669 * LTR itself (in the PCIe capability).
1671 pci_restore_ltr_state(dev
);
1673 pci_restore_pcie_state(dev
);
1674 pci_restore_pasid_state(dev
);
1675 pci_restore_pri_state(dev
);
1676 pci_restore_ats_state(dev
);
1677 pci_restore_vc_state(dev
);
1678 pci_restore_rebar_state(dev
);
1679 pci_restore_dpc_state(dev
);
1681 pci_aer_clear_status(dev
);
1682 pci_restore_aer_state(dev
);
1684 pci_restore_config_space(dev
);
1686 pci_restore_pcix_state(dev
);
1687 pci_restore_msi_state(dev
);
1689 /* Restore ACS and IOV configuration state */
1690 pci_enable_acs(dev
);
1691 pci_restore_iov_state(dev
);
1693 dev
->state_saved
= false;
1695 EXPORT_SYMBOL(pci_restore_state
);
1697 struct pci_saved_state
{
1698 u32 config_space
[16];
1699 struct pci_cap_saved_data cap
[];
1703 * pci_store_saved_state - Allocate and return an opaque struct containing
1704 * the device saved state.
1705 * @dev: PCI device that we're dealing with
1707 * Return NULL if no state or error.
1709 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1711 struct pci_saved_state
*state
;
1712 struct pci_cap_saved_state
*tmp
;
1713 struct pci_cap_saved_data
*cap
;
1716 if (!dev
->state_saved
)
1719 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1721 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1722 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1724 state
= kzalloc(size
, GFP_KERNEL
);
1728 memcpy(state
->config_space
, dev
->saved_config_space
,
1729 sizeof(state
->config_space
));
1732 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1733 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1734 memcpy(cap
, &tmp
->cap
, len
);
1735 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1737 /* Empty cap_save terminates list */
1741 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1744 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1745 * @dev: PCI device that we're dealing with
1746 * @state: Saved state returned from pci_store_saved_state()
1748 int pci_load_saved_state(struct pci_dev
*dev
,
1749 struct pci_saved_state
*state
)
1751 struct pci_cap_saved_data
*cap
;
1753 dev
->state_saved
= false;
1758 memcpy(dev
->saved_config_space
, state
->config_space
,
1759 sizeof(state
->config_space
));
1763 struct pci_cap_saved_state
*tmp
;
1765 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1766 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1769 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1770 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1771 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1774 dev
->state_saved
= true;
1777 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1780 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1781 * and free the memory allocated for it.
1782 * @dev: PCI device that we're dealing with
1783 * @state: Pointer to saved state returned from pci_store_saved_state()
1785 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1786 struct pci_saved_state
**state
)
1788 int ret
= pci_load_saved_state(dev
, *state
);
1793 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1795 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1797 return pci_enable_resources(dev
, bars
);
1800 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1803 struct pci_dev
*bridge
;
1807 err
= pci_set_power_state(dev
, PCI_D0
);
1808 if (err
< 0 && err
!= -EIO
)
1811 bridge
= pci_upstream_bridge(dev
);
1813 pcie_aspm_powersave_config_link(bridge
);
1815 err
= pcibios_enable_device(dev
, bars
);
1818 pci_fixup_device(pci_fixup_enable
, dev
);
1820 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1823 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1825 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1826 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1827 pci_write_config_word(dev
, PCI_COMMAND
,
1828 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1835 * pci_reenable_device - Resume abandoned device
1836 * @dev: PCI device to be resumed
1838 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1839 * to be called by normal code, write proper resume handler and use it instead.
1841 int pci_reenable_device(struct pci_dev
*dev
)
1843 if (pci_is_enabled(dev
))
1844 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1847 EXPORT_SYMBOL(pci_reenable_device
);
1849 static void pci_enable_bridge(struct pci_dev
*dev
)
1851 struct pci_dev
*bridge
;
1854 bridge
= pci_upstream_bridge(dev
);
1856 pci_enable_bridge(bridge
);
1858 if (pci_is_enabled(dev
)) {
1859 if (!dev
->is_busmaster
)
1860 pci_set_master(dev
);
1864 retval
= pci_enable_device(dev
);
1866 pci_err(dev
, "Error enabling bridge (%d), continuing\n",
1868 pci_set_master(dev
);
1871 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1873 struct pci_dev
*bridge
;
1878 * Power state could be unknown at this point, either due to a fresh
1879 * boot or a device removal call. So get the current power state
1880 * so that things like MSI message writing will behave as expected
1881 * (e.g. if the device really is in D0 at enable time).
1885 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1886 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1889 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1890 return 0; /* already enabled */
1892 bridge
= pci_upstream_bridge(dev
);
1894 pci_enable_bridge(bridge
);
1896 /* only skip sriov related */
1897 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1898 if (dev
->resource
[i
].flags
& flags
)
1900 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1901 if (dev
->resource
[i
].flags
& flags
)
1904 err
= do_pci_enable_device(dev
, bars
);
1906 atomic_dec(&dev
->enable_cnt
);
1911 * pci_enable_device_io - Initialize a device for use with IO space
1912 * @dev: PCI device to be initialized
1914 * Initialize device before it's used by a driver. Ask low-level code
1915 * to enable I/O resources. Wake up the device if it was suspended.
1916 * Beware, this function can fail.
1918 int pci_enable_device_io(struct pci_dev
*dev
)
1920 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1922 EXPORT_SYMBOL(pci_enable_device_io
);
1925 * pci_enable_device_mem - Initialize a device for use with Memory space
1926 * @dev: PCI device to be initialized
1928 * Initialize device before it's used by a driver. Ask low-level code
1929 * to enable Memory resources. Wake up the device if it was suspended.
1930 * Beware, this function can fail.
1932 int pci_enable_device_mem(struct pci_dev
*dev
)
1934 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1936 EXPORT_SYMBOL(pci_enable_device_mem
);
1939 * pci_enable_device - Initialize device before it's used by a driver.
1940 * @dev: PCI device to be initialized
1942 * Initialize device before it's used by a driver. Ask low-level code
1943 * to enable I/O and memory. Wake up the device if it was suspended.
1944 * Beware, this function can fail.
1946 * Note we don't actually enable the device many times if we call
1947 * this function repeatedly (we just increment the count).
1949 int pci_enable_device(struct pci_dev
*dev
)
1951 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1953 EXPORT_SYMBOL(pci_enable_device
);
1956 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1957 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1958 * there's no need to track it separately. pci_devres is initialized
1959 * when a device is enabled using managed PCI device enable interface.
1962 unsigned int enabled
:1;
1963 unsigned int pinned
:1;
1964 unsigned int orig_intx
:1;
1965 unsigned int restore_intx
:1;
1970 static void pcim_release(struct device
*gendev
, void *res
)
1972 struct pci_dev
*dev
= to_pci_dev(gendev
);
1973 struct pci_devres
*this = res
;
1976 if (dev
->msi_enabled
)
1977 pci_disable_msi(dev
);
1978 if (dev
->msix_enabled
)
1979 pci_disable_msix(dev
);
1981 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1982 if (this->region_mask
& (1 << i
))
1983 pci_release_region(dev
, i
);
1988 if (this->restore_intx
)
1989 pci_intx(dev
, this->orig_intx
);
1991 if (this->enabled
&& !this->pinned
)
1992 pci_disable_device(dev
);
1995 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1997 struct pci_devres
*dr
, *new_dr
;
1999 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2003 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
2006 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
2009 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
2011 if (pci_is_managed(pdev
))
2012 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2017 * pcim_enable_device - Managed pci_enable_device()
2018 * @pdev: PCI device to be initialized
2020 * Managed pci_enable_device().
2022 int pcim_enable_device(struct pci_dev
*pdev
)
2024 struct pci_devres
*dr
;
2027 dr
= get_pci_dr(pdev
);
2033 rc
= pci_enable_device(pdev
);
2035 pdev
->is_managed
= 1;
2040 EXPORT_SYMBOL(pcim_enable_device
);
2043 * pcim_pin_device - Pin managed PCI device
2044 * @pdev: PCI device to pin
2046 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2047 * driver detach. @pdev must have been enabled with
2048 * pcim_enable_device().
2050 void pcim_pin_device(struct pci_dev
*pdev
)
2052 struct pci_devres
*dr
;
2054 dr
= find_pci_dr(pdev
);
2055 WARN_ON(!dr
|| !dr
->enabled
);
2059 EXPORT_SYMBOL(pcim_pin_device
);
2062 * pcibios_add_device - provide arch specific hooks when adding device dev
2063 * @dev: the PCI device being added
2065 * Permits the platform to provide architecture specific functionality when
2066 * devices are added. This is the default implementation. Architecture
2067 * implementations can override this.
2069 int __weak
pcibios_add_device(struct pci_dev
*dev
)
2075 * pcibios_release_device - provide arch specific hooks when releasing
2077 * @dev: the PCI device being released
2079 * Permits the platform to provide architecture specific functionality when
2080 * devices are released. This is the default implementation. Architecture
2081 * implementations can override this.
2083 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
2086 * pcibios_disable_device - disable arch specific PCI resources for device dev
2087 * @dev: the PCI device to disable
2089 * Disables architecture specific PCI resources for the device. This
2090 * is the default implementation. Architecture implementations can
2093 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
2096 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2097 * @irq: ISA IRQ to penalize
2098 * @active: IRQ active or not
2100 * Permits the platform to provide architecture-specific functionality when
2101 * penalizing ISA IRQs. This is the default implementation. Architecture
2102 * implementations can override this.
2104 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
2106 static void do_pci_disable_device(struct pci_dev
*dev
)
2110 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
2111 if (pci_command
& PCI_COMMAND_MASTER
) {
2112 pci_command
&= ~PCI_COMMAND_MASTER
;
2113 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
2116 pcibios_disable_device(dev
);
2120 * pci_disable_enabled_device - Disable device without updating enable_cnt
2121 * @dev: PCI device to disable
2123 * NOTE: This function is a backend of PCI power management routines and is
2124 * not supposed to be called drivers.
2126 void pci_disable_enabled_device(struct pci_dev
*dev
)
2128 if (pci_is_enabled(dev
))
2129 do_pci_disable_device(dev
);
2133 * pci_disable_device - Disable PCI device after use
2134 * @dev: PCI device to be disabled
2136 * Signal to the system that the PCI device is not in use by the system
2137 * anymore. This only involves disabling PCI bus-mastering, if active.
2139 * Note we don't actually disable the device until all callers of
2140 * pci_enable_device() have called pci_disable_device().
2142 void pci_disable_device(struct pci_dev
*dev
)
2144 struct pci_devres
*dr
;
2146 dr
= find_pci_dr(dev
);
2150 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
2151 "disabling already-disabled device");
2153 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
2156 do_pci_disable_device(dev
);
2158 dev
->is_busmaster
= 0;
2160 EXPORT_SYMBOL(pci_disable_device
);
2163 * pcibios_set_pcie_reset_state - set reset state for device dev
2164 * @dev: the PCIe device reset
2165 * @state: Reset state to enter into
2167 * Set the PCIe reset state for the device. This is the default
2168 * implementation. Architecture implementations can override this.
2170 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
2171 enum pcie_reset_state state
)
2177 * pci_set_pcie_reset_state - set reset state for device dev
2178 * @dev: the PCIe device reset
2179 * @state: Reset state to enter into
2181 * Sets the PCI reset state for the device.
2183 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
2185 return pcibios_set_pcie_reset_state(dev
, state
);
2187 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
2189 void pcie_clear_device_status(struct pci_dev
*dev
)
2193 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
2194 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
2198 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2199 * @dev: PCIe root port or event collector.
2201 void pcie_clear_root_pme_status(struct pci_dev
*dev
)
2203 pcie_capability_set_dword(dev
, PCI_EXP_RTSTA
, PCI_EXP_RTSTA_PME
);
2207 * pci_check_pme_status - Check if given device has generated PME.
2208 * @dev: Device to check.
2210 * Check the PME status of the device and if set, clear it and clear PME enable
2211 * (if set). Return 'true' if PME status and PME enable were both set or
2212 * 'false' otherwise.
2214 bool pci_check_pme_status(struct pci_dev
*dev
)
2223 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
2224 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
2225 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
2228 /* Clear PME status. */
2229 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2230 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
2231 /* Disable PME to avoid interrupt flood. */
2232 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2236 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
2242 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2243 * @dev: Device to handle.
2244 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2246 * Check if @dev has generated PME and queue a resume request for it in that
2249 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
2251 if (pme_poll_reset
&& dev
->pme_poll
)
2252 dev
->pme_poll
= false;
2254 if (pci_check_pme_status(dev
)) {
2255 pci_wakeup_event(dev
);
2256 pm_request_resume(&dev
->dev
);
2262 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2263 * @bus: Top bus of the subtree to walk.
2265 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
2268 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
2273 * pci_pme_capable - check the capability of PCI device to generate PME#
2274 * @dev: PCI device to handle.
2275 * @state: PCI state from which device will issue PME#.
2277 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
2282 return !!(dev
->pme_support
& (1 << state
));
2284 EXPORT_SYMBOL(pci_pme_capable
);
2286 static void pci_pme_list_scan(struct work_struct
*work
)
2288 struct pci_pme_device
*pme_dev
, *n
;
2290 mutex_lock(&pci_pme_list_mutex
);
2291 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
2292 if (pme_dev
->dev
->pme_poll
) {
2293 struct pci_dev
*bridge
;
2295 bridge
= pme_dev
->dev
->bus
->self
;
2297 * If bridge is in low power state, the
2298 * configuration space of subordinate devices
2299 * may be not accessible
2301 if (bridge
&& bridge
->current_state
!= PCI_D0
)
2304 * If the device is in D3cold it should not be
2307 if (pme_dev
->dev
->current_state
== PCI_D3cold
)
2310 pci_pme_wakeup(pme_dev
->dev
, NULL
);
2312 list_del(&pme_dev
->list
);
2316 if (!list_empty(&pci_pme_list
))
2317 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
2318 msecs_to_jiffies(PME_TIMEOUT
));
2319 mutex_unlock(&pci_pme_list_mutex
);
2322 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
2326 if (!dev
->pme_support
)
2329 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2330 /* Clear PME_Status by writing 1 to it and enable PME# */
2331 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
2333 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2335 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2339 * pci_pme_restore - Restore PME configuration after config space restore.
2340 * @dev: PCI device to update.
2342 void pci_pme_restore(struct pci_dev
*dev
)
2346 if (!dev
->pme_support
)
2349 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2350 if (dev
->wakeup_prepared
) {
2351 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
2352 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
2354 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2355 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2357 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2361 * pci_pme_active - enable or disable PCI device's PME# function
2362 * @dev: PCI device to handle.
2363 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2365 * The caller must verify that the device is capable of generating PME# before
2366 * calling this function with @enable equal to 'true'.
2368 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
2370 __pci_pme_active(dev
, enable
);
2373 * PCI (as opposed to PCIe) PME requires that the device have
2374 * its PME# line hooked up correctly. Not all hardware vendors
2375 * do this, so the PME never gets delivered and the device
2376 * remains asleep. The easiest way around this is to
2377 * periodically walk the list of suspended devices and check
2378 * whether any have their PME flag set. The assumption is that
2379 * we'll wake up often enough anyway that this won't be a huge
2380 * hit, and the power savings from the devices will still be a
2383 * Although PCIe uses in-band PME message instead of PME# line
2384 * to report PME, PME does not work for some PCIe devices in
2385 * reality. For example, there are devices that set their PME
2386 * status bits, but don't really bother to send a PME message;
2387 * there are PCI Express Root Ports that don't bother to
2388 * trigger interrupts when they receive PME messages from the
2389 * devices below. So PME poll is used for PCIe devices too.
2392 if (dev
->pme_poll
) {
2393 struct pci_pme_device
*pme_dev
;
2395 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
2398 pci_warn(dev
, "can't enable PME#\n");
2402 mutex_lock(&pci_pme_list_mutex
);
2403 list_add(&pme_dev
->list
, &pci_pme_list
);
2404 if (list_is_singular(&pci_pme_list
))
2405 queue_delayed_work(system_freezable_wq
,
2407 msecs_to_jiffies(PME_TIMEOUT
));
2408 mutex_unlock(&pci_pme_list_mutex
);
2410 mutex_lock(&pci_pme_list_mutex
);
2411 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
2412 if (pme_dev
->dev
== dev
) {
2413 list_del(&pme_dev
->list
);
2418 mutex_unlock(&pci_pme_list_mutex
);
2422 pci_dbg(dev
, "PME# %s\n", enable
? "enabled" : "disabled");
2424 EXPORT_SYMBOL(pci_pme_active
);
2427 * __pci_enable_wake - enable PCI device as wakeup event source
2428 * @dev: PCI device affected
2429 * @state: PCI state from which device will issue wakeup events
2430 * @enable: True to enable event generation; false to disable
2432 * This enables the device as a wakeup event source, or disables it.
2433 * When such events involves platform-specific hooks, those hooks are
2434 * called automatically by this routine.
2436 * Devices with legacy power management (no standard PCI PM capabilities)
2437 * always require such platform hooks.
2440 * 0 is returned on success
2441 * -EINVAL is returned if device is not supposed to wake up the system
2442 * Error code depending on the platform is returned if both the platform and
2443 * the native mechanism fail to enable the generation of wake-up events
2445 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
2450 * Bridges that are not power-manageable directly only signal
2451 * wakeup on behalf of subordinate devices which is set up
2452 * elsewhere, so skip them. However, bridges that are
2453 * power-manageable may signal wakeup for themselves (for example,
2454 * on a hotplug event) and they need to be covered here.
2456 if (!pci_power_manageable(dev
))
2459 /* Don't do the same thing twice in a row for one device. */
2460 if (!!enable
== !!dev
->wakeup_prepared
)
2464 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2465 * Anderson we should be doing PME# wake enable followed by ACPI wake
2466 * enable. To disable wake-up we call the platform first, for symmetry.
2472 if (pci_pme_capable(dev
, state
))
2473 pci_pme_active(dev
, true);
2476 error
= platform_pci_set_wakeup(dev
, true);
2480 dev
->wakeup_prepared
= true;
2482 platform_pci_set_wakeup(dev
, false);
2483 pci_pme_active(dev
, false);
2484 dev
->wakeup_prepared
= false;
2491 * pci_enable_wake - change wakeup settings for a PCI device
2492 * @pci_dev: Target device
2493 * @state: PCI state from which device will issue wakeup events
2494 * @enable: Whether or not to enable event generation
2496 * If @enable is set, check device_may_wakeup() for the device before calling
2497 * __pci_enable_wake() for it.
2499 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
2501 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
2504 return __pci_enable_wake(pci_dev
, state
, enable
);
2506 EXPORT_SYMBOL(pci_enable_wake
);
2509 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2510 * @dev: PCI device to prepare
2511 * @enable: True to enable wake-up event generation; false to disable
2513 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2514 * and this function allows them to set that up cleanly - pci_enable_wake()
2515 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2516 * ordering constraints.
2518 * This function only returns error code if the device is not allowed to wake
2519 * up the system from sleep or it is not capable of generating PME# from both
2520 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2522 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2524 return pci_pme_capable(dev
, PCI_D3cold
) ?
2525 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2526 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2528 EXPORT_SYMBOL(pci_wake_from_d3
);
2531 * pci_target_state - find an appropriate low power state for a given PCI dev
2533 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2535 * Use underlying platform code to find a supported low power state for @dev.
2536 * If the platform can't manage @dev, return the deepest state from which it
2537 * can generate wake events, based on any available PME info.
2539 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2541 pci_power_t target_state
= PCI_D3hot
;
2543 if (platform_pci_power_manageable(dev
)) {
2545 * Call the platform to find the target state for the device.
2547 pci_power_t state
= platform_pci_choose_state(dev
);
2550 case PCI_POWER_ERROR
:
2555 if (pci_no_d1d2(dev
))
2557 /* else, fall through */
2559 target_state
= state
;
2562 return target_state
;
2566 target_state
= PCI_D0
;
2569 * If the device is in D3cold even though it's not power-manageable by
2570 * the platform, it may have been powered down by non-standard means.
2571 * Best to let it slumber.
2573 if (dev
->current_state
== PCI_D3cold
)
2574 target_state
= PCI_D3cold
;
2578 * Find the deepest state from which the device can generate
2581 if (dev
->pme_support
) {
2583 && !(dev
->pme_support
& (1 << target_state
)))
2588 return target_state
;
2592 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2593 * into a sleep state
2594 * @dev: Device to handle.
2596 * Choose the power state appropriate for the device depending on whether
2597 * it can wake up the system and/or is power manageable by the platform
2598 * (PCI_D3hot is the default) and put the device into that state.
2600 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2602 bool wakeup
= device_may_wakeup(&dev
->dev
);
2603 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2606 if (target_state
== PCI_POWER_ERROR
)
2609 pci_enable_wake(dev
, target_state
, wakeup
);
2611 error
= pci_set_power_state(dev
, target_state
);
2614 pci_enable_wake(dev
, target_state
, false);
2618 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2621 * pci_back_from_sleep - turn PCI device on during system-wide transition
2622 * into working state
2623 * @dev: Device to handle.
2625 * Disable device's system wake-up capability and put it into D0.
2627 int pci_back_from_sleep(struct pci_dev
*dev
)
2629 pci_enable_wake(dev
, PCI_D0
, false);
2630 return pci_set_power_state(dev
, PCI_D0
);
2632 EXPORT_SYMBOL(pci_back_from_sleep
);
2635 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2636 * @dev: PCI device being suspended.
2638 * Prepare @dev to generate wake-up events at run time and put it into a low
2641 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2643 pci_power_t target_state
;
2646 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2647 if (target_state
== PCI_POWER_ERROR
)
2650 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2652 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2654 error
= pci_set_power_state(dev
, target_state
);
2657 pci_enable_wake(dev
, target_state
, false);
2658 dev
->runtime_d3cold
= false;
2665 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2666 * @dev: Device to check.
2668 * Return true if the device itself is capable of generating wake-up events
2669 * (through the platform or using the native PCIe PME) or if the device supports
2670 * PME and one of its upstream bridges can generate wake-up events.
2672 bool pci_dev_run_wake(struct pci_dev
*dev
)
2674 struct pci_bus
*bus
= dev
->bus
;
2676 if (!dev
->pme_support
)
2679 /* PME-capable in principle, but not from the target power state */
2680 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2683 if (device_can_wakeup(&dev
->dev
))
2686 while (bus
->parent
) {
2687 struct pci_dev
*bridge
= bus
->self
;
2689 if (device_can_wakeup(&bridge
->dev
))
2695 /* We have reached the root bus. */
2697 return device_can_wakeup(bus
->bridge
);
2701 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2704 * pci_dev_need_resume - Check if it is necessary to resume the device.
2705 * @pci_dev: Device to check.
2707 * Return 'true' if the device is not runtime-suspended or it has to be
2708 * reconfigured due to wakeup settings difference between system and runtime
2709 * suspend, or the current power state of it is not suitable for the upcoming
2710 * (system-wide) transition.
2712 bool pci_dev_need_resume(struct pci_dev
*pci_dev
)
2714 struct device
*dev
= &pci_dev
->dev
;
2715 pci_power_t target_state
;
2717 if (!pm_runtime_suspended(dev
) || platform_pci_need_resume(pci_dev
))
2720 target_state
= pci_target_state(pci_dev
, device_may_wakeup(dev
));
2723 * If the earlier platform check has not triggered, D3cold is just power
2724 * removal on top of D3hot, so no need to resume the device in that
2727 return target_state
!= pci_dev
->current_state
&&
2728 target_state
!= PCI_D3cold
&&
2729 pci_dev
->current_state
!= PCI_D3hot
;
2733 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2734 * @pci_dev: Device to check.
2736 * If the device is suspended and it is not configured for system wakeup,
2737 * disable PME for it to prevent it from waking up the system unnecessarily.
2739 * Note that if the device's power state is D3cold and the platform check in
2740 * pci_dev_need_resume() has not triggered, the device's configuration need not
2743 void pci_dev_adjust_pme(struct pci_dev
*pci_dev
)
2745 struct device
*dev
= &pci_dev
->dev
;
2747 spin_lock_irq(&dev
->power
.lock
);
2749 if (pm_runtime_suspended(dev
) && !device_may_wakeup(dev
) &&
2750 pci_dev
->current_state
< PCI_D3cold
)
2751 __pci_pme_active(pci_dev
, false);
2753 spin_unlock_irq(&dev
->power
.lock
);
2757 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2758 * @pci_dev: Device to handle.
2760 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2761 * it might have been disabled during the prepare phase of system suspend if
2762 * the device was not configured for system wakeup.
2764 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2766 struct device
*dev
= &pci_dev
->dev
;
2768 if (!pci_dev_run_wake(pci_dev
))
2771 spin_lock_irq(&dev
->power
.lock
);
2773 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2774 __pci_pme_active(pci_dev
, true);
2776 spin_unlock_irq(&dev
->power
.lock
);
2779 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2781 struct device
*dev
= &pdev
->dev
;
2782 struct device
*parent
= dev
->parent
;
2785 pm_runtime_get_sync(parent
);
2786 pm_runtime_get_noresume(dev
);
2788 * pdev->current_state is set to PCI_D3cold during suspending,
2789 * so wait until suspending completes
2791 pm_runtime_barrier(dev
);
2793 * Only need to resume devices in D3cold, because config
2794 * registers are still accessible for devices suspended but
2797 if (pdev
->current_state
== PCI_D3cold
)
2798 pm_runtime_resume(dev
);
2801 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2803 struct device
*dev
= &pdev
->dev
;
2804 struct device
*parent
= dev
->parent
;
2806 pm_runtime_put(dev
);
2808 pm_runtime_put_sync(parent
);
2811 static const struct dmi_system_id bridge_d3_blacklist
[] = {
2815 * Gigabyte X299 root port is not marked as hotplug capable
2816 * which allows Linux to power manage it. However, this
2817 * confuses the BIOS SMI handler so don't power manage root
2818 * ports on that system.
2820 .ident
= "X299 DESIGNARE EX-CF",
2822 DMI_MATCH(DMI_BOARD_VENDOR
, "Gigabyte Technology Co., Ltd."),
2823 DMI_MATCH(DMI_BOARD_NAME
, "X299 DESIGNARE EX-CF"),
2831 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2832 * @bridge: Bridge to check
2834 * This function checks if it is possible to move the bridge to D3.
2835 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2837 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2839 if (!pci_is_pcie(bridge
))
2842 switch (pci_pcie_type(bridge
)) {
2843 case PCI_EXP_TYPE_ROOT_PORT
:
2844 case PCI_EXP_TYPE_UPSTREAM
:
2845 case PCI_EXP_TYPE_DOWNSTREAM
:
2846 if (pci_bridge_d3_disable
)
2850 * Hotplug ports handled by firmware in System Management Mode
2851 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2853 if (bridge
->is_hotplug_bridge
&& !pciehp_is_native(bridge
))
2856 if (pci_bridge_d3_force
)
2859 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2860 if (bridge
->is_thunderbolt
)
2863 /* Platform might know better if the bridge supports D3 */
2864 if (platform_pci_bridge_d3(bridge
))
2868 * Hotplug ports handled natively by the OS were not validated
2869 * by vendors for runtime D3 at least until 2018 because there
2870 * was no OS support.
2872 if (bridge
->is_hotplug_bridge
)
2875 if (dmi_check_system(bridge_d3_blacklist
))
2879 * It should be safe to put PCIe ports from 2015 or newer
2882 if (dmi_get_bios_year() >= 2015)
2890 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2892 bool *d3cold_ok
= data
;
2894 if (/* The device needs to be allowed to go D3cold ... */
2895 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
2897 /* ... and if it is wakeup capable to do so from D3cold. */
2898 (device_may_wakeup(&dev
->dev
) &&
2899 !pci_pme_capable(dev
, PCI_D3cold
)) ||
2901 /* If it is a bridge it must be allowed to go to D3. */
2902 !pci_power_manageable(dev
))
2910 * pci_bridge_d3_update - Update bridge D3 capabilities
2911 * @dev: PCI device which is changed
2913 * Update upstream bridge PM capabilities accordingly depending on if the
2914 * device PM configuration was changed or the device is being removed. The
2915 * change is also propagated upstream.
2917 void pci_bridge_d3_update(struct pci_dev
*dev
)
2919 bool remove
= !device_is_registered(&dev
->dev
);
2920 struct pci_dev
*bridge
;
2921 bool d3cold_ok
= true;
2923 bridge
= pci_upstream_bridge(dev
);
2924 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
2928 * If D3 is currently allowed for the bridge, removing one of its
2929 * children won't change that.
2931 if (remove
&& bridge
->bridge_d3
)
2935 * If D3 is currently allowed for the bridge and a child is added or
2936 * changed, disallowance of D3 can only be caused by that child, so
2937 * we only need to check that single device, not any of its siblings.
2939 * If D3 is currently not allowed for the bridge, checking the device
2940 * first may allow us to skip checking its siblings.
2943 pci_dev_check_d3cold(dev
, &d3cold_ok
);
2946 * If D3 is currently not allowed for the bridge, this may be caused
2947 * either by the device being changed/removed or any of its siblings,
2948 * so we need to go through all children to find out if one of them
2949 * continues to block D3.
2951 if (d3cold_ok
&& !bridge
->bridge_d3
)
2952 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
2955 if (bridge
->bridge_d3
!= d3cold_ok
) {
2956 bridge
->bridge_d3
= d3cold_ok
;
2957 /* Propagate change to upstream bridges */
2958 pci_bridge_d3_update(bridge
);
2963 * pci_d3cold_enable - Enable D3cold for device
2964 * @dev: PCI device to handle
2966 * This function can be used in drivers to enable D3cold from the device
2967 * they handle. It also updates upstream PCI bridge PM capabilities
2970 void pci_d3cold_enable(struct pci_dev
*dev
)
2972 if (dev
->no_d3cold
) {
2973 dev
->no_d3cold
= false;
2974 pci_bridge_d3_update(dev
);
2977 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
2980 * pci_d3cold_disable - Disable D3cold for device
2981 * @dev: PCI device to handle
2983 * This function can be used in drivers to disable D3cold from the device
2984 * they handle. It also updates upstream PCI bridge PM capabilities
2987 void pci_d3cold_disable(struct pci_dev
*dev
)
2989 if (!dev
->no_d3cold
) {
2990 dev
->no_d3cold
= true;
2991 pci_bridge_d3_update(dev
);
2994 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
2997 * pci_pm_init - Initialize PM functions of given PCI device
2998 * @dev: PCI device to handle.
3000 void pci_pm_init(struct pci_dev
*dev
)
3006 pm_runtime_forbid(&dev
->dev
);
3007 pm_runtime_set_active(&dev
->dev
);
3008 pm_runtime_enable(&dev
->dev
);
3009 device_enable_async_suspend(&dev
->dev
);
3010 dev
->wakeup_prepared
= false;
3013 dev
->pme_support
= 0;
3015 /* find PCI PM capability in list */
3016 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3019 /* Check device's ability to generate PME# */
3020 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
3022 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
3023 pci_err(dev
, "unsupported PM cap regs version (%u)\n",
3024 pmc
& PCI_PM_CAP_VER_MASK
);
3029 dev
->d3hot_delay
= PCI_PM_D3HOT_WAIT
;
3030 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
3031 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
3032 dev
->d3cold_allowed
= true;
3034 dev
->d1_support
= false;
3035 dev
->d2_support
= false;
3036 if (!pci_no_d1d2(dev
)) {
3037 if (pmc
& PCI_PM_CAP_D1
)
3038 dev
->d1_support
= true;
3039 if (pmc
& PCI_PM_CAP_D2
)
3040 dev
->d2_support
= true;
3042 if (dev
->d1_support
|| dev
->d2_support
)
3043 pci_info(dev
, "supports%s%s\n",
3044 dev
->d1_support
? " D1" : "",
3045 dev
->d2_support
? " D2" : "");
3048 pmc
&= PCI_PM_CAP_PME_MASK
;
3050 pci_info(dev
, "PME# supported from%s%s%s%s%s\n",
3051 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
3052 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
3053 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
3054 (pmc
& PCI_PM_CAP_PME_D3hot
) ? " D3hot" : "",
3055 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
3056 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
3057 dev
->pme_poll
= true;
3059 * Make device's PM flags reflect the wake-up capability, but
3060 * let the user space enable it to wake up the system as needed.
3062 device_set_wakeup_capable(&dev
->dev
, true);
3063 /* Disable the PME# generation functionality */
3064 pci_pme_active(dev
, false);
3067 pci_read_config_word(dev
, PCI_STATUS
, &status
);
3068 if (status
& PCI_STATUS_IMM_READY
)
3072 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
3074 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
3078 case PCI_EA_P_VF_MEM
:
3079 flags
|= IORESOURCE_MEM
;
3081 case PCI_EA_P_MEM_PREFETCH
:
3082 case PCI_EA_P_VF_MEM_PREFETCH
:
3083 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
3086 flags
|= IORESOURCE_IO
;
3095 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
3098 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
3099 return &dev
->resource
[bei
];
3100 #ifdef CONFIG_PCI_IOV
3101 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
3102 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
3103 return &dev
->resource
[PCI_IOV_RESOURCES
+
3104 bei
- PCI_EA_BEI_VF_BAR0
];
3106 else if (bei
== PCI_EA_BEI_ROM
)
3107 return &dev
->resource
[PCI_ROM_RESOURCE
];
3112 /* Read an Enhanced Allocation (EA) entry */
3113 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
3115 struct resource
*res
;
3116 int ent_size
, ent_offset
= offset
;
3117 resource_size_t start
, end
;
3118 unsigned long flags
;
3119 u32 dw0
, bei
, base
, max_offset
;
3121 bool support_64
= (sizeof(resource_size_t
) >= 8);
3123 pci_read_config_dword(dev
, ent_offset
, &dw0
);
3126 /* Entry size field indicates DWORDs after 1st */
3127 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
3129 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
3132 bei
= (dw0
& PCI_EA_BEI
) >> 4;
3133 prop
= (dw0
& PCI_EA_PP
) >> 8;
3136 * If the Property is in the reserved range, try the Secondary
3139 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
3140 prop
= (dw0
& PCI_EA_SP
) >> 16;
3141 if (prop
> PCI_EA_P_BRIDGE_IO
)
3144 res
= pci_ea_get_resource(dev
, bei
, prop
);
3146 pci_err(dev
, "Unsupported EA entry BEI: %u\n", bei
);
3150 flags
= pci_ea_flags(dev
, prop
);
3152 pci_err(dev
, "Unsupported EA properties: %#x\n", prop
);
3157 pci_read_config_dword(dev
, ent_offset
, &base
);
3158 start
= (base
& PCI_EA_FIELD_MASK
);
3161 /* Read MaxOffset */
3162 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
3165 /* Read Base MSBs (if 64-bit entry) */
3166 if (base
& PCI_EA_IS_64
) {
3169 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
3172 flags
|= IORESOURCE_MEM_64
;
3174 /* entry starts above 32-bit boundary, can't use */
3175 if (!support_64
&& base_upper
)
3179 start
|= ((u64
)base_upper
<< 32);
3182 end
= start
+ (max_offset
| 0x03);
3184 /* Read MaxOffset MSBs (if 64-bit entry) */
3185 if (max_offset
& PCI_EA_IS_64
) {
3186 u32 max_offset_upper
;
3188 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
3191 flags
|= IORESOURCE_MEM_64
;
3193 /* entry too big, can't use */
3194 if (!support_64
&& max_offset_upper
)
3198 end
+= ((u64
)max_offset_upper
<< 32);
3202 pci_err(dev
, "EA Entry crosses address boundary\n");
3206 if (ent_size
!= ent_offset
- offset
) {
3207 pci_err(dev
, "EA Entry Size (%d) does not match length read (%d)\n",
3208 ent_size
, ent_offset
- offset
);
3212 res
->name
= pci_name(dev
);
3217 if (bei
<= PCI_EA_BEI_BAR5
)
3218 pci_info(dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3220 else if (bei
== PCI_EA_BEI_ROM
)
3221 pci_info(dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3223 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
3224 pci_info(dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3225 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
3227 pci_info(dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3231 return offset
+ ent_size
;
3234 /* Enhanced Allocation Initialization */
3235 void pci_ea_init(struct pci_dev
*dev
)
3242 /* find PCI EA capability in list */
3243 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
3247 /* determine the number of entries */
3248 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
3250 num_ent
&= PCI_EA_NUM_ENT_MASK
;
3252 offset
= ea
+ PCI_EA_FIRST_ENT
;
3254 /* Skip DWORD 2 for type 1 functions */
3255 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
3258 /* parse each EA entry */
3259 for (i
= 0; i
< num_ent
; ++i
)
3260 offset
= pci_ea_read(dev
, offset
);
3263 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
3264 struct pci_cap_saved_state
*new_cap
)
3266 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
3270 * _pci_add_cap_save_buffer - allocate buffer for saving given
3271 * capability registers
3272 * @dev: the PCI device
3273 * @cap: the capability to allocate the buffer for
3274 * @extended: Standard or Extended capability ID
3275 * @size: requested size of the buffer
3277 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
3278 bool extended
, unsigned int size
)
3281 struct pci_cap_saved_state
*save_state
;
3284 pos
= pci_find_ext_capability(dev
, cap
);
3286 pos
= pci_find_capability(dev
, cap
);
3291 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
3295 save_state
->cap
.cap_nr
= cap
;
3296 save_state
->cap
.cap_extended
= extended
;
3297 save_state
->cap
.size
= size
;
3298 pci_add_saved_cap(dev
, save_state
);
3303 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
3305 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
3308 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
3310 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
3314 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3315 * @dev: the PCI device
3317 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
3321 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
3322 PCI_EXP_SAVE_REGS
* sizeof(u16
));
3324 pci_err(dev
, "unable to preallocate PCI Express save buffer\n");
3326 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
3328 pci_err(dev
, "unable to preallocate PCI-X save buffer\n");
3330 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_LTR
,
3333 pci_err(dev
, "unable to allocate suspend buffer for LTR\n");
3335 pci_allocate_vc_save_buffers(dev
);
3338 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
3340 struct pci_cap_saved_state
*tmp
;
3341 struct hlist_node
*n
;
3343 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
3348 * pci_configure_ari - enable or disable ARI forwarding
3349 * @dev: the PCI device
3351 * If @dev and its upstream bridge both support ARI, enable ARI in the
3352 * bridge. Otherwise, disable ARI in the bridge.
3354 void pci_configure_ari(struct pci_dev
*dev
)
3357 struct pci_dev
*bridge
;
3359 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
3362 bridge
= dev
->bus
->self
;
3366 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3367 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
3370 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
3371 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
3372 PCI_EXP_DEVCTL2_ARI
);
3373 bridge
->ari_enabled
= 1;
3375 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
3376 PCI_EXP_DEVCTL2_ARI
);
3377 bridge
->ari_enabled
= 0;
3381 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3386 pos
= pdev
->acs_cap
;
3391 * Except for egress control, capabilities are either required
3392 * or only required if controllable. Features missing from the
3393 * capability field can therefore be assumed as hard-wired enabled.
3395 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
3396 acs_flags
&= (cap
| PCI_ACS_EC
);
3398 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
3399 return (ctrl
& acs_flags
) == acs_flags
;
3403 * pci_acs_enabled - test ACS against required flags for a given device
3404 * @pdev: device to test
3405 * @acs_flags: required PCI ACS flags
3407 * Return true if the device supports the provided flags. Automatically
3408 * filters out flags that are not implemented on multifunction devices.
3410 * Note that this interface checks the effective ACS capabilities of the
3411 * device rather than the actual capabilities. For instance, most single
3412 * function endpoints are not required to support ACS because they have no
3413 * opportunity for peer-to-peer access. We therefore return 'true'
3414 * regardless of whether the device exposes an ACS capability. This makes
3415 * it much easier for callers of this function to ignore the actual type
3416 * or topology of the device when testing ACS support.
3418 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3422 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
3427 * Conventional PCI and PCI-X devices never support ACS, either
3428 * effectively or actually. The shared bus topology implies that
3429 * any device on the bus can receive or snoop DMA.
3431 if (!pci_is_pcie(pdev
))
3434 switch (pci_pcie_type(pdev
)) {
3436 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3437 * but since their primary interface is PCI/X, we conservatively
3438 * handle them as we would a non-PCIe device.
3440 case PCI_EXP_TYPE_PCIE_BRIDGE
:
3442 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3443 * applicable... must never implement an ACS Extended Capability...".
3444 * This seems arbitrary, but we take a conservative interpretation
3445 * of this statement.
3447 case PCI_EXP_TYPE_PCI_BRIDGE
:
3448 case PCI_EXP_TYPE_RC_EC
:
3451 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3452 * implement ACS in order to indicate their peer-to-peer capabilities,
3453 * regardless of whether they are single- or multi-function devices.
3455 case PCI_EXP_TYPE_DOWNSTREAM
:
3456 case PCI_EXP_TYPE_ROOT_PORT
:
3457 return pci_acs_flags_enabled(pdev
, acs_flags
);
3459 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3460 * implemented by the remaining PCIe types to indicate peer-to-peer
3461 * capabilities, but only when they are part of a multifunction
3462 * device. The footnote for section 6.12 indicates the specific
3463 * PCIe types included here.
3465 case PCI_EXP_TYPE_ENDPOINT
:
3466 case PCI_EXP_TYPE_UPSTREAM
:
3467 case PCI_EXP_TYPE_LEG_END
:
3468 case PCI_EXP_TYPE_RC_END
:
3469 if (!pdev
->multifunction
)
3472 return pci_acs_flags_enabled(pdev
, acs_flags
);
3476 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3477 * to single function devices with the exception of downstream ports.
3483 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3484 * @start: starting downstream device
3485 * @end: ending upstream device or NULL to search to the root bus
3486 * @acs_flags: required flags
3488 * Walk up a device tree from start to end testing PCI ACS support. If
3489 * any step along the way does not support the required flags, return false.
3491 bool pci_acs_path_enabled(struct pci_dev
*start
,
3492 struct pci_dev
*end
, u16 acs_flags
)
3494 struct pci_dev
*pdev
, *parent
= start
;
3499 if (!pci_acs_enabled(pdev
, acs_flags
))
3502 if (pci_is_root_bus(pdev
->bus
))
3503 return (end
== NULL
);
3505 parent
= pdev
->bus
->self
;
3506 } while (pdev
!= end
);
3512 * pci_acs_init - Initialize ACS if hardware supports it
3513 * @dev: the PCI device
3515 void pci_acs_init(struct pci_dev
*dev
)
3517 dev
->acs_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
3520 pci_enable_acs(dev
);
3524 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3528 * Helper to find the position of the ctrl register for a BAR.
3529 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3530 * Returns -ENOENT if no ctrl register for the BAR could be found.
3532 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3534 unsigned int pos
, nbars
, i
;
3537 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3541 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3542 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3543 PCI_REBAR_CTRL_NBAR_SHIFT
;
3545 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3548 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3549 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3558 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3560 * @bar: BAR to query
3562 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3563 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3565 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3570 pos
= pci_rebar_find_pos(pdev
, bar
);
3574 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3575 return (cap
& PCI_REBAR_CAP_SIZES
) >> 4;
3579 * pci_rebar_get_current_size - get the current size of a BAR
3581 * @bar: BAR to set size to
3583 * Read the size of a BAR from the resizable BAR config.
3584 * Returns size if found or negative error code.
3586 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3591 pos
= pci_rebar_find_pos(pdev
, bar
);
3595 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3596 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> PCI_REBAR_CTRL_BAR_SHIFT
;
3600 * pci_rebar_set_size - set a new size for a BAR
3602 * @bar: BAR to set size to
3603 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3605 * Set the new size of a BAR as defined in the spec.
3606 * Returns zero if resizing was successful, error code otherwise.
3608 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3613 pos
= pci_rebar_find_pos(pdev
, bar
);
3617 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3618 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3619 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
3620 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3625 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3626 * @dev: the PCI device
3627 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3628 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3629 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3630 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3632 * Return 0 if all upstream bridges support AtomicOp routing, egress
3633 * blocking is disabled on all upstream ports, and the root port supports
3634 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3635 * AtomicOp completion), or negative otherwise.
3637 int pci_enable_atomic_ops_to_root(struct pci_dev
*dev
, u32 cap_mask
)
3639 struct pci_bus
*bus
= dev
->bus
;
3640 struct pci_dev
*bridge
;
3643 if (!pci_is_pcie(dev
))
3647 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3648 * AtomicOp requesters. For now, we only support endpoints as
3649 * requesters and root ports as completers. No endpoints as
3650 * completers, and no peer-to-peer.
3653 switch (pci_pcie_type(dev
)) {
3654 case PCI_EXP_TYPE_ENDPOINT
:
3655 case PCI_EXP_TYPE_LEG_END
:
3656 case PCI_EXP_TYPE_RC_END
:
3662 while (bus
->parent
) {
3665 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3667 switch (pci_pcie_type(bridge
)) {
3668 /* Ensure switch ports support AtomicOp routing */
3669 case PCI_EXP_TYPE_UPSTREAM
:
3670 case PCI_EXP_TYPE_DOWNSTREAM
:
3671 if (!(cap
& PCI_EXP_DEVCAP2_ATOMIC_ROUTE
))
3675 /* Ensure root port supports all the sizes we care about */
3676 case PCI_EXP_TYPE_ROOT_PORT
:
3677 if ((cap
& cap_mask
) != cap_mask
)
3682 /* Ensure upstream ports don't block AtomicOps on egress */
3683 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
) {
3684 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
,
3686 if (ctl2
& PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
)
3693 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
3694 PCI_EXP_DEVCTL2_ATOMIC_REQ
);
3697 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root
);
3700 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3701 * @dev: the PCI device
3702 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3704 * Perform INTx swizzling for a device behind one level of bridge. This is
3705 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3706 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3707 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3708 * the PCI Express Base Specification, Revision 2.1)
3710 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3714 if (pci_ari_enabled(dev
->bus
))
3717 slot
= PCI_SLOT(dev
->devfn
);
3719 return (((pin
- 1) + slot
) % 4) + 1;
3722 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3730 while (!pci_is_root_bus(dev
->bus
)) {
3731 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3732 dev
= dev
->bus
->self
;
3739 * pci_common_swizzle - swizzle INTx all the way to root bridge
3740 * @dev: the PCI device
3741 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3743 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3744 * bridges all the way up to a PCI root bus.
3746 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3750 while (!pci_is_root_bus(dev
->bus
)) {
3751 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3752 dev
= dev
->bus
->self
;
3755 return PCI_SLOT(dev
->devfn
);
3757 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3760 * pci_release_region - Release a PCI bar
3761 * @pdev: PCI device whose resources were previously reserved by
3762 * pci_request_region()
3763 * @bar: BAR to release
3765 * Releases the PCI I/O and memory resources previously reserved by a
3766 * successful call to pci_request_region(). Call this function only
3767 * after all use of the PCI regions has ceased.
3769 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3771 struct pci_devres
*dr
;
3773 if (pci_resource_len(pdev
, bar
) == 0)
3775 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3776 release_region(pci_resource_start(pdev
, bar
),
3777 pci_resource_len(pdev
, bar
));
3778 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3779 release_mem_region(pci_resource_start(pdev
, bar
),
3780 pci_resource_len(pdev
, bar
));
3782 dr
= find_pci_dr(pdev
);
3784 dr
->region_mask
&= ~(1 << bar
);
3786 EXPORT_SYMBOL(pci_release_region
);
3789 * __pci_request_region - Reserved PCI I/O and memory resource
3790 * @pdev: PCI device whose resources are to be reserved
3791 * @bar: BAR to be reserved
3792 * @res_name: Name to be associated with resource.
3793 * @exclusive: whether the region access is exclusive or not
3795 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3796 * being reserved by owner @res_name. Do not access any
3797 * address inside the PCI regions unless this call returns
3800 * If @exclusive is set, then the region is marked so that userspace
3801 * is explicitly not allowed to map the resource via /dev/mem or
3802 * sysfs MMIO access.
3804 * Returns 0 on success, or %EBUSY on error. A warning
3805 * message is also printed on failure.
3807 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3808 const char *res_name
, int exclusive
)
3810 struct pci_devres
*dr
;
3812 if (pci_resource_len(pdev
, bar
) == 0)
3815 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3816 if (!request_region(pci_resource_start(pdev
, bar
),
3817 pci_resource_len(pdev
, bar
), res_name
))
3819 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3820 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3821 pci_resource_len(pdev
, bar
), res_name
,
3826 dr
= find_pci_dr(pdev
);
3828 dr
->region_mask
|= 1 << bar
;
3833 pci_warn(pdev
, "BAR %d: can't reserve %pR\n", bar
,
3834 &pdev
->resource
[bar
]);
3839 * pci_request_region - Reserve PCI I/O and memory resource
3840 * @pdev: PCI device whose resources are to be reserved
3841 * @bar: BAR to be reserved
3842 * @res_name: Name to be associated with resource
3844 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3845 * being reserved by owner @res_name. Do not access any
3846 * address inside the PCI regions unless this call returns
3849 * Returns 0 on success, or %EBUSY on error. A warning
3850 * message is also printed on failure.
3852 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3854 return __pci_request_region(pdev
, bar
, res_name
, 0);
3856 EXPORT_SYMBOL(pci_request_region
);
3859 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3860 * @pdev: PCI device whose resources were previously reserved
3861 * @bars: Bitmask of BARs to be released
3863 * Release selected PCI I/O and memory resources previously reserved.
3864 * Call this function only after all use of the PCI regions has ceased.
3866 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
3870 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
3871 if (bars
& (1 << i
))
3872 pci_release_region(pdev
, i
);
3874 EXPORT_SYMBOL(pci_release_selected_regions
);
3876 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3877 const char *res_name
, int excl
)
3881 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
3882 if (bars
& (1 << i
))
3883 if (__pci_request_region(pdev
, i
, res_name
, excl
))
3889 if (bars
& (1 << i
))
3890 pci_release_region(pdev
, i
);
3897 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3898 * @pdev: PCI device whose resources are to be reserved
3899 * @bars: Bitmask of BARs to be requested
3900 * @res_name: Name to be associated with resource
3902 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3903 const char *res_name
)
3905 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
3907 EXPORT_SYMBOL(pci_request_selected_regions
);
3909 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
3910 const char *res_name
)
3912 return __pci_request_selected_regions(pdev
, bars
, res_name
,
3913 IORESOURCE_EXCLUSIVE
);
3915 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3918 * pci_release_regions - Release reserved PCI I/O and memory resources
3919 * @pdev: PCI device whose resources were previously reserved by
3920 * pci_request_regions()
3922 * Releases all PCI I/O and memory resources previously reserved by a
3923 * successful call to pci_request_regions(). Call this function only
3924 * after all use of the PCI regions has ceased.
3927 void pci_release_regions(struct pci_dev
*pdev
)
3929 pci_release_selected_regions(pdev
, (1 << PCI_STD_NUM_BARS
) - 1);
3931 EXPORT_SYMBOL(pci_release_regions
);
3934 * pci_request_regions - Reserve PCI I/O and memory resources
3935 * @pdev: PCI device whose resources are to be reserved
3936 * @res_name: Name to be associated with resource.
3938 * Mark all PCI regions associated with PCI device @pdev as
3939 * being reserved by owner @res_name. Do not access any
3940 * address inside the PCI regions unless this call returns
3943 * Returns 0 on success, or %EBUSY on error. A warning
3944 * message is also printed on failure.
3946 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
3948 return pci_request_selected_regions(pdev
,
3949 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
3951 EXPORT_SYMBOL(pci_request_regions
);
3954 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
3955 * @pdev: PCI device whose resources are to be reserved
3956 * @res_name: Name to be associated with resource.
3958 * Mark all PCI regions associated with PCI device @pdev as being reserved
3959 * by owner @res_name. Do not access any address inside the PCI regions
3960 * unless this call returns successfully.
3962 * pci_request_regions_exclusive() will mark the region so that /dev/mem
3963 * and the sysfs MMIO access will not be allowed.
3965 * Returns 0 on success, or %EBUSY on error. A warning message is also
3966 * printed on failure.
3968 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
3970 return pci_request_selected_regions_exclusive(pdev
,
3971 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
3973 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3976 * Record the PCI IO range (expressed as CPU physical address + size).
3977 * Return a negative value if an error has occurred, zero otherwise
3979 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
3980 resource_size_t size
)
3984 struct logic_pio_hwaddr
*range
;
3986 if (!size
|| addr
+ size
< addr
)
3989 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
3993 range
->fwnode
= fwnode
;
3995 range
->hw_start
= addr
;
3996 range
->flags
= LOGIC_PIO_CPU_MMIO
;
3998 ret
= logic_pio_register_range(range
);
4006 phys_addr_t
pci_pio_to_address(unsigned long pio
)
4008 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
4011 if (pio
>= MMIO_UPPER_LIMIT
)
4014 address
= logic_pio_to_hwaddr(pio
);
4020 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
4023 return logic_pio_trans_cpuaddr(address
);
4025 if (address
> IO_SPACE_LIMIT
)
4026 return (unsigned long)-1;
4028 return (unsigned long) address
;
4033 * pci_remap_iospace - Remap the memory mapped I/O space
4034 * @res: Resource describing the I/O space
4035 * @phys_addr: physical address of range to be mapped
4037 * Remap the memory mapped I/O space described by the @res and the CPU
4038 * physical address @phys_addr into virtual address space. Only
4039 * architectures that have memory mapped IO functions defined (and the
4040 * PCI_IOBASE value defined) should call this function.
4042 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
4044 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4045 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4047 if (!(res
->flags
& IORESOURCE_IO
))
4050 if (res
->end
> IO_SPACE_LIMIT
)
4053 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
4054 pgprot_device(PAGE_KERNEL
));
4057 * This architecture does not have memory mapped I/O space,
4058 * so this function should never be called
4060 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4064 EXPORT_SYMBOL(pci_remap_iospace
);
4067 * pci_unmap_iospace - Unmap the memory mapped I/O space
4068 * @res: resource to be unmapped
4070 * Unmap the CPU virtual address @res from virtual address space. Only
4071 * architectures that have memory mapped IO functions defined (and the
4072 * PCI_IOBASE value defined) should call this function.
4074 void pci_unmap_iospace(struct resource
*res
)
4076 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4077 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4079 unmap_kernel_range(vaddr
, resource_size(res
));
4082 EXPORT_SYMBOL(pci_unmap_iospace
);
4084 static void devm_pci_unmap_iospace(struct device
*dev
, void *ptr
)
4086 struct resource
**res
= ptr
;
4088 pci_unmap_iospace(*res
);
4092 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4093 * @dev: Generic device to remap IO address for
4094 * @res: Resource describing the I/O space
4095 * @phys_addr: physical address of range to be mapped
4097 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4100 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
4101 phys_addr_t phys_addr
)
4103 const struct resource
**ptr
;
4106 ptr
= devres_alloc(devm_pci_unmap_iospace
, sizeof(*ptr
), GFP_KERNEL
);
4110 error
= pci_remap_iospace(res
, phys_addr
);
4115 devres_add(dev
, ptr
);
4120 EXPORT_SYMBOL(devm_pci_remap_iospace
);
4123 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4124 * @dev: Generic device to remap IO address for
4125 * @offset: Resource address to map
4126 * @size: Size of map
4128 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4131 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
4132 resource_size_t offset
,
4133 resource_size_t size
)
4135 void __iomem
**ptr
, *addr
;
4137 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
4141 addr
= pci_remap_cfgspace(offset
, size
);
4144 devres_add(dev
, ptr
);
4150 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
4153 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4154 * @dev: generic device to handle the resource for
4155 * @res: configuration space resource to be handled
4157 * Checks that a resource is a valid memory region, requests the memory
4158 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4159 * proper PCI configuration space memory attributes are guaranteed.
4161 * All operations are managed and will be undone on driver detach.
4163 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4164 * on failure. Usage example::
4166 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4167 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4169 * return PTR_ERR(base);
4171 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
4172 struct resource
*res
)
4174 resource_size_t size
;
4176 void __iomem
*dest_ptr
;
4180 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
4181 dev_err(dev
, "invalid resource\n");
4182 return IOMEM_ERR_PTR(-EINVAL
);
4185 size
= resource_size(res
);
4186 name
= res
->name
?: dev_name(dev
);
4188 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
4189 dev_err(dev
, "can't request region for resource %pR\n", res
);
4190 return IOMEM_ERR_PTR(-EBUSY
);
4193 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
4195 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
4196 devm_release_mem_region(dev
, res
->start
, size
);
4197 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
4202 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
4204 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
4208 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
4210 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
4212 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
4213 if (cmd
!= old_cmd
) {
4214 pci_dbg(dev
, "%s bus mastering\n",
4215 enable
? "enabling" : "disabling");
4216 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4218 dev
->is_busmaster
= enable
;
4222 * pcibios_setup - process "pci=" kernel boot arguments
4223 * @str: string used to pass in "pci=" kernel boot arguments
4225 * Process kernel boot arguments. This is the default implementation.
4226 * Architecture specific implementations can override this as necessary.
4228 char * __weak __init
pcibios_setup(char *str
)
4234 * pcibios_set_master - enable PCI bus-mastering for device dev
4235 * @dev: the PCI device to enable
4237 * Enables PCI bus-mastering for the device. This is the default
4238 * implementation. Architecture specific implementations can override
4239 * this if necessary.
4241 void __weak
pcibios_set_master(struct pci_dev
*dev
)
4245 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4246 if (pci_is_pcie(dev
))
4249 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
4251 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
4252 else if (lat
> pcibios_max_latency
)
4253 lat
= pcibios_max_latency
;
4257 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
4261 * pci_set_master - enables bus-mastering for device dev
4262 * @dev: the PCI device to enable
4264 * Enables bus-mastering on the device and calls pcibios_set_master()
4265 * to do the needed arch specific settings.
4267 void pci_set_master(struct pci_dev
*dev
)
4269 __pci_set_master(dev
, true);
4270 pcibios_set_master(dev
);
4272 EXPORT_SYMBOL(pci_set_master
);
4275 * pci_clear_master - disables bus-mastering for device dev
4276 * @dev: the PCI device to disable
4278 void pci_clear_master(struct pci_dev
*dev
)
4280 __pci_set_master(dev
, false);
4282 EXPORT_SYMBOL(pci_clear_master
);
4285 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4286 * @dev: the PCI device for which MWI is to be enabled
4288 * Helper function for pci_set_mwi.
4289 * Originally copied from drivers/net/acenic.c.
4290 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4292 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4294 int pci_set_cacheline_size(struct pci_dev
*dev
)
4298 if (!pci_cache_line_size
)
4301 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4302 equal to or multiple of the right value. */
4303 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4304 if (cacheline_size
>= pci_cache_line_size
&&
4305 (cacheline_size
% pci_cache_line_size
) == 0)
4308 /* Write the correct value. */
4309 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
4311 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4312 if (cacheline_size
== pci_cache_line_size
)
4315 pci_info(dev
, "cache line size of %d is not supported\n",
4316 pci_cache_line_size
<< 2);
4320 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
4323 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4324 * @dev: the PCI device for which MWI is enabled
4326 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4328 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4330 int pci_set_mwi(struct pci_dev
*dev
)
4332 #ifdef PCI_DISABLE_MWI
4338 rc
= pci_set_cacheline_size(dev
);
4342 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4343 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
4344 pci_dbg(dev
, "enabling Mem-Wr-Inval\n");
4345 cmd
|= PCI_COMMAND_INVALIDATE
;
4346 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4351 EXPORT_SYMBOL(pci_set_mwi
);
4354 * pcim_set_mwi - a device-managed pci_set_mwi()
4355 * @dev: the PCI device for which MWI is enabled
4357 * Managed pci_set_mwi().
4359 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4361 int pcim_set_mwi(struct pci_dev
*dev
)
4363 struct pci_devres
*dr
;
4365 dr
= find_pci_dr(dev
);
4370 return pci_set_mwi(dev
);
4372 EXPORT_SYMBOL(pcim_set_mwi
);
4375 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4376 * @dev: the PCI device for which MWI is enabled
4378 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4379 * Callers are not required to check the return value.
4381 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4383 int pci_try_set_mwi(struct pci_dev
*dev
)
4385 #ifdef PCI_DISABLE_MWI
4388 return pci_set_mwi(dev
);
4391 EXPORT_SYMBOL(pci_try_set_mwi
);
4394 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4395 * @dev: the PCI device to disable
4397 * Disables PCI Memory-Write-Invalidate transaction on the device
4399 void pci_clear_mwi(struct pci_dev
*dev
)
4401 #ifndef PCI_DISABLE_MWI
4404 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4405 if (cmd
& PCI_COMMAND_INVALIDATE
) {
4406 cmd
&= ~PCI_COMMAND_INVALIDATE
;
4407 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4411 EXPORT_SYMBOL(pci_clear_mwi
);
4414 * pci_intx - enables/disables PCI INTx for device dev
4415 * @pdev: the PCI device to operate on
4416 * @enable: boolean: whether to enable or disable PCI INTx
4418 * Enables/disables PCI INTx for device @pdev
4420 void pci_intx(struct pci_dev
*pdev
, int enable
)
4422 u16 pci_command
, new;
4424 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
4427 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
4429 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
4431 if (new != pci_command
) {
4432 struct pci_devres
*dr
;
4434 pci_write_config_word(pdev
, PCI_COMMAND
, new);
4436 dr
= find_pci_dr(pdev
);
4437 if (dr
&& !dr
->restore_intx
) {
4438 dr
->restore_intx
= 1;
4439 dr
->orig_intx
= !enable
;
4443 EXPORT_SYMBOL_GPL(pci_intx
);
4445 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
4447 struct pci_bus
*bus
= dev
->bus
;
4448 bool mask_updated
= true;
4449 u32 cmd_status_dword
;
4450 u16 origcmd
, newcmd
;
4451 unsigned long flags
;
4455 * We do a single dword read to retrieve both command and status.
4456 * Document assumptions that make this possible.
4458 BUILD_BUG_ON(PCI_COMMAND
% 4);
4459 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
4461 raw_spin_lock_irqsave(&pci_lock
, flags
);
4463 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
4465 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
4468 * Check interrupt status register to see whether our device
4469 * triggered the interrupt (when masking) or the next IRQ is
4470 * already pending (when unmasking).
4472 if (mask
!= irq_pending
) {
4473 mask_updated
= false;
4477 origcmd
= cmd_status_dword
;
4478 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
4480 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
4481 if (newcmd
!= origcmd
)
4482 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
4485 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
4487 return mask_updated
;
4491 * pci_check_and_mask_intx - mask INTx on pending interrupt
4492 * @dev: the PCI device to operate on
4494 * Check if the device dev has its INTx line asserted, mask it and return
4495 * true in that case. False is returned if no interrupt was pending.
4497 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
4499 return pci_check_and_set_intx_mask(dev
, true);
4501 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
4504 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4505 * @dev: the PCI device to operate on
4507 * Check if the device dev has its INTx line asserted, unmask it if not and
4508 * return true. False is returned and the mask remains active if there was
4509 * still an interrupt pending.
4511 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
4513 return pci_check_and_set_intx_mask(dev
, false);
4515 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
4518 * pci_wait_for_pending_transaction - wait for pending transaction
4519 * @dev: the PCI device to operate on
4521 * Return 0 if transaction is pending 1 otherwise.
4523 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
4525 if (!pci_is_pcie(dev
))
4528 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
4529 PCI_EXP_DEVSTA_TRPND
);
4531 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
4534 * pcie_has_flr - check if a device supports function level resets
4535 * @dev: device to check
4537 * Returns true if the device advertises support for PCIe function level
4540 bool pcie_has_flr(struct pci_dev
*dev
)
4544 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4547 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
4548 return cap
& PCI_EXP_DEVCAP_FLR
;
4550 EXPORT_SYMBOL_GPL(pcie_has_flr
);
4553 * pcie_flr - initiate a PCIe function level reset
4554 * @dev: device to reset
4556 * Initiate a function level reset on @dev. The caller should ensure the
4557 * device supports FLR before calling this function, e.g. by using the
4558 * pcie_has_flr() helper.
4560 int pcie_flr(struct pci_dev
*dev
)
4562 if (!pci_wait_for_pending_transaction(dev
))
4563 pci_err(dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
4565 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
4571 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4572 * 100ms, but may silently discard requests while the FLR is in
4573 * progress. Wait 100ms before trying to access the device.
4577 return pci_dev_wait(dev
, "FLR", PCIE_RESET_READY_POLL_MS
);
4579 EXPORT_SYMBOL_GPL(pcie_flr
);
4581 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
4586 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4590 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4593 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4594 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4601 * Wait for Transaction Pending bit to clear. A word-aligned test
4602 * is used, so we use the control offset rather than status and shift
4603 * the test bit to match.
4605 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4606 PCI_AF_STATUS_TP
<< 8))
4607 pci_err(dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4609 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4615 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4616 * updated 27 July 2006; a device must complete an FLR within
4617 * 100ms, but may silently discard requests while the FLR is in
4618 * progress. Wait 100ms before trying to access the device.
4622 return pci_dev_wait(dev
, "AF_FLR", PCIE_RESET_READY_POLL_MS
);
4626 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4627 * @dev: Device to reset.
4628 * @probe: If set, only check if the device can be reset this way.
4630 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4631 * unset, it will be reinitialized internally when going from PCI_D3hot to
4632 * PCI_D0. If that's the case and the device is not in a low-power state
4633 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4635 * NOTE: This causes the caller to sleep for twice the device power transition
4636 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4637 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4638 * Moreover, only devices in D0 can be reset by this function.
4640 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
4644 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4647 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4648 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4654 if (dev
->current_state
!= PCI_D0
)
4657 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4659 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4660 pci_dev_d3_sleep(dev
);
4662 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4664 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4665 pci_dev_d3_sleep(dev
);
4667 return pci_dev_wait(dev
, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS
);
4671 * pcie_wait_for_link_delay - Wait until link is active or inactive
4672 * @pdev: Bridge device
4673 * @active: waiting for active or inactive?
4674 * @delay: Delay to wait after link has become active (in ms)
4676 * Use this to wait till link becomes active or inactive.
4678 static bool pcie_wait_for_link_delay(struct pci_dev
*pdev
, bool active
,
4686 * Some controllers might not implement link active reporting. In this
4687 * case, we wait for 1000 ms + any delay requested by the caller.
4689 if (!pdev
->link_active_reporting
) {
4690 msleep(timeout
+ delay
);
4695 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4696 * after which we should expect an link active if the reset was
4697 * successful. If so, software must wait a minimum 100ms before sending
4698 * configuration requests to devices downstream this port.
4700 * If the link fails to activate, either the device was physically
4701 * removed or the link is permanently failed.
4706 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
4707 ret
= !!(lnk_status
& PCI_EXP_LNKSTA_DLLLA
);
4718 return ret
== active
;
4722 * pcie_wait_for_link - Wait until link is active or inactive
4723 * @pdev: Bridge device
4724 * @active: waiting for active or inactive?
4726 * Use this to wait till link becomes active or inactive.
4728 bool pcie_wait_for_link(struct pci_dev
*pdev
, bool active
)
4730 return pcie_wait_for_link_delay(pdev
, active
, 100);
4734 * Find maximum D3cold delay required by all the devices on the bus. The
4735 * spec says 100 ms, but firmware can lower it and we allow drivers to
4736 * increase it as well.
4738 * Called with @pci_bus_sem locked for reading.
4740 static int pci_bus_max_d3cold_delay(const struct pci_bus
*bus
)
4742 const struct pci_dev
*pdev
;
4743 int min_delay
= 100;
4746 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
4747 if (pdev
->d3cold_delay
< min_delay
)
4748 min_delay
= pdev
->d3cold_delay
;
4749 if (pdev
->d3cold_delay
> max_delay
)
4750 max_delay
= pdev
->d3cold_delay
;
4753 return max(min_delay
, max_delay
);
4757 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4760 * Handle necessary delays before access to the devices on the secondary
4761 * side of the bridge are permitted after D3cold to D0 transition.
4763 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4764 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4767 void pci_bridge_wait_for_secondary_bus(struct pci_dev
*dev
)
4769 struct pci_dev
*child
;
4772 if (pci_dev_is_disconnected(dev
))
4775 if (!pci_is_bridge(dev
) || !dev
->bridge_d3
)
4778 down_read(&pci_bus_sem
);
4781 * We only deal with devices that are present currently on the bus.
4782 * For any hot-added devices the access delay is handled in pciehp
4783 * board_added(). In case of ACPI hotplug the firmware is expected
4784 * to configure the devices before OS is notified.
4786 if (!dev
->subordinate
|| list_empty(&dev
->subordinate
->devices
)) {
4787 up_read(&pci_bus_sem
);
4791 /* Take d3cold_delay requirements into account */
4792 delay
= pci_bus_max_d3cold_delay(dev
->subordinate
);
4794 up_read(&pci_bus_sem
);
4798 child
= list_first_entry(&dev
->subordinate
->devices
, struct pci_dev
,
4800 up_read(&pci_bus_sem
);
4803 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4804 * accessing the device after reset (that is 1000 ms + 100 ms). In
4805 * practice this should not be needed because we don't do power
4806 * management for them (see pci_bridge_d3_possible()).
4808 if (!pci_is_pcie(dev
)) {
4809 pci_dbg(dev
, "waiting %d ms for secondary bus\n", 1000 + delay
);
4810 msleep(1000 + delay
);
4815 * For PCIe downstream and root ports that do not support speeds
4816 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4817 * speeds (gen3) we need to wait first for the data link layer to
4820 * However, 100 ms is the minimum and the PCIe spec says the
4821 * software must allow at least 1s before it can determine that the
4822 * device that did not respond is a broken device. There is
4823 * evidence that 100 ms is not always enough, for example certain
4824 * Titan Ridge xHCI controller does not always respond to
4825 * configuration requests if we only wait for 100 ms (see
4826 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4828 * Therefore we wait for 100 ms and check for the device presence.
4829 * If it is still not present give it an additional 100 ms.
4831 if (!pcie_downstream_port(dev
))
4834 if (pcie_get_speed_cap(dev
) <= PCIE_SPEED_5_0GT
) {
4835 pci_dbg(dev
, "waiting %d ms for downstream link\n", delay
);
4838 pci_dbg(dev
, "waiting %d ms for downstream link, after activation\n",
4840 if (!pcie_wait_for_link_delay(dev
, true, delay
)) {
4841 /* Did not train, no need to wait any further */
4842 pci_info(dev
, "Data Link Layer Link Active not set in 1000 msec\n");
4847 if (!pci_device_is_present(child
)) {
4848 pci_dbg(child
, "waiting additional %d ms to become accessible\n", delay
);
4853 void pci_reset_secondary_bus(struct pci_dev
*dev
)
4857 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
4858 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
4859 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4862 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4863 * this to 2ms to ensure that we meet the minimum requirement.
4867 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
4868 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4871 * Trhfa for conventional PCI is 2^25 clock cycles.
4872 * Assuming a minimum 33MHz clock this results in a 1s
4873 * delay before we can consider subordinate devices to
4874 * be re-initialized. PCIe has some ways to shorten this,
4875 * but we don't make use of them yet.
4880 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
4882 pci_reset_secondary_bus(dev
);
4886 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4887 * @dev: Bridge device
4889 * Use the bridge control register to assert reset on the secondary bus.
4890 * Devices on the secondary bus are left in power-on state.
4892 int pci_bridge_secondary_bus_reset(struct pci_dev
*dev
)
4894 pcibios_reset_secondary_bus(dev
);
4896 return pci_dev_wait(dev
, "bus reset", PCIE_RESET_READY_POLL_MS
);
4898 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset
);
4900 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
4902 struct pci_dev
*pdev
;
4904 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
4905 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4908 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4915 return pci_bridge_secondary_bus_reset(dev
->bus
->self
);
4918 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
4922 if (!hotplug
|| !try_module_get(hotplug
->owner
))
4925 if (hotplug
->ops
->reset_slot
)
4926 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
4928 module_put(hotplug
->owner
);
4933 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
4935 if (dev
->multifunction
|| dev
->subordinate
|| !dev
->slot
||
4936 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4939 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
4942 static void pci_dev_lock(struct pci_dev
*dev
)
4944 pci_cfg_access_lock(dev
);
4945 /* block PM suspend, driver probe, etc. */
4946 device_lock(&dev
->dev
);
4949 /* Return 1 on successful lock, 0 on contention */
4950 static int pci_dev_trylock(struct pci_dev
*dev
)
4952 if (pci_cfg_access_trylock(dev
)) {
4953 if (device_trylock(&dev
->dev
))
4955 pci_cfg_access_unlock(dev
);
4961 static void pci_dev_unlock(struct pci_dev
*dev
)
4963 device_unlock(&dev
->dev
);
4964 pci_cfg_access_unlock(dev
);
4967 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
4969 const struct pci_error_handlers
*err_handler
=
4970 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4973 * dev->driver->err_handler->reset_prepare() is protected against
4974 * races with ->remove() by the device lock, which must be held by
4977 if (err_handler
&& err_handler
->reset_prepare
)
4978 err_handler
->reset_prepare(dev
);
4981 * Wake-up device prior to save. PM registers default to D0 after
4982 * reset and a simple register restore doesn't reliably return
4983 * to a non-D0 state anyway.
4985 pci_set_power_state(dev
, PCI_D0
);
4987 pci_save_state(dev
);
4989 * Disable the device by clearing the Command register, except for
4990 * INTx-disable which is set. This not only disables MMIO and I/O port
4991 * BARs, but also prevents the device from being Bus Master, preventing
4992 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4993 * compliant devices, INTx-disable prevents legacy interrupts.
4995 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
4998 static void pci_dev_restore(struct pci_dev
*dev
)
5000 const struct pci_error_handlers
*err_handler
=
5001 dev
->driver
? dev
->driver
->err_handler
: NULL
;
5003 pci_restore_state(dev
);
5006 * dev->driver->err_handler->reset_done() is protected against
5007 * races with ->remove() by the device lock, which must be held by
5010 if (err_handler
&& err_handler
->reset_done
)
5011 err_handler
->reset_done(dev
);
5015 * __pci_reset_function_locked - reset a PCI device function while holding
5016 * the @dev mutex lock.
5017 * @dev: PCI device to reset
5019 * Some devices allow an individual function to be reset without affecting
5020 * other functions in the same device. The PCI device must be responsive
5021 * to PCI config space in order to use this function.
5023 * The device function is presumed to be unused and the caller is holding
5024 * the device mutex lock when this function is called.
5026 * Resetting the device will make the contents of PCI configuration space
5027 * random, so any caller of this must be prepared to reinitialise the
5028 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5031 * Returns 0 if the device function was successfully reset or negative if the
5032 * device doesn't support resetting a single function.
5034 int __pci_reset_function_locked(struct pci_dev
*dev
)
5041 * A reset method returns -ENOTTY if it doesn't support this device
5042 * and we should try the next method.
5044 * If it returns 0 (success), we're finished. If it returns any
5045 * other error, we're also finished: this indicates that further
5046 * reset mechanisms might be broken on the device.
5048 rc
= pci_dev_specific_reset(dev
, 0);
5051 if (pcie_has_flr(dev
)) {
5056 rc
= pci_af_flr(dev
, 0);
5059 rc
= pci_pm_reset(dev
, 0);
5062 rc
= pci_dev_reset_slot_function(dev
, 0);
5065 return pci_parent_bus_reset(dev
, 0);
5067 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
5070 * pci_probe_reset_function - check whether the device can be safely reset
5071 * @dev: PCI device to reset
5073 * Some devices allow an individual function to be reset without affecting
5074 * other functions in the same device. The PCI device must be responsive
5075 * to PCI config space in order to use this function.
5077 * Returns 0 if the device function can be reset or negative if the
5078 * device doesn't support resetting a single function.
5080 int pci_probe_reset_function(struct pci_dev
*dev
)
5086 rc
= pci_dev_specific_reset(dev
, 1);
5089 if (pcie_has_flr(dev
))
5091 rc
= pci_af_flr(dev
, 1);
5094 rc
= pci_pm_reset(dev
, 1);
5097 rc
= pci_dev_reset_slot_function(dev
, 1);
5101 return pci_parent_bus_reset(dev
, 1);
5105 * pci_reset_function - quiesce and reset a PCI device function
5106 * @dev: PCI device to reset
5108 * Some devices allow an individual function to be reset without affecting
5109 * other functions in the same device. The PCI device must be responsive
5110 * to PCI config space in order to use this function.
5112 * This function does not just reset the PCI portion of a device, but
5113 * clears all the state associated with the device. This function differs
5114 * from __pci_reset_function_locked() in that it saves and restores device state
5115 * over the reset and takes the PCI device lock.
5117 * Returns 0 if the device function was successfully reset or negative if the
5118 * device doesn't support resetting a single function.
5120 int pci_reset_function(struct pci_dev
*dev
)
5128 pci_dev_save_and_disable(dev
);
5130 rc
= __pci_reset_function_locked(dev
);
5132 pci_dev_restore(dev
);
5133 pci_dev_unlock(dev
);
5137 EXPORT_SYMBOL_GPL(pci_reset_function
);
5140 * pci_reset_function_locked - quiesce and reset a PCI device function
5141 * @dev: PCI device to reset
5143 * Some devices allow an individual function to be reset without affecting
5144 * other functions in the same device. The PCI device must be responsive
5145 * to PCI config space in order to use this function.
5147 * This function does not just reset the PCI portion of a device, but
5148 * clears all the state associated with the device. This function differs
5149 * from __pci_reset_function_locked() in that it saves and restores device state
5150 * over the reset. It also differs from pci_reset_function() in that it
5151 * requires the PCI device lock to be held.
5153 * Returns 0 if the device function was successfully reset or negative if the
5154 * device doesn't support resetting a single function.
5156 int pci_reset_function_locked(struct pci_dev
*dev
)
5163 pci_dev_save_and_disable(dev
);
5165 rc
= __pci_reset_function_locked(dev
);
5167 pci_dev_restore(dev
);
5171 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
5174 * pci_try_reset_function - quiesce and reset a PCI device function
5175 * @dev: PCI device to reset
5177 * Same as above, except return -EAGAIN if unable to lock device.
5179 int pci_try_reset_function(struct pci_dev
*dev
)
5186 if (!pci_dev_trylock(dev
))
5189 pci_dev_save_and_disable(dev
);
5190 rc
= __pci_reset_function_locked(dev
);
5191 pci_dev_restore(dev
);
5192 pci_dev_unlock(dev
);
5196 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
5198 /* Do any devices on or below this bus prevent a bus reset? */
5199 static bool pci_bus_resetable(struct pci_bus
*bus
)
5201 struct pci_dev
*dev
;
5204 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5207 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5208 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5209 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5216 /* Lock devices from the top of the tree down */
5217 static void pci_bus_lock(struct pci_bus
*bus
)
5219 struct pci_dev
*dev
;
5221 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5223 if (dev
->subordinate
)
5224 pci_bus_lock(dev
->subordinate
);
5228 /* Unlock devices from the bottom of the tree up */
5229 static void pci_bus_unlock(struct pci_bus
*bus
)
5231 struct pci_dev
*dev
;
5233 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5234 if (dev
->subordinate
)
5235 pci_bus_unlock(dev
->subordinate
);
5236 pci_dev_unlock(dev
);
5240 /* Return 1 on successful lock, 0 on contention */
5241 static int pci_bus_trylock(struct pci_bus
*bus
)
5243 struct pci_dev
*dev
;
5245 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5246 if (!pci_dev_trylock(dev
))
5248 if (dev
->subordinate
) {
5249 if (!pci_bus_trylock(dev
->subordinate
)) {
5250 pci_dev_unlock(dev
);
5258 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
5259 if (dev
->subordinate
)
5260 pci_bus_unlock(dev
->subordinate
);
5261 pci_dev_unlock(dev
);
5266 /* Do any devices on or below this slot prevent a bus reset? */
5267 static bool pci_slot_resetable(struct pci_slot
*slot
)
5269 struct pci_dev
*dev
;
5271 if (slot
->bus
->self
&&
5272 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5275 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5276 if (!dev
->slot
|| dev
->slot
!= slot
)
5278 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5279 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5286 /* Lock devices from the top of the tree down */
5287 static void pci_slot_lock(struct pci_slot
*slot
)
5289 struct pci_dev
*dev
;
5291 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5292 if (!dev
->slot
|| dev
->slot
!= slot
)
5295 if (dev
->subordinate
)
5296 pci_bus_lock(dev
->subordinate
);
5300 /* Unlock devices from the bottom of the tree up */
5301 static void pci_slot_unlock(struct pci_slot
*slot
)
5303 struct pci_dev
*dev
;
5305 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5306 if (!dev
->slot
|| dev
->slot
!= slot
)
5308 if (dev
->subordinate
)
5309 pci_bus_unlock(dev
->subordinate
);
5310 pci_dev_unlock(dev
);
5314 /* Return 1 on successful lock, 0 on contention */
5315 static int pci_slot_trylock(struct pci_slot
*slot
)
5317 struct pci_dev
*dev
;
5319 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5320 if (!dev
->slot
|| dev
->slot
!= slot
)
5322 if (!pci_dev_trylock(dev
))
5324 if (dev
->subordinate
) {
5325 if (!pci_bus_trylock(dev
->subordinate
)) {
5326 pci_dev_unlock(dev
);
5334 list_for_each_entry_continue_reverse(dev
,
5335 &slot
->bus
->devices
, bus_list
) {
5336 if (!dev
->slot
|| dev
->slot
!= slot
)
5338 if (dev
->subordinate
)
5339 pci_bus_unlock(dev
->subordinate
);
5340 pci_dev_unlock(dev
);
5346 * Save and disable devices from the top of the tree down while holding
5347 * the @dev mutex lock for the entire tree.
5349 static void pci_bus_save_and_disable_locked(struct pci_bus
*bus
)
5351 struct pci_dev
*dev
;
5353 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5354 pci_dev_save_and_disable(dev
);
5355 if (dev
->subordinate
)
5356 pci_bus_save_and_disable_locked(dev
->subordinate
);
5361 * Restore devices from top of the tree down while holding @dev mutex lock
5362 * for the entire tree. Parent bridges need to be restored before we can
5363 * get to subordinate devices.
5365 static void pci_bus_restore_locked(struct pci_bus
*bus
)
5367 struct pci_dev
*dev
;
5369 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5370 pci_dev_restore(dev
);
5371 if (dev
->subordinate
)
5372 pci_bus_restore_locked(dev
->subordinate
);
5377 * Save and disable devices from the top of the tree down while holding
5378 * the @dev mutex lock for the entire tree.
5380 static void pci_slot_save_and_disable_locked(struct pci_slot
*slot
)
5382 struct pci_dev
*dev
;
5384 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5385 if (!dev
->slot
|| dev
->slot
!= slot
)
5387 pci_dev_save_and_disable(dev
);
5388 if (dev
->subordinate
)
5389 pci_bus_save_and_disable_locked(dev
->subordinate
);
5394 * Restore devices from top of the tree down while holding @dev mutex lock
5395 * for the entire tree. Parent bridges need to be restored before we can
5396 * get to subordinate devices.
5398 static void pci_slot_restore_locked(struct pci_slot
*slot
)
5400 struct pci_dev
*dev
;
5402 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5403 if (!dev
->slot
|| dev
->slot
!= slot
)
5405 pci_dev_restore(dev
);
5406 if (dev
->subordinate
)
5407 pci_bus_restore_locked(dev
->subordinate
);
5411 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
5415 if (!slot
|| !pci_slot_resetable(slot
))
5419 pci_slot_lock(slot
);
5423 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
5426 pci_slot_unlock(slot
);
5432 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5433 * @slot: PCI slot to probe
5435 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5437 int pci_probe_reset_slot(struct pci_slot
*slot
)
5439 return pci_slot_reset(slot
, 1);
5441 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
5444 * __pci_reset_slot - Try to reset a PCI slot
5445 * @slot: PCI slot to reset
5447 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5448 * independent of other slots. For instance, some slots may support slot power
5449 * control. In the case of a 1:1 bus to slot architecture, this function may
5450 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5451 * Generally a slot reset should be attempted before a bus reset. All of the
5452 * function of the slot and any subordinate buses behind the slot are reset
5453 * through this function. PCI config space of all devices in the slot and
5454 * behind the slot is saved before and restored after reset.
5456 * Same as above except return -EAGAIN if the slot cannot be locked
5458 static int __pci_reset_slot(struct pci_slot
*slot
)
5462 rc
= pci_slot_reset(slot
, 1);
5466 if (pci_slot_trylock(slot
)) {
5467 pci_slot_save_and_disable_locked(slot
);
5469 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
5470 pci_slot_restore_locked(slot
);
5471 pci_slot_unlock(slot
);
5478 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
5482 if (!bus
->self
|| !pci_bus_resetable(bus
))
5492 ret
= pci_bridge_secondary_bus_reset(bus
->self
);
5494 pci_bus_unlock(bus
);
5500 * pci_bus_error_reset - reset the bridge's subordinate bus
5501 * @bridge: The parent device that connects to the bus to reset
5503 * This function will first try to reset the slots on this bus if the method is
5504 * available. If slot reset fails or is not available, this will fall back to a
5505 * secondary bus reset.
5507 int pci_bus_error_reset(struct pci_dev
*bridge
)
5509 struct pci_bus
*bus
= bridge
->subordinate
;
5510 struct pci_slot
*slot
;
5515 mutex_lock(&pci_slot_mutex
);
5516 if (list_empty(&bus
->slots
))
5519 list_for_each_entry(slot
, &bus
->slots
, list
)
5520 if (pci_probe_reset_slot(slot
))
5523 list_for_each_entry(slot
, &bus
->slots
, list
)
5524 if (pci_slot_reset(slot
, 0))
5527 mutex_unlock(&pci_slot_mutex
);
5530 mutex_unlock(&pci_slot_mutex
);
5531 return pci_bus_reset(bridge
->subordinate
, 0);
5535 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5536 * @bus: PCI bus to probe
5538 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5540 int pci_probe_reset_bus(struct pci_bus
*bus
)
5542 return pci_bus_reset(bus
, 1);
5544 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
5547 * __pci_reset_bus - Try to reset a PCI bus
5548 * @bus: top level PCI bus to reset
5550 * Same as above except return -EAGAIN if the bus cannot be locked
5552 static int __pci_reset_bus(struct pci_bus
*bus
)
5556 rc
= pci_bus_reset(bus
, 1);
5560 if (pci_bus_trylock(bus
)) {
5561 pci_bus_save_and_disable_locked(bus
);
5563 rc
= pci_bridge_secondary_bus_reset(bus
->self
);
5564 pci_bus_restore_locked(bus
);
5565 pci_bus_unlock(bus
);
5573 * pci_reset_bus - Try to reset a PCI bus
5574 * @pdev: top level PCI device to reset via slot/bus
5576 * Same as above except return -EAGAIN if the bus cannot be locked
5578 int pci_reset_bus(struct pci_dev
*pdev
)
5580 return (!pci_probe_reset_slot(pdev
->slot
)) ?
5581 __pci_reset_slot(pdev
->slot
) : __pci_reset_bus(pdev
->bus
);
5583 EXPORT_SYMBOL_GPL(pci_reset_bus
);
5586 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5587 * @dev: PCI device to query
5589 * Returns mmrbc: maximum designed memory read count in bytes or
5590 * appropriate error value.
5592 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
5597 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5601 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5604 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
5606 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
5609 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5610 * @dev: PCI device to query
5612 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5615 int pcix_get_mmrbc(struct pci_dev
*dev
)
5620 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5624 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5627 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
5629 EXPORT_SYMBOL(pcix_get_mmrbc
);
5632 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5633 * @dev: PCI device to query
5634 * @mmrbc: maximum memory read count in bytes
5635 * valid values are 512, 1024, 2048, 4096
5637 * If possible sets maximum memory read byte count, some bridges have errata
5638 * that prevent this.
5640 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
5646 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
5649 v
= ffs(mmrbc
) - 10;
5651 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5655 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5658 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
5661 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5664 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
5666 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
5669 cmd
&= ~PCI_X_CMD_MAX_READ
;
5671 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
5676 EXPORT_SYMBOL(pcix_set_mmrbc
);
5679 * pcie_get_readrq - get PCI Express read request size
5680 * @dev: PCI device to query
5682 * Returns maximum memory read request in bytes or appropriate error value.
5684 int pcie_get_readrq(struct pci_dev
*dev
)
5688 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
5690 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5692 EXPORT_SYMBOL(pcie_get_readrq
);
5695 * pcie_set_readrq - set PCI Express maximum memory read request
5696 * @dev: PCI device to query
5697 * @rq: maximum memory read count in bytes
5698 * valid values are 128, 256, 512, 1024, 2048, 4096
5700 * If possible sets maximum memory read request in bytes
5702 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
5707 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
5711 * If using the "performance" PCIe config, we clamp the read rq
5712 * size to the max packet size to keep the host bridge from
5713 * generating requests larger than we can cope with.
5715 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
5716 int mps
= pcie_get_mps(dev
);
5722 v
= (ffs(rq
) - 8) << 12;
5724 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
5725 PCI_EXP_DEVCTL_READRQ
, v
);
5727 return pcibios_err_to_errno(ret
);
5729 EXPORT_SYMBOL(pcie_set_readrq
);
5732 * pcie_get_mps - get PCI Express maximum payload size
5733 * @dev: PCI device to query
5735 * Returns maximum payload size in bytes
5737 int pcie_get_mps(struct pci_dev
*dev
)
5741 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
5743 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
5745 EXPORT_SYMBOL(pcie_get_mps
);
5748 * pcie_set_mps - set PCI Express maximum payload size
5749 * @dev: PCI device to query
5750 * @mps: maximum payload size in bytes
5751 * valid values are 128, 256, 512, 1024, 2048, 4096
5753 * If possible sets maximum payload size
5755 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
5760 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
5764 if (v
> dev
->pcie_mpss
)
5768 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
5769 PCI_EXP_DEVCTL_PAYLOAD
, v
);
5771 return pcibios_err_to_errno(ret
);
5773 EXPORT_SYMBOL(pcie_set_mps
);
5776 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5777 * device and its bandwidth limitation
5778 * @dev: PCI device to query
5779 * @limiting_dev: storage for device causing the bandwidth limitation
5780 * @speed: storage for speed of limiting device
5781 * @width: storage for width of limiting device
5783 * Walk up the PCI device chain and find the point where the minimum
5784 * bandwidth is available. Return the bandwidth available there and (if
5785 * limiting_dev, speed, and width pointers are supplied) information about
5786 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5789 u32
pcie_bandwidth_available(struct pci_dev
*dev
, struct pci_dev
**limiting_dev
,
5790 enum pci_bus_speed
*speed
,
5791 enum pcie_link_width
*width
)
5794 enum pci_bus_speed next_speed
;
5795 enum pcie_link_width next_width
;
5799 *speed
= PCI_SPEED_UNKNOWN
;
5801 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
5806 pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
5808 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
5809 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
5810 PCI_EXP_LNKSTA_NLW_SHIFT
;
5812 next_bw
= next_width
* PCIE_SPEED2MBS_ENC(next_speed
);
5814 /* Check if current device limits the total bandwidth */
5815 if (!bw
|| next_bw
<= bw
) {
5819 *limiting_dev
= dev
;
5821 *speed
= next_speed
;
5823 *width
= next_width
;
5826 dev
= pci_upstream_bridge(dev
);
5831 EXPORT_SYMBOL(pcie_bandwidth_available
);
5834 * pcie_get_speed_cap - query for the PCI device's link speed capability
5835 * @dev: PCI device to query
5837 * Query the PCI device speed capability. Return the maximum link speed
5838 * supported by the device.
5840 enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev
*dev
)
5842 u32 lnkcap2
, lnkcap
;
5845 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
5846 * implementation note there recommends using the Supported Link
5847 * Speeds Vector in Link Capabilities 2 when supported.
5849 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
5850 * should use the Supported Link Speeds field in Link Capabilities,
5851 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
5853 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
5855 /* PCIe r3.0-compliant */
5857 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2
);
5859 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
5860 if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_5_0GB
)
5861 return PCIE_SPEED_5_0GT
;
5862 else if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_2_5GB
)
5863 return PCIE_SPEED_2_5GT
;
5865 return PCI_SPEED_UNKNOWN
;
5867 EXPORT_SYMBOL(pcie_get_speed_cap
);
5870 * pcie_get_width_cap - query for the PCI device's link width capability
5871 * @dev: PCI device to query
5873 * Query the PCI device width capability. Return the maximum link width
5874 * supported by the device.
5876 enum pcie_link_width
pcie_get_width_cap(struct pci_dev
*dev
)
5880 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
5882 return (lnkcap
& PCI_EXP_LNKCAP_MLW
) >> 4;
5884 return PCIE_LNK_WIDTH_UNKNOWN
;
5886 EXPORT_SYMBOL(pcie_get_width_cap
);
5889 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5891 * @speed: storage for link speed
5892 * @width: storage for link width
5894 * Calculate a PCI device's link bandwidth by querying for its link speed
5895 * and width, multiplying them, and applying encoding overhead. The result
5896 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5898 u32
pcie_bandwidth_capable(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
5899 enum pcie_link_width
*width
)
5901 *speed
= pcie_get_speed_cap(dev
);
5902 *width
= pcie_get_width_cap(dev
);
5904 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
)
5907 return *width
* PCIE_SPEED2MBS_ENC(*speed
);
5911 * __pcie_print_link_status - Report the PCI device's link speed and width
5912 * @dev: PCI device to query
5913 * @verbose: Print info even when enough bandwidth is available
5915 * If the available bandwidth at the device is less than the device is
5916 * capable of, report the device's maximum possible bandwidth and the
5917 * upstream link that limits its performance. If @verbose, always print
5918 * the available bandwidth, even if the device isn't constrained.
5920 void __pcie_print_link_status(struct pci_dev
*dev
, bool verbose
)
5922 enum pcie_link_width width
, width_cap
;
5923 enum pci_bus_speed speed
, speed_cap
;
5924 struct pci_dev
*limiting_dev
= NULL
;
5925 u32 bw_avail
, bw_cap
;
5927 bw_cap
= pcie_bandwidth_capable(dev
, &speed_cap
, &width_cap
);
5928 bw_avail
= pcie_bandwidth_available(dev
, &limiting_dev
, &speed
, &width
);
5930 if (bw_avail
>= bw_cap
&& verbose
)
5931 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5932 bw_cap
/ 1000, bw_cap
% 1000,
5933 pci_speed_string(speed_cap
), width_cap
);
5934 else if (bw_avail
< bw_cap
)
5935 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5936 bw_avail
/ 1000, bw_avail
% 1000,
5937 pci_speed_string(speed
), width
,
5938 limiting_dev
? pci_name(limiting_dev
) : "<unknown>",
5939 bw_cap
/ 1000, bw_cap
% 1000,
5940 pci_speed_string(speed_cap
), width_cap
);
5944 * pcie_print_link_status - Report the PCI device's link speed and width
5945 * @dev: PCI device to query
5947 * Report the available bandwidth at the device.
5949 void pcie_print_link_status(struct pci_dev
*dev
)
5951 __pcie_print_link_status(dev
, true);
5953 EXPORT_SYMBOL(pcie_print_link_status
);
5956 * pci_select_bars - Make BAR mask from the type of resource
5957 * @dev: the PCI device for which BAR mask is made
5958 * @flags: resource type mask to be selected
5960 * This helper routine makes bar mask from the type of resource.
5962 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
5965 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
5966 if (pci_resource_flags(dev
, i
) & flags
)
5970 EXPORT_SYMBOL(pci_select_bars
);
5972 /* Some architectures require additional programming to enable VGA */
5973 static arch_set_vga_state_t arch_set_vga_state
;
5975 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
5977 arch_set_vga_state
= func
; /* NULL disables */
5980 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
5981 unsigned int command_bits
, u32 flags
)
5983 if (arch_set_vga_state
)
5984 return arch_set_vga_state(dev
, decode
, command_bits
,
5990 * pci_set_vga_state - set VGA decode state on device and parents if requested
5991 * @dev: the PCI device
5992 * @decode: true = enable decoding, false = disable decoding
5993 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5994 * @flags: traverse ancestors and change bridges
5995 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5997 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
5998 unsigned int command_bits
, u32 flags
)
6000 struct pci_bus
*bus
;
6001 struct pci_dev
*bridge
;
6005 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
6007 /* ARCH specific VGA enables */
6008 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
6012 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
6013 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
6015 cmd
|= command_bits
;
6017 cmd
&= ~command_bits
;
6018 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
6021 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
6028 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6031 cmd
|= PCI_BRIDGE_CTL_VGA
;
6033 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
6034 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6043 bool pci_pr3_present(struct pci_dev
*pdev
)
6045 struct acpi_device
*adev
;
6050 adev
= ACPI_COMPANION(&pdev
->dev
);
6054 return adev
->power
.flags
.power_resources
&&
6055 acpi_has_method(adev
->handle
, "_PR3");
6057 EXPORT_SYMBOL_GPL(pci_pr3_present
);
6061 * pci_add_dma_alias - Add a DMA devfn alias for a device
6062 * @dev: the PCI device for which alias is added
6063 * @devfn_from: alias slot and function
6064 * @nr_devfns: number of subsequent devfns to alias
6066 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6067 * which is used to program permissible bus-devfn source addresses for DMA
6068 * requests in an IOMMU. These aliases factor into IOMMU group creation
6069 * and are useful for devices generating DMA requests beyond or different
6070 * from their logical bus-devfn. Examples include device quirks where the
6071 * device simply uses the wrong devfn, as well as non-transparent bridges
6072 * where the alias may be a proxy for devices in another domain.
6074 * IOMMU group creation is performed during device discovery or addition,
6075 * prior to any potential DMA mapping and therefore prior to driver probing
6076 * (especially for userspace assigned devices where IOMMU group definition
6077 * cannot be left as a userspace activity). DMA aliases should therefore
6078 * be configured via quirks, such as the PCI fixup header quirk.
6080 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn_from
, unsigned nr_devfns
)
6084 nr_devfns
= min(nr_devfns
, (unsigned) MAX_NR_DEVFNS
- devfn_from
);
6085 devfn_to
= devfn_from
+ nr_devfns
- 1;
6087 if (!dev
->dma_alias_mask
)
6088 dev
->dma_alias_mask
= bitmap_zalloc(MAX_NR_DEVFNS
, GFP_KERNEL
);
6089 if (!dev
->dma_alias_mask
) {
6090 pci_warn(dev
, "Unable to allocate DMA alias mask\n");
6094 bitmap_set(dev
->dma_alias_mask
, devfn_from
, nr_devfns
);
6097 pci_info(dev
, "Enabling fixed DMA alias to %02x.%d\n",
6098 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
));
6099 else if (nr_devfns
> 1)
6100 pci_info(dev
, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6101 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
),
6102 PCI_SLOT(devfn_to
), PCI_FUNC(devfn_to
));
6105 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
6107 return (dev1
->dma_alias_mask
&&
6108 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
6109 (dev2
->dma_alias_mask
&&
6110 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
)) ||
6111 pci_real_dma_dev(dev1
) == dev2
||
6112 pci_real_dma_dev(dev2
) == dev1
;
6115 bool pci_device_is_present(struct pci_dev
*pdev
)
6119 if (pci_dev_is_disconnected(pdev
))
6121 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
6123 EXPORT_SYMBOL_GPL(pci_device_is_present
);
6125 void pci_ignore_hotplug(struct pci_dev
*dev
)
6127 struct pci_dev
*bridge
= dev
->bus
->self
;
6129 dev
->ignore_hotplug
= 1;
6130 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6132 bridge
->ignore_hotplug
= 1;
6134 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
6137 * pci_real_dma_dev - Get PCI DMA device for PCI device
6138 * @dev: the PCI device that may have a PCI DMA alias
6140 * Permits the platform to provide architecture-specific functionality to
6141 * devices needing to alias DMA to another PCI device on another PCI bus. If
6142 * the PCI device is on the same bus, it is recommended to use
6143 * pci_add_dma_alias(). This is the default implementation. Architecture
6144 * implementations can override this.
6146 struct pci_dev __weak
*pci_real_dma_dev(struct pci_dev
*dev
)
6151 resource_size_t __weak
pcibios_default_alignment(void)
6157 * Arches that don't want to expose struct resource to userland as-is in
6158 * sysfs and /proc can implement their own pci_resource_to_user().
6160 void __weak
pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
6161 const struct resource
*rsrc
,
6162 resource_size_t
*start
, resource_size_t
*end
)
6164 *start
= rsrc
->start
;
6168 static char *resource_alignment_param
;
6169 static DEFINE_SPINLOCK(resource_alignment_lock
);
6172 * pci_specified_resource_alignment - get resource alignment specified by user.
6173 * @dev: the PCI device to get
6174 * @resize: whether or not to change resources' size when reassigning alignment
6176 * RETURNS: Resource alignment if it is specified.
6177 * Zero if it is not specified.
6179 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
6182 int align_order
, count
;
6183 resource_size_t align
= pcibios_default_alignment();
6187 spin_lock(&resource_alignment_lock
);
6188 p
= resource_alignment_param
;
6191 if (pci_has_flag(PCI_PROBE_ONLY
)) {
6193 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6199 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
6206 ret
= pci_dev_str_match(dev
, p
, &p
);
6209 if (align_order
== -1)
6212 align
= 1 << align_order
;
6214 } else if (ret
< 0) {
6215 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6220 if (*p
!= ';' && *p
!= ',') {
6221 /* End of param or invalid format */
6227 spin_unlock(&resource_alignment_lock
);
6231 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
6232 resource_size_t align
, bool resize
)
6234 struct resource
*r
= &dev
->resource
[bar
];
6235 resource_size_t size
;
6237 if (!(r
->flags
& IORESOURCE_MEM
))
6240 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
6241 pci_info(dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
6242 bar
, r
, (unsigned long long)align
);
6246 size
= resource_size(r
);
6251 * Increase the alignment of the resource. There are two ways we
6254 * 1) Increase the size of the resource. BARs are aligned on their
6255 * size, so when we reallocate space for this resource, we'll
6256 * allocate it with the larger alignment. This also prevents
6257 * assignment of any other BARs inside the alignment region, so
6258 * if we're requesting page alignment, this means no other BARs
6259 * will share the page.
6261 * The disadvantage is that this makes the resource larger than
6262 * the hardware BAR, which may break drivers that compute things
6263 * based on the resource size, e.g., to find registers at a
6264 * fixed offset before the end of the BAR.
6266 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6267 * set r->start to the desired alignment. By itself this
6268 * doesn't prevent other BARs being put inside the alignment
6269 * region, but if we realign *every* resource of every device in
6270 * the system, none of them will share an alignment region.
6272 * When the user has requested alignment for only some devices via
6273 * the "pci=resource_alignment" argument, "resize" is true and we
6274 * use the first method. Otherwise we assume we're aligning all
6275 * devices and we use the second.
6278 pci_info(dev
, "BAR%d %pR: requesting alignment to %#llx\n",
6279 bar
, r
, (unsigned long long)align
);
6285 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
6286 r
->flags
|= IORESOURCE_STARTALIGN
;
6288 r
->end
= r
->start
+ size
- 1;
6290 r
->flags
|= IORESOURCE_UNSET
;
6294 * This function disables memory decoding and releases memory resources
6295 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6296 * It also rounds up size to specified alignment.
6297 * Later on, the kernel will assign page-aligned memory resource back
6300 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
6304 resource_size_t align
;
6306 bool resize
= false;
6309 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6310 * 3.4.1.11. Their resources are allocated from the space
6311 * described by the VF BARx register in the PF's SR-IOV capability.
6312 * We can't influence their alignment here.
6317 /* check if specified PCI is target device to reassign */
6318 align
= pci_specified_resource_alignment(dev
, &resize
);
6322 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
6323 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
6324 pci_warn(dev
, "Can't reassign resources to host bridge\n");
6328 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
6329 command
&= ~PCI_COMMAND_MEMORY
;
6330 pci_write_config_word(dev
, PCI_COMMAND
, command
);
6332 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
6333 pci_request_resource_alignment(dev
, i
, align
, resize
);
6336 * Need to disable bridge's resource window,
6337 * to enable the kernel to reassign new resource
6340 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
6341 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
6342 r
= &dev
->resource
[i
];
6343 if (!(r
->flags
& IORESOURCE_MEM
))
6345 r
->flags
|= IORESOURCE_UNSET
;
6346 r
->end
= resource_size(r
) - 1;
6349 pci_disable_bridge_window(dev
);
6353 static ssize_t
resource_alignment_show(struct bus_type
*bus
, char *buf
)
6357 spin_lock(&resource_alignment_lock
);
6358 if (resource_alignment_param
)
6359 count
= scnprintf(buf
, PAGE_SIZE
, "%s", resource_alignment_param
);
6360 spin_unlock(&resource_alignment_lock
);
6363 * When set by the command line, resource_alignment_param will not
6364 * have a trailing line feed, which is ugly. So conditionally add
6367 if (count
>= 2 && buf
[count
- 2] != '\n' && count
< PAGE_SIZE
- 1) {
6368 buf
[count
- 1] = '\n';
6375 static ssize_t
resource_alignment_store(struct bus_type
*bus
,
6376 const char *buf
, size_t count
)
6378 char *param
= kstrndup(buf
, count
, GFP_KERNEL
);
6383 spin_lock(&resource_alignment_lock
);
6384 kfree(resource_alignment_param
);
6385 resource_alignment_param
= param
;
6386 spin_unlock(&resource_alignment_lock
);
6390 static BUS_ATTR_RW(resource_alignment
);
6392 static int __init
pci_resource_alignment_sysfs_init(void)
6394 return bus_create_file(&pci_bus_type
,
6395 &bus_attr_resource_alignment
);
6397 late_initcall(pci_resource_alignment_sysfs_init
);
6399 static void pci_no_domains(void)
6401 #ifdef CONFIG_PCI_DOMAINS
6402 pci_domains_supported
= 0;
6406 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6407 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
6409 static int pci_get_new_domain_nr(void)
6411 return atomic_inc_return(&__domain_nr
);
6414 static int of_pci_bus_find_domain_nr(struct device
*parent
)
6416 static int use_dt_domains
= -1;
6420 domain
= of_get_pci_domain_nr(parent
->of_node
);
6423 * Check DT domain and use_dt_domains values.
6425 * If DT domain property is valid (domain >= 0) and
6426 * use_dt_domains != 0, the DT assignment is valid since this means
6427 * we have not previously allocated a domain number by using
6428 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6429 * 1, to indicate that we have just assigned a domain number from
6432 * If DT domain property value is not valid (ie domain < 0), and we
6433 * have not previously assigned a domain number from DT
6434 * (use_dt_domains != 1) we should assign a domain number by
6437 * pci_get_new_domain_nr()
6439 * API and update the use_dt_domains value to keep track of method we
6440 * are using to assign domain numbers (use_dt_domains = 0).
6442 * All other combinations imply we have a platform that is trying
6443 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6444 * which is a recipe for domain mishandling and it is prevented by
6445 * invalidating the domain value (domain = -1) and printing a
6446 * corresponding error.
6448 if (domain
>= 0 && use_dt_domains
) {
6450 } else if (domain
< 0 && use_dt_domains
!= 1) {
6452 domain
= pci_get_new_domain_nr();
6455 pr_err("Node %pOF has ", parent
->of_node
);
6456 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6463 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
6465 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
6466 acpi_pci_bus_find_domain_nr(bus
);
6471 * pci_ext_cfg_avail - can we access extended PCI config space?
6473 * Returns 1 if we can access PCI extended config space (offsets
6474 * greater than 0xff). This is the default implementation. Architecture
6475 * implementations can override this.
6477 int __weak
pci_ext_cfg_avail(void)
6482 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
6485 EXPORT_SYMBOL(pci_fixup_cardbus
);
6487 static int __init
pci_setup(char *str
)
6490 char *k
= strchr(str
, ',');
6493 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
6494 if (!strcmp(str
, "nomsi")) {
6496 } else if (!strncmp(str
, "noats", 5)) {
6497 pr_info("PCIe: ATS is disabled\n");
6498 pcie_ats_disabled
= true;
6499 } else if (!strcmp(str
, "noaer")) {
6501 } else if (!strcmp(str
, "earlydump")) {
6502 pci_early_dump
= true;
6503 } else if (!strncmp(str
, "realloc=", 8)) {
6504 pci_realloc_get_opt(str
+ 8);
6505 } else if (!strncmp(str
, "realloc", 7)) {
6506 pci_realloc_get_opt("on");
6507 } else if (!strcmp(str
, "nodomains")) {
6509 } else if (!strncmp(str
, "noari", 5)) {
6510 pcie_ari_disabled
= true;
6511 } else if (!strncmp(str
, "cbiosize=", 9)) {
6512 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
6513 } else if (!strncmp(str
, "cbmemsize=", 10)) {
6514 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
6515 } else if (!strncmp(str
, "resource_alignment=", 19)) {
6516 resource_alignment_param
= str
+ 19;
6517 } else if (!strncmp(str
, "ecrc=", 5)) {
6518 pcie_ecrc_get_policy(str
+ 5);
6519 } else if (!strncmp(str
, "hpiosize=", 9)) {
6520 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
6521 } else if (!strncmp(str
, "hpmmiosize=", 11)) {
6522 pci_hotplug_mmio_size
= memparse(str
+ 11, &str
);
6523 } else if (!strncmp(str
, "hpmmioprefsize=", 15)) {
6524 pci_hotplug_mmio_pref_size
= memparse(str
+ 15, &str
);
6525 } else if (!strncmp(str
, "hpmemsize=", 10)) {
6526 pci_hotplug_mmio_size
= memparse(str
+ 10, &str
);
6527 pci_hotplug_mmio_pref_size
= pci_hotplug_mmio_size
;
6528 } else if (!strncmp(str
, "hpbussize=", 10)) {
6529 pci_hotplug_bus_size
=
6530 simple_strtoul(str
+ 10, &str
, 0);
6531 if (pci_hotplug_bus_size
> 0xff)
6532 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
6533 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
6534 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
6535 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
6536 pcie_bus_config
= PCIE_BUS_SAFE
;
6537 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
6538 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
6539 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
6540 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
6541 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
6542 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
6543 } else if (!strncmp(str
, "disable_acs_redir=", 18)) {
6544 disable_acs_redir_param
= str
+ 18;
6546 pr_err("PCI: Unknown option `%s'\n", str
);
6553 early_param("pci", pci_setup
);
6556 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6557 * in pci_setup(), above, to point to data in the __initdata section which
6558 * will be freed after the init sequence is complete. We can't allocate memory
6559 * in pci_setup() because some architectures do not have any memory allocation
6560 * service available during an early_param() call. So we allocate memory and
6561 * copy the variable here before the init section is freed.
6564 static int __init
pci_realloc_setup_params(void)
6566 resource_alignment_param
= kstrdup(resource_alignment_param
,
6568 disable_acs_redir_param
= kstrdup(disable_acs_redir_param
, GFP_KERNEL
);
6572 pure_initcall(pci_realloc_setup_params
);