2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
14 #include <linux/of_pci.h>
15 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/string.h>
21 #include <linux/log2.h>
22 #include <linux/pci-aspm.h>
23 #include <linux/pm_wakeup.h>
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/pci_hotplug.h>
28 #include <asm-generic/pci-bridge.h>
29 #include <asm/setup.h>
30 #include <linux/aer.h>
33 const char *pci_power_names
[] = {
34 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
36 EXPORT_SYMBOL_GPL(pci_power_names
);
38 int isa_dma_bridge_buggy
;
39 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
42 EXPORT_SYMBOL(pci_pci_problems
);
44 unsigned int pci_pm_d3_delay
;
46 static void pci_pme_list_scan(struct work_struct
*work
);
48 static LIST_HEAD(pci_pme_list
);
49 static DEFINE_MUTEX(pci_pme_list_mutex
);
50 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
52 struct pci_pme_device
{
53 struct list_head list
;
57 #define PME_TIMEOUT 1000 /* How long between PME checks */
59 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
61 unsigned int delay
= dev
->d3_delay
;
63 if (delay
< pci_pm_d3_delay
)
64 delay
= pci_pm_d3_delay
;
69 #ifdef CONFIG_PCI_DOMAINS
70 int pci_domains_supported
= 1;
73 #define DEFAULT_CARDBUS_IO_SIZE (256)
74 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
75 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
76 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
77 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
79 #define DEFAULT_HOTPLUG_IO_SIZE (256)
80 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
81 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
82 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
83 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
85 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
88 * The default CLS is used if arch didn't set CLS explicitly and not
89 * all pci devices agree on the same value. Arch can override either
90 * the dfl or actual value as it sees fit. Don't forget this is
91 * measured in 32-bit words, not bytes.
93 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
94 u8 pci_cache_line_size
;
97 * If we set up a device for bus mastering, we need to check the latency
98 * timer as certain BIOSes forget to set it properly.
100 unsigned int pcibios_max_latency
= 255;
102 /* If set, the PCIe ARI capability will not be used. */
103 static bool pcie_ari_disabled
;
106 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
107 * @bus: pointer to PCI bus structure to search
109 * Given a PCI bus, returns the highest PCI bus number present in the set
110 * including the given PCI bus and its list of child PCI buses.
112 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
115 unsigned char max
, n
;
117 max
= bus
->busn_res
.end
;
118 list_for_each_entry(tmp
, &bus
->children
, node
) {
119 n
= pci_bus_max_busnr(tmp
);
125 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
127 #ifdef CONFIG_HAS_IOMEM
128 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
130 struct resource
*res
= &pdev
->resource
[bar
];
133 * Make sure the BAR is actually a memory resource, not an IO resource
135 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
136 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
139 return ioremap_nocache(res
->start
, resource_size(res
));
141 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
143 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
146 * Make sure the BAR is actually a memory resource, not an IO resource
148 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
152 return ioremap_wc(pci_resource_start(pdev
, bar
),
153 pci_resource_len(pdev
, bar
));
155 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
159 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
160 u8 pos
, int cap
, int *ttl
)
165 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
171 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
183 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
186 int ttl
= PCI_FIND_CAP_TTL
;
188 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
191 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
193 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
194 pos
+ PCI_CAP_LIST_NEXT
, cap
);
196 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
198 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
199 unsigned int devfn
, u8 hdr_type
)
203 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
204 if (!(status
& PCI_STATUS_CAP_LIST
))
208 case PCI_HEADER_TYPE_NORMAL
:
209 case PCI_HEADER_TYPE_BRIDGE
:
210 return PCI_CAPABILITY_LIST
;
211 case PCI_HEADER_TYPE_CARDBUS
:
212 return PCI_CB_CAPABILITY_LIST
;
219 * pci_find_capability - query for devices' capabilities
220 * @dev: PCI device to query
221 * @cap: capability code
223 * Tell if a device supports a given PCI capability.
224 * Returns the address of the requested capability structure within the
225 * device's PCI configuration space or 0 in case the device does not
226 * support it. Possible values for @cap:
228 * %PCI_CAP_ID_PM Power Management
229 * %PCI_CAP_ID_AGP Accelerated Graphics Port
230 * %PCI_CAP_ID_VPD Vital Product Data
231 * %PCI_CAP_ID_SLOTID Slot Identification
232 * %PCI_CAP_ID_MSI Message Signalled Interrupts
233 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
234 * %PCI_CAP_ID_PCIX PCI-X
235 * %PCI_CAP_ID_EXP PCI Express
237 int pci_find_capability(struct pci_dev
*dev
, int cap
)
241 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
243 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
247 EXPORT_SYMBOL(pci_find_capability
);
250 * pci_bus_find_capability - query for devices' capabilities
251 * @bus: the PCI bus to query
252 * @devfn: PCI device to query
253 * @cap: capability code
255 * Like pci_find_capability() but works for pci devices that do not have a
256 * pci_dev structure set up yet.
258 * Returns the address of the requested capability structure within the
259 * device's PCI configuration space or 0 in case the device does not
262 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
267 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
269 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
271 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
275 EXPORT_SYMBOL(pci_bus_find_capability
);
278 * pci_find_next_ext_capability - Find an extended capability
279 * @dev: PCI device to query
280 * @start: address at which to start looking (0 to start at beginning of list)
281 * @cap: capability code
283 * Returns the address of the next matching extended capability structure
284 * within the device's PCI configuration space or 0 if the device does
285 * not support it. Some capabilities can occur several times, e.g., the
286 * vendor-specific capability, and this provides a way to find them all.
288 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
292 int pos
= PCI_CFG_SPACE_SIZE
;
294 /* minimum 8 bytes per capability */
295 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
297 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
303 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
307 * If we have no capabilities, this is indicated by cap ID,
308 * cap version and next pointer all being 0.
314 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
317 pos
= PCI_EXT_CAP_NEXT(header
);
318 if (pos
< PCI_CFG_SPACE_SIZE
)
321 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
327 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
330 * pci_find_ext_capability - Find an extended capability
331 * @dev: PCI device to query
332 * @cap: capability code
334 * Returns the address of the requested extended capability structure
335 * within the device's PCI configuration space or 0 if the device does
336 * not support it. Possible values for @cap:
338 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
339 * %PCI_EXT_CAP_ID_VC Virtual Channel
340 * %PCI_EXT_CAP_ID_DSN Device Serial Number
341 * %PCI_EXT_CAP_ID_PWR Power Budgeting
343 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
345 return pci_find_next_ext_capability(dev
, 0, cap
);
347 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
349 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
351 int rc
, ttl
= PCI_FIND_CAP_TTL
;
354 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
355 mask
= HT_3BIT_CAP_MASK
;
357 mask
= HT_5BIT_CAP_MASK
;
359 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
360 PCI_CAP_ID_HT
, &ttl
);
362 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
363 if (rc
!= PCIBIOS_SUCCESSFUL
)
366 if ((cap
& mask
) == ht_cap
)
369 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
370 pos
+ PCI_CAP_LIST_NEXT
,
371 PCI_CAP_ID_HT
, &ttl
);
377 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
378 * @dev: PCI device to query
379 * @pos: Position from which to continue searching
380 * @ht_cap: Hypertransport capability code
382 * To be used in conjunction with pci_find_ht_capability() to search for
383 * all capabilities matching @ht_cap. @pos should always be a value returned
384 * from pci_find_ht_capability().
386 * NB. To be 100% safe against broken PCI devices, the caller should take
387 * steps to avoid an infinite loop.
389 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
391 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
393 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
396 * pci_find_ht_capability - query a device's Hypertransport capabilities
397 * @dev: PCI device to query
398 * @ht_cap: Hypertransport capability code
400 * Tell if a device supports a given Hypertransport capability.
401 * Returns an address within the device's PCI configuration space
402 * or 0 in case the device does not support the request capability.
403 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
404 * which has a Hypertransport capability matching @ht_cap.
406 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
410 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
412 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
416 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
419 * pci_find_parent_resource - return resource region of parent bus of given region
420 * @dev: PCI device structure contains resources to be searched
421 * @res: child resource record for which parent is sought
423 * For given resource region of given device, return the resource
424 * region of parent bus the given region is contained in.
426 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
427 struct resource
*res
)
429 const struct pci_bus
*bus
= dev
->bus
;
433 pci_bus_for_each_resource(bus
, r
, i
) {
436 if (res
->start
&& resource_contains(r
, res
)) {
439 * If the window is prefetchable but the BAR is
440 * not, the allocator made a mistake.
442 if (r
->flags
& IORESOURCE_PREFETCH
&&
443 !(res
->flags
& IORESOURCE_PREFETCH
))
447 * If we're below a transparent bridge, there may
448 * be both a positively-decoded aperture and a
449 * subtractively-decoded region that contain the BAR.
450 * We want the positively-decoded one, so this depends
451 * on pci_bus_for_each_resource() giving us those
459 EXPORT_SYMBOL(pci_find_parent_resource
);
462 * pci_find_pcie_root_port - return PCIe Root Port
463 * @dev: PCI device to query
465 * Traverse up the parent chain and return the PCIe Root Port PCI Device
466 * for a given PCI Device.
468 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
)
470 struct pci_dev
*bridge
, *highest_pcie_bridge
= NULL
;
472 bridge
= pci_upstream_bridge(dev
);
473 while (bridge
&& pci_is_pcie(bridge
)) {
474 highest_pcie_bridge
= bridge
;
475 bridge
= pci_upstream_bridge(bridge
);
478 if (pci_pcie_type(highest_pcie_bridge
) != PCI_EXP_TYPE_ROOT_PORT
)
481 return highest_pcie_bridge
;
483 EXPORT_SYMBOL(pci_find_pcie_root_port
);
486 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
487 * @dev: the PCI device to operate on
488 * @pos: config space offset of status word
489 * @mask: mask of bit(s) to care about in status word
491 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
493 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
497 /* Wait for Transaction Pending bit clean */
498 for (i
= 0; i
< 4; i
++) {
501 msleep((1 << (i
- 1)) * 100);
503 pci_read_config_word(dev
, pos
, &status
);
504 if (!(status
& mask
))
512 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
513 * @dev: PCI device to have its BARs restored
515 * Restore the BAR values for a given device, so as to make it
516 * accessible by its driver.
518 static void pci_restore_bars(struct pci_dev
*dev
)
522 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
523 pci_update_resource(dev
, i
);
526 static struct pci_platform_pm_ops
*pci_platform_pm
;
528 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
530 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
533 pci_platform_pm
= ops
;
537 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
539 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
542 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
545 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
548 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
550 return pci_platform_pm
?
551 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
554 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
556 return pci_platform_pm
?
557 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
560 static inline int platform_pci_run_wake(struct pci_dev
*dev
, bool enable
)
562 return pci_platform_pm
?
563 pci_platform_pm
->run_wake(dev
, enable
) : -ENODEV
;
566 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
568 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
572 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
574 * @dev: PCI device to handle.
575 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
578 * -EINVAL if the requested state is invalid.
579 * -EIO if device does not support PCI PM or its PM capabilities register has a
580 * wrong version, or device doesn't support the requested state.
581 * 0 if device already is in the requested state.
582 * 0 if device's power state has been successfully changed.
584 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
587 bool need_restore
= false;
589 /* Check if we're already there */
590 if (dev
->current_state
== state
)
596 if (state
< PCI_D0
|| state
> PCI_D3hot
)
599 /* Validate current state:
600 * Can enter D0 from any state, but if we can only go deeper
601 * to sleep if we're already in a low power state
603 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
604 && dev
->current_state
> state
) {
605 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
606 dev
->current_state
, state
);
610 /* check if this device supports the desired state */
611 if ((state
== PCI_D1
&& !dev
->d1_support
)
612 || (state
== PCI_D2
&& !dev
->d2_support
))
615 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
617 /* If we're (effectively) in D3, force entire word to 0.
618 * This doesn't affect PME_Status, disables PME_En, and
619 * sets PowerState to 0.
621 switch (dev
->current_state
) {
625 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
630 case PCI_UNKNOWN
: /* Boot-up */
631 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
632 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
634 /* Fall-through: force to D0 */
640 /* enter specified state */
641 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
643 /* Mandatory power management transition delays */
644 /* see PCI PM 1.1 5.6.1 table 18 */
645 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
646 pci_dev_d3_sleep(dev
);
647 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
648 udelay(PCI_PM_D2_DELAY
);
650 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
651 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
652 if (dev
->current_state
!= state
&& printk_ratelimit())
653 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
657 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
658 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
659 * from D3hot to D0 _may_ perform an internal reset, thereby
660 * going to "D0 Uninitialized" rather than "D0 Initialized".
661 * For example, at least some versions of the 3c905B and the
662 * 3c556B exhibit this behaviour.
664 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
665 * devices in a D3hot state at boot. Consequently, we need to
666 * restore at least the BARs so that the device will be
667 * accessible to its driver.
670 pci_restore_bars(dev
);
673 pcie_aspm_pm_state_change(dev
->bus
->self
);
679 * pci_update_current_state - Read PCI power state of given device from its
680 * PCI PM registers and cache it
681 * @dev: PCI device to handle.
682 * @state: State to cache in case the device doesn't have the PM capability
684 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
690 * Configuration space is not accessible for device in
691 * D3cold, so just keep or set D3cold for safety
693 if (dev
->current_state
== PCI_D3cold
)
695 if (state
== PCI_D3cold
) {
696 dev
->current_state
= PCI_D3cold
;
699 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
700 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
702 dev
->current_state
= state
;
707 * pci_power_up - Put the given device into D0 forcibly
708 * @dev: PCI device to power up
710 void pci_power_up(struct pci_dev
*dev
)
712 if (platform_pci_power_manageable(dev
))
713 platform_pci_set_power_state(dev
, PCI_D0
);
715 pci_raw_set_power_state(dev
, PCI_D0
);
716 pci_update_current_state(dev
, PCI_D0
);
720 * pci_platform_power_transition - Use platform to change device power state
721 * @dev: PCI device to handle.
722 * @state: State to put the device into.
724 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
728 if (platform_pci_power_manageable(dev
)) {
729 error
= platform_pci_set_power_state(dev
, state
);
731 pci_update_current_state(dev
, state
);
735 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
736 dev
->current_state
= PCI_D0
;
742 * pci_wakeup - Wake up a PCI device
743 * @pci_dev: Device to handle.
744 * @ign: ignored parameter
746 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
748 pci_wakeup_event(pci_dev
);
749 pm_request_resume(&pci_dev
->dev
);
754 * pci_wakeup_bus - Walk given bus and wake up devices on it
755 * @bus: Top bus of the subtree to walk.
757 static void pci_wakeup_bus(struct pci_bus
*bus
)
760 pci_walk_bus(bus
, pci_wakeup
, NULL
);
764 * __pci_start_power_transition - Start power transition of a PCI device
765 * @dev: PCI device to handle.
766 * @state: State to put the device into.
768 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
770 if (state
== PCI_D0
) {
771 pci_platform_power_transition(dev
, PCI_D0
);
773 * Mandatory power management transition delays, see
774 * PCI Express Base Specification Revision 2.0 Section
775 * 6.6.1: Conventional Reset. Do not delay for
776 * devices powered on/off by corresponding bridge,
777 * because have already delayed for the bridge.
779 if (dev
->runtime_d3cold
) {
780 msleep(dev
->d3cold_delay
);
782 * When powering on a bridge from D3cold, the
783 * whole hierarchy may be powered on into
784 * D0uninitialized state, resume them to give
785 * them a chance to suspend again
787 pci_wakeup_bus(dev
->subordinate
);
793 * __pci_dev_set_current_state - Set current state of a PCI device
794 * @dev: Device to handle
795 * @data: pointer to state to be set
797 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
799 pci_power_t state
= *(pci_power_t
*)data
;
801 dev
->current_state
= state
;
806 * __pci_bus_set_current_state - Walk given bus and set current state of devices
807 * @bus: Top bus of the subtree to walk.
808 * @state: state to be set
810 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
813 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
817 * __pci_complete_power_transition - Complete power transition of a PCI device
818 * @dev: PCI device to handle.
819 * @state: State to put the device into.
821 * This function should not be called directly by device drivers.
823 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
829 ret
= pci_platform_power_transition(dev
, state
);
830 /* Power off the bridge may power off the whole hierarchy */
831 if (!ret
&& state
== PCI_D3cold
)
832 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
835 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
838 * pci_set_power_state - Set the power state of a PCI device
839 * @dev: PCI device to handle.
840 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
842 * Transition a device to a new power state, using the platform firmware and/or
843 * the device's PCI PM registers.
846 * -EINVAL if the requested state is invalid.
847 * -EIO if device does not support PCI PM or its PM capabilities register has a
848 * wrong version, or device doesn't support the requested state.
849 * 0 if device already is in the requested state.
850 * 0 if device's power state has been successfully changed.
852 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
856 /* bound the state we're entering */
857 if (state
> PCI_D3cold
)
859 else if (state
< PCI_D0
)
861 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
863 * If the device or the parent bridge do not support PCI PM,
864 * ignore the request if we're doing anything other than putting
865 * it into D0 (which would only happen on boot).
869 /* Check if we're already there */
870 if (dev
->current_state
== state
)
873 __pci_start_power_transition(dev
, state
);
875 /* This device is quirked not to be put into D3, so
876 don't put it in D3 */
877 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
881 * To put device in D3cold, we put device into D3hot in native
882 * way, then put device into D3cold with platform ops
884 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
887 if (!__pci_complete_power_transition(dev
, state
))
892 EXPORT_SYMBOL(pci_set_power_state
);
895 * pci_choose_state - Choose the power state of a PCI device
896 * @dev: PCI device to be suspended
897 * @state: target sleep state for the whole system. This is the value
898 * that is passed to suspend() function.
900 * Returns PCI power state suitable for given device and given system
904 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
911 ret
= platform_pci_choose_state(dev
);
912 if (ret
!= PCI_POWER_ERROR
)
915 switch (state
.event
) {
918 case PM_EVENT_FREEZE
:
919 case PM_EVENT_PRETHAW
:
920 /* REVISIT both freeze and pre-thaw "should" use D0 */
921 case PM_EVENT_SUSPEND
:
922 case PM_EVENT_HIBERNATE
:
925 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
931 EXPORT_SYMBOL(pci_choose_state
);
933 #define PCI_EXP_SAVE_REGS 7
935 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
936 u16 cap
, bool extended
)
938 struct pci_cap_saved_state
*tmp
;
940 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
941 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
947 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
949 return _pci_find_saved_cap(dev
, cap
, false);
952 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
954 return _pci_find_saved_cap(dev
, cap
, true);
957 static int pci_save_pcie_state(struct pci_dev
*dev
)
960 struct pci_cap_saved_state
*save_state
;
963 if (!pci_is_pcie(dev
))
966 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
968 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
972 cap
= (u16
*)&save_state
->cap
.data
[0];
973 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
974 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
975 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
976 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
977 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
978 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
979 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
984 static void pci_restore_pcie_state(struct pci_dev
*dev
)
987 struct pci_cap_saved_state
*save_state
;
990 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
994 cap
= (u16
*)&save_state
->cap
.data
[0];
995 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
996 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
997 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
998 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
999 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1000 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1001 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1005 static int pci_save_pcix_state(struct pci_dev
*dev
)
1008 struct pci_cap_saved_state
*save_state
;
1010 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1014 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1016 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1020 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1021 (u16
*)save_state
->cap
.data
);
1026 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1029 struct pci_cap_saved_state
*save_state
;
1032 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1033 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1034 if (!save_state
|| !pos
)
1036 cap
= (u16
*)&save_state
->cap
.data
[0];
1038 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1043 * pci_save_state - save the PCI configuration space of a device before suspending
1044 * @dev: - PCI device that we're dealing with
1046 int pci_save_state(struct pci_dev
*dev
)
1049 /* XXX: 100% dword access ok here? */
1050 for (i
= 0; i
< 16; i
++)
1051 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1052 dev
->state_saved
= true;
1054 i
= pci_save_pcie_state(dev
);
1058 i
= pci_save_pcix_state(dev
);
1062 return pci_save_vc_state(dev
);
1064 EXPORT_SYMBOL(pci_save_state
);
1066 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1067 u32 saved_val
, int retry
)
1071 pci_read_config_dword(pdev
, offset
, &val
);
1072 if (val
== saved_val
)
1076 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1077 offset
, val
, saved_val
);
1078 pci_write_config_dword(pdev
, offset
, saved_val
);
1082 pci_read_config_dword(pdev
, offset
, &val
);
1083 if (val
== saved_val
)
1090 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1091 int start
, int end
, int retry
)
1095 for (index
= end
; index
>= start
; index
--)
1096 pci_restore_config_dword(pdev
, 4 * index
,
1097 pdev
->saved_config_space
[index
],
1101 static void pci_restore_config_space(struct pci_dev
*pdev
)
1103 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1104 pci_restore_config_space_range(pdev
, 10, 15, 0);
1105 /* Restore BARs before the command register. */
1106 pci_restore_config_space_range(pdev
, 4, 9, 10);
1107 pci_restore_config_space_range(pdev
, 0, 3, 0);
1109 pci_restore_config_space_range(pdev
, 0, 15, 0);
1114 * pci_restore_state - Restore the saved state of a PCI device
1115 * @dev: - PCI device that we're dealing with
1117 void pci_restore_state(struct pci_dev
*dev
)
1119 if (!dev
->state_saved
)
1122 /* PCI Express register must be restored first */
1123 pci_restore_pcie_state(dev
);
1124 pci_restore_ats_state(dev
);
1125 pci_restore_vc_state(dev
);
1127 pci_cleanup_aer_error_status_regs(dev
);
1129 pci_restore_config_space(dev
);
1131 pci_restore_pcix_state(dev
);
1132 pci_restore_msi_state(dev
);
1134 /* Restore ACS and IOV configuration state */
1135 pci_enable_acs(dev
);
1136 pci_restore_iov_state(dev
);
1138 dev
->state_saved
= false;
1140 EXPORT_SYMBOL(pci_restore_state
);
1142 struct pci_saved_state
{
1143 u32 config_space
[16];
1144 struct pci_cap_saved_data cap
[0];
1148 * pci_store_saved_state - Allocate and return an opaque struct containing
1149 * the device saved state.
1150 * @dev: PCI device that we're dealing with
1152 * Return NULL if no state or error.
1154 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1156 struct pci_saved_state
*state
;
1157 struct pci_cap_saved_state
*tmp
;
1158 struct pci_cap_saved_data
*cap
;
1161 if (!dev
->state_saved
)
1164 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1166 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1167 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1169 state
= kzalloc(size
, GFP_KERNEL
);
1173 memcpy(state
->config_space
, dev
->saved_config_space
,
1174 sizeof(state
->config_space
));
1177 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1178 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1179 memcpy(cap
, &tmp
->cap
, len
);
1180 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1182 /* Empty cap_save terminates list */
1186 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1189 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1190 * @dev: PCI device that we're dealing with
1191 * @state: Saved state returned from pci_store_saved_state()
1193 int pci_load_saved_state(struct pci_dev
*dev
,
1194 struct pci_saved_state
*state
)
1196 struct pci_cap_saved_data
*cap
;
1198 dev
->state_saved
= false;
1203 memcpy(dev
->saved_config_space
, state
->config_space
,
1204 sizeof(state
->config_space
));
1208 struct pci_cap_saved_state
*tmp
;
1210 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1211 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1214 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1215 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1216 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1219 dev
->state_saved
= true;
1222 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1225 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1226 * and free the memory allocated for it.
1227 * @dev: PCI device that we're dealing with
1228 * @state: Pointer to saved state returned from pci_store_saved_state()
1230 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1231 struct pci_saved_state
**state
)
1233 int ret
= pci_load_saved_state(dev
, *state
);
1238 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1240 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1242 return pci_enable_resources(dev
, bars
);
1245 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1248 struct pci_dev
*bridge
;
1252 err
= pci_set_power_state(dev
, PCI_D0
);
1253 if (err
< 0 && err
!= -EIO
)
1256 bridge
= pci_upstream_bridge(dev
);
1258 pcie_aspm_powersave_config_link(bridge
);
1260 err
= pcibios_enable_device(dev
, bars
);
1263 pci_fixup_device(pci_fixup_enable
, dev
);
1265 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1268 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1270 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1271 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1272 pci_write_config_word(dev
, PCI_COMMAND
,
1273 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1280 * pci_reenable_device - Resume abandoned device
1281 * @dev: PCI device to be resumed
1283 * Note this function is a backend of pci_default_resume and is not supposed
1284 * to be called by normal code, write proper resume handler and use it instead.
1286 int pci_reenable_device(struct pci_dev
*dev
)
1288 if (pci_is_enabled(dev
))
1289 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1292 EXPORT_SYMBOL(pci_reenable_device
);
1294 static void pci_enable_bridge(struct pci_dev
*dev
)
1296 struct pci_dev
*bridge
;
1299 bridge
= pci_upstream_bridge(dev
);
1301 pci_enable_bridge(bridge
);
1303 if (pci_is_enabled(dev
)) {
1304 if (!dev
->is_busmaster
)
1305 pci_set_master(dev
);
1309 retval
= pci_enable_device(dev
);
1311 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1313 pci_set_master(dev
);
1316 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1318 struct pci_dev
*bridge
;
1323 * Power state could be unknown at this point, either due to a fresh
1324 * boot or a device removal call. So get the current power state
1325 * so that things like MSI message writing will behave as expected
1326 * (e.g. if the device really is in D0 at enable time).
1330 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1331 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1334 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1335 return 0; /* already enabled */
1337 bridge
= pci_upstream_bridge(dev
);
1339 pci_enable_bridge(bridge
);
1341 /* only skip sriov related */
1342 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1343 if (dev
->resource
[i
].flags
& flags
)
1345 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1346 if (dev
->resource
[i
].flags
& flags
)
1349 err
= do_pci_enable_device(dev
, bars
);
1351 atomic_dec(&dev
->enable_cnt
);
1356 * pci_enable_device_io - Initialize a device for use with IO space
1357 * @dev: PCI device to be initialized
1359 * Initialize device before it's used by a driver. Ask low-level code
1360 * to enable I/O resources. Wake up the device if it was suspended.
1361 * Beware, this function can fail.
1363 int pci_enable_device_io(struct pci_dev
*dev
)
1365 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1367 EXPORT_SYMBOL(pci_enable_device_io
);
1370 * pci_enable_device_mem - Initialize a device for use with Memory space
1371 * @dev: PCI device to be initialized
1373 * Initialize device before it's used by a driver. Ask low-level code
1374 * to enable Memory resources. Wake up the device if it was suspended.
1375 * Beware, this function can fail.
1377 int pci_enable_device_mem(struct pci_dev
*dev
)
1379 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1381 EXPORT_SYMBOL(pci_enable_device_mem
);
1384 * pci_enable_device - Initialize device before it's used by a driver.
1385 * @dev: PCI device to be initialized
1387 * Initialize device before it's used by a driver. Ask low-level code
1388 * to enable I/O and memory. Wake up the device if it was suspended.
1389 * Beware, this function can fail.
1391 * Note we don't actually enable the device many times if we call
1392 * this function repeatedly (we just increment the count).
1394 int pci_enable_device(struct pci_dev
*dev
)
1396 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1398 EXPORT_SYMBOL(pci_enable_device
);
1401 * Managed PCI resources. This manages device on/off, intx/msi/msix
1402 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1403 * there's no need to track it separately. pci_devres is initialized
1404 * when a device is enabled using managed PCI device enable interface.
1407 unsigned int enabled
:1;
1408 unsigned int pinned
:1;
1409 unsigned int orig_intx
:1;
1410 unsigned int restore_intx
:1;
1414 static void pcim_release(struct device
*gendev
, void *res
)
1416 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
1417 struct pci_devres
*this = res
;
1420 if (dev
->msi_enabled
)
1421 pci_disable_msi(dev
);
1422 if (dev
->msix_enabled
)
1423 pci_disable_msix(dev
);
1425 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1426 if (this->region_mask
& (1 << i
))
1427 pci_release_region(dev
, i
);
1429 if (this->restore_intx
)
1430 pci_intx(dev
, this->orig_intx
);
1432 if (this->enabled
&& !this->pinned
)
1433 pci_disable_device(dev
);
1436 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1438 struct pci_devres
*dr
, *new_dr
;
1440 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1444 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1447 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1450 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1452 if (pci_is_managed(pdev
))
1453 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1458 * pcim_enable_device - Managed pci_enable_device()
1459 * @pdev: PCI device to be initialized
1461 * Managed pci_enable_device().
1463 int pcim_enable_device(struct pci_dev
*pdev
)
1465 struct pci_devres
*dr
;
1468 dr
= get_pci_dr(pdev
);
1474 rc
= pci_enable_device(pdev
);
1476 pdev
->is_managed
= 1;
1481 EXPORT_SYMBOL(pcim_enable_device
);
1484 * pcim_pin_device - Pin managed PCI device
1485 * @pdev: PCI device to pin
1487 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1488 * driver detach. @pdev must have been enabled with
1489 * pcim_enable_device().
1491 void pcim_pin_device(struct pci_dev
*pdev
)
1493 struct pci_devres
*dr
;
1495 dr
= find_pci_dr(pdev
);
1496 WARN_ON(!dr
|| !dr
->enabled
);
1500 EXPORT_SYMBOL(pcim_pin_device
);
1503 * pcibios_add_device - provide arch specific hooks when adding device dev
1504 * @dev: the PCI device being added
1506 * Permits the platform to provide architecture specific functionality when
1507 * devices are added. This is the default implementation. Architecture
1508 * implementations can override this.
1510 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1516 * pcibios_release_device - provide arch specific hooks when releasing device dev
1517 * @dev: the PCI device being released
1519 * Permits the platform to provide architecture specific functionality when
1520 * devices are released. This is the default implementation. Architecture
1521 * implementations can override this.
1523 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1526 * pcibios_disable_device - disable arch specific PCI resources for device dev
1527 * @dev: the PCI device to disable
1529 * Disables architecture specific PCI resources for the device. This
1530 * is the default implementation. Architecture implementations can
1533 void __weak
pcibios_disable_device (struct pci_dev
*dev
) {}
1536 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1537 * @irq: ISA IRQ to penalize
1538 * @active: IRQ active or not
1540 * Permits the platform to provide architecture-specific functionality when
1541 * penalizing ISA IRQs. This is the default implementation. Architecture
1542 * implementations can override this.
1544 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1546 static void do_pci_disable_device(struct pci_dev
*dev
)
1550 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1551 if (pci_command
& PCI_COMMAND_MASTER
) {
1552 pci_command
&= ~PCI_COMMAND_MASTER
;
1553 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1556 pcibios_disable_device(dev
);
1560 * pci_disable_enabled_device - Disable device without updating enable_cnt
1561 * @dev: PCI device to disable
1563 * NOTE: This function is a backend of PCI power management routines and is
1564 * not supposed to be called drivers.
1566 void pci_disable_enabled_device(struct pci_dev
*dev
)
1568 if (pci_is_enabled(dev
))
1569 do_pci_disable_device(dev
);
1573 * pci_disable_device - Disable PCI device after use
1574 * @dev: PCI device to be disabled
1576 * Signal to the system that the PCI device is not in use by the system
1577 * anymore. This only involves disabling PCI bus-mastering, if active.
1579 * Note we don't actually disable the device until all callers of
1580 * pci_enable_device() have called pci_disable_device().
1582 void pci_disable_device(struct pci_dev
*dev
)
1584 struct pci_devres
*dr
;
1586 dr
= find_pci_dr(dev
);
1590 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1591 "disabling already-disabled device");
1593 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1596 do_pci_disable_device(dev
);
1598 dev
->is_busmaster
= 0;
1600 EXPORT_SYMBOL(pci_disable_device
);
1603 * pcibios_set_pcie_reset_state - set reset state for device dev
1604 * @dev: the PCIe device reset
1605 * @state: Reset state to enter into
1608 * Sets the PCIe reset state for the device. This is the default
1609 * implementation. Architecture implementations can override this.
1611 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1612 enum pcie_reset_state state
)
1618 * pci_set_pcie_reset_state - set reset state for device dev
1619 * @dev: the PCIe device reset
1620 * @state: Reset state to enter into
1623 * Sets the PCI reset state for the device.
1625 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1627 return pcibios_set_pcie_reset_state(dev
, state
);
1629 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1632 * pci_check_pme_status - Check if given device has generated PME.
1633 * @dev: Device to check.
1635 * Check the PME status of the device and if set, clear it and clear PME enable
1636 * (if set). Return 'true' if PME status and PME enable were both set or
1637 * 'false' otherwise.
1639 bool pci_check_pme_status(struct pci_dev
*dev
)
1648 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1649 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1650 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1653 /* Clear PME status. */
1654 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1655 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1656 /* Disable PME to avoid interrupt flood. */
1657 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1661 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1667 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1668 * @dev: Device to handle.
1669 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1671 * Check if @dev has generated PME and queue a resume request for it in that
1674 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1676 if (pme_poll_reset
&& dev
->pme_poll
)
1677 dev
->pme_poll
= false;
1679 if (pci_check_pme_status(dev
)) {
1680 pci_wakeup_event(dev
);
1681 pm_request_resume(&dev
->dev
);
1687 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1688 * @bus: Top bus of the subtree to walk.
1690 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1693 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1698 * pci_pme_capable - check the capability of PCI device to generate PME#
1699 * @dev: PCI device to handle.
1700 * @state: PCI state from which device will issue PME#.
1702 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1707 return !!(dev
->pme_support
& (1 << state
));
1709 EXPORT_SYMBOL(pci_pme_capable
);
1711 static void pci_pme_list_scan(struct work_struct
*work
)
1713 struct pci_pme_device
*pme_dev
, *n
;
1715 mutex_lock(&pci_pme_list_mutex
);
1716 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1717 if (pme_dev
->dev
->pme_poll
) {
1718 struct pci_dev
*bridge
;
1720 bridge
= pme_dev
->dev
->bus
->self
;
1722 * If bridge is in low power state, the
1723 * configuration space of subordinate devices
1724 * may be not accessible
1726 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1728 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1730 list_del(&pme_dev
->list
);
1734 if (!list_empty(&pci_pme_list
))
1735 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
1736 msecs_to_jiffies(PME_TIMEOUT
));
1737 mutex_unlock(&pci_pme_list_mutex
);
1740 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
1744 if (!dev
->pme_support
)
1747 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1748 /* Clear PME_Status by writing 1 to it and enable PME# */
1749 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1751 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1753 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1757 * pci_pme_active - enable or disable PCI device's PME# function
1758 * @dev: PCI device to handle.
1759 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1761 * The caller must verify that the device is capable of generating PME# before
1762 * calling this function with @enable equal to 'true'.
1764 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1766 __pci_pme_active(dev
, enable
);
1769 * PCI (as opposed to PCIe) PME requires that the device have
1770 * its PME# line hooked up correctly. Not all hardware vendors
1771 * do this, so the PME never gets delivered and the device
1772 * remains asleep. The easiest way around this is to
1773 * periodically walk the list of suspended devices and check
1774 * whether any have their PME flag set. The assumption is that
1775 * we'll wake up often enough anyway that this won't be a huge
1776 * hit, and the power savings from the devices will still be a
1779 * Although PCIe uses in-band PME message instead of PME# line
1780 * to report PME, PME does not work for some PCIe devices in
1781 * reality. For example, there are devices that set their PME
1782 * status bits, but don't really bother to send a PME message;
1783 * there are PCI Express Root Ports that don't bother to
1784 * trigger interrupts when they receive PME messages from the
1785 * devices below. So PME poll is used for PCIe devices too.
1788 if (dev
->pme_poll
) {
1789 struct pci_pme_device
*pme_dev
;
1791 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1794 dev_warn(&dev
->dev
, "can't enable PME#\n");
1798 mutex_lock(&pci_pme_list_mutex
);
1799 list_add(&pme_dev
->list
, &pci_pme_list
);
1800 if (list_is_singular(&pci_pme_list
))
1801 queue_delayed_work(system_freezable_wq
,
1803 msecs_to_jiffies(PME_TIMEOUT
));
1804 mutex_unlock(&pci_pme_list_mutex
);
1806 mutex_lock(&pci_pme_list_mutex
);
1807 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1808 if (pme_dev
->dev
== dev
) {
1809 list_del(&pme_dev
->list
);
1814 mutex_unlock(&pci_pme_list_mutex
);
1818 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1820 EXPORT_SYMBOL(pci_pme_active
);
1823 * __pci_enable_wake - enable PCI device as wakeup event source
1824 * @dev: PCI device affected
1825 * @state: PCI state from which device will issue wakeup events
1826 * @runtime: True if the events are to be generated at run time
1827 * @enable: True to enable event generation; false to disable
1829 * This enables the device as a wakeup event source, or disables it.
1830 * When such events involves platform-specific hooks, those hooks are
1831 * called automatically by this routine.
1833 * Devices with legacy power management (no standard PCI PM capabilities)
1834 * always require such platform hooks.
1837 * 0 is returned on success
1838 * -EINVAL is returned if device is not supposed to wake up the system
1839 * Error code depending on the platform is returned if both the platform and
1840 * the native mechanism fail to enable the generation of wake-up events
1842 int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
,
1843 bool runtime
, bool enable
)
1847 if (enable
&& !runtime
&& !device_may_wakeup(&dev
->dev
))
1850 /* Don't do the same thing twice in a row for one device. */
1851 if (!!enable
== !!dev
->wakeup_prepared
)
1855 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1856 * Anderson we should be doing PME# wake enable followed by ACPI wake
1857 * enable. To disable wake-up we call the platform first, for symmetry.
1863 if (pci_pme_capable(dev
, state
))
1864 pci_pme_active(dev
, true);
1867 error
= runtime
? platform_pci_run_wake(dev
, true) :
1868 platform_pci_sleep_wake(dev
, true);
1872 dev
->wakeup_prepared
= true;
1875 platform_pci_run_wake(dev
, false);
1877 platform_pci_sleep_wake(dev
, false);
1878 pci_pme_active(dev
, false);
1879 dev
->wakeup_prepared
= false;
1884 EXPORT_SYMBOL(__pci_enable_wake
);
1887 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1888 * @dev: PCI device to prepare
1889 * @enable: True to enable wake-up event generation; false to disable
1891 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1892 * and this function allows them to set that up cleanly - pci_enable_wake()
1893 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1894 * ordering constraints.
1896 * This function only returns error code if the device is not capable of
1897 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1898 * enable wake-up power for it.
1900 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1902 return pci_pme_capable(dev
, PCI_D3cold
) ?
1903 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1904 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1906 EXPORT_SYMBOL(pci_wake_from_d3
);
1909 * pci_target_state - find an appropriate low power state for a given PCI dev
1912 * Use underlying platform code to find a supported low power state for @dev.
1913 * If the platform can't manage @dev, return the deepest state from which it
1914 * can generate wake events, based on any available PME info.
1916 static pci_power_t
pci_target_state(struct pci_dev
*dev
)
1918 pci_power_t target_state
= PCI_D3hot
;
1920 if (platform_pci_power_manageable(dev
)) {
1922 * Call the platform to choose the target state of the device
1923 * and enable wake-up from this state if supported.
1925 pci_power_t state
= platform_pci_choose_state(dev
);
1928 case PCI_POWER_ERROR
:
1933 if (pci_no_d1d2(dev
))
1936 target_state
= state
;
1938 } else if (!dev
->pm_cap
) {
1939 target_state
= PCI_D0
;
1940 } else if (device_may_wakeup(&dev
->dev
)) {
1942 * Find the deepest state from which the device can generate
1943 * wake-up events, make it the target state and enable device
1946 if (dev
->pme_support
) {
1948 && !(dev
->pme_support
& (1 << target_state
)))
1953 return target_state
;
1957 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1958 * @dev: Device to handle.
1960 * Choose the power state appropriate for the device depending on whether
1961 * it can wake up the system and/or is power manageable by the platform
1962 * (PCI_D3hot is the default) and put the device into that state.
1964 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1966 pci_power_t target_state
= pci_target_state(dev
);
1969 if (target_state
== PCI_POWER_ERROR
)
1972 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1974 error
= pci_set_power_state(dev
, target_state
);
1977 pci_enable_wake(dev
, target_state
, false);
1981 EXPORT_SYMBOL(pci_prepare_to_sleep
);
1984 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1985 * @dev: Device to handle.
1987 * Disable device's system wake-up capability and put it into D0.
1989 int pci_back_from_sleep(struct pci_dev
*dev
)
1991 pci_enable_wake(dev
, PCI_D0
, false);
1992 return pci_set_power_state(dev
, PCI_D0
);
1994 EXPORT_SYMBOL(pci_back_from_sleep
);
1997 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1998 * @dev: PCI device being suspended.
2000 * Prepare @dev to generate wake-up events at run time and put it into a low
2003 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2005 pci_power_t target_state
= pci_target_state(dev
);
2008 if (target_state
== PCI_POWER_ERROR
)
2011 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2013 __pci_enable_wake(dev
, target_state
, true, pci_dev_run_wake(dev
));
2015 error
= pci_set_power_state(dev
, target_state
);
2018 __pci_enable_wake(dev
, target_state
, true, false);
2019 dev
->runtime_d3cold
= false;
2026 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2027 * @dev: Device to check.
2029 * Return true if the device itself is capable of generating wake-up events
2030 * (through the platform or using the native PCIe PME) or if the device supports
2031 * PME and one of its upstream bridges can generate wake-up events.
2033 bool pci_dev_run_wake(struct pci_dev
*dev
)
2035 struct pci_bus
*bus
= dev
->bus
;
2037 if (device_run_wake(&dev
->dev
))
2040 if (!dev
->pme_support
)
2043 /* PME-capable in principle, but not from the intended sleep state */
2044 if (!pci_pme_capable(dev
, pci_target_state(dev
)))
2047 while (bus
->parent
) {
2048 struct pci_dev
*bridge
= bus
->self
;
2050 if (device_run_wake(&bridge
->dev
))
2056 /* We have reached the root bus. */
2058 return device_run_wake(bus
->bridge
);
2062 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2065 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2066 * @pci_dev: Device to check.
2068 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2069 * reconfigured due to wakeup settings difference between system and runtime
2070 * suspend and the current power state of it is suitable for the upcoming
2071 * (system) transition.
2073 * If the device is not configured for system wakeup, disable PME for it before
2074 * returning 'true' to prevent it from waking up the system unnecessarily.
2076 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2078 struct device
*dev
= &pci_dev
->dev
;
2080 if (!pm_runtime_suspended(dev
)
2081 || pci_target_state(pci_dev
) != pci_dev
->current_state
2082 || platform_pci_need_resume(pci_dev
))
2086 * At this point the device is good to go unless it's been configured
2087 * to generate PME at the runtime suspend time, but it is not supposed
2088 * to wake up the system. In that case, simply disable PME for it
2089 * (it will have to be re-enabled on exit from system resume).
2091 * If the device's power state is D3cold and the platform check above
2092 * hasn't triggered, the device's configuration is suitable and we don't
2093 * need to manipulate it at all.
2095 spin_lock_irq(&dev
->power
.lock
);
2097 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
&&
2098 !device_may_wakeup(dev
))
2099 __pci_pme_active(pci_dev
, false);
2101 spin_unlock_irq(&dev
->power
.lock
);
2106 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2107 * @pci_dev: Device to handle.
2109 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2110 * it might have been disabled during the prepare phase of system suspend if
2111 * the device was not configured for system wakeup.
2113 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2115 struct device
*dev
= &pci_dev
->dev
;
2117 if (!pci_dev_run_wake(pci_dev
))
2120 spin_lock_irq(&dev
->power
.lock
);
2122 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2123 __pci_pme_active(pci_dev
, true);
2125 spin_unlock_irq(&dev
->power
.lock
);
2128 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2130 struct device
*dev
= &pdev
->dev
;
2131 struct device
*parent
= dev
->parent
;
2134 pm_runtime_get_sync(parent
);
2135 pm_runtime_get_noresume(dev
);
2137 * pdev->current_state is set to PCI_D3cold during suspending,
2138 * so wait until suspending completes
2140 pm_runtime_barrier(dev
);
2142 * Only need to resume devices in D3cold, because config
2143 * registers are still accessible for devices suspended but
2146 if (pdev
->current_state
== PCI_D3cold
)
2147 pm_runtime_resume(dev
);
2150 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2152 struct device
*dev
= &pdev
->dev
;
2153 struct device
*parent
= dev
->parent
;
2155 pm_runtime_put(dev
);
2157 pm_runtime_put_sync(parent
);
2161 * pci_pm_init - Initialize PM functions of given PCI device
2162 * @dev: PCI device to handle.
2164 void pci_pm_init(struct pci_dev
*dev
)
2169 pm_runtime_forbid(&dev
->dev
);
2170 pm_runtime_set_active(&dev
->dev
);
2171 pm_runtime_enable(&dev
->dev
);
2172 device_enable_async_suspend(&dev
->dev
);
2173 dev
->wakeup_prepared
= false;
2176 dev
->pme_support
= 0;
2178 /* find PCI PM capability in list */
2179 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2182 /* Check device's ability to generate PME# */
2183 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2185 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2186 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2187 pmc
& PCI_PM_CAP_VER_MASK
);
2192 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2193 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2194 dev
->d3cold_allowed
= true;
2196 dev
->d1_support
= false;
2197 dev
->d2_support
= false;
2198 if (!pci_no_d1d2(dev
)) {
2199 if (pmc
& PCI_PM_CAP_D1
)
2200 dev
->d1_support
= true;
2201 if (pmc
& PCI_PM_CAP_D2
)
2202 dev
->d2_support
= true;
2204 if (dev
->d1_support
|| dev
->d2_support
)
2205 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2206 dev
->d1_support
? " D1" : "",
2207 dev
->d2_support
? " D2" : "");
2210 pmc
&= PCI_PM_CAP_PME_MASK
;
2212 dev_printk(KERN_DEBUG
, &dev
->dev
,
2213 "PME# supported from%s%s%s%s%s\n",
2214 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2215 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2216 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2217 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2218 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2219 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2220 dev
->pme_poll
= true;
2222 * Make device's PM flags reflect the wake-up capability, but
2223 * let the user space enable it to wake up the system as needed.
2225 device_set_wakeup_capable(&dev
->dev
, true);
2226 /* Disable the PME# generation functionality */
2227 pci_pme_active(dev
, false);
2231 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
2233 unsigned long flags
= IORESOURCE_PCI_FIXED
;
2237 case PCI_EA_P_VF_MEM
:
2238 flags
|= IORESOURCE_MEM
;
2240 case PCI_EA_P_MEM_PREFETCH
:
2241 case PCI_EA_P_VF_MEM_PREFETCH
:
2242 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
2245 flags
|= IORESOURCE_IO
;
2254 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
2257 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
2258 return &dev
->resource
[bei
];
2259 #ifdef CONFIG_PCI_IOV
2260 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
2261 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
2262 return &dev
->resource
[PCI_IOV_RESOURCES
+
2263 bei
- PCI_EA_BEI_VF_BAR0
];
2265 else if (bei
== PCI_EA_BEI_ROM
)
2266 return &dev
->resource
[PCI_ROM_RESOURCE
];
2271 /* Read an Enhanced Allocation (EA) entry */
2272 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
2274 struct resource
*res
;
2275 int ent_size
, ent_offset
= offset
;
2276 resource_size_t start
, end
;
2277 unsigned long flags
;
2278 u32 dw0
, bei
, base
, max_offset
;
2280 bool support_64
= (sizeof(resource_size_t
) >= 8);
2282 pci_read_config_dword(dev
, ent_offset
, &dw0
);
2285 /* Entry size field indicates DWORDs after 1st */
2286 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
2288 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
2291 bei
= (dw0
& PCI_EA_BEI
) >> 4;
2292 prop
= (dw0
& PCI_EA_PP
) >> 8;
2295 * If the Property is in the reserved range, try the Secondary
2298 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
2299 prop
= (dw0
& PCI_EA_SP
) >> 16;
2300 if (prop
> PCI_EA_P_BRIDGE_IO
)
2303 res
= pci_ea_get_resource(dev
, bei
, prop
);
2305 dev_err(&dev
->dev
, "Unsupported EA entry BEI: %u\n", bei
);
2309 flags
= pci_ea_flags(dev
, prop
);
2311 dev_err(&dev
->dev
, "Unsupported EA properties: %#x\n", prop
);
2316 pci_read_config_dword(dev
, ent_offset
, &base
);
2317 start
= (base
& PCI_EA_FIELD_MASK
);
2320 /* Read MaxOffset */
2321 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
2324 /* Read Base MSBs (if 64-bit entry) */
2325 if (base
& PCI_EA_IS_64
) {
2328 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
2331 flags
|= IORESOURCE_MEM_64
;
2333 /* entry starts above 32-bit boundary, can't use */
2334 if (!support_64
&& base_upper
)
2338 start
|= ((u64
)base_upper
<< 32);
2341 end
= start
+ (max_offset
| 0x03);
2343 /* Read MaxOffset MSBs (if 64-bit entry) */
2344 if (max_offset
& PCI_EA_IS_64
) {
2345 u32 max_offset_upper
;
2347 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
2350 flags
|= IORESOURCE_MEM_64
;
2352 /* entry too big, can't use */
2353 if (!support_64
&& max_offset_upper
)
2357 end
+= ((u64
)max_offset_upper
<< 32);
2361 dev_err(&dev
->dev
, "EA Entry crosses address boundary\n");
2365 if (ent_size
!= ent_offset
- offset
) {
2367 "EA Entry Size (%d) does not match length read (%d)\n",
2368 ent_size
, ent_offset
- offset
);
2372 res
->name
= pci_name(dev
);
2377 if (bei
<= PCI_EA_BEI_BAR5
)
2378 dev_printk(KERN_DEBUG
, &dev
->dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2380 else if (bei
== PCI_EA_BEI_ROM
)
2381 dev_printk(KERN_DEBUG
, &dev
->dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2383 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
2384 dev_printk(KERN_DEBUG
, &dev
->dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2385 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
2387 dev_printk(KERN_DEBUG
, &dev
->dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2391 return offset
+ ent_size
;
2394 /* Enhanced Allocation Initalization */
2395 void pci_ea_init(struct pci_dev
*dev
)
2402 /* find PCI EA capability in list */
2403 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
2407 /* determine the number of entries */
2408 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
2410 num_ent
&= PCI_EA_NUM_ENT_MASK
;
2412 offset
= ea
+ PCI_EA_FIRST_ENT
;
2414 /* Skip DWORD 2 for type 1 functions */
2415 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2418 /* parse each EA entry */
2419 for (i
= 0; i
< num_ent
; ++i
)
2420 offset
= pci_ea_read(dev
, offset
);
2423 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2424 struct pci_cap_saved_state
*new_cap
)
2426 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2430 * _pci_add_cap_save_buffer - allocate buffer for saving given
2431 * capability registers
2432 * @dev: the PCI device
2433 * @cap: the capability to allocate the buffer for
2434 * @extended: Standard or Extended capability ID
2435 * @size: requested size of the buffer
2437 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2438 bool extended
, unsigned int size
)
2441 struct pci_cap_saved_state
*save_state
;
2444 pos
= pci_find_ext_capability(dev
, cap
);
2446 pos
= pci_find_capability(dev
, cap
);
2451 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2455 save_state
->cap
.cap_nr
= cap
;
2456 save_state
->cap
.cap_extended
= extended
;
2457 save_state
->cap
.size
= size
;
2458 pci_add_saved_cap(dev
, save_state
);
2463 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2465 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2468 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2470 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2474 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2475 * @dev: the PCI device
2477 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2481 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2482 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2485 "unable to preallocate PCI Express save buffer\n");
2487 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2490 "unable to preallocate PCI-X save buffer\n");
2492 pci_allocate_vc_save_buffers(dev
);
2495 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2497 struct pci_cap_saved_state
*tmp
;
2498 struct hlist_node
*n
;
2500 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2505 * pci_configure_ari - enable or disable ARI forwarding
2506 * @dev: the PCI device
2508 * If @dev and its upstream bridge both support ARI, enable ARI in the
2509 * bridge. Otherwise, disable ARI in the bridge.
2511 void pci_configure_ari(struct pci_dev
*dev
)
2514 struct pci_dev
*bridge
;
2516 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2519 bridge
= dev
->bus
->self
;
2523 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2524 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2527 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2528 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2529 PCI_EXP_DEVCTL2_ARI
);
2530 bridge
->ari_enabled
= 1;
2532 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2533 PCI_EXP_DEVCTL2_ARI
);
2534 bridge
->ari_enabled
= 0;
2538 static int pci_acs_enable
;
2541 * pci_request_acs - ask for ACS to be enabled if supported
2543 void pci_request_acs(void)
2549 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2550 * @dev: the PCI device
2552 static int pci_std_enable_acs(struct pci_dev
*dev
)
2558 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2562 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2563 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2565 /* Source Validation */
2566 ctrl
|= (cap
& PCI_ACS_SV
);
2568 /* P2P Request Redirect */
2569 ctrl
|= (cap
& PCI_ACS_RR
);
2571 /* P2P Completion Redirect */
2572 ctrl
|= (cap
& PCI_ACS_CR
);
2574 /* Upstream Forwarding */
2575 ctrl
|= (cap
& PCI_ACS_UF
);
2577 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2583 * pci_enable_acs - enable ACS if hardware support it
2584 * @dev: the PCI device
2586 void pci_enable_acs(struct pci_dev
*dev
)
2588 if (!pci_acs_enable
)
2591 if (!pci_std_enable_acs(dev
))
2594 pci_dev_specific_enable_acs(dev
);
2597 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2602 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2607 * Except for egress control, capabilities are either required
2608 * or only required if controllable. Features missing from the
2609 * capability field can therefore be assumed as hard-wired enabled.
2611 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2612 acs_flags
&= (cap
| PCI_ACS_EC
);
2614 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2615 return (ctrl
& acs_flags
) == acs_flags
;
2619 * pci_acs_enabled - test ACS against required flags for a given device
2620 * @pdev: device to test
2621 * @acs_flags: required PCI ACS flags
2623 * Return true if the device supports the provided flags. Automatically
2624 * filters out flags that are not implemented on multifunction devices.
2626 * Note that this interface checks the effective ACS capabilities of the
2627 * device rather than the actual capabilities. For instance, most single
2628 * function endpoints are not required to support ACS because they have no
2629 * opportunity for peer-to-peer access. We therefore return 'true'
2630 * regardless of whether the device exposes an ACS capability. This makes
2631 * it much easier for callers of this function to ignore the actual type
2632 * or topology of the device when testing ACS support.
2634 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2638 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2643 * Conventional PCI and PCI-X devices never support ACS, either
2644 * effectively or actually. The shared bus topology implies that
2645 * any device on the bus can receive or snoop DMA.
2647 if (!pci_is_pcie(pdev
))
2650 switch (pci_pcie_type(pdev
)) {
2652 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2653 * but since their primary interface is PCI/X, we conservatively
2654 * handle them as we would a non-PCIe device.
2656 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2658 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2659 * applicable... must never implement an ACS Extended Capability...".
2660 * This seems arbitrary, but we take a conservative interpretation
2661 * of this statement.
2663 case PCI_EXP_TYPE_PCI_BRIDGE
:
2664 case PCI_EXP_TYPE_RC_EC
:
2667 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2668 * implement ACS in order to indicate their peer-to-peer capabilities,
2669 * regardless of whether they are single- or multi-function devices.
2671 case PCI_EXP_TYPE_DOWNSTREAM
:
2672 case PCI_EXP_TYPE_ROOT_PORT
:
2673 return pci_acs_flags_enabled(pdev
, acs_flags
);
2675 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2676 * implemented by the remaining PCIe types to indicate peer-to-peer
2677 * capabilities, but only when they are part of a multifunction
2678 * device. The footnote for section 6.12 indicates the specific
2679 * PCIe types included here.
2681 case PCI_EXP_TYPE_ENDPOINT
:
2682 case PCI_EXP_TYPE_UPSTREAM
:
2683 case PCI_EXP_TYPE_LEG_END
:
2684 case PCI_EXP_TYPE_RC_END
:
2685 if (!pdev
->multifunction
)
2688 return pci_acs_flags_enabled(pdev
, acs_flags
);
2692 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2693 * to single function devices with the exception of downstream ports.
2699 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2700 * @start: starting downstream device
2701 * @end: ending upstream device or NULL to search to the root bus
2702 * @acs_flags: required flags
2704 * Walk up a device tree from start to end testing PCI ACS support. If
2705 * any step along the way does not support the required flags, return false.
2707 bool pci_acs_path_enabled(struct pci_dev
*start
,
2708 struct pci_dev
*end
, u16 acs_flags
)
2710 struct pci_dev
*pdev
, *parent
= start
;
2715 if (!pci_acs_enabled(pdev
, acs_flags
))
2718 if (pci_is_root_bus(pdev
->bus
))
2719 return (end
== NULL
);
2721 parent
= pdev
->bus
->self
;
2722 } while (pdev
!= end
);
2728 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2729 * @dev: the PCI device
2730 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2732 * Perform INTx swizzling for a device behind one level of bridge. This is
2733 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2734 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2735 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2736 * the PCI Express Base Specification, Revision 2.1)
2738 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
2742 if (pci_ari_enabled(dev
->bus
))
2745 slot
= PCI_SLOT(dev
->devfn
);
2747 return (((pin
- 1) + slot
) % 4) + 1;
2750 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
2758 while (!pci_is_root_bus(dev
->bus
)) {
2759 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2760 dev
= dev
->bus
->self
;
2767 * pci_common_swizzle - swizzle INTx all the way to root bridge
2768 * @dev: the PCI device
2769 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2771 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2772 * bridges all the way up to a PCI root bus.
2774 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
2778 while (!pci_is_root_bus(dev
->bus
)) {
2779 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
2780 dev
= dev
->bus
->self
;
2783 return PCI_SLOT(dev
->devfn
);
2785 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
2788 * pci_release_region - Release a PCI bar
2789 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2790 * @bar: BAR to release
2792 * Releases the PCI I/O and memory resources previously reserved by a
2793 * successful call to pci_request_region. Call this function only
2794 * after all use of the PCI regions has ceased.
2796 void pci_release_region(struct pci_dev
*pdev
, int bar
)
2798 struct pci_devres
*dr
;
2800 if (pci_resource_len(pdev
, bar
) == 0)
2802 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
2803 release_region(pci_resource_start(pdev
, bar
),
2804 pci_resource_len(pdev
, bar
));
2805 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
2806 release_mem_region(pci_resource_start(pdev
, bar
),
2807 pci_resource_len(pdev
, bar
));
2809 dr
= find_pci_dr(pdev
);
2811 dr
->region_mask
&= ~(1 << bar
);
2813 EXPORT_SYMBOL(pci_release_region
);
2816 * __pci_request_region - Reserved PCI I/O and memory resource
2817 * @pdev: PCI device whose resources are to be reserved
2818 * @bar: BAR to be reserved
2819 * @res_name: Name to be associated with resource.
2820 * @exclusive: whether the region access is exclusive or not
2822 * Mark the PCI region associated with PCI device @pdev BR @bar as
2823 * being reserved by owner @res_name. Do not access any
2824 * address inside the PCI regions unless this call returns
2827 * If @exclusive is set, then the region is marked so that userspace
2828 * is explicitly not allowed to map the resource via /dev/mem or
2829 * sysfs MMIO access.
2831 * Returns 0 on success, or %EBUSY on error. A warning
2832 * message is also printed on failure.
2834 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
2835 const char *res_name
, int exclusive
)
2837 struct pci_devres
*dr
;
2839 if (pci_resource_len(pdev
, bar
) == 0)
2842 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
2843 if (!request_region(pci_resource_start(pdev
, bar
),
2844 pci_resource_len(pdev
, bar
), res_name
))
2846 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
2847 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
2848 pci_resource_len(pdev
, bar
), res_name
,
2853 dr
= find_pci_dr(pdev
);
2855 dr
->region_mask
|= 1 << bar
;
2860 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
2861 &pdev
->resource
[bar
]);
2866 * pci_request_region - Reserve PCI I/O and memory resource
2867 * @pdev: PCI device whose resources are to be reserved
2868 * @bar: BAR to be reserved
2869 * @res_name: Name to be associated with resource
2871 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2872 * being reserved by owner @res_name. Do not access any
2873 * address inside the PCI regions unless this call returns
2876 * Returns 0 on success, or %EBUSY on error. A warning
2877 * message is also printed on failure.
2879 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
2881 return __pci_request_region(pdev
, bar
, res_name
, 0);
2883 EXPORT_SYMBOL(pci_request_region
);
2886 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2887 * @pdev: PCI device whose resources are to be reserved
2888 * @bar: BAR to be reserved
2889 * @res_name: Name to be associated with resource.
2891 * Mark the PCI region associated with PCI device @pdev BR @bar as
2892 * being reserved by owner @res_name. Do not access any
2893 * address inside the PCI regions unless this call returns
2896 * Returns 0 on success, or %EBUSY on error. A warning
2897 * message is also printed on failure.
2899 * The key difference that _exclusive makes it that userspace is
2900 * explicitly not allowed to map the resource via /dev/mem or
2903 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
2904 const char *res_name
)
2906 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
2908 EXPORT_SYMBOL(pci_request_region_exclusive
);
2911 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2912 * @pdev: PCI device whose resources were previously reserved
2913 * @bars: Bitmask of BARs to be released
2915 * Release selected PCI I/O and memory resources previously reserved.
2916 * Call this function only after all use of the PCI regions has ceased.
2918 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
2922 for (i
= 0; i
< 6; i
++)
2923 if (bars
& (1 << i
))
2924 pci_release_region(pdev
, i
);
2926 EXPORT_SYMBOL(pci_release_selected_regions
);
2928 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2929 const char *res_name
, int excl
)
2933 for (i
= 0; i
< 6; i
++)
2934 if (bars
& (1 << i
))
2935 if (__pci_request_region(pdev
, i
, res_name
, excl
))
2941 if (bars
& (1 << i
))
2942 pci_release_region(pdev
, i
);
2949 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2950 * @pdev: PCI device whose resources are to be reserved
2951 * @bars: Bitmask of BARs to be requested
2952 * @res_name: Name to be associated with resource
2954 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
2955 const char *res_name
)
2957 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
2959 EXPORT_SYMBOL(pci_request_selected_regions
);
2961 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
2962 const char *res_name
)
2964 return __pci_request_selected_regions(pdev
, bars
, res_name
,
2965 IORESOURCE_EXCLUSIVE
);
2967 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2970 * pci_release_regions - Release reserved PCI I/O and memory resources
2971 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2973 * Releases all PCI I/O and memory resources previously reserved by a
2974 * successful call to pci_request_regions. Call this function only
2975 * after all use of the PCI regions has ceased.
2978 void pci_release_regions(struct pci_dev
*pdev
)
2980 pci_release_selected_regions(pdev
, (1 << 6) - 1);
2982 EXPORT_SYMBOL(pci_release_regions
);
2985 * pci_request_regions - Reserved PCI I/O and memory resources
2986 * @pdev: PCI device whose resources are to be reserved
2987 * @res_name: Name to be associated with resource.
2989 * Mark all PCI regions associated with PCI device @pdev as
2990 * being reserved by owner @res_name. Do not access any
2991 * address inside the PCI regions unless this call returns
2994 * Returns 0 on success, or %EBUSY on error. A warning
2995 * message is also printed on failure.
2997 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
2999 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
3001 EXPORT_SYMBOL(pci_request_regions
);
3004 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3005 * @pdev: PCI device whose resources are to be reserved
3006 * @res_name: Name to be associated with resource.
3008 * Mark all PCI regions associated with PCI device @pdev as
3009 * being reserved by owner @res_name. Do not access any
3010 * address inside the PCI regions unless this call returns
3013 * pci_request_regions_exclusive() will mark the region so that
3014 * /dev/mem and the sysfs MMIO access will not be allowed.
3016 * Returns 0 on success, or %EBUSY on error. A warning
3017 * message is also printed on failure.
3019 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
3021 return pci_request_selected_regions_exclusive(pdev
,
3022 ((1 << 6) - 1), res_name
);
3024 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3027 * pci_remap_iospace - Remap the memory mapped I/O space
3028 * @res: Resource describing the I/O space
3029 * @phys_addr: physical address of range to be mapped
3031 * Remap the memory mapped I/O space described by the @res
3032 * and the CPU physical address @phys_addr into virtual address space.
3033 * Only architectures that have memory mapped IO functions defined
3034 * (and the PCI_IOBASE value defined) should call this function.
3036 int __weak
pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
3038 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3039 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3041 if (!(res
->flags
& IORESOURCE_IO
))
3044 if (res
->end
> IO_SPACE_LIMIT
)
3047 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
3048 pgprot_device(PAGE_KERNEL
));
3050 /* this architecture does not have memory mapped I/O space,
3051 so this function should never be called */
3052 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3057 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
3061 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
3063 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
3065 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
3066 if (cmd
!= old_cmd
) {
3067 dev_dbg(&dev
->dev
, "%s bus mastering\n",
3068 enable
? "enabling" : "disabling");
3069 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3071 dev
->is_busmaster
= enable
;
3075 * pcibios_setup - process "pci=" kernel boot arguments
3076 * @str: string used to pass in "pci=" kernel boot arguments
3078 * Process kernel boot arguments. This is the default implementation.
3079 * Architecture specific implementations can override this as necessary.
3081 char * __weak __init
pcibios_setup(char *str
)
3087 * pcibios_set_master - enable PCI bus-mastering for device dev
3088 * @dev: the PCI device to enable
3090 * Enables PCI bus-mastering for the device. This is the default
3091 * implementation. Architecture specific implementations can override
3092 * this if necessary.
3094 void __weak
pcibios_set_master(struct pci_dev
*dev
)
3098 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3099 if (pci_is_pcie(dev
))
3102 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
3104 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
3105 else if (lat
> pcibios_max_latency
)
3106 lat
= pcibios_max_latency
;
3110 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
3114 * pci_set_master - enables bus-mastering for device dev
3115 * @dev: the PCI device to enable
3117 * Enables bus-mastering on the device and calls pcibios_set_master()
3118 * to do the needed arch specific settings.
3120 void pci_set_master(struct pci_dev
*dev
)
3122 __pci_set_master(dev
, true);
3123 pcibios_set_master(dev
);
3125 EXPORT_SYMBOL(pci_set_master
);
3128 * pci_clear_master - disables bus-mastering for device dev
3129 * @dev: the PCI device to disable
3131 void pci_clear_master(struct pci_dev
*dev
)
3133 __pci_set_master(dev
, false);
3135 EXPORT_SYMBOL(pci_clear_master
);
3138 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3139 * @dev: the PCI device for which MWI is to be enabled
3141 * Helper function for pci_set_mwi.
3142 * Originally copied from drivers/net/acenic.c.
3143 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3145 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3147 int pci_set_cacheline_size(struct pci_dev
*dev
)
3151 if (!pci_cache_line_size
)
3154 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3155 equal to or multiple of the right value. */
3156 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3157 if (cacheline_size
>= pci_cache_line_size
&&
3158 (cacheline_size
% pci_cache_line_size
) == 0)
3161 /* Write the correct value. */
3162 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
3164 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3165 if (cacheline_size
== pci_cache_line_size
)
3168 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
3169 pci_cache_line_size
<< 2);
3173 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
3176 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3177 * @dev: the PCI device for which MWI is enabled
3179 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3181 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3183 int pci_set_mwi(struct pci_dev
*dev
)
3185 #ifdef PCI_DISABLE_MWI
3191 rc
= pci_set_cacheline_size(dev
);
3195 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3196 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
3197 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
3198 cmd
|= PCI_COMMAND_INVALIDATE
;
3199 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3204 EXPORT_SYMBOL(pci_set_mwi
);
3207 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3208 * @dev: the PCI device for which MWI is enabled
3210 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3211 * Callers are not required to check the return value.
3213 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3215 int pci_try_set_mwi(struct pci_dev
*dev
)
3217 #ifdef PCI_DISABLE_MWI
3220 return pci_set_mwi(dev
);
3223 EXPORT_SYMBOL(pci_try_set_mwi
);
3226 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3227 * @dev: the PCI device to disable
3229 * Disables PCI Memory-Write-Invalidate transaction on the device
3231 void pci_clear_mwi(struct pci_dev
*dev
)
3233 #ifndef PCI_DISABLE_MWI
3236 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3237 if (cmd
& PCI_COMMAND_INVALIDATE
) {
3238 cmd
&= ~PCI_COMMAND_INVALIDATE
;
3239 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3243 EXPORT_SYMBOL(pci_clear_mwi
);
3246 * pci_intx - enables/disables PCI INTx for device dev
3247 * @pdev: the PCI device to operate on
3248 * @enable: boolean: whether to enable or disable PCI INTx
3250 * Enables/disables PCI INTx for device dev
3252 void pci_intx(struct pci_dev
*pdev
, int enable
)
3254 u16 pci_command
, new;
3256 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
3259 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
3261 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
3263 if (new != pci_command
) {
3264 struct pci_devres
*dr
;
3266 pci_write_config_word(pdev
, PCI_COMMAND
, new);
3268 dr
= find_pci_dr(pdev
);
3269 if (dr
&& !dr
->restore_intx
) {
3270 dr
->restore_intx
= 1;
3271 dr
->orig_intx
= !enable
;
3275 EXPORT_SYMBOL_GPL(pci_intx
);
3278 * pci_intx_mask_supported - probe for INTx masking support
3279 * @dev: the PCI device to operate on
3281 * Check if the device dev support INTx masking via the config space
3284 bool pci_intx_mask_supported(struct pci_dev
*dev
)
3286 bool mask_supported
= false;
3289 if (dev
->broken_intx_masking
)
3292 pci_cfg_access_lock(dev
);
3294 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
3295 pci_write_config_word(dev
, PCI_COMMAND
,
3296 orig
^ PCI_COMMAND_INTX_DISABLE
);
3297 pci_read_config_word(dev
, PCI_COMMAND
, &new);
3300 * There's no way to protect against hardware bugs or detect them
3301 * reliably, but as long as we know what the value should be, let's
3302 * go ahead and check it.
3304 if ((new ^ orig
) & ~PCI_COMMAND_INTX_DISABLE
) {
3305 dev_err(&dev
->dev
, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3307 } else if ((new ^ orig
) & PCI_COMMAND_INTX_DISABLE
) {
3308 mask_supported
= true;
3309 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
3312 pci_cfg_access_unlock(dev
);
3313 return mask_supported
;
3315 EXPORT_SYMBOL_GPL(pci_intx_mask_supported
);
3317 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3319 struct pci_bus
*bus
= dev
->bus
;
3320 bool mask_updated
= true;
3321 u32 cmd_status_dword
;
3322 u16 origcmd
, newcmd
;
3323 unsigned long flags
;
3327 * We do a single dword read to retrieve both command and status.
3328 * Document assumptions that make this possible.
3330 BUILD_BUG_ON(PCI_COMMAND
% 4);
3331 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3333 raw_spin_lock_irqsave(&pci_lock
, flags
);
3335 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3337 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3340 * Check interrupt status register to see whether our device
3341 * triggered the interrupt (when masking) or the next IRQ is
3342 * already pending (when unmasking).
3344 if (mask
!= irq_pending
) {
3345 mask_updated
= false;
3349 origcmd
= cmd_status_dword
;
3350 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3352 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3353 if (newcmd
!= origcmd
)
3354 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3357 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3359 return mask_updated
;
3363 * pci_check_and_mask_intx - mask INTx on pending interrupt
3364 * @dev: the PCI device to operate on
3366 * Check if the device dev has its INTx line asserted, mask it and
3367 * return true in that case. False is returned if not interrupt was
3370 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3372 return pci_check_and_set_intx_mask(dev
, true);
3374 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3377 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3378 * @dev: the PCI device to operate on
3380 * Check if the device dev has its INTx line asserted, unmask it if not
3381 * and return true. False is returned and the mask remains active if
3382 * there was still an interrupt pending.
3384 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3386 return pci_check_and_set_intx_mask(dev
, false);
3388 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3390 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
3392 return dma_set_max_seg_size(&dev
->dev
, size
);
3394 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
3396 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
3398 return dma_set_seg_boundary(&dev
->dev
, mask
);
3400 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
3403 * pci_wait_for_pending_transaction - waits for pending transaction
3404 * @dev: the PCI device to operate on
3406 * Return 0 if transaction is pending 1 otherwise.
3408 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3410 if (!pci_is_pcie(dev
))
3413 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3414 PCI_EXP_DEVSTA_TRPND
);
3416 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3418 static int pcie_flr(struct pci_dev
*dev
, int probe
)
3422 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3423 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
3429 if (!pci_wait_for_pending_transaction(dev
))
3430 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
3432 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3437 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3442 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3446 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
3447 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
3454 * Wait for Transaction Pending bit to clear. A word-aligned test
3455 * is used, so we use the conrol offset rather than status and shift
3456 * the test bit to match.
3458 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
3459 PCI_AF_STATUS_TP
<< 8))
3460 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3462 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
3468 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3469 * @dev: Device to reset.
3470 * @probe: If set, only check if the device can be reset this way.
3472 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3473 * unset, it will be reinitialized internally when going from PCI_D3hot to
3474 * PCI_D0. If that's the case and the device is not in a low-power state
3475 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3477 * NOTE: This causes the caller to sleep for twice the device power transition
3478 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3479 * by default (i.e. unless the @dev's d3_delay field has a different value).
3480 * Moreover, only devices in D0 can be reset by this function.
3482 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
3486 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
3489 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
3490 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
3496 if (dev
->current_state
!= PCI_D0
)
3499 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3501 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3502 pci_dev_d3_sleep(dev
);
3504 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
3506 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
3507 pci_dev_d3_sleep(dev
);
3512 void pci_reset_secondary_bus(struct pci_dev
*dev
)
3516 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
3517 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
3518 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3520 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3521 * this to 2ms to ensure that we meet the minimum requirement.
3525 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
3526 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
3529 * Trhfa for conventional PCI is 2^25 clock cycles.
3530 * Assuming a minimum 33MHz clock this results in a 1s
3531 * delay before we can consider subordinate devices to
3532 * be re-initialized. PCIe has some ways to shorten this,
3533 * but we don't make use of them yet.
3538 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
3540 pci_reset_secondary_bus(dev
);
3544 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3545 * @dev: Bridge device
3547 * Use the bridge control register to assert reset on the secondary bus.
3548 * Devices on the secondary bus are left in power-on state.
3550 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
3552 pcibios_reset_secondary_bus(dev
);
3554 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
3556 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
3558 struct pci_dev
*pdev
;
3560 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
3561 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3564 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3571 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
3576 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
3580 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
3583 if (hotplug
->ops
->reset_slot
)
3584 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
3586 module_put(hotplug
->ops
->owner
);
3591 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
3593 struct pci_dev
*pdev
;
3595 if (dev
->subordinate
|| !dev
->slot
||
3596 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
3599 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
3600 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
3603 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
3606 static int __pci_dev_reset(struct pci_dev
*dev
, int probe
)
3612 rc
= pci_dev_specific_reset(dev
, probe
);
3616 rc
= pcie_flr(dev
, probe
);
3620 rc
= pci_af_flr(dev
, probe
);
3624 rc
= pci_pm_reset(dev
, probe
);
3628 rc
= pci_dev_reset_slot_function(dev
, probe
);
3632 rc
= pci_parent_bus_reset(dev
, probe
);
3637 static void pci_dev_lock(struct pci_dev
*dev
)
3639 pci_cfg_access_lock(dev
);
3640 /* block PM suspend, driver probe, etc. */
3641 device_lock(&dev
->dev
);
3644 /* Return 1 on successful lock, 0 on contention */
3645 static int pci_dev_trylock(struct pci_dev
*dev
)
3647 if (pci_cfg_access_trylock(dev
)) {
3648 if (device_trylock(&dev
->dev
))
3650 pci_cfg_access_unlock(dev
);
3656 static void pci_dev_unlock(struct pci_dev
*dev
)
3658 device_unlock(&dev
->dev
);
3659 pci_cfg_access_unlock(dev
);
3663 * pci_reset_notify - notify device driver of reset
3664 * @dev: device to be notified of reset
3665 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3668 * Must be called prior to device access being disabled and after device
3669 * access is restored.
3671 static void pci_reset_notify(struct pci_dev
*dev
, bool prepare
)
3673 const struct pci_error_handlers
*err_handler
=
3674 dev
->driver
? dev
->driver
->err_handler
: NULL
;
3675 if (err_handler
&& err_handler
->reset_notify
)
3676 err_handler
->reset_notify(dev
, prepare
);
3679 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
3681 pci_reset_notify(dev
, true);
3684 * Wake-up device prior to save. PM registers default to D0 after
3685 * reset and a simple register restore doesn't reliably return
3686 * to a non-D0 state anyway.
3688 pci_set_power_state(dev
, PCI_D0
);
3690 pci_save_state(dev
);
3692 * Disable the device by clearing the Command register, except for
3693 * INTx-disable which is set. This not only disables MMIO and I/O port
3694 * BARs, but also prevents the device from being Bus Master, preventing
3695 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3696 * compliant devices, INTx-disable prevents legacy interrupts.
3698 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
3701 static void pci_dev_restore(struct pci_dev
*dev
)
3703 pci_restore_state(dev
);
3704 pci_reset_notify(dev
, false);
3707 static int pci_dev_reset(struct pci_dev
*dev
, int probe
)
3714 rc
= __pci_dev_reset(dev
, probe
);
3717 pci_dev_unlock(dev
);
3723 * __pci_reset_function - reset a PCI device function
3724 * @dev: PCI device to reset
3726 * Some devices allow an individual function to be reset without affecting
3727 * other functions in the same device. The PCI device must be responsive
3728 * to PCI config space in order to use this function.
3730 * The device function is presumed to be unused when this function is called.
3731 * Resetting the device will make the contents of PCI configuration space
3732 * random, so any caller of this must be prepared to reinitialise the
3733 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3736 * Returns 0 if the device function was successfully reset or negative if the
3737 * device doesn't support resetting a single function.
3739 int __pci_reset_function(struct pci_dev
*dev
)
3741 return pci_dev_reset(dev
, 0);
3743 EXPORT_SYMBOL_GPL(__pci_reset_function
);
3746 * __pci_reset_function_locked - reset a PCI device function while holding
3747 * the @dev mutex lock.
3748 * @dev: PCI device to reset
3750 * Some devices allow an individual function to be reset without affecting
3751 * other functions in the same device. The PCI device must be responsive
3752 * to PCI config space in order to use this function.
3754 * The device function is presumed to be unused and the caller is holding
3755 * the device mutex lock when this function is called.
3756 * Resetting the device will make the contents of PCI configuration space
3757 * random, so any caller of this must be prepared to reinitialise the
3758 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3761 * Returns 0 if the device function was successfully reset or negative if the
3762 * device doesn't support resetting a single function.
3764 int __pci_reset_function_locked(struct pci_dev
*dev
)
3766 return __pci_dev_reset(dev
, 0);
3768 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
3771 * pci_probe_reset_function - check whether the device can be safely reset
3772 * @dev: PCI device to reset
3774 * Some devices allow an individual function to be reset without affecting
3775 * other functions in the same device. The PCI device must be responsive
3776 * to PCI config space in order to use this function.
3778 * Returns 0 if the device function can be reset or negative if the
3779 * device doesn't support resetting a single function.
3781 int pci_probe_reset_function(struct pci_dev
*dev
)
3783 return pci_dev_reset(dev
, 1);
3787 * pci_reset_function - quiesce and reset a PCI device function
3788 * @dev: PCI device to reset
3790 * Some devices allow an individual function to be reset without affecting
3791 * other functions in the same device. The PCI device must be responsive
3792 * to PCI config space in order to use this function.
3794 * This function does not just reset the PCI portion of a device, but
3795 * clears all the state associated with the device. This function differs
3796 * from __pci_reset_function in that it saves and restores device state
3799 * Returns 0 if the device function was successfully reset or negative if the
3800 * device doesn't support resetting a single function.
3802 int pci_reset_function(struct pci_dev
*dev
)
3806 rc
= pci_dev_reset(dev
, 1);
3810 pci_dev_save_and_disable(dev
);
3812 rc
= pci_dev_reset(dev
, 0);
3814 pci_dev_restore(dev
);
3818 EXPORT_SYMBOL_GPL(pci_reset_function
);
3821 * pci_try_reset_function - quiesce and reset a PCI device function
3822 * @dev: PCI device to reset
3824 * Same as above, except return -EAGAIN if unable to lock device.
3826 int pci_try_reset_function(struct pci_dev
*dev
)
3830 rc
= pci_dev_reset(dev
, 1);
3834 pci_dev_save_and_disable(dev
);
3836 if (pci_dev_trylock(dev
)) {
3837 rc
= __pci_dev_reset(dev
, 0);
3838 pci_dev_unlock(dev
);
3842 pci_dev_restore(dev
);
3846 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
3848 /* Do any devices on or below this bus prevent a bus reset? */
3849 static bool pci_bus_resetable(struct pci_bus
*bus
)
3851 struct pci_dev
*dev
;
3853 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3854 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3855 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3862 /* Lock devices from the top of the tree down */
3863 static void pci_bus_lock(struct pci_bus
*bus
)
3865 struct pci_dev
*dev
;
3867 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3869 if (dev
->subordinate
)
3870 pci_bus_lock(dev
->subordinate
);
3874 /* Unlock devices from the bottom of the tree up */
3875 static void pci_bus_unlock(struct pci_bus
*bus
)
3877 struct pci_dev
*dev
;
3879 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3880 if (dev
->subordinate
)
3881 pci_bus_unlock(dev
->subordinate
);
3882 pci_dev_unlock(dev
);
3886 /* Return 1 on successful lock, 0 on contention */
3887 static int pci_bus_trylock(struct pci_bus
*bus
)
3889 struct pci_dev
*dev
;
3891 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3892 if (!pci_dev_trylock(dev
))
3894 if (dev
->subordinate
) {
3895 if (!pci_bus_trylock(dev
->subordinate
)) {
3896 pci_dev_unlock(dev
);
3904 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
3905 if (dev
->subordinate
)
3906 pci_bus_unlock(dev
->subordinate
);
3907 pci_dev_unlock(dev
);
3912 /* Do any devices on or below this slot prevent a bus reset? */
3913 static bool pci_slot_resetable(struct pci_slot
*slot
)
3915 struct pci_dev
*dev
;
3917 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3918 if (!dev
->slot
|| dev
->slot
!= slot
)
3920 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
3921 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
3928 /* Lock devices from the top of the tree down */
3929 static void pci_slot_lock(struct pci_slot
*slot
)
3931 struct pci_dev
*dev
;
3933 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3934 if (!dev
->slot
|| dev
->slot
!= slot
)
3937 if (dev
->subordinate
)
3938 pci_bus_lock(dev
->subordinate
);
3942 /* Unlock devices from the bottom of the tree up */
3943 static void pci_slot_unlock(struct pci_slot
*slot
)
3945 struct pci_dev
*dev
;
3947 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3948 if (!dev
->slot
|| dev
->slot
!= slot
)
3950 if (dev
->subordinate
)
3951 pci_bus_unlock(dev
->subordinate
);
3952 pci_dev_unlock(dev
);
3956 /* Return 1 on successful lock, 0 on contention */
3957 static int pci_slot_trylock(struct pci_slot
*slot
)
3959 struct pci_dev
*dev
;
3961 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
3962 if (!dev
->slot
|| dev
->slot
!= slot
)
3964 if (!pci_dev_trylock(dev
))
3966 if (dev
->subordinate
) {
3967 if (!pci_bus_trylock(dev
->subordinate
)) {
3968 pci_dev_unlock(dev
);
3976 list_for_each_entry_continue_reverse(dev
,
3977 &slot
->bus
->devices
, bus_list
) {
3978 if (!dev
->slot
|| dev
->slot
!= slot
)
3980 if (dev
->subordinate
)
3981 pci_bus_unlock(dev
->subordinate
);
3982 pci_dev_unlock(dev
);
3987 /* Save and disable devices from the top of the tree down */
3988 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
3990 struct pci_dev
*dev
;
3992 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
3993 pci_dev_save_and_disable(dev
);
3994 if (dev
->subordinate
)
3995 pci_bus_save_and_disable(dev
->subordinate
);
4000 * Restore devices from top of the tree down - parent bridges need to be
4001 * restored before we can get to subordinate devices.
4003 static void pci_bus_restore(struct pci_bus
*bus
)
4005 struct pci_dev
*dev
;
4007 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4008 pci_dev_restore(dev
);
4009 if (dev
->subordinate
)
4010 pci_bus_restore(dev
->subordinate
);
4014 /* Save and disable devices from the top of the tree down */
4015 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
4017 struct pci_dev
*dev
;
4019 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4020 if (!dev
->slot
|| dev
->slot
!= slot
)
4022 pci_dev_save_and_disable(dev
);
4023 if (dev
->subordinate
)
4024 pci_bus_save_and_disable(dev
->subordinate
);
4029 * Restore devices from top of the tree down - parent bridges need to be
4030 * restored before we can get to subordinate devices.
4032 static void pci_slot_restore(struct pci_slot
*slot
)
4034 struct pci_dev
*dev
;
4036 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4037 if (!dev
->slot
|| dev
->slot
!= slot
)
4039 pci_dev_restore(dev
);
4040 if (dev
->subordinate
)
4041 pci_bus_restore(dev
->subordinate
);
4045 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
4049 if (!slot
|| !pci_slot_resetable(slot
))
4053 pci_slot_lock(slot
);
4057 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
4060 pci_slot_unlock(slot
);
4066 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4067 * @slot: PCI slot to probe
4069 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4071 int pci_probe_reset_slot(struct pci_slot
*slot
)
4073 return pci_slot_reset(slot
, 1);
4075 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
4078 * pci_reset_slot - reset a PCI slot
4079 * @slot: PCI slot to reset
4081 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4082 * independent of other slots. For instance, some slots may support slot power
4083 * control. In the case of a 1:1 bus to slot architecture, this function may
4084 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4085 * Generally a slot reset should be attempted before a bus reset. All of the
4086 * function of the slot and any subordinate buses behind the slot are reset
4087 * through this function. PCI config space of all devices in the slot and
4088 * behind the slot is saved before and restored after reset.
4090 * Return 0 on success, non-zero on error.
4092 int pci_reset_slot(struct pci_slot
*slot
)
4096 rc
= pci_slot_reset(slot
, 1);
4100 pci_slot_save_and_disable(slot
);
4102 rc
= pci_slot_reset(slot
, 0);
4104 pci_slot_restore(slot
);
4108 EXPORT_SYMBOL_GPL(pci_reset_slot
);
4111 * pci_try_reset_slot - Try to reset a PCI slot
4112 * @slot: PCI slot to reset
4114 * Same as above except return -EAGAIN if the slot cannot be locked
4116 int pci_try_reset_slot(struct pci_slot
*slot
)
4120 rc
= pci_slot_reset(slot
, 1);
4124 pci_slot_save_and_disable(slot
);
4126 if (pci_slot_trylock(slot
)) {
4128 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
4129 pci_slot_unlock(slot
);
4133 pci_slot_restore(slot
);
4137 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
4139 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
4141 if (!bus
->self
|| !pci_bus_resetable(bus
))
4151 pci_reset_bridge_secondary_bus(bus
->self
);
4153 pci_bus_unlock(bus
);
4159 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4160 * @bus: PCI bus to probe
4162 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4164 int pci_probe_reset_bus(struct pci_bus
*bus
)
4166 return pci_bus_reset(bus
, 1);
4168 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
4171 * pci_reset_bus - reset a PCI bus
4172 * @bus: top level PCI bus to reset
4174 * Do a bus reset on the given bus and any subordinate buses, saving
4175 * and restoring state of all devices.
4177 * Return 0 on success, non-zero on error.
4179 int pci_reset_bus(struct pci_bus
*bus
)
4183 rc
= pci_bus_reset(bus
, 1);
4187 pci_bus_save_and_disable(bus
);
4189 rc
= pci_bus_reset(bus
, 0);
4191 pci_bus_restore(bus
);
4195 EXPORT_SYMBOL_GPL(pci_reset_bus
);
4198 * pci_try_reset_bus - Try to reset a PCI bus
4199 * @bus: top level PCI bus to reset
4201 * Same as above except return -EAGAIN if the bus cannot be locked
4203 int pci_try_reset_bus(struct pci_bus
*bus
)
4207 rc
= pci_bus_reset(bus
, 1);
4211 pci_bus_save_and_disable(bus
);
4213 if (pci_bus_trylock(bus
)) {
4215 pci_reset_bridge_secondary_bus(bus
->self
);
4216 pci_bus_unlock(bus
);
4220 pci_bus_restore(bus
);
4224 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
4227 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4228 * @dev: PCI device to query
4230 * Returns mmrbc: maximum designed memory read count in bytes
4231 * or appropriate error value.
4233 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
4238 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4242 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4245 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
4247 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
4250 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4251 * @dev: PCI device to query
4253 * Returns mmrbc: maximum memory read count in bytes
4254 * or appropriate error value.
4256 int pcix_get_mmrbc(struct pci_dev
*dev
)
4261 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4265 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4268 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
4270 EXPORT_SYMBOL(pcix_get_mmrbc
);
4273 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4274 * @dev: PCI device to query
4275 * @mmrbc: maximum memory read count in bytes
4276 * valid values are 512, 1024, 2048, 4096
4278 * If possible sets maximum memory read byte count, some bridges have erratas
4279 * that prevent this.
4281 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4287 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4290 v
= ffs(mmrbc
) - 10;
4292 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4296 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4299 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4302 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4305 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4307 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4310 cmd
&= ~PCI_X_CMD_MAX_READ
;
4312 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4317 EXPORT_SYMBOL(pcix_set_mmrbc
);
4320 * pcie_get_readrq - get PCI Express read request size
4321 * @dev: PCI device to query
4323 * Returns maximum memory read request in bytes
4324 * or appropriate error value.
4326 int pcie_get_readrq(struct pci_dev
*dev
)
4330 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4332 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4334 EXPORT_SYMBOL(pcie_get_readrq
);
4337 * pcie_set_readrq - set PCI Express maximum memory read request
4338 * @dev: PCI device to query
4339 * @rq: maximum memory read count in bytes
4340 * valid values are 128, 256, 512, 1024, 2048, 4096
4342 * If possible sets maximum memory read request in bytes
4344 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4348 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4352 * If using the "performance" PCIe config, we clamp the
4353 * read rq size to the max packet size to prevent the
4354 * host bridge generating requests larger than we can
4357 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4358 int mps
= pcie_get_mps(dev
);
4364 v
= (ffs(rq
) - 8) << 12;
4366 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4367 PCI_EXP_DEVCTL_READRQ
, v
);
4369 EXPORT_SYMBOL(pcie_set_readrq
);
4372 * pcie_get_mps - get PCI Express maximum payload size
4373 * @dev: PCI device to query
4375 * Returns maximum payload size in bytes
4377 int pcie_get_mps(struct pci_dev
*dev
)
4381 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4383 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
4385 EXPORT_SYMBOL(pcie_get_mps
);
4388 * pcie_set_mps - set PCI Express maximum payload size
4389 * @dev: PCI device to query
4390 * @mps: maximum payload size in bytes
4391 * valid values are 128, 256, 512, 1024, 2048, 4096
4393 * If possible sets maximum payload size
4395 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
4399 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
4403 if (v
> dev
->pcie_mpss
)
4407 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4408 PCI_EXP_DEVCTL_PAYLOAD
, v
);
4410 EXPORT_SYMBOL(pcie_set_mps
);
4413 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4414 * @dev: PCI device to query
4415 * @speed: storage for minimum speed
4416 * @width: storage for minimum width
4418 * This function will walk up the PCI device chain and determine the minimum
4419 * link width and speed of the device.
4421 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
4422 enum pcie_link_width
*width
)
4426 *speed
= PCI_SPEED_UNKNOWN
;
4427 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
4431 enum pci_bus_speed next_speed
;
4432 enum pcie_link_width next_width
;
4434 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
4438 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
4439 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
4440 PCI_EXP_LNKSTA_NLW_SHIFT
;
4442 if (next_speed
< *speed
)
4443 *speed
= next_speed
;
4445 if (next_width
< *width
)
4446 *width
= next_width
;
4448 dev
= dev
->bus
->self
;
4453 EXPORT_SYMBOL(pcie_get_minimum_link
);
4456 * pci_select_bars - Make BAR mask from the type of resource
4457 * @dev: the PCI device for which BAR mask is made
4458 * @flags: resource type mask to be selected
4460 * This helper routine makes bar mask from the type of resource.
4462 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
4465 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
4466 if (pci_resource_flags(dev
, i
) & flags
)
4470 EXPORT_SYMBOL(pci_select_bars
);
4472 /* Some architectures require additional programming to enable VGA */
4473 static arch_set_vga_state_t arch_set_vga_state
;
4475 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
4477 arch_set_vga_state
= func
; /* NULL disables */
4480 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
4481 unsigned int command_bits
, u32 flags
)
4483 if (arch_set_vga_state
)
4484 return arch_set_vga_state(dev
, decode
, command_bits
,
4490 * pci_set_vga_state - set VGA decode state on device and parents if requested
4491 * @dev: the PCI device
4492 * @decode: true = enable decoding, false = disable decoding
4493 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4494 * @flags: traverse ancestors and change bridges
4495 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4497 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
4498 unsigned int command_bits
, u32 flags
)
4500 struct pci_bus
*bus
;
4501 struct pci_dev
*bridge
;
4505 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
4507 /* ARCH specific VGA enables */
4508 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
4512 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
4513 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4515 cmd
|= command_bits
;
4517 cmd
&= ~command_bits
;
4518 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4521 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
4528 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4531 cmd
|= PCI_BRIDGE_CTL_VGA
;
4533 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
4534 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
4542 bool pci_device_is_present(struct pci_dev
*pdev
)
4546 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
4548 EXPORT_SYMBOL_GPL(pci_device_is_present
);
4550 void pci_ignore_hotplug(struct pci_dev
*dev
)
4552 struct pci_dev
*bridge
= dev
->bus
->self
;
4554 dev
->ignore_hotplug
= 1;
4555 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4557 bridge
->ignore_hotplug
= 1;
4559 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
4561 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4562 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
4563 static DEFINE_SPINLOCK(resource_alignment_lock
);
4566 * pci_specified_resource_alignment - get resource alignment specified by user.
4567 * @dev: the PCI device to get
4569 * RETURNS: Resource alignment if it is specified.
4570 * Zero if it is not specified.
4572 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
4574 int seg
, bus
, slot
, func
, align_order
, count
;
4575 resource_size_t align
= 0;
4578 spin_lock(&resource_alignment_lock
);
4579 p
= resource_alignment_param
;
4582 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
4588 if (sscanf(p
, "%x:%x:%x.%x%n",
4589 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
4591 if (sscanf(p
, "%x:%x.%x%n",
4592 &bus
, &slot
, &func
, &count
) != 3) {
4593 /* Invalid format */
4594 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
4600 if (seg
== pci_domain_nr(dev
->bus
) &&
4601 bus
== dev
->bus
->number
&&
4602 slot
== PCI_SLOT(dev
->devfn
) &&
4603 func
== PCI_FUNC(dev
->devfn
)) {
4604 if (align_order
== -1)
4607 align
= 1 << align_order
;
4611 if (*p
!= ';' && *p
!= ',') {
4612 /* End of param or invalid format */
4617 spin_unlock(&resource_alignment_lock
);
4622 * This function disables memory decoding and releases memory resources
4623 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4624 * It also rounds up size to specified alignment.
4625 * Later on, the kernel will assign page-aligned memory resource back
4628 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
4632 resource_size_t align
, size
;
4635 /* check if specified PCI is target device to reassign */
4636 align
= pci_specified_resource_alignment(dev
);
4640 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
4641 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
4643 "Can't reassign resources to host bridge.\n");
4648 "Disabling memory decoding and releasing memory resources.\n");
4649 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
4650 command
&= ~PCI_COMMAND_MEMORY
;
4651 pci_write_config_word(dev
, PCI_COMMAND
, command
);
4653 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++) {
4654 r
= &dev
->resource
[i
];
4655 if (!(r
->flags
& IORESOURCE_MEM
))
4657 size
= resource_size(r
);
4661 "Rounding up size of resource #%d to %#llx.\n",
4662 i
, (unsigned long long)size
);
4664 r
->flags
|= IORESOURCE_UNSET
;
4668 /* Need to disable bridge's resource window,
4669 * to enable the kernel to reassign new resource
4672 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
4673 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
4674 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
4675 r
= &dev
->resource
[i
];
4676 if (!(r
->flags
& IORESOURCE_MEM
))
4678 r
->flags
|= IORESOURCE_UNSET
;
4679 r
->end
= resource_size(r
) - 1;
4682 pci_disable_bridge_window(dev
);
4686 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
4688 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
4689 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
4690 spin_lock(&resource_alignment_lock
);
4691 strncpy(resource_alignment_param
, buf
, count
);
4692 resource_alignment_param
[count
] = '\0';
4693 spin_unlock(&resource_alignment_lock
);
4697 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
4700 spin_lock(&resource_alignment_lock
);
4701 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
4702 spin_unlock(&resource_alignment_lock
);
4706 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
4708 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
4711 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
4712 const char *buf
, size_t count
)
4714 return pci_set_resource_alignment_param(buf
, count
);
4717 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
4718 pci_resource_alignment_store
);
4720 static int __init
pci_resource_alignment_sysfs_init(void)
4722 return bus_create_file(&pci_bus_type
,
4723 &bus_attr_resource_alignment
);
4725 late_initcall(pci_resource_alignment_sysfs_init
);
4727 static void pci_no_domains(void)
4729 #ifdef CONFIG_PCI_DOMAINS
4730 pci_domains_supported
= 0;
4734 #ifdef CONFIG_PCI_DOMAINS
4735 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
4737 int pci_get_new_domain_nr(void)
4739 return atomic_inc_return(&__domain_nr
);
4742 #ifdef CONFIG_PCI_DOMAINS_GENERIC
4743 void pci_bus_assign_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
4745 static int use_dt_domains
= -1;
4749 domain
= of_get_pci_domain_nr(parent
->of_node
);
4751 * Check DT domain and use_dt_domains values.
4753 * If DT domain property is valid (domain >= 0) and
4754 * use_dt_domains != 0, the DT assignment is valid since this means
4755 * we have not previously allocated a domain number by using
4756 * pci_get_new_domain_nr(); we should also update use_dt_domains to
4757 * 1, to indicate that we have just assigned a domain number from
4760 * If DT domain property value is not valid (ie domain < 0), and we
4761 * have not previously assigned a domain number from DT
4762 * (use_dt_domains != 1) we should assign a domain number by
4765 * pci_get_new_domain_nr()
4767 * API and update the use_dt_domains value to keep track of method we
4768 * are using to assign domain numbers (use_dt_domains = 0).
4770 * All other combinations imply we have a platform that is trying
4771 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
4772 * which is a recipe for domain mishandling and it is prevented by
4773 * invalidating the domain value (domain = -1) and printing a
4774 * corresponding error.
4776 if (domain
>= 0 && use_dt_domains
) {
4778 } else if (domain
< 0 && use_dt_domains
!= 1) {
4780 domain
= pci_get_new_domain_nr();
4782 dev_err(parent
, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
4783 parent
->of_node
->full_name
);
4787 bus
->domain_nr
= domain
;
4793 * pci_ext_cfg_avail - can we access extended PCI config space?
4795 * Returns 1 if we can access PCI extended config space (offsets
4796 * greater than 0xff). This is the default implementation. Architecture
4797 * implementations can override this.
4799 int __weak
pci_ext_cfg_avail(void)
4804 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
4807 EXPORT_SYMBOL(pci_fixup_cardbus
);
4809 static int __init
pci_setup(char *str
)
4812 char *k
= strchr(str
, ',');
4815 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
4816 if (!strcmp(str
, "nomsi")) {
4818 } else if (!strcmp(str
, "noaer")) {
4820 } else if (!strncmp(str
, "realloc=", 8)) {
4821 pci_realloc_get_opt(str
+ 8);
4822 } else if (!strncmp(str
, "realloc", 7)) {
4823 pci_realloc_get_opt("on");
4824 } else if (!strcmp(str
, "nodomains")) {
4826 } else if (!strncmp(str
, "noari", 5)) {
4827 pcie_ari_disabled
= true;
4828 } else if (!strncmp(str
, "cbiosize=", 9)) {
4829 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
4830 } else if (!strncmp(str
, "cbmemsize=", 10)) {
4831 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
4832 } else if (!strncmp(str
, "resource_alignment=", 19)) {
4833 pci_set_resource_alignment_param(str
+ 19,
4835 } else if (!strncmp(str
, "ecrc=", 5)) {
4836 pcie_ecrc_get_policy(str
+ 5);
4837 } else if (!strncmp(str
, "hpiosize=", 9)) {
4838 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
4839 } else if (!strncmp(str
, "hpmemsize=", 10)) {
4840 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
4841 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
4842 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
4843 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
4844 pcie_bus_config
= PCIE_BUS_SAFE
;
4845 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
4846 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
4847 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
4848 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
4849 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
4850 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
4852 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
4860 early_param("pci", pci_setup
);