2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <asm/dma.h> /* isa_dma_bridge_buggy */
24 unsigned int pci_pm_d3_delay
= 10;
26 #ifdef CONFIG_PCI_DOMAINS
27 int pci_domains_supported
= 1;
30 #define DEFAULT_CARDBUS_IO_SIZE (256)
31 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
32 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
33 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
34 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
37 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
38 * @bus: pointer to PCI bus structure to search
40 * Given a PCI bus, returns the highest PCI bus number present in the set
41 * including the given PCI bus and its list of child PCI buses.
43 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
45 struct list_head
*tmp
;
48 max
= bus
->subordinate
;
49 list_for_each(tmp
, &bus
->children
) {
50 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
56 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
60 * pci_max_busnr - returns maximum PCI bus number
62 * Returns the highest PCI bus number present in the system global list of
65 unsigned char __devinit
68 struct pci_bus
*bus
= NULL
;
72 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
73 n
= pci_bus_max_busnr(bus
);
82 #define PCI_FIND_CAP_TTL 48
84 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
85 u8 pos
, int cap
, int *ttl
)
90 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
94 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
100 pos
+= PCI_CAP_LIST_NEXT
;
105 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
108 int ttl
= PCI_FIND_CAP_TTL
;
110 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
113 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
115 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
116 pos
+ PCI_CAP_LIST_NEXT
, cap
);
118 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
120 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
121 unsigned int devfn
, u8 hdr_type
)
125 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
126 if (!(status
& PCI_STATUS_CAP_LIST
))
130 case PCI_HEADER_TYPE_NORMAL
:
131 case PCI_HEADER_TYPE_BRIDGE
:
132 return PCI_CAPABILITY_LIST
;
133 case PCI_HEADER_TYPE_CARDBUS
:
134 return PCI_CB_CAPABILITY_LIST
;
143 * pci_find_capability - query for devices' capabilities
144 * @dev: PCI device to query
145 * @cap: capability code
147 * Tell if a device supports a given PCI capability.
148 * Returns the address of the requested capability structure within the
149 * device's PCI configuration space or 0 in case the device does not
150 * support it. Possible values for @cap:
152 * %PCI_CAP_ID_PM Power Management
153 * %PCI_CAP_ID_AGP Accelerated Graphics Port
154 * %PCI_CAP_ID_VPD Vital Product Data
155 * %PCI_CAP_ID_SLOTID Slot Identification
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
158 * %PCI_CAP_ID_PCIX PCI-X
159 * %PCI_CAP_ID_EXP PCI Express
161 int pci_find_capability(struct pci_dev
*dev
, int cap
)
165 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
167 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
173 * pci_bus_find_capability - query for devices' capabilities
174 * @bus: the PCI bus to query
175 * @devfn: PCI device to query
176 * @cap: capability code
178 * Like pci_find_capability() but works for pci devices that do not have a
179 * pci_dev structure set up yet.
181 * Returns the address of the requested capability structure within the
182 * device's PCI configuration space or 0 in case the device does not
185 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
190 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
192 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
194 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
200 * pci_find_ext_capability - Find an extended capability
201 * @dev: PCI device to query
202 * @cap: capability code
204 * Returns the address of the requested extended capability structure
205 * within the device's PCI configuration space or 0 if the device does
206 * not support it. Possible values for @cap:
208 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
209 * %PCI_EXT_CAP_ID_VC Virtual Channel
210 * %PCI_EXT_CAP_ID_DSN Device Serial Number
211 * %PCI_EXT_CAP_ID_PWR Power Budgeting
213 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
217 int pos
= PCI_CFG_SPACE_SIZE
;
219 /* minimum 8 bytes per capability */
220 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
222 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
225 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
229 * If we have no capabilities, this is indicated by cap ID,
230 * cap version and next pointer all being 0.
236 if (PCI_EXT_CAP_ID(header
) == cap
)
239 pos
= PCI_EXT_CAP_NEXT(header
);
240 if (pos
< PCI_CFG_SPACE_SIZE
)
243 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
249 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
251 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
253 int rc
, ttl
= PCI_FIND_CAP_TTL
;
256 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
257 mask
= HT_3BIT_CAP_MASK
;
259 mask
= HT_5BIT_CAP_MASK
;
261 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
262 PCI_CAP_ID_HT
, &ttl
);
264 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
265 if (rc
!= PCIBIOS_SUCCESSFUL
)
268 if ((cap
& mask
) == ht_cap
)
271 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
272 pos
+ PCI_CAP_LIST_NEXT
,
273 PCI_CAP_ID_HT
, &ttl
);
279 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
280 * @dev: PCI device to query
281 * @pos: Position from which to continue searching
282 * @ht_cap: Hypertransport capability code
284 * To be used in conjunction with pci_find_ht_capability() to search for
285 * all capabilities matching @ht_cap. @pos should always be a value returned
286 * from pci_find_ht_capability().
288 * NB. To be 100% safe against broken PCI devices, the caller should take
289 * steps to avoid an infinite loop.
291 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
293 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
295 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
298 * pci_find_ht_capability - query a device's Hypertransport capabilities
299 * @dev: PCI device to query
300 * @ht_cap: Hypertransport capability code
302 * Tell if a device supports a given Hypertransport capability.
303 * Returns an address within the device's PCI configuration space
304 * or 0 in case the device does not support the request capability.
305 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
306 * which has a Hypertransport capability matching @ht_cap.
308 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
312 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
314 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
318 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
321 * pci_find_parent_resource - return resource region of parent bus of given region
322 * @dev: PCI device structure contains resources to be searched
323 * @res: child resource record for which parent is sought
325 * For given resource region of given device, return the resource
326 * region of parent bus the given region is contained in or where
327 * it should be allocated from.
330 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
332 const struct pci_bus
*bus
= dev
->bus
;
334 struct resource
*best
= NULL
;
336 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
337 struct resource
*r
= bus
->resource
[i
];
340 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
341 continue; /* Not contained */
342 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
343 continue; /* Wrong type */
344 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
345 return r
; /* Exact match */
346 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
347 best
= r
; /* Approximating prefetchable by non-prefetchable */
353 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
354 * @dev: PCI device to have its BARs restored
356 * Restore the BAR values for a given device, so as to make it
357 * accessible by its driver.
360 pci_restore_bars(struct pci_dev
*dev
)
364 switch (dev
->hdr_type
) {
365 case PCI_HEADER_TYPE_NORMAL
:
368 case PCI_HEADER_TYPE_BRIDGE
:
371 case PCI_HEADER_TYPE_CARDBUS
:
375 /* Should never get here, but just in case... */
379 for (i
= 0; i
< numres
; i
++)
380 pci_update_resource(dev
, &dev
->resource
[i
], i
);
383 static struct pci_platform_pm_ops
*pci_platform_pm
;
385 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
387 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
388 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
390 pci_platform_pm
= ops
;
394 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
396 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
399 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
402 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
405 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
407 return pci_platform_pm
?
408 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
411 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
413 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
416 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
418 return pci_platform_pm
?
419 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
423 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
425 * @dev: PCI device to handle.
426 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
429 * -EINVAL if the requested state is invalid.
430 * -EIO if device does not support PCI PM or its PM capabilities register has a
431 * wrong version, or device doesn't support the requested state.
432 * 0 if device already is in the requested state.
433 * 0 if device's power state has been successfully changed.
436 pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
439 bool need_restore
= false;
444 if (state
< PCI_D0
|| state
> PCI_D3hot
)
447 /* Validate current state:
448 * Can enter D0 from any state, but if we can only go deeper
449 * to sleep if we're already in a low power state
451 if (dev
->current_state
== state
) {
452 /* we're already there */
454 } else if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
455 && dev
->current_state
> state
) {
456 dev_err(&dev
->dev
, "invalid power transition "
457 "(from state %d to %d)\n", dev
->current_state
, state
);
461 /* check if this device supports the desired state */
462 if ((state
== PCI_D1
&& !dev
->d1_support
)
463 || (state
== PCI_D2
&& !dev
->d2_support
))
466 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
468 /* If we're (effectively) in D3, force entire word to 0.
469 * This doesn't affect PME_Status, disables PME_En, and
470 * sets PowerState to 0.
472 switch (dev
->current_state
) {
476 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
479 case PCI_UNKNOWN
: /* Boot-up */
480 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
481 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
483 /* Fall-through: force to D0 */
489 /* enter specified state */
490 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
492 /* Mandatory power management transition delays */
493 /* see PCI PM 1.1 5.6.1 table 18 */
494 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
495 msleep(pci_pm_d3_delay
);
496 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
499 dev
->current_state
= state
;
501 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
502 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
503 * from D3hot to D0 _may_ perform an internal reset, thereby
504 * going to "D0 Uninitialized" rather than "D0 Initialized".
505 * For example, at least some versions of the 3c905B and the
506 * 3c556B exhibit this behaviour.
508 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
509 * devices in a D3hot state at boot. Consequently, we need to
510 * restore at least the BARs so that the device will be
511 * accessible to its driver.
514 pci_restore_bars(dev
);
517 pcie_aspm_pm_state_change(dev
->bus
->self
);
523 * pci_update_current_state - Read PCI power state of given device from its
524 * PCI PM registers and cache it
525 * @dev: PCI device to handle.
527 static void pci_update_current_state(struct pci_dev
*dev
)
532 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
533 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
538 * pci_set_power_state - Set the power state of a PCI device
539 * @dev: PCI device to handle.
540 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
542 * Transition a device to a new power state, using the platform formware and/or
543 * the device's PCI PM registers.
546 * -EINVAL if the requested state is invalid.
547 * -EIO if device does not support PCI PM or its PM capabilities register has a
548 * wrong version, or device doesn't support the requested state.
549 * 0 if device already is in the requested state.
550 * 0 if device's power state has been successfully changed.
552 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
556 /* bound the state we're entering */
557 if (state
> PCI_D3hot
)
559 else if (state
< PCI_D0
)
561 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
563 * If the device or the parent bridge do not support PCI PM,
564 * ignore the request if we're doing anything other than putting
565 * it into D0 (which would only happen on boot).
569 if (state
== PCI_D0
&& platform_pci_power_manageable(dev
)) {
571 * Allow the platform to change the state, for example via ACPI
572 * _PR0, _PS0 and some such, but do not trust it.
574 int ret
= platform_pci_set_power_state(dev
, PCI_D0
);
576 pci_update_current_state(dev
);
578 /* This device is quirked not to be put into D3, so
579 don't put it in D3 */
580 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
583 error
= pci_raw_set_power_state(dev
, state
);
585 if (state
> PCI_D0
&& platform_pci_power_manageable(dev
)) {
586 /* Allow the platform to finalize the transition */
587 int ret
= platform_pci_set_power_state(dev
, state
);
589 pci_update_current_state(dev
);
598 * pci_choose_state - Choose the power state of a PCI device
599 * @dev: PCI device to be suspended
600 * @state: target sleep state for the whole system. This is the value
601 * that is passed to suspend() function.
603 * Returns PCI power state suitable for given device and given system
607 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
611 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
614 ret
= platform_pci_choose_state(dev
);
615 if (ret
!= PCI_POWER_ERROR
)
618 switch (state
.event
) {
621 case PM_EVENT_FREEZE
:
622 case PM_EVENT_PRETHAW
:
623 /* REVISIT both freeze and pre-thaw "should" use D0 */
624 case PM_EVENT_SUSPEND
:
625 case PM_EVENT_HIBERNATE
:
628 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
635 EXPORT_SYMBOL(pci_choose_state
);
637 static int pci_save_pcie_state(struct pci_dev
*dev
)
640 struct pci_cap_saved_state
*save_state
;
644 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
648 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
650 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
) * 4, GFP_KERNEL
);
654 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
657 cap
= (u16
*)&save_state
->data
[0];
659 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
660 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
661 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
662 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
663 save_state
->cap_nr
= PCI_CAP_ID_EXP
;
665 pci_add_saved_cap(dev
, save_state
);
669 static void pci_restore_pcie_state(struct pci_dev
*dev
)
672 struct pci_cap_saved_state
*save_state
;
675 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
676 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
677 if (!save_state
|| pos
<= 0)
679 cap
= (u16
*)&save_state
->data
[0];
681 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
682 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
683 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
684 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
688 static int pci_save_pcix_state(struct pci_dev
*dev
)
691 struct pci_cap_saved_state
*save_state
;
695 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
699 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
701 save_state
= kzalloc(sizeof(*save_state
) + sizeof(u16
), GFP_KERNEL
);
705 dev_err(&dev
->dev
, "out of memory in pci_save_pcie_state\n");
708 cap
= (u16
*)&save_state
->data
[0];
710 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, &cap
[i
++]);
711 save_state
->cap_nr
= PCI_CAP_ID_PCIX
;
713 pci_add_saved_cap(dev
, save_state
);
717 static void pci_restore_pcix_state(struct pci_dev
*dev
)
720 struct pci_cap_saved_state
*save_state
;
723 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
724 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
725 if (!save_state
|| pos
<= 0)
727 cap
= (u16
*)&save_state
->data
[0];
729 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
734 * pci_save_state - save the PCI configuration space of a device before suspending
735 * @dev: - PCI device that we're dealing with
738 pci_save_state(struct pci_dev
*dev
)
741 /* XXX: 100% dword access ok here? */
742 for (i
= 0; i
< 16; i
++)
743 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
744 if ((i
= pci_save_pcie_state(dev
)) != 0)
746 if ((i
= pci_save_pcix_state(dev
)) != 0)
752 * pci_restore_state - Restore the saved state of a PCI device
753 * @dev: - PCI device that we're dealing with
756 pci_restore_state(struct pci_dev
*dev
)
761 /* PCI Express register must be restored first */
762 pci_restore_pcie_state(dev
);
765 * The Base Address register should be programmed before the command
768 for (i
= 15; i
>= 0; i
--) {
769 pci_read_config_dword(dev
, i
* 4, &val
);
770 if (val
!= dev
->saved_config_space
[i
]) {
771 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
772 "space at offset %#x (was %#x, writing %#x)\n",
773 i
, val
, (int)dev
->saved_config_space
[i
]);
774 pci_write_config_dword(dev
,i
* 4,
775 dev
->saved_config_space
[i
]);
778 pci_restore_pcix_state(dev
);
779 pci_restore_msi_state(dev
);
784 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
788 err
= pci_set_power_state(dev
, PCI_D0
);
789 if (err
< 0 && err
!= -EIO
)
791 err
= pcibios_enable_device(dev
, bars
);
794 pci_fixup_device(pci_fixup_enable
, dev
);
800 * pci_reenable_device - Resume abandoned device
801 * @dev: PCI device to be resumed
803 * Note this function is a backend of pci_default_resume and is not supposed
804 * to be called by normal code, write proper resume handler and use it instead.
806 int pci_reenable_device(struct pci_dev
*dev
)
808 if (atomic_read(&dev
->enable_cnt
))
809 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
813 static int __pci_enable_device_flags(struct pci_dev
*dev
,
814 resource_size_t flags
)
819 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
820 return 0; /* already enabled */
822 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
823 if (dev
->resource
[i
].flags
& flags
)
826 err
= do_pci_enable_device(dev
, bars
);
828 atomic_dec(&dev
->enable_cnt
);
833 * pci_enable_device_io - Initialize a device for use with IO space
834 * @dev: PCI device to be initialized
836 * Initialize device before it's used by a driver. Ask low-level code
837 * to enable I/O resources. Wake up the device if it was suspended.
838 * Beware, this function can fail.
840 int pci_enable_device_io(struct pci_dev
*dev
)
842 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
846 * pci_enable_device_mem - Initialize a device for use with Memory space
847 * @dev: PCI device to be initialized
849 * Initialize device before it's used by a driver. Ask low-level code
850 * to enable Memory resources. Wake up the device if it was suspended.
851 * Beware, this function can fail.
853 int pci_enable_device_mem(struct pci_dev
*dev
)
855 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
859 * pci_enable_device - Initialize device before it's used by a driver.
860 * @dev: PCI device to be initialized
862 * Initialize device before it's used by a driver. Ask low-level code
863 * to enable I/O and memory. Wake up the device if it was suspended.
864 * Beware, this function can fail.
866 * Note we don't actually enable the device many times if we call
867 * this function repeatedly (we just increment the count).
869 int pci_enable_device(struct pci_dev
*dev
)
871 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
875 * Managed PCI resources. This manages device on/off, intx/msi/msix
876 * on/off and BAR regions. pci_dev itself records msi/msix status, so
877 * there's no need to track it separately. pci_devres is initialized
878 * when a device is enabled using managed PCI device enable interface.
881 unsigned int enabled
:1;
882 unsigned int pinned
:1;
883 unsigned int orig_intx
:1;
884 unsigned int restore_intx
:1;
888 static void pcim_release(struct device
*gendev
, void *res
)
890 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
891 struct pci_devres
*this = res
;
894 if (dev
->msi_enabled
)
895 pci_disable_msi(dev
);
896 if (dev
->msix_enabled
)
897 pci_disable_msix(dev
);
899 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
900 if (this->region_mask
& (1 << i
))
901 pci_release_region(dev
, i
);
903 if (this->restore_intx
)
904 pci_intx(dev
, this->orig_intx
);
906 if (this->enabled
&& !this->pinned
)
907 pci_disable_device(dev
);
910 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
912 struct pci_devres
*dr
, *new_dr
;
914 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
918 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
921 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
924 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
926 if (pci_is_managed(pdev
))
927 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
932 * pcim_enable_device - Managed pci_enable_device()
933 * @pdev: PCI device to be initialized
935 * Managed pci_enable_device().
937 int pcim_enable_device(struct pci_dev
*pdev
)
939 struct pci_devres
*dr
;
942 dr
= get_pci_dr(pdev
);
948 rc
= pci_enable_device(pdev
);
950 pdev
->is_managed
= 1;
957 * pcim_pin_device - Pin managed PCI device
958 * @pdev: PCI device to pin
960 * Pin managed PCI device @pdev. Pinned device won't be disabled on
961 * driver detach. @pdev must have been enabled with
962 * pcim_enable_device().
964 void pcim_pin_device(struct pci_dev
*pdev
)
966 struct pci_devres
*dr
;
968 dr
= find_pci_dr(pdev
);
969 WARN_ON(!dr
|| !dr
->enabled
);
975 * pcibios_disable_device - disable arch specific PCI resources for device dev
976 * @dev: the PCI device to disable
978 * Disables architecture specific PCI resources for the device. This
979 * is the default implementation. Architecture implementations can
982 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
985 * pci_disable_device - Disable PCI device after use
986 * @dev: PCI device to be disabled
988 * Signal to the system that the PCI device is not in use by the system
989 * anymore. This only involves disabling PCI bus-mastering, if active.
991 * Note we don't actually disable the device until all callers of
992 * pci_device_enable() have called pci_device_disable().
995 pci_disable_device(struct pci_dev
*dev
)
997 struct pci_devres
*dr
;
1000 dr
= find_pci_dr(dev
);
1004 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1007 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1008 if (pci_command
& PCI_COMMAND_MASTER
) {
1009 pci_command
&= ~PCI_COMMAND_MASTER
;
1010 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1012 dev
->is_busmaster
= 0;
1014 pcibios_disable_device(dev
);
1018 * pcibios_set_pcie_reset_state - set reset state for device dev
1019 * @dev: the PCI-E device reset
1020 * @state: Reset state to enter into
1023 * Sets the PCI-E reset state for the device. This is the default
1024 * implementation. Architecture implementations can override this.
1026 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1027 enum pcie_reset_state state
)
1033 * pci_set_pcie_reset_state - set reset state for device dev
1034 * @dev: the PCI-E device reset
1035 * @state: Reset state to enter into
1038 * Sets the PCI reset state for the device.
1040 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1042 return pcibios_set_pcie_reset_state(dev
, state
);
1046 * pci_pme_capable - check the capability of PCI device to generate PME#
1047 * @dev: PCI device to handle.
1048 * @state: PCI state from which device will issue PME#.
1050 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1055 return !!(dev
->pme_support
& (1 << state
));
1059 * pci_pme_active - enable or disable PCI device's PME# function
1060 * @dev: PCI device to handle.
1061 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1063 * The caller must verify that the device is capable of generating PME# before
1064 * calling this function with @enable equal to 'true'.
1066 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1073 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1074 /* Clear PME_Status by writing 1 to it and enable PME# */
1075 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1077 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1079 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1081 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1082 enable
? "enabled" : "disabled");
1086 * pci_enable_wake - enable PCI device as wakeup event source
1087 * @dev: PCI device affected
1088 * @state: PCI state from which device will issue wakeup events
1089 * @enable: True to enable event generation; false to disable
1091 * This enables the device as a wakeup event source, or disables it.
1092 * When such events involves platform-specific hooks, those hooks are
1093 * called automatically by this routine.
1095 * Devices with legacy power management (no standard PCI PM capabilities)
1096 * always require such platform hooks.
1099 * 0 is returned on success
1100 * -EINVAL is returned if device is not supposed to wake up the system
1101 * Error code depending on the platform is returned if both the platform and
1102 * the native mechanism fail to enable the generation of wake-up events
1104 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1107 bool pme_done
= false;
1109 if (!device_may_wakeup(&dev
->dev
))
1113 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1114 * Anderson we should be doing PME# wake enable followed by ACPI wake
1115 * enable. To disable wake-up we call the platform first, for symmetry.
1118 if (!enable
&& platform_pci_can_wakeup(dev
))
1119 error
= platform_pci_sleep_wake(dev
, false);
1121 if (!enable
|| pci_pme_capable(dev
, state
)) {
1122 pci_pme_active(dev
, enable
);
1126 if (enable
&& platform_pci_can_wakeup(dev
))
1127 error
= platform_pci_sleep_wake(dev
, true);
1129 return pme_done
? 0 : error
;
1133 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1134 * @dev: PCI device to prepare
1135 * @enable: True to enable wake-up event generation; false to disable
1137 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1138 * and this function allows them to set that up cleanly - pci_enable_wake()
1139 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1140 * ordering constraints.
1142 * This function only returns error code if the device is not capable of
1143 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1144 * enable wake-up power for it.
1146 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1148 return pci_pme_capable(dev
, PCI_D3cold
) ?
1149 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1150 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1154 * pci_target_state - find an appropriate low power state for a given PCI dev
1157 * Use underlying platform code to find a supported low power state for @dev.
1158 * If the platform can't manage @dev, return the deepest state from which it
1159 * can generate wake events, based on any available PME info.
1161 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1163 pci_power_t target_state
= PCI_D3hot
;
1165 if (platform_pci_power_manageable(dev
)) {
1167 * Call the platform to choose the target state of the device
1168 * and enable wake-up from this state if supported.
1170 pci_power_t state
= platform_pci_choose_state(dev
);
1173 case PCI_POWER_ERROR
:
1178 if (pci_no_d1d2(dev
))
1181 target_state
= state
;
1183 } else if (device_may_wakeup(&dev
->dev
)) {
1185 * Find the deepest state from which the device can generate
1186 * wake-up events, make it the target state and enable device
1190 return PCI_POWER_ERROR
;
1192 if (dev
->pme_support
) {
1194 && !(dev
->pme_support
& (1 << target_state
)))
1199 return target_state
;
1203 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1204 * @dev: Device to handle.
1206 * Choose the power state appropriate for the device depending on whether
1207 * it can wake up the system and/or is power manageable by the platform
1208 * (PCI_D3hot is the default) and put the device into that state.
1210 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1212 pci_power_t target_state
= pci_target_state(dev
);
1215 if (target_state
== PCI_POWER_ERROR
)
1218 pci_enable_wake(dev
, target_state
, true);
1220 error
= pci_set_power_state(dev
, target_state
);
1223 pci_enable_wake(dev
, target_state
, false);
1229 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1230 * @dev: Device to handle.
1232 * Disable device's sytem wake-up capability and put it into D0.
1234 int pci_back_from_sleep(struct pci_dev
*dev
)
1236 pci_enable_wake(dev
, PCI_D0
, false);
1237 return pci_set_power_state(dev
, PCI_D0
);
1241 * pci_pm_init - Initialize PM functions of given PCI device
1242 * @dev: PCI device to handle.
1244 void pci_pm_init(struct pci_dev
*dev
)
1251 /* find PCI PM capability in list */
1252 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1255 /* Check device's ability to generate PME# */
1256 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1258 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1259 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1260 pmc
& PCI_PM_CAP_VER_MASK
);
1266 dev
->d1_support
= false;
1267 dev
->d2_support
= false;
1268 if (!pci_no_d1d2(dev
)) {
1269 if (pmc
& PCI_PM_CAP_D1
)
1270 dev
->d1_support
= true;
1271 if (pmc
& PCI_PM_CAP_D2
)
1272 dev
->d2_support
= true;
1274 if (dev
->d1_support
|| dev
->d2_support
)
1275 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1276 dev
->d1_support
? " D1" : "",
1277 dev
->d2_support
? " D2" : "");
1280 pmc
&= PCI_PM_CAP_PME_MASK
;
1282 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1283 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1284 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1285 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1286 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1287 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1288 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1290 * Make device's PM flags reflect the wake-up capability, but
1291 * let the user space enable it to wake up the system as needed.
1293 device_set_wakeup_capable(&dev
->dev
, true);
1294 device_set_wakeup_enable(&dev
->dev
, false);
1295 /* Disable the PME# generation functionality */
1296 pci_pme_active(dev
, false);
1298 dev
->pme_support
= 0;
1303 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1311 while (dev
->bus
->self
) {
1312 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
1313 dev
= dev
->bus
->self
;
1320 * pci_release_region - Release a PCI bar
1321 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1322 * @bar: BAR to release
1324 * Releases the PCI I/O and memory resources previously reserved by a
1325 * successful call to pci_request_region. Call this function only
1326 * after all use of the PCI regions has ceased.
1328 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1330 struct pci_devres
*dr
;
1332 if (pci_resource_len(pdev
, bar
) == 0)
1334 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1335 release_region(pci_resource_start(pdev
, bar
),
1336 pci_resource_len(pdev
, bar
));
1337 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1338 release_mem_region(pci_resource_start(pdev
, bar
),
1339 pci_resource_len(pdev
, bar
));
1341 dr
= find_pci_dr(pdev
);
1343 dr
->region_mask
&= ~(1 << bar
);
1347 * pci_request_region - Reserved PCI I/O and memory resource
1348 * @pdev: PCI device whose resources are to be reserved
1349 * @bar: BAR to be reserved
1350 * @res_name: Name to be associated with resource.
1352 * Mark the PCI region associated with PCI device @pdev BR @bar as
1353 * being reserved by owner @res_name. Do not access any
1354 * address inside the PCI regions unless this call returns
1357 * Returns 0 on success, or %EBUSY on error. A warning
1358 * message is also printed on failure.
1360 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1362 struct pci_devres
*dr
;
1364 if (pci_resource_len(pdev
, bar
) == 0)
1367 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1368 if (!request_region(pci_resource_start(pdev
, bar
),
1369 pci_resource_len(pdev
, bar
), res_name
))
1372 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1373 if (!request_mem_region(pci_resource_start(pdev
, bar
),
1374 pci_resource_len(pdev
, bar
), res_name
))
1378 dr
= find_pci_dr(pdev
);
1380 dr
->region_mask
|= 1 << bar
;
1385 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1387 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1388 &pdev
->resource
[bar
]);
1393 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1394 * @pdev: PCI device whose resources were previously reserved
1395 * @bars: Bitmask of BARs to be released
1397 * Release selected PCI I/O and memory resources previously reserved.
1398 * Call this function only after all use of the PCI regions has ceased.
1400 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1404 for (i
= 0; i
< 6; i
++)
1405 if (bars
& (1 << i
))
1406 pci_release_region(pdev
, i
);
1410 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1411 * @pdev: PCI device whose resources are to be reserved
1412 * @bars: Bitmask of BARs to be requested
1413 * @res_name: Name to be associated with resource
1415 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1416 const char *res_name
)
1420 for (i
= 0; i
< 6; i
++)
1421 if (bars
& (1 << i
))
1422 if(pci_request_region(pdev
, i
, res_name
))
1428 if (bars
& (1 << i
))
1429 pci_release_region(pdev
, i
);
1435 * pci_release_regions - Release reserved PCI I/O and memory resources
1436 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1438 * Releases all PCI I/O and memory resources previously reserved by a
1439 * successful call to pci_request_regions. Call this function only
1440 * after all use of the PCI regions has ceased.
1443 void pci_release_regions(struct pci_dev
*pdev
)
1445 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1449 * pci_request_regions - Reserved PCI I/O and memory resources
1450 * @pdev: PCI device whose resources are to be reserved
1451 * @res_name: Name to be associated with resource.
1453 * Mark all PCI regions associated with PCI device @pdev as
1454 * being reserved by owner @res_name. Do not access any
1455 * address inside the PCI regions unless this call returns
1458 * Returns 0 on success, or %EBUSY on error. A warning
1459 * message is also printed on failure.
1461 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1463 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1467 * pci_set_master - enables bus-mastering for device dev
1468 * @dev: the PCI device to enable
1470 * Enables bus-mastering on the device and calls pcibios_set_master()
1471 * to do the needed arch specific settings.
1474 pci_set_master(struct pci_dev
*dev
)
1478 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1479 if (! (cmd
& PCI_COMMAND_MASTER
)) {
1480 dev_dbg(&dev
->dev
, "enabling bus mastering\n");
1481 cmd
|= PCI_COMMAND_MASTER
;
1482 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1484 dev
->is_busmaster
= 1;
1485 pcibios_set_master(dev
);
1488 #ifdef PCI_DISABLE_MWI
1489 int pci_set_mwi(struct pci_dev
*dev
)
1494 int pci_try_set_mwi(struct pci_dev
*dev
)
1499 void pci_clear_mwi(struct pci_dev
*dev
)
1505 #ifndef PCI_CACHE_LINE_BYTES
1506 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1509 /* This can be overridden by arch code. */
1510 /* Don't forget this is measured in 32-bit words, not bytes */
1511 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1514 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1515 * @dev: the PCI device for which MWI is to be enabled
1517 * Helper function for pci_set_mwi.
1518 * Originally copied from drivers/net/acenic.c.
1519 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1521 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1524 pci_set_cacheline_size(struct pci_dev
*dev
)
1528 if (!pci_cache_line_size
)
1529 return -EINVAL
; /* The system doesn't support MWI. */
1531 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1532 equal to or multiple of the right value. */
1533 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1534 if (cacheline_size
>= pci_cache_line_size
&&
1535 (cacheline_size
% pci_cache_line_size
) == 0)
1538 /* Write the correct value. */
1539 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1541 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1542 if (cacheline_size
== pci_cache_line_size
)
1545 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1546 "supported\n", pci_cache_line_size
<< 2);
1552 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1553 * @dev: the PCI device for which MWI is enabled
1555 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1557 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1560 pci_set_mwi(struct pci_dev
*dev
)
1565 rc
= pci_set_cacheline_size(dev
);
1569 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1570 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1571 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1572 cmd
|= PCI_COMMAND_INVALIDATE
;
1573 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1580 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1581 * @dev: the PCI device for which MWI is enabled
1583 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1584 * Callers are not required to check the return value.
1586 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1588 int pci_try_set_mwi(struct pci_dev
*dev
)
1590 int rc
= pci_set_mwi(dev
);
1595 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1596 * @dev: the PCI device to disable
1598 * Disables PCI Memory-Write-Invalidate transaction on the device
1601 pci_clear_mwi(struct pci_dev
*dev
)
1605 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1606 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1607 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1608 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1611 #endif /* ! PCI_DISABLE_MWI */
1614 * pci_intx - enables/disables PCI INTx for device dev
1615 * @pdev: the PCI device to operate on
1616 * @enable: boolean: whether to enable or disable PCI INTx
1618 * Enables/disables PCI INTx for device dev
1621 pci_intx(struct pci_dev
*pdev
, int enable
)
1623 u16 pci_command
, new;
1625 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1628 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1630 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1633 if (new != pci_command
) {
1634 struct pci_devres
*dr
;
1636 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1638 dr
= find_pci_dr(pdev
);
1639 if (dr
&& !dr
->restore_intx
) {
1640 dr
->restore_intx
= 1;
1641 dr
->orig_intx
= !enable
;
1647 * pci_msi_off - disables any msi or msix capabilities
1648 * @dev: the PCI device to operate on
1650 * If you want to use msi see pci_enable_msi and friends.
1651 * This is a lower level primitive that allows us to disable
1652 * msi operation at the device level.
1654 void pci_msi_off(struct pci_dev
*dev
)
1659 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1661 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
1662 control
&= ~PCI_MSI_FLAGS_ENABLE
;
1663 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
1665 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1667 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
1668 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
1669 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
1673 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
1675 * These can be overridden by arch-specific implementations
1678 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
1680 if (!pci_dma_supported(dev
, mask
))
1683 dev
->dma_mask
= mask
;
1689 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
1691 if (!pci_dma_supported(dev
, mask
))
1694 dev
->dev
.coherent_dma_mask
= mask
;
1700 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
1701 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
1703 return dma_set_max_seg_size(&dev
->dev
, size
);
1705 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
1708 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
1709 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
1711 return dma_set_seg_boundary(&dev
->dev
, mask
);
1713 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
1717 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
1718 * @dev: PCI device to query
1720 * Returns mmrbc: maximum designed memory read count in bytes
1721 * or appropriate error value.
1723 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
1728 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1732 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1736 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
1738 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
1741 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
1742 * @dev: PCI device to query
1744 * Returns mmrbc: maximum memory read count in bytes
1745 * or appropriate error value.
1747 int pcix_get_mmrbc(struct pci_dev
*dev
)
1752 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1756 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1758 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
1762 EXPORT_SYMBOL(pcix_get_mmrbc
);
1765 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
1766 * @dev: PCI device to query
1767 * @mmrbc: maximum memory read count in bytes
1768 * valid values are 512, 1024, 2048, 4096
1770 * If possible sets maximum memory read byte count, some bridges have erratas
1771 * that prevent this.
1773 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
1775 int cap
, err
= -EINVAL
;
1776 u32 stat
, cmd
, v
, o
;
1778 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
1781 v
= ffs(mmrbc
) - 10;
1783 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1787 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
1791 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
1794 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
1798 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
1800 if (v
> o
&& dev
->bus
&&
1801 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
1804 cmd
&= ~PCI_X_CMD_MAX_READ
;
1806 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
1811 EXPORT_SYMBOL(pcix_set_mmrbc
);
1814 * pcie_get_readrq - get PCI Express read request size
1815 * @dev: PCI device to query
1817 * Returns maximum memory read request in bytes
1818 * or appropriate error value.
1820 int pcie_get_readrq(struct pci_dev
*dev
)
1825 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1829 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1831 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
1835 EXPORT_SYMBOL(pcie_get_readrq
);
1838 * pcie_set_readrq - set PCI Express maximum memory read request
1839 * @dev: PCI device to query
1840 * @rq: maximum memory read count in bytes
1841 * valid values are 128, 256, 512, 1024, 2048, 4096
1843 * If possible sets maximum read byte count
1845 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
1847 int cap
, err
= -EINVAL
;
1850 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
1853 v
= (ffs(rq
) - 8) << 12;
1855 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
1859 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
1863 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
1864 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
1866 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
1872 EXPORT_SYMBOL(pcie_set_readrq
);
1875 * pci_select_bars - Make BAR mask from the type of resource
1876 * @dev: the PCI device for which BAR mask is made
1877 * @flags: resource type mask to be selected
1879 * This helper routine makes bar mask from the type of resource.
1881 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
1884 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
1885 if (pci_resource_flags(dev
, i
) & flags
)
1890 static void __devinit
pci_no_domains(void)
1892 #ifdef CONFIG_PCI_DOMAINS
1893 pci_domains_supported
= 0;
1897 static int __devinit
pci_init(void)
1899 struct pci_dev
*dev
= NULL
;
1901 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
1902 pci_fixup_device(pci_fixup_final
, dev
);
1907 static int __devinit
pci_setup(char *str
)
1910 char *k
= strchr(str
, ',');
1913 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
1914 if (!strcmp(str
, "nomsi")) {
1916 } else if (!strcmp(str
, "noaer")) {
1918 } else if (!strcmp(str
, "nodomains")) {
1920 } else if (!strncmp(str
, "cbiosize=", 9)) {
1921 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
1922 } else if (!strncmp(str
, "cbmemsize=", 10)) {
1923 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
1925 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
1933 early_param("pci", pci_setup
);
1935 device_initcall(pci_init
);
1937 EXPORT_SYMBOL(pci_reenable_device
);
1938 EXPORT_SYMBOL(pci_enable_device_io
);
1939 EXPORT_SYMBOL(pci_enable_device_mem
);
1940 EXPORT_SYMBOL(pci_enable_device
);
1941 EXPORT_SYMBOL(pcim_enable_device
);
1942 EXPORT_SYMBOL(pcim_pin_device
);
1943 EXPORT_SYMBOL(pci_disable_device
);
1944 EXPORT_SYMBOL(pci_find_capability
);
1945 EXPORT_SYMBOL(pci_bus_find_capability
);
1946 EXPORT_SYMBOL(pci_release_regions
);
1947 EXPORT_SYMBOL(pci_request_regions
);
1948 EXPORT_SYMBOL(pci_release_region
);
1949 EXPORT_SYMBOL(pci_request_region
);
1950 EXPORT_SYMBOL(pci_release_selected_regions
);
1951 EXPORT_SYMBOL(pci_request_selected_regions
);
1952 EXPORT_SYMBOL(pci_set_master
);
1953 EXPORT_SYMBOL(pci_set_mwi
);
1954 EXPORT_SYMBOL(pci_try_set_mwi
);
1955 EXPORT_SYMBOL(pci_clear_mwi
);
1956 EXPORT_SYMBOL_GPL(pci_intx
);
1957 EXPORT_SYMBOL(pci_set_dma_mask
);
1958 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
1959 EXPORT_SYMBOL(pci_assign_resource
);
1960 EXPORT_SYMBOL(pci_find_parent_resource
);
1961 EXPORT_SYMBOL(pci_select_bars
);
1963 EXPORT_SYMBOL(pci_set_power_state
);
1964 EXPORT_SYMBOL(pci_save_state
);
1965 EXPORT_SYMBOL(pci_restore_state
);
1966 EXPORT_SYMBOL(pci_pme_capable
);
1967 EXPORT_SYMBOL(pci_pme_active
);
1968 EXPORT_SYMBOL(pci_enable_wake
);
1969 EXPORT_SYMBOL(pci_wake_from_d3
);
1970 EXPORT_SYMBOL(pci_target_state
);
1971 EXPORT_SYMBOL(pci_prepare_to_sleep
);
1972 EXPORT_SYMBOL(pci_back_from_sleep
);
1973 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);