1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex
);
39 const char *pci_power_names
[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names
);
44 int isa_dma_bridge_buggy
;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
48 EXPORT_SYMBOL(pci_pci_problems
);
50 unsigned int pci_pm_d3hot_delay
;
52 static void pci_pme_list_scan(struct work_struct
*work
);
54 static LIST_HEAD(pci_pme_list
);
55 static DEFINE_MUTEX(pci_pme_list_mutex
);
56 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
58 struct pci_pme_device
{
59 struct list_head list
;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
67 unsigned int delay
= dev
->d3hot_delay
;
69 if (delay
< pci_pm_d3hot_delay
)
70 delay
= pci_pm_d3hot_delay
;
76 bool pci_reset_supported(struct pci_dev
*dev
)
78 return dev
->reset_methods
[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported
= 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
89 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size
= DEFAULT_HOTPLUG_MMIO_SIZE
;
102 unsigned long pci_hotplug_mmio_pref_size
= DEFAULT_HOTPLUG_MMIO_PREF_SIZE
;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_SAFE
;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PEER2PEER
;
118 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
128 u8 pci_cache_line_size
;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency
= 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled
;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled
;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled
;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled
);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable
;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force
;
156 static int __init
pcie_port_pm_setup(char *str
)
158 if (!strcmp(str
, "off"))
159 pci_bridge_d3_disable
= true;
160 else if (!strcmp(str
, "force"))
161 pci_bridge_d3_force
= true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup
);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
176 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
179 unsigned char max
, n
;
181 max
= bus
->busn_res
.end
;
182 list_for_each_entry(tmp
, &bus
->children
, node
) {
183 n
= pci_bus_max_busnr(tmp
);
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
195 * Returns error bits set in PCI_STATUS and clears them.
197 int pci_status_get_and_clear_errors(struct pci_dev
*pdev
)
202 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
203 if (ret
!= PCIBIOS_SUCCESSFUL
)
206 status
&= PCI_STATUS_ERROR_BITS
;
208 pci_write_config_word(pdev
, PCI_STATUS
, status
);
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors
);
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem
*__pci_ioremap_resource(struct pci_dev
*pdev
, int bar
,
218 struct resource
*res
= &pdev
->resource
[bar
];
219 resource_size_t start
= res
->start
;
220 resource_size_t size
= resource_size(res
);
223 * Make sure the BAR is actually a memory resource, not an IO resource
225 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
226 pci_err(pdev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
231 return ioremap_wc(start
, size
);
233 return ioremap(start
, size
);
236 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
238 return __pci_ioremap_resource(pdev
, bar
, false);
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
242 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
244 return __pci_ioremap_resource(pdev
, bar
, true);
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
268 static int pci_dev_str_match_path(struct pci_dev
*dev
, const char *path
,
272 int seg
, bus
, slot
, func
;
276 *endptr
= strchrnul(path
, ';');
278 wpath
= kmemdup_nul(path
, *endptr
- path
, GFP_ATOMIC
);
283 p
= strrchr(wpath
, '/');
286 ret
= sscanf(p
, "/%x.%x%c", &slot
, &func
, &end
);
292 if (dev
->devfn
!= PCI_DEVFN(slot
, func
)) {
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
303 dev
= pci_upstream_bridge(dev
);
312 ret
= sscanf(wpath
, "%x:%x:%x.%x%c", &seg
, &bus
, &slot
,
316 ret
= sscanf(wpath
, "%x:%x.%x%c", &bus
, &slot
, &func
, &end
);
323 ret
= (seg
== pci_domain_nr(dev
->bus
) &&
324 bus
== dev
->bus
->number
&&
325 dev
->devfn
== PCI_DEVFN(slot
, func
));
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
362 static int pci_dev_str_match(struct pci_dev
*dev
, const char *p
,
367 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
369 if (strncmp(p
, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 ret
= sscanf(p
, "%hx:%hx:%hx:%hx%n", &vendor
, &device
,
373 &subsystem_vendor
, &subsystem_device
, &count
);
375 ret
= sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
);
379 subsystem_vendor
= 0;
380 subsystem_device
= 0;
385 if ((!vendor
|| vendor
== dev
->vendor
) &&
386 (!device
|| device
== dev
->device
) &&
387 (!subsystem_vendor
||
388 subsystem_vendor
== dev
->subsystem_vendor
) &&
389 (!subsystem_device
||
390 subsystem_device
== dev
->subsystem_device
))
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
397 ret
= pci_dev_str_match_path(dev
, p
, &p
);
412 static u8
__pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
413 u8 pos
, int cap
, int *ttl
)
418 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
424 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
436 static u8
__pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
439 int ttl
= PCI_FIND_CAP_TTL
;
441 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
444 u8
pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
446 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
447 pos
+ PCI_CAP_LIST_NEXT
, cap
);
449 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
451 static u8
__pci_bus_find_cap_start(struct pci_bus
*bus
,
452 unsigned int devfn
, u8 hdr_type
)
456 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
457 if (!(status
& PCI_STATUS_CAP_LIST
))
461 case PCI_HEADER_TYPE_NORMAL
:
462 case PCI_HEADER_TYPE_BRIDGE
:
463 return PCI_CAPABILITY_LIST
;
464 case PCI_HEADER_TYPE_CARDBUS
:
465 return PCI_CB_CAPABILITY_LIST
;
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
490 u8
pci_find_capability(struct pci_dev
*dev
, int cap
)
494 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
496 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
500 EXPORT_SYMBOL(pci_find_capability
);
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
515 u8
pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
519 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
521 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
523 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
527 EXPORT_SYMBOL(pci_bus_find_capability
);
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
540 u16
pci_find_next_ext_capability(struct pci_dev
*dev
, u16 start
, int cap
)
544 u16 pos
= PCI_CFG_SPACE_SIZE
;
546 /* minimum 8 bytes per capability */
547 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
549 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
555 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
566 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
569 pos
= PCI_EXT_CAP_NEXT(header
);
570 if (pos
< PCI_CFG_SPACE_SIZE
)
573 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 u16
pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
597 return pci_find_next_ext_capability(dev
, 0, cap
);
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
608 * Returns the DSN, or zero if the capability does not exist.
610 u64
pci_get_dsn(struct pci_dev
*dev
)
616 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_DSN
);
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
626 pci_read_config_dword(dev
, pos
, &dword
);
628 pci_read_config_dword(dev
, pos
+ 4, &dword
);
629 dsn
|= ((u64
)dword
) << 32;
633 EXPORT_SYMBOL_GPL(pci_get_dsn
);
635 static u8
__pci_find_next_ht_cap(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
637 int rc
, ttl
= PCI_FIND_CAP_TTL
;
640 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
641 mask
= HT_3BIT_CAP_MASK
;
643 mask
= HT_5BIT_CAP_MASK
;
645 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
646 PCI_CAP_ID_HT
, &ttl
);
648 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
649 if (rc
!= PCIBIOS_SUCCESSFUL
)
652 if ((cap
& mask
) == ht_cap
)
655 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
656 pos
+ PCI_CAP_LIST_NEXT
,
657 PCI_CAP_ID_HT
, &ttl
);
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
676 u8
pci_find_next_ht_capability(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
678 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
693 u8
pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
697 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
699 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
715 u16
pci_find_vsec_capability(struct pci_dev
*dev
, u16 vendor
, int cap
)
720 if (vendor
!= dev
->vendor
)
723 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
724 PCI_EXT_CAP_ID_VNDR
))) {
725 if (pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
,
726 &header
) == PCIBIOS_SUCCESSFUL
&&
727 PCI_VNDR_HEADER_ID(header
) == cap
)
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability
);
736 * pci_find_parent_resource - return resource region of parent bus of given
738 * @dev: PCI device structure contains resources to be searched
739 * @res: child resource record for which parent is sought
741 * For given resource region of given device, return the resource region of
742 * parent bus the given region is contained in.
744 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
745 struct resource
*res
)
747 const struct pci_bus
*bus
= dev
->bus
;
751 pci_bus_for_each_resource(bus
, r
, i
) {
754 if (resource_contains(r
, res
)) {
757 * If the window is prefetchable but the BAR is
758 * not, the allocator made a mistake.
760 if (r
->flags
& IORESOURCE_PREFETCH
&&
761 !(res
->flags
& IORESOURCE_PREFETCH
))
765 * If we're below a transparent bridge, there may
766 * be both a positively-decoded aperture and a
767 * subtractively-decoded region that contain the BAR.
768 * We want the positively-decoded one, so this depends
769 * on pci_bus_for_each_resource() giving us those
777 EXPORT_SYMBOL(pci_find_parent_resource
);
780 * pci_find_resource - Return matching PCI device resource
781 * @dev: PCI device to query
782 * @res: Resource to look for
784 * Goes over standard PCI resources (BARs) and checks if the given resource
785 * is partially or fully contained in any of them. In that case the
786 * matching resource is returned, %NULL otherwise.
788 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
792 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
793 struct resource
*r
= &dev
->resource
[i
];
795 if (r
->start
&& resource_contains(r
, res
))
801 EXPORT_SYMBOL(pci_find_resource
);
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
805 * @dev: the PCI device to operate on
806 * @pos: config space offset of status word
807 * @mask: mask of bit(s) to care about in status word
809 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
811 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
815 /* Wait for Transaction Pending bit clean */
816 for (i
= 0; i
< 4; i
++) {
819 msleep((1 << (i
- 1)) * 100);
821 pci_read_config_word(dev
, pos
, &status
);
822 if (!(status
& mask
))
829 static int pci_acs_enable
;
832 * pci_request_acs - ask for ACS to be enabled if supported
834 void pci_request_acs(void)
839 static const char *disable_acs_redir_param
;
842 * pci_disable_acs_redir - disable ACS redirect capabilities
843 * @dev: the PCI device
845 * For only devices specified in the disable_acs_redir parameter.
847 static void pci_disable_acs_redir(struct pci_dev
*dev
)
854 if (!disable_acs_redir_param
)
857 p
= disable_acs_redir_param
;
859 ret
= pci_dev_str_match(dev
, p
, &p
);
861 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
862 disable_acs_redir_param
);
865 } else if (ret
== 1) {
870 if (*p
!= ';' && *p
!= ',') {
871 /* End of param or invalid format */
880 if (!pci_dev_specific_disable_acs_redir(dev
))
885 pci_warn(dev
, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
889 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
891 /* P2P Request & Completion Redirect */
892 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
894 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
896 pci_info(dev
, "disabled ACS redirect\n");
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
901 * @dev: the PCI device
903 static void pci_std_enable_acs(struct pci_dev
*dev
)
913 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
914 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
916 /* Source Validation */
917 ctrl
|= (cap
& PCI_ACS_SV
);
919 /* P2P Request Redirect */
920 ctrl
|= (cap
& PCI_ACS_RR
);
922 /* P2P Completion Redirect */
923 ctrl
|= (cap
& PCI_ACS_CR
);
925 /* Upstream Forwarding */
926 ctrl
|= (cap
& PCI_ACS_UF
);
928 /* Enable Translation Blocking for external devices and noats */
929 if (pci_ats_disabled() || dev
->external_facing
|| dev
->untrusted
)
930 ctrl
|= (cap
& PCI_ACS_TB
);
932 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
936 * pci_enable_acs - enable ACS if hardware support it
937 * @dev: the PCI device
939 static void pci_enable_acs(struct pci_dev
*dev
)
942 goto disable_acs_redir
;
944 if (!pci_dev_specific_enable_acs(dev
))
945 goto disable_acs_redir
;
947 pci_std_enable_acs(dev
);
951 * Note: pci_disable_acs_redir() must be called even if ACS was not
952 * enabled by the kernel because it may have been enabled by
953 * platform firmware. So if we are told to disable it, we should
954 * always disable it after setting the kernel's default
957 pci_disable_acs_redir(dev
);
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
962 * @dev: PCI device to have its BARs restored
964 * Restore the BAR values for a given device, so as to make it
965 * accessible by its driver.
967 static void pci_restore_bars(struct pci_dev
*dev
)
971 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
972 pci_update_resource(dev
, i
);
975 static const struct pci_platform_pm_ops
*pci_platform_pm
;
977 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
979 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
980 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
982 pci_platform_pm
= ops
;
986 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
988 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
991 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
994 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
997 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
999 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
1002 static inline void platform_pci_refresh_power_state(struct pci_dev
*dev
)
1004 if (pci_platform_pm
&& pci_platform_pm
->refresh_state
)
1005 pci_platform_pm
->refresh_state(dev
);
1008 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
1010 return pci_platform_pm
?
1011 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
1014 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
1016 return pci_platform_pm
?
1017 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
1020 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
1022 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
1025 static inline bool platform_pci_bridge_d3(struct pci_dev
*dev
)
1027 if (pci_platform_pm
&& pci_platform_pm
->bridge_d3
)
1028 return pci_platform_pm
->bridge_d3(dev
);
1033 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1035 * @dev: PCI device to handle.
1036 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1039 * -EINVAL if the requested state is invalid.
1040 * -EIO if device does not support PCI PM or its PM capabilities register has a
1041 * wrong version, or device doesn't support the requested state.
1042 * 0 if device already is in the requested state.
1043 * 0 if device's power state has been successfully changed.
1045 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1048 bool need_restore
= false;
1050 /* Check if we're already there */
1051 if (dev
->current_state
== state
)
1057 if (state
< PCI_D0
|| state
> PCI_D3hot
)
1061 * Validate transition: We can enter D0 from any state, but if
1062 * we're already in a low-power state, we can only go deeper. E.g.,
1063 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1064 * we'd have to go from D3 to D0, then to D1.
1066 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
1067 && dev
->current_state
> state
) {
1068 pci_err(dev
, "invalid power transition (from %s to %s)\n",
1069 pci_power_name(dev
->current_state
),
1070 pci_power_name(state
));
1074 /* Check if this device supports the desired state */
1075 if ((state
== PCI_D1
&& !dev
->d1_support
)
1076 || (state
== PCI_D2
&& !dev
->d2_support
))
1079 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1080 if (pmcsr
== (u16
) ~0) {
1081 pci_err(dev
, "can't change power state from %s to %s (config space inaccessible)\n",
1082 pci_power_name(dev
->current_state
),
1083 pci_power_name(state
));
1088 * If we're (effectively) in D3, force entire word to 0.
1089 * This doesn't affect PME_Status, disables PME_En, and
1090 * sets PowerState to 0.
1092 switch (dev
->current_state
) {
1096 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
1101 case PCI_UNKNOWN
: /* Boot-up */
1102 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
1103 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
1104 need_restore
= true;
1105 fallthrough
; /* force to D0 */
1111 /* Enter specified state */
1112 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1115 * Mandatory power management transition delays; see PCI PM 1.1
1118 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
1119 pci_dev_d3_sleep(dev
);
1120 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
1121 udelay(PCI_PM_D2_DELAY
);
1123 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1124 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1125 if (dev
->current_state
!= state
)
1126 pci_info_ratelimited(dev
, "refused to change power state from %s to %s\n",
1127 pci_power_name(dev
->current_state
),
1128 pci_power_name(state
));
1131 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1132 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1133 * from D3hot to D0 _may_ perform an internal reset, thereby
1134 * going to "D0 Uninitialized" rather than "D0 Initialized".
1135 * For example, at least some versions of the 3c905B and the
1136 * 3c556B exhibit this behaviour.
1138 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1139 * devices in a D3hot state at boot. Consequently, we need to
1140 * restore at least the BARs so that the device will be
1141 * accessible to its driver.
1144 pci_restore_bars(dev
);
1147 pcie_aspm_pm_state_change(dev
->bus
->self
);
1153 * pci_update_current_state - Read power state of given device and cache it
1154 * @dev: PCI device to handle.
1155 * @state: State to cache in case the device doesn't have the PM capability
1157 * The power state is read from the PMCSR register, which however is
1158 * inaccessible in D3cold. The platform firmware is therefore queried first
1159 * to detect accessibility of the register. In case the platform firmware
1160 * reports an incorrect state or the device isn't power manageable by the
1161 * platform at all, we try to detect D3cold by testing accessibility of the
1162 * vendor ID in config space.
1164 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
1166 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
1167 !pci_device_is_present(dev
)) {
1168 dev
->current_state
= PCI_D3cold
;
1169 } else if (dev
->pm_cap
) {
1172 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1173 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1175 dev
->current_state
= state
;
1180 * pci_refresh_power_state - Refresh the given device's power state data
1181 * @dev: Target PCI device.
1183 * Ask the platform to refresh the devices power state information and invoke
1184 * pci_update_current_state() to update its current PCI power state.
1186 void pci_refresh_power_state(struct pci_dev
*dev
)
1188 if (platform_pci_power_manageable(dev
))
1189 platform_pci_refresh_power_state(dev
);
1191 pci_update_current_state(dev
, dev
->current_state
);
1195 * pci_platform_power_transition - Use platform to change device power state
1196 * @dev: PCI device to handle.
1197 * @state: State to put the device into.
1199 int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
1203 if (platform_pci_power_manageable(dev
)) {
1204 error
= platform_pci_set_power_state(dev
, state
);
1206 pci_update_current_state(dev
, state
);
1210 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
1211 dev
->current_state
= PCI_D0
;
1215 EXPORT_SYMBOL_GPL(pci_platform_power_transition
);
1217 static int pci_resume_one(struct pci_dev
*pci_dev
, void *ign
)
1219 pm_request_resume(&pci_dev
->dev
);
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1225 * @bus: Top bus of the subtree to walk.
1227 void pci_resume_bus(struct pci_bus
*bus
)
1230 pci_walk_bus(bus
, pci_resume_one
, NULL
);
1233 static int pci_dev_wait(struct pci_dev
*dev
, char *reset_type
, int timeout
)
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 data to complete the read (except when
1243 * CRS SV is enabled and the read was for the Vendor ID; in that
1244 * case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1250 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1252 if (delay
> timeout
) {
1253 pci_warn(dev
, "not ready %dms after %s; giving up\n",
1254 delay
- 1, reset_type
);
1259 pci_info(dev
, "not ready %dms after %s; waiting\n",
1260 delay
- 1, reset_type
);
1264 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1268 pci_info(dev
, "ready %dms after %s\n", delay
- 1,
1275 * pci_power_up - Put the given device into D0
1276 * @dev: PCI device to power up
1278 int pci_power_up(struct pci_dev
*dev
)
1280 pci_platform_power_transition(dev
, PCI_D0
);
1283 * Mandatory power management transition delays are handled in
1284 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1285 * corresponding bridge.
1287 if (dev
->runtime_d3cold
) {
1289 * When powering on a bridge from D3cold, the whole hierarchy
1290 * may be powered on into D0uninitialized state, resume them to
1291 * give them a chance to suspend again
1293 pci_resume_bus(dev
->subordinate
);
1296 return pci_raw_set_power_state(dev
, PCI_D0
);
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1301 * @dev: Device to handle
1302 * @data: pointer to state to be set
1304 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
1306 pci_power_t state
= *(pci_power_t
*)data
;
1308 dev
->current_state
= state
;
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1314 * @bus: Top bus of the subtree to walk.
1315 * @state: state to be set
1317 void pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
1320 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
1324 * pci_set_power_state - Set the power state of a PCI device
1325 * @dev: PCI device to handle.
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1328 * Transition a device to a new power state, using the platform firmware and/or
1329 * the device's PCI PM registers.
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1335 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1336 * 0 if device already is in the requested state.
1337 * 0 if the transition is to D3 but D3 is not supported.
1338 * 0 if device's power state has been successfully changed.
1340 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1344 /* Bound the state we're entering */
1345 if (state
> PCI_D3cold
)
1347 else if (state
< PCI_D0
)
1349 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
1352 * If the device or the parent bridge do not support PCI
1353 * PM, ignore the request if we're doing anything other
1354 * than putting it into D0 (which would only happen on
1359 /* Check if we're already there */
1360 if (dev
->current_state
== state
)
1363 if (state
== PCI_D0
)
1364 return pci_power_up(dev
);
1367 * This device is quirked not to be put into D3, so don't put it in
1370 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
1374 * To put device in D3cold, we put device into D3hot in native
1375 * way, then put device into D3cold with platform ops
1377 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
1380 if (pci_platform_power_transition(dev
, state
))
1383 /* Powering off a bridge may power off the whole hierarchy */
1384 if (state
== PCI_D3cold
)
1385 pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
1389 EXPORT_SYMBOL(pci_set_power_state
);
1392 * pci_choose_state - Choose the power state of a PCI device
1393 * @dev: PCI device to be suspended
1394 * @state: target sleep state for the whole system. This is the value
1395 * that is passed to suspend() function.
1397 * Returns PCI power state suitable for given device and given system
1400 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
1407 ret
= platform_pci_choose_state(dev
);
1408 if (ret
!= PCI_POWER_ERROR
)
1411 switch (state
.event
) {
1414 case PM_EVENT_FREEZE
:
1415 case PM_EVENT_PRETHAW
:
1416 /* REVISIT both freeze and pre-thaw "should" use D0 */
1417 case PM_EVENT_SUSPEND
:
1418 case PM_EVENT_HIBERNATE
:
1421 pci_info(dev
, "unrecognized suspend event %d\n",
1427 EXPORT_SYMBOL(pci_choose_state
);
1429 #define PCI_EXP_SAVE_REGS 7
1431 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
1432 u16 cap
, bool extended
)
1434 struct pci_cap_saved_state
*tmp
;
1436 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
1437 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
1443 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
1445 return _pci_find_saved_cap(dev
, cap
, false);
1448 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1450 return _pci_find_saved_cap(dev
, cap
, true);
1453 static int pci_save_pcie_state(struct pci_dev
*dev
)
1456 struct pci_cap_saved_state
*save_state
;
1459 if (!pci_is_pcie(dev
))
1462 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1464 pci_err(dev
, "buffer not found in %s\n", __func__
);
1468 cap
= (u16
*)&save_state
->cap
.data
[0];
1469 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1470 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1471 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1472 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1473 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1474 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1475 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1480 void pci_bridge_reconfigure_ltr(struct pci_dev
*dev
)
1482 #ifdef CONFIG_PCIEASPM
1483 struct pci_dev
*bridge
;
1486 bridge
= pci_upstream_bridge(dev
);
1487 if (bridge
&& bridge
->ltr_path
) {
1488 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
, &ctl
);
1489 if (!(ctl
& PCI_EXP_DEVCTL2_LTR_EN
)) {
1490 pci_dbg(bridge
, "re-enabling LTR\n");
1491 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
1492 PCI_EXP_DEVCTL2_LTR_EN
);
1498 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1501 struct pci_cap_saved_state
*save_state
;
1504 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1509 * Downstream ports reset the LTR enable bit when link goes down.
1510 * Check and re-configure the bit here before restoring device.
1511 * PCIe r5.0, sec 7.5.3.16.
1513 pci_bridge_reconfigure_ltr(dev
);
1515 cap
= (u16
*)&save_state
->cap
.data
[0];
1516 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1517 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1518 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1519 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1520 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1521 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1522 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1525 static int pci_save_pcix_state(struct pci_dev
*dev
)
1528 struct pci_cap_saved_state
*save_state
;
1530 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1534 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1536 pci_err(dev
, "buffer not found in %s\n", __func__
);
1540 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1541 (u16
*)save_state
->cap
.data
);
1546 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1549 struct pci_cap_saved_state
*save_state
;
1552 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1553 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1554 if (!save_state
|| !pos
)
1556 cap
= (u16
*)&save_state
->cap
.data
[0];
1558 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1561 static void pci_save_ltr_state(struct pci_dev
*dev
)
1564 struct pci_cap_saved_state
*save_state
;
1567 if (!pci_is_pcie(dev
))
1570 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1574 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1576 pci_err(dev
, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1580 cap
= (u16
*)&save_state
->cap
.data
[0];
1581 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, cap
++);
1582 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, cap
++);
1585 static void pci_restore_ltr_state(struct pci_dev
*dev
)
1587 struct pci_cap_saved_state
*save_state
;
1591 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1592 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1593 if (!save_state
|| !ltr
)
1596 cap
= (u16
*)&save_state
->cap
.data
[0];
1597 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, *cap
++);
1598 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, *cap
++);
1602 * pci_save_state - save the PCI configuration space of a device before
1604 * @dev: PCI device that we're dealing with
1606 int pci_save_state(struct pci_dev
*dev
)
1609 /* XXX: 100% dword access ok here? */
1610 for (i
= 0; i
< 16; i
++) {
1611 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1612 pci_dbg(dev
, "saving config space at offset %#x (reading %#x)\n",
1613 i
* 4, dev
->saved_config_space
[i
]);
1615 dev
->state_saved
= true;
1617 i
= pci_save_pcie_state(dev
);
1621 i
= pci_save_pcix_state(dev
);
1625 pci_save_ltr_state(dev
);
1626 pci_save_aspm_l1ss_state(dev
);
1627 pci_save_dpc_state(dev
);
1628 pci_save_aer_state(dev
);
1629 pci_save_ptm_state(dev
);
1630 return pci_save_vc_state(dev
);
1632 EXPORT_SYMBOL(pci_save_state
);
1634 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1635 u32 saved_val
, int retry
, bool force
)
1639 pci_read_config_dword(pdev
, offset
, &val
);
1640 if (!force
&& val
== saved_val
)
1644 pci_dbg(pdev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1645 offset
, val
, saved_val
);
1646 pci_write_config_dword(pdev
, offset
, saved_val
);
1650 pci_read_config_dword(pdev
, offset
, &val
);
1651 if (val
== saved_val
)
1658 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1659 int start
, int end
, int retry
,
1664 for (index
= end
; index
>= start
; index
--)
1665 pci_restore_config_dword(pdev
, 4 * index
,
1666 pdev
->saved_config_space
[index
],
1670 static void pci_restore_config_space(struct pci_dev
*pdev
)
1672 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1673 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1674 /* Restore BARs before the command register. */
1675 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1676 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1677 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1678 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1681 * Force rewriting of prefetch registers to avoid S3 resume
1682 * issues on Intel PCI bridges that occur when these
1683 * registers are not explicitly written.
1685 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1686 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1688 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1692 static void pci_restore_rebar_state(struct pci_dev
*pdev
)
1694 unsigned int pos
, nbars
, i
;
1697 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
1701 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1702 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
1703 PCI_REBAR_CTRL_NBAR_SHIFT
;
1705 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
1706 struct resource
*res
;
1709 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1710 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
1711 res
= pdev
->resource
+ bar_idx
;
1712 size
= pci_rebar_bytes_to_size(resource_size(res
));
1713 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
1714 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
1715 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
1720 * pci_restore_state - Restore the saved state of a PCI device
1721 * @dev: PCI device that we're dealing with
1723 void pci_restore_state(struct pci_dev
*dev
)
1725 if (!dev
->state_saved
)
1729 * Restore max latencies (in the LTR capability) before enabling
1730 * LTR itself (in the PCIe capability).
1732 pci_restore_ltr_state(dev
);
1733 pci_restore_aspm_l1ss_state(dev
);
1735 pci_restore_pcie_state(dev
);
1736 pci_restore_pasid_state(dev
);
1737 pci_restore_pri_state(dev
);
1738 pci_restore_ats_state(dev
);
1739 pci_restore_vc_state(dev
);
1740 pci_restore_rebar_state(dev
);
1741 pci_restore_dpc_state(dev
);
1742 pci_restore_ptm_state(dev
);
1744 pci_aer_clear_status(dev
);
1745 pci_restore_aer_state(dev
);
1747 pci_restore_config_space(dev
);
1749 pci_restore_pcix_state(dev
);
1750 pci_restore_msi_state(dev
);
1752 /* Restore ACS and IOV configuration state */
1753 pci_enable_acs(dev
);
1754 pci_restore_iov_state(dev
);
1756 dev
->state_saved
= false;
1758 EXPORT_SYMBOL(pci_restore_state
);
1760 struct pci_saved_state
{
1761 u32 config_space
[16];
1762 struct pci_cap_saved_data cap
[];
1766 * pci_store_saved_state - Allocate and return an opaque struct containing
1767 * the device saved state.
1768 * @dev: PCI device that we're dealing with
1770 * Return NULL if no state or error.
1772 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1774 struct pci_saved_state
*state
;
1775 struct pci_cap_saved_state
*tmp
;
1776 struct pci_cap_saved_data
*cap
;
1779 if (!dev
->state_saved
)
1782 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1784 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1785 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1787 state
= kzalloc(size
, GFP_KERNEL
);
1791 memcpy(state
->config_space
, dev
->saved_config_space
,
1792 sizeof(state
->config_space
));
1795 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1796 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1797 memcpy(cap
, &tmp
->cap
, len
);
1798 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1800 /* Empty cap_save terminates list */
1804 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1807 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1808 * @dev: PCI device that we're dealing with
1809 * @state: Saved state returned from pci_store_saved_state()
1811 int pci_load_saved_state(struct pci_dev
*dev
,
1812 struct pci_saved_state
*state
)
1814 struct pci_cap_saved_data
*cap
;
1816 dev
->state_saved
= false;
1821 memcpy(dev
->saved_config_space
, state
->config_space
,
1822 sizeof(state
->config_space
));
1826 struct pci_cap_saved_state
*tmp
;
1828 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1829 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1832 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1833 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1834 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1837 dev
->state_saved
= true;
1840 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1843 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1844 * and free the memory allocated for it.
1845 * @dev: PCI device that we're dealing with
1846 * @state: Pointer to saved state returned from pci_store_saved_state()
1848 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1849 struct pci_saved_state
**state
)
1851 int ret
= pci_load_saved_state(dev
, *state
);
1856 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1858 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1860 return pci_enable_resources(dev
, bars
);
1863 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1866 struct pci_dev
*bridge
;
1870 err
= pci_set_power_state(dev
, PCI_D0
);
1871 if (err
< 0 && err
!= -EIO
)
1874 bridge
= pci_upstream_bridge(dev
);
1876 pcie_aspm_powersave_config_link(bridge
);
1878 err
= pcibios_enable_device(dev
, bars
);
1881 pci_fixup_device(pci_fixup_enable
, dev
);
1883 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1886 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1888 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1889 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1890 pci_write_config_word(dev
, PCI_COMMAND
,
1891 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1898 * pci_reenable_device - Resume abandoned device
1899 * @dev: PCI device to be resumed
1901 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1902 * to be called by normal code, write proper resume handler and use it instead.
1904 int pci_reenable_device(struct pci_dev
*dev
)
1906 if (pci_is_enabled(dev
))
1907 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1910 EXPORT_SYMBOL(pci_reenable_device
);
1912 static void pci_enable_bridge(struct pci_dev
*dev
)
1914 struct pci_dev
*bridge
;
1917 bridge
= pci_upstream_bridge(dev
);
1919 pci_enable_bridge(bridge
);
1921 if (pci_is_enabled(dev
)) {
1922 if (!dev
->is_busmaster
)
1923 pci_set_master(dev
);
1927 retval
= pci_enable_device(dev
);
1929 pci_err(dev
, "Error enabling bridge (%d), continuing\n",
1931 pci_set_master(dev
);
1934 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1936 struct pci_dev
*bridge
;
1941 * Power state could be unknown at this point, either due to a fresh
1942 * boot or a device removal call. So get the current power state
1943 * so that things like MSI message writing will behave as expected
1944 * (e.g. if the device really is in D0 at enable time).
1946 pci_update_current_state(dev
, dev
->current_state
);
1948 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1949 return 0; /* already enabled */
1951 bridge
= pci_upstream_bridge(dev
);
1953 pci_enable_bridge(bridge
);
1955 /* only skip sriov related */
1956 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1957 if (dev
->resource
[i
].flags
& flags
)
1959 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1960 if (dev
->resource
[i
].flags
& flags
)
1963 err
= do_pci_enable_device(dev
, bars
);
1965 atomic_dec(&dev
->enable_cnt
);
1970 * pci_enable_device_io - Initialize a device for use with IO space
1971 * @dev: PCI device to be initialized
1973 * Initialize device before it's used by a driver. Ask low-level code
1974 * to enable I/O resources. Wake up the device if it was suspended.
1975 * Beware, this function can fail.
1977 int pci_enable_device_io(struct pci_dev
*dev
)
1979 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1981 EXPORT_SYMBOL(pci_enable_device_io
);
1984 * pci_enable_device_mem - Initialize a device for use with Memory space
1985 * @dev: PCI device to be initialized
1987 * Initialize device before it's used by a driver. Ask low-level code
1988 * to enable Memory resources. Wake up the device if it was suspended.
1989 * Beware, this function can fail.
1991 int pci_enable_device_mem(struct pci_dev
*dev
)
1993 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1995 EXPORT_SYMBOL(pci_enable_device_mem
);
1998 * pci_enable_device - Initialize device before it's used by a driver.
1999 * @dev: PCI device to be initialized
2001 * Initialize device before it's used by a driver. Ask low-level code
2002 * to enable I/O and memory. Wake up the device if it was suspended.
2003 * Beware, this function can fail.
2005 * Note we don't actually enable the device many times if we call
2006 * this function repeatedly (we just increment the count).
2008 int pci_enable_device(struct pci_dev
*dev
)
2010 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
2012 EXPORT_SYMBOL(pci_enable_device
);
2015 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2016 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2017 * there's no need to track it separately. pci_devres is initialized
2018 * when a device is enabled using managed PCI device enable interface.
2021 unsigned int enabled
:1;
2022 unsigned int pinned
:1;
2023 unsigned int orig_intx
:1;
2024 unsigned int restore_intx
:1;
2029 static void pcim_release(struct device
*gendev
, void *res
)
2031 struct pci_dev
*dev
= to_pci_dev(gendev
);
2032 struct pci_devres
*this = res
;
2035 if (dev
->msi_enabled
)
2036 pci_disable_msi(dev
);
2037 if (dev
->msix_enabled
)
2038 pci_disable_msix(dev
);
2040 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
2041 if (this->region_mask
& (1 << i
))
2042 pci_release_region(dev
, i
);
2047 if (this->restore_intx
)
2048 pci_intx(dev
, this->orig_intx
);
2050 if (this->enabled
&& !this->pinned
)
2051 pci_disable_device(dev
);
2054 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
2056 struct pci_devres
*dr
, *new_dr
;
2058 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2062 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
2065 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
2068 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
2070 if (pci_is_managed(pdev
))
2071 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2076 * pcim_enable_device - Managed pci_enable_device()
2077 * @pdev: PCI device to be initialized
2079 * Managed pci_enable_device().
2081 int pcim_enable_device(struct pci_dev
*pdev
)
2083 struct pci_devres
*dr
;
2086 dr
= get_pci_dr(pdev
);
2092 rc
= pci_enable_device(pdev
);
2094 pdev
->is_managed
= 1;
2099 EXPORT_SYMBOL(pcim_enable_device
);
2102 * pcim_pin_device - Pin managed PCI device
2103 * @pdev: PCI device to pin
2105 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2106 * driver detach. @pdev must have been enabled with
2107 * pcim_enable_device().
2109 void pcim_pin_device(struct pci_dev
*pdev
)
2111 struct pci_devres
*dr
;
2113 dr
= find_pci_dr(pdev
);
2114 WARN_ON(!dr
|| !dr
->enabled
);
2118 EXPORT_SYMBOL(pcim_pin_device
);
2121 * pcibios_add_device - provide arch specific hooks when adding device dev
2122 * @dev: the PCI device being added
2124 * Permits the platform to provide architecture specific functionality when
2125 * devices are added. This is the default implementation. Architecture
2126 * implementations can override this.
2128 int __weak
pcibios_add_device(struct pci_dev
*dev
)
2134 * pcibios_release_device - provide arch specific hooks when releasing
2136 * @dev: the PCI device being released
2138 * Permits the platform to provide architecture specific functionality when
2139 * devices are released. This is the default implementation. Architecture
2140 * implementations can override this.
2142 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
2145 * pcibios_disable_device - disable arch specific PCI resources for device dev
2146 * @dev: the PCI device to disable
2148 * Disables architecture specific PCI resources for the device. This
2149 * is the default implementation. Architecture implementations can
2152 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
2155 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2156 * @irq: ISA IRQ to penalize
2157 * @active: IRQ active or not
2159 * Permits the platform to provide architecture-specific functionality when
2160 * penalizing ISA IRQs. This is the default implementation. Architecture
2161 * implementations can override this.
2163 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
2165 static void do_pci_disable_device(struct pci_dev
*dev
)
2169 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
2170 if (pci_command
& PCI_COMMAND_MASTER
) {
2171 pci_command
&= ~PCI_COMMAND_MASTER
;
2172 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
2175 pcibios_disable_device(dev
);
2179 * pci_disable_enabled_device - Disable device without updating enable_cnt
2180 * @dev: PCI device to disable
2182 * NOTE: This function is a backend of PCI power management routines and is
2183 * not supposed to be called drivers.
2185 void pci_disable_enabled_device(struct pci_dev
*dev
)
2187 if (pci_is_enabled(dev
))
2188 do_pci_disable_device(dev
);
2192 * pci_disable_device - Disable PCI device after use
2193 * @dev: PCI device to be disabled
2195 * Signal to the system that the PCI device is not in use by the system
2196 * anymore. This only involves disabling PCI bus-mastering, if active.
2198 * Note we don't actually disable the device until all callers of
2199 * pci_enable_device() have called pci_disable_device().
2201 void pci_disable_device(struct pci_dev
*dev
)
2203 struct pci_devres
*dr
;
2205 dr
= find_pci_dr(dev
);
2209 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
2210 "disabling already-disabled device");
2212 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
2215 do_pci_disable_device(dev
);
2217 dev
->is_busmaster
= 0;
2219 EXPORT_SYMBOL(pci_disable_device
);
2222 * pcibios_set_pcie_reset_state - set reset state for device dev
2223 * @dev: the PCIe device reset
2224 * @state: Reset state to enter into
2226 * Set the PCIe reset state for the device. This is the default
2227 * implementation. Architecture implementations can override this.
2229 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
2230 enum pcie_reset_state state
)
2236 * pci_set_pcie_reset_state - set reset state for device dev
2237 * @dev: the PCIe device reset
2238 * @state: Reset state to enter into
2240 * Sets the PCI reset state for the device.
2242 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
2244 return pcibios_set_pcie_reset_state(dev
, state
);
2246 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
2248 void pcie_clear_device_status(struct pci_dev
*dev
)
2252 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
2253 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
2257 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2258 * @dev: PCIe root port or event collector.
2260 void pcie_clear_root_pme_status(struct pci_dev
*dev
)
2262 pcie_capability_set_dword(dev
, PCI_EXP_RTSTA
, PCI_EXP_RTSTA_PME
);
2266 * pci_check_pme_status - Check if given device has generated PME.
2267 * @dev: Device to check.
2269 * Check the PME status of the device and if set, clear it and clear PME enable
2270 * (if set). Return 'true' if PME status and PME enable were both set or
2271 * 'false' otherwise.
2273 bool pci_check_pme_status(struct pci_dev
*dev
)
2282 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
2283 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
2284 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
2287 /* Clear PME status. */
2288 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2289 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
2290 /* Disable PME to avoid interrupt flood. */
2291 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2295 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
2301 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2302 * @dev: Device to handle.
2303 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2305 * Check if @dev has generated PME and queue a resume request for it in that
2308 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
2310 if (pme_poll_reset
&& dev
->pme_poll
)
2311 dev
->pme_poll
= false;
2313 if (pci_check_pme_status(dev
)) {
2314 pci_wakeup_event(dev
);
2315 pm_request_resume(&dev
->dev
);
2321 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2322 * @bus: Top bus of the subtree to walk.
2324 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
2327 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
2332 * pci_pme_capable - check the capability of PCI device to generate PME#
2333 * @dev: PCI device to handle.
2334 * @state: PCI state from which device will issue PME#.
2336 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
2341 return !!(dev
->pme_support
& (1 << state
));
2343 EXPORT_SYMBOL(pci_pme_capable
);
2345 static void pci_pme_list_scan(struct work_struct
*work
)
2347 struct pci_pme_device
*pme_dev
, *n
;
2349 mutex_lock(&pci_pme_list_mutex
);
2350 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
2351 if (pme_dev
->dev
->pme_poll
) {
2352 struct pci_dev
*bridge
;
2354 bridge
= pme_dev
->dev
->bus
->self
;
2356 * If bridge is in low power state, the
2357 * configuration space of subordinate devices
2358 * may be not accessible
2360 if (bridge
&& bridge
->current_state
!= PCI_D0
)
2363 * If the device is in D3cold it should not be
2366 if (pme_dev
->dev
->current_state
== PCI_D3cold
)
2369 pci_pme_wakeup(pme_dev
->dev
, NULL
);
2371 list_del(&pme_dev
->list
);
2375 if (!list_empty(&pci_pme_list
))
2376 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
2377 msecs_to_jiffies(PME_TIMEOUT
));
2378 mutex_unlock(&pci_pme_list_mutex
);
2381 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
2385 if (!dev
->pme_support
)
2388 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2389 /* Clear PME_Status by writing 1 to it and enable PME# */
2390 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
2392 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2394 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2398 * pci_pme_restore - Restore PME configuration after config space restore.
2399 * @dev: PCI device to update.
2401 void pci_pme_restore(struct pci_dev
*dev
)
2405 if (!dev
->pme_support
)
2408 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2409 if (dev
->wakeup_prepared
) {
2410 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
2411 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
2413 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2414 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2416 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2420 * pci_pme_active - enable or disable PCI device's PME# function
2421 * @dev: PCI device to handle.
2422 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2424 * The caller must verify that the device is capable of generating PME# before
2425 * calling this function with @enable equal to 'true'.
2427 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
2429 __pci_pme_active(dev
, enable
);
2432 * PCI (as opposed to PCIe) PME requires that the device have
2433 * its PME# line hooked up correctly. Not all hardware vendors
2434 * do this, so the PME never gets delivered and the device
2435 * remains asleep. The easiest way around this is to
2436 * periodically walk the list of suspended devices and check
2437 * whether any have their PME flag set. The assumption is that
2438 * we'll wake up often enough anyway that this won't be a huge
2439 * hit, and the power savings from the devices will still be a
2442 * Although PCIe uses in-band PME message instead of PME# line
2443 * to report PME, PME does not work for some PCIe devices in
2444 * reality. For example, there are devices that set their PME
2445 * status bits, but don't really bother to send a PME message;
2446 * there are PCI Express Root Ports that don't bother to
2447 * trigger interrupts when they receive PME messages from the
2448 * devices below. So PME poll is used for PCIe devices too.
2451 if (dev
->pme_poll
) {
2452 struct pci_pme_device
*pme_dev
;
2454 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
2457 pci_warn(dev
, "can't enable PME#\n");
2461 mutex_lock(&pci_pme_list_mutex
);
2462 list_add(&pme_dev
->list
, &pci_pme_list
);
2463 if (list_is_singular(&pci_pme_list
))
2464 queue_delayed_work(system_freezable_wq
,
2466 msecs_to_jiffies(PME_TIMEOUT
));
2467 mutex_unlock(&pci_pme_list_mutex
);
2469 mutex_lock(&pci_pme_list_mutex
);
2470 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
2471 if (pme_dev
->dev
== dev
) {
2472 list_del(&pme_dev
->list
);
2477 mutex_unlock(&pci_pme_list_mutex
);
2481 pci_dbg(dev
, "PME# %s\n", enable
? "enabled" : "disabled");
2483 EXPORT_SYMBOL(pci_pme_active
);
2486 * __pci_enable_wake - enable PCI device as wakeup event source
2487 * @dev: PCI device affected
2488 * @state: PCI state from which device will issue wakeup events
2489 * @enable: True to enable event generation; false to disable
2491 * This enables the device as a wakeup event source, or disables it.
2492 * When such events involves platform-specific hooks, those hooks are
2493 * called automatically by this routine.
2495 * Devices with legacy power management (no standard PCI PM capabilities)
2496 * always require such platform hooks.
2499 * 0 is returned on success
2500 * -EINVAL is returned if device is not supposed to wake up the system
2501 * Error code depending on the platform is returned if both the platform and
2502 * the native mechanism fail to enable the generation of wake-up events
2504 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
2509 * Bridges that are not power-manageable directly only signal
2510 * wakeup on behalf of subordinate devices which is set up
2511 * elsewhere, so skip them. However, bridges that are
2512 * power-manageable may signal wakeup for themselves (for example,
2513 * on a hotplug event) and they need to be covered here.
2515 if (!pci_power_manageable(dev
))
2518 /* Don't do the same thing twice in a row for one device. */
2519 if (!!enable
== !!dev
->wakeup_prepared
)
2523 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2524 * Anderson we should be doing PME# wake enable followed by ACPI wake
2525 * enable. To disable wake-up we call the platform first, for symmetry.
2532 * Enable PME signaling if the device can signal PME from
2533 * D3cold regardless of whether or not it can signal PME from
2534 * the current target state, because that will allow it to
2535 * signal PME when the hierarchy above it goes into D3cold and
2536 * the device itself ends up in D3cold as a result of that.
2538 if (pci_pme_capable(dev
, state
) || pci_pme_capable(dev
, PCI_D3cold
))
2539 pci_pme_active(dev
, true);
2542 error
= platform_pci_set_wakeup(dev
, true);
2546 dev
->wakeup_prepared
= true;
2548 platform_pci_set_wakeup(dev
, false);
2549 pci_pme_active(dev
, false);
2550 dev
->wakeup_prepared
= false;
2557 * pci_enable_wake - change wakeup settings for a PCI device
2558 * @pci_dev: Target device
2559 * @state: PCI state from which device will issue wakeup events
2560 * @enable: Whether or not to enable event generation
2562 * If @enable is set, check device_may_wakeup() for the device before calling
2563 * __pci_enable_wake() for it.
2565 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
2567 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
2570 return __pci_enable_wake(pci_dev
, state
, enable
);
2572 EXPORT_SYMBOL(pci_enable_wake
);
2575 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2576 * @dev: PCI device to prepare
2577 * @enable: True to enable wake-up event generation; false to disable
2579 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2580 * and this function allows them to set that up cleanly - pci_enable_wake()
2581 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2582 * ordering constraints.
2584 * This function only returns error code if the device is not allowed to wake
2585 * up the system from sleep or it is not capable of generating PME# from both
2586 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2588 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2590 return pci_pme_capable(dev
, PCI_D3cold
) ?
2591 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2592 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2594 EXPORT_SYMBOL(pci_wake_from_d3
);
2597 * pci_target_state - find an appropriate low power state for a given PCI dev
2599 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2601 * Use underlying platform code to find a supported low power state for @dev.
2602 * If the platform can't manage @dev, return the deepest state from which it
2603 * can generate wake events, based on any available PME info.
2605 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2607 pci_power_t target_state
= PCI_D3hot
;
2609 if (platform_pci_power_manageable(dev
)) {
2611 * Call the platform to find the target state for the device.
2613 pci_power_t state
= platform_pci_choose_state(dev
);
2616 case PCI_POWER_ERROR
:
2621 if (pci_no_d1d2(dev
))
2625 target_state
= state
;
2628 return target_state
;
2632 target_state
= PCI_D0
;
2635 * If the device is in D3cold even though it's not power-manageable by
2636 * the platform, it may have been powered down by non-standard means.
2637 * Best to let it slumber.
2639 if (dev
->current_state
== PCI_D3cold
)
2640 target_state
= PCI_D3cold
;
2642 if (wakeup
&& dev
->pme_support
) {
2643 pci_power_t state
= target_state
;
2646 * Find the deepest state from which the device can generate
2649 while (state
&& !(dev
->pme_support
& (1 << state
)))
2654 else if (dev
->pme_support
& 1)
2658 return target_state
;
2662 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2663 * into a sleep state
2664 * @dev: Device to handle.
2666 * Choose the power state appropriate for the device depending on whether
2667 * it can wake up the system and/or is power manageable by the platform
2668 * (PCI_D3hot is the default) and put the device into that state.
2670 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2672 bool wakeup
= device_may_wakeup(&dev
->dev
);
2673 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2676 if (target_state
== PCI_POWER_ERROR
)
2680 * There are systems (for example, Intel mobile chips since Coffee
2681 * Lake) where the power drawn while suspended can be significantly
2682 * reduced by disabling PTM on PCIe root ports as this allows the
2683 * port to enter a lower-power PM state and the SoC to reach a
2684 * lower-power idle state as a whole.
2686 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2687 pci_disable_ptm(dev
);
2689 pci_enable_wake(dev
, target_state
, wakeup
);
2691 error
= pci_set_power_state(dev
, target_state
);
2694 pci_enable_wake(dev
, target_state
, false);
2695 pci_restore_ptm_state(dev
);
2700 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2703 * pci_back_from_sleep - turn PCI device on during system-wide transition
2704 * into working state
2705 * @dev: Device to handle.
2707 * Disable device's system wake-up capability and put it into D0.
2709 int pci_back_from_sleep(struct pci_dev
*dev
)
2711 pci_enable_wake(dev
, PCI_D0
, false);
2712 return pci_set_power_state(dev
, PCI_D0
);
2714 EXPORT_SYMBOL(pci_back_from_sleep
);
2717 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2718 * @dev: PCI device being suspended.
2720 * Prepare @dev to generate wake-up events at run time and put it into a low
2723 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2725 pci_power_t target_state
;
2728 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2729 if (target_state
== PCI_POWER_ERROR
)
2732 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2735 * There are systems (for example, Intel mobile chips since Coffee
2736 * Lake) where the power drawn while suspended can be significantly
2737 * reduced by disabling PTM on PCIe root ports as this allows the
2738 * port to enter a lower-power PM state and the SoC to reach a
2739 * lower-power idle state as a whole.
2741 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2742 pci_disable_ptm(dev
);
2744 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2746 error
= pci_set_power_state(dev
, target_state
);
2749 pci_enable_wake(dev
, target_state
, false);
2750 pci_restore_ptm_state(dev
);
2751 dev
->runtime_d3cold
= false;
2758 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2759 * @dev: Device to check.
2761 * Return true if the device itself is capable of generating wake-up events
2762 * (through the platform or using the native PCIe PME) or if the device supports
2763 * PME and one of its upstream bridges can generate wake-up events.
2765 bool pci_dev_run_wake(struct pci_dev
*dev
)
2767 struct pci_bus
*bus
= dev
->bus
;
2769 if (!dev
->pme_support
)
2772 /* PME-capable in principle, but not from the target power state */
2773 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2776 if (device_can_wakeup(&dev
->dev
))
2779 while (bus
->parent
) {
2780 struct pci_dev
*bridge
= bus
->self
;
2782 if (device_can_wakeup(&bridge
->dev
))
2788 /* We have reached the root bus. */
2790 return device_can_wakeup(bus
->bridge
);
2794 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2797 * pci_dev_need_resume - Check if it is necessary to resume the device.
2798 * @pci_dev: Device to check.
2800 * Return 'true' if the device is not runtime-suspended or it has to be
2801 * reconfigured due to wakeup settings difference between system and runtime
2802 * suspend, or the current power state of it is not suitable for the upcoming
2803 * (system-wide) transition.
2805 bool pci_dev_need_resume(struct pci_dev
*pci_dev
)
2807 struct device
*dev
= &pci_dev
->dev
;
2808 pci_power_t target_state
;
2810 if (!pm_runtime_suspended(dev
) || platform_pci_need_resume(pci_dev
))
2813 target_state
= pci_target_state(pci_dev
, device_may_wakeup(dev
));
2816 * If the earlier platform check has not triggered, D3cold is just power
2817 * removal on top of D3hot, so no need to resume the device in that
2820 return target_state
!= pci_dev
->current_state
&&
2821 target_state
!= PCI_D3cold
&&
2822 pci_dev
->current_state
!= PCI_D3hot
;
2826 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2827 * @pci_dev: Device to check.
2829 * If the device is suspended and it is not configured for system wakeup,
2830 * disable PME for it to prevent it from waking up the system unnecessarily.
2832 * Note that if the device's power state is D3cold and the platform check in
2833 * pci_dev_need_resume() has not triggered, the device's configuration need not
2836 void pci_dev_adjust_pme(struct pci_dev
*pci_dev
)
2838 struct device
*dev
= &pci_dev
->dev
;
2840 spin_lock_irq(&dev
->power
.lock
);
2842 if (pm_runtime_suspended(dev
) && !device_may_wakeup(dev
) &&
2843 pci_dev
->current_state
< PCI_D3cold
)
2844 __pci_pme_active(pci_dev
, false);
2846 spin_unlock_irq(&dev
->power
.lock
);
2850 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2851 * @pci_dev: Device to handle.
2853 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2854 * it might have been disabled during the prepare phase of system suspend if
2855 * the device was not configured for system wakeup.
2857 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2859 struct device
*dev
= &pci_dev
->dev
;
2861 if (!pci_dev_run_wake(pci_dev
))
2864 spin_lock_irq(&dev
->power
.lock
);
2866 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2867 __pci_pme_active(pci_dev
, true);
2869 spin_unlock_irq(&dev
->power
.lock
);
2872 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2874 struct device
*dev
= &pdev
->dev
;
2875 struct device
*parent
= dev
->parent
;
2878 pm_runtime_get_sync(parent
);
2879 pm_runtime_get_noresume(dev
);
2881 * pdev->current_state is set to PCI_D3cold during suspending,
2882 * so wait until suspending completes
2884 pm_runtime_barrier(dev
);
2886 * Only need to resume devices in D3cold, because config
2887 * registers are still accessible for devices suspended but
2890 if (pdev
->current_state
== PCI_D3cold
)
2891 pm_runtime_resume(dev
);
2894 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2896 struct device
*dev
= &pdev
->dev
;
2897 struct device
*parent
= dev
->parent
;
2899 pm_runtime_put(dev
);
2901 pm_runtime_put_sync(parent
);
2904 static const struct dmi_system_id bridge_d3_blacklist
[] = {
2908 * Gigabyte X299 root port is not marked as hotplug capable
2909 * which allows Linux to power manage it. However, this
2910 * confuses the BIOS SMI handler so don't power manage root
2911 * ports on that system.
2913 .ident
= "X299 DESIGNARE EX-CF",
2915 DMI_MATCH(DMI_BOARD_VENDOR
, "Gigabyte Technology Co., Ltd."),
2916 DMI_MATCH(DMI_BOARD_NAME
, "X299 DESIGNARE EX-CF"),
2921 * Downstream device is not accessible after putting a root port
2922 * into D3cold and back into D0 on Elo i2.
2926 DMI_MATCH(DMI_SYS_VENDOR
, "Elo Touch Solutions"),
2927 DMI_MATCH(DMI_PRODUCT_NAME
, "Elo i2"),
2928 DMI_MATCH(DMI_PRODUCT_VERSION
, "RevB"),
2936 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2937 * @bridge: Bridge to check
2939 * This function checks if it is possible to move the bridge to D3.
2940 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2942 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2944 if (!pci_is_pcie(bridge
))
2947 switch (pci_pcie_type(bridge
)) {
2948 case PCI_EXP_TYPE_ROOT_PORT
:
2949 case PCI_EXP_TYPE_UPSTREAM
:
2950 case PCI_EXP_TYPE_DOWNSTREAM
:
2951 if (pci_bridge_d3_disable
)
2955 * Hotplug ports handled by firmware in System Management Mode
2956 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2958 if (bridge
->is_hotplug_bridge
&& !pciehp_is_native(bridge
))
2961 if (pci_bridge_d3_force
)
2964 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2965 if (bridge
->is_thunderbolt
)
2968 /* Platform might know better if the bridge supports D3 */
2969 if (platform_pci_bridge_d3(bridge
))
2973 * Hotplug ports handled natively by the OS were not validated
2974 * by vendors for runtime D3 at least until 2018 because there
2975 * was no OS support.
2977 if (bridge
->is_hotplug_bridge
)
2980 if (dmi_check_system(bridge_d3_blacklist
))
2984 * It should be safe to put PCIe ports from 2015 or newer
2987 if (dmi_get_bios_year() >= 2015)
2995 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2997 bool *d3cold_ok
= data
;
2999 if (/* The device needs to be allowed to go D3cold ... */
3000 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
3002 /* ... and if it is wakeup capable to do so from D3cold. */
3003 (device_may_wakeup(&dev
->dev
) &&
3004 !pci_pme_capable(dev
, PCI_D3cold
)) ||
3006 /* If it is a bridge it must be allowed to go to D3. */
3007 !pci_power_manageable(dev
))
3015 * pci_bridge_d3_update - Update bridge D3 capabilities
3016 * @dev: PCI device which is changed
3018 * Update upstream bridge PM capabilities accordingly depending on if the
3019 * device PM configuration was changed or the device is being removed. The
3020 * change is also propagated upstream.
3022 void pci_bridge_d3_update(struct pci_dev
*dev
)
3024 bool remove
= !device_is_registered(&dev
->dev
);
3025 struct pci_dev
*bridge
;
3026 bool d3cold_ok
= true;
3028 bridge
= pci_upstream_bridge(dev
);
3029 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
3033 * If D3 is currently allowed for the bridge, removing one of its
3034 * children won't change that.
3036 if (remove
&& bridge
->bridge_d3
)
3040 * If D3 is currently allowed for the bridge and a child is added or
3041 * changed, disallowance of D3 can only be caused by that child, so
3042 * we only need to check that single device, not any of its siblings.
3044 * If D3 is currently not allowed for the bridge, checking the device
3045 * first may allow us to skip checking its siblings.
3048 pci_dev_check_d3cold(dev
, &d3cold_ok
);
3051 * If D3 is currently not allowed for the bridge, this may be caused
3052 * either by the device being changed/removed or any of its siblings,
3053 * so we need to go through all children to find out if one of them
3054 * continues to block D3.
3056 if (d3cold_ok
&& !bridge
->bridge_d3
)
3057 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
3060 if (bridge
->bridge_d3
!= d3cold_ok
) {
3061 bridge
->bridge_d3
= d3cold_ok
;
3062 /* Propagate change to upstream bridges */
3063 pci_bridge_d3_update(bridge
);
3068 * pci_d3cold_enable - Enable D3cold for device
3069 * @dev: PCI device to handle
3071 * This function can be used in drivers to enable D3cold from the device
3072 * they handle. It also updates upstream PCI bridge PM capabilities
3075 void pci_d3cold_enable(struct pci_dev
*dev
)
3077 if (dev
->no_d3cold
) {
3078 dev
->no_d3cold
= false;
3079 pci_bridge_d3_update(dev
);
3082 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
3085 * pci_d3cold_disable - Disable D3cold for device
3086 * @dev: PCI device to handle
3088 * This function can be used in drivers to disable D3cold from the device
3089 * they handle. It also updates upstream PCI bridge PM capabilities
3092 void pci_d3cold_disable(struct pci_dev
*dev
)
3094 if (!dev
->no_d3cold
) {
3095 dev
->no_d3cold
= true;
3096 pci_bridge_d3_update(dev
);
3099 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
3102 * pci_pm_init - Initialize PM functions of given PCI device
3103 * @dev: PCI device to handle.
3105 void pci_pm_init(struct pci_dev
*dev
)
3111 pm_runtime_forbid(&dev
->dev
);
3112 pm_runtime_set_active(&dev
->dev
);
3113 pm_runtime_enable(&dev
->dev
);
3114 device_enable_async_suspend(&dev
->dev
);
3115 dev
->wakeup_prepared
= false;
3118 dev
->pme_support
= 0;
3120 /* find PCI PM capability in list */
3121 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3124 /* Check device's ability to generate PME# */
3125 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
3127 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
3128 pci_err(dev
, "unsupported PM cap regs version (%u)\n",
3129 pmc
& PCI_PM_CAP_VER_MASK
);
3134 dev
->d3hot_delay
= PCI_PM_D3HOT_WAIT
;
3135 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
3136 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
3137 dev
->d3cold_allowed
= true;
3139 dev
->d1_support
= false;
3140 dev
->d2_support
= false;
3141 if (!pci_no_d1d2(dev
)) {
3142 if (pmc
& PCI_PM_CAP_D1
)
3143 dev
->d1_support
= true;
3144 if (pmc
& PCI_PM_CAP_D2
)
3145 dev
->d2_support
= true;
3147 if (dev
->d1_support
|| dev
->d2_support
)
3148 pci_info(dev
, "supports%s%s\n",
3149 dev
->d1_support
? " D1" : "",
3150 dev
->d2_support
? " D2" : "");
3153 pmc
&= PCI_PM_CAP_PME_MASK
;
3155 pci_info(dev
, "PME# supported from%s%s%s%s%s\n",
3156 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
3157 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
3158 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
3159 (pmc
& PCI_PM_CAP_PME_D3hot
) ? " D3hot" : "",
3160 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
3161 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
3162 dev
->pme_poll
= true;
3164 * Make device's PM flags reflect the wake-up capability, but
3165 * let the user space enable it to wake up the system as needed.
3167 device_set_wakeup_capable(&dev
->dev
, true);
3168 /* Disable the PME# generation functionality */
3169 pci_pme_active(dev
, false);
3172 pci_read_config_word(dev
, PCI_STATUS
, &status
);
3173 if (status
& PCI_STATUS_IMM_READY
)
3177 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
3179 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
3183 case PCI_EA_P_VF_MEM
:
3184 flags
|= IORESOURCE_MEM
;
3186 case PCI_EA_P_MEM_PREFETCH
:
3187 case PCI_EA_P_VF_MEM_PREFETCH
:
3188 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
3191 flags
|= IORESOURCE_IO
;
3200 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
3203 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
3204 return &dev
->resource
[bei
];
3205 #ifdef CONFIG_PCI_IOV
3206 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
3207 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
3208 return &dev
->resource
[PCI_IOV_RESOURCES
+
3209 bei
- PCI_EA_BEI_VF_BAR0
];
3211 else if (bei
== PCI_EA_BEI_ROM
)
3212 return &dev
->resource
[PCI_ROM_RESOURCE
];
3217 /* Read an Enhanced Allocation (EA) entry */
3218 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
3220 struct resource
*res
;
3221 int ent_size
, ent_offset
= offset
;
3222 resource_size_t start
, end
;
3223 unsigned long flags
;
3224 u32 dw0
, bei
, base
, max_offset
;
3226 bool support_64
= (sizeof(resource_size_t
) >= 8);
3228 pci_read_config_dword(dev
, ent_offset
, &dw0
);
3231 /* Entry size field indicates DWORDs after 1st */
3232 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
3234 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
3237 bei
= (dw0
& PCI_EA_BEI
) >> 4;
3238 prop
= (dw0
& PCI_EA_PP
) >> 8;
3241 * If the Property is in the reserved range, try the Secondary
3244 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
3245 prop
= (dw0
& PCI_EA_SP
) >> 16;
3246 if (prop
> PCI_EA_P_BRIDGE_IO
)
3249 res
= pci_ea_get_resource(dev
, bei
, prop
);
3251 pci_err(dev
, "Unsupported EA entry BEI: %u\n", bei
);
3255 flags
= pci_ea_flags(dev
, prop
);
3257 pci_err(dev
, "Unsupported EA properties: %#x\n", prop
);
3262 pci_read_config_dword(dev
, ent_offset
, &base
);
3263 start
= (base
& PCI_EA_FIELD_MASK
);
3266 /* Read MaxOffset */
3267 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
3270 /* Read Base MSBs (if 64-bit entry) */
3271 if (base
& PCI_EA_IS_64
) {
3274 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
3277 flags
|= IORESOURCE_MEM_64
;
3279 /* entry starts above 32-bit boundary, can't use */
3280 if (!support_64
&& base_upper
)
3284 start
|= ((u64
)base_upper
<< 32);
3287 end
= start
+ (max_offset
| 0x03);
3289 /* Read MaxOffset MSBs (if 64-bit entry) */
3290 if (max_offset
& PCI_EA_IS_64
) {
3291 u32 max_offset_upper
;
3293 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
3296 flags
|= IORESOURCE_MEM_64
;
3298 /* entry too big, can't use */
3299 if (!support_64
&& max_offset_upper
)
3303 end
+= ((u64
)max_offset_upper
<< 32);
3307 pci_err(dev
, "EA Entry crosses address boundary\n");
3311 if (ent_size
!= ent_offset
- offset
) {
3312 pci_err(dev
, "EA Entry Size (%d) does not match length read (%d)\n",
3313 ent_size
, ent_offset
- offset
);
3317 res
->name
= pci_name(dev
);
3322 if (bei
<= PCI_EA_BEI_BAR5
)
3323 pci_info(dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3325 else if (bei
== PCI_EA_BEI_ROM
)
3326 pci_info(dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3328 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
3329 pci_info(dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3330 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
3332 pci_info(dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3336 return offset
+ ent_size
;
3339 /* Enhanced Allocation Initialization */
3340 void pci_ea_init(struct pci_dev
*dev
)
3347 /* find PCI EA capability in list */
3348 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
3352 /* determine the number of entries */
3353 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
3355 num_ent
&= PCI_EA_NUM_ENT_MASK
;
3357 offset
= ea
+ PCI_EA_FIRST_ENT
;
3359 /* Skip DWORD 2 for type 1 functions */
3360 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
3363 /* parse each EA entry */
3364 for (i
= 0; i
< num_ent
; ++i
)
3365 offset
= pci_ea_read(dev
, offset
);
3368 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
3369 struct pci_cap_saved_state
*new_cap
)
3371 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
3375 * _pci_add_cap_save_buffer - allocate buffer for saving given
3376 * capability registers
3377 * @dev: the PCI device
3378 * @cap: the capability to allocate the buffer for
3379 * @extended: Standard or Extended capability ID
3380 * @size: requested size of the buffer
3382 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
3383 bool extended
, unsigned int size
)
3386 struct pci_cap_saved_state
*save_state
;
3389 pos
= pci_find_ext_capability(dev
, cap
);
3391 pos
= pci_find_capability(dev
, cap
);
3396 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
3400 save_state
->cap
.cap_nr
= cap
;
3401 save_state
->cap
.cap_extended
= extended
;
3402 save_state
->cap
.size
= size
;
3403 pci_add_saved_cap(dev
, save_state
);
3408 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
3410 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
3413 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
3415 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
3419 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3420 * @dev: the PCI device
3422 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
3426 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
3427 PCI_EXP_SAVE_REGS
* sizeof(u16
));
3429 pci_err(dev
, "unable to preallocate PCI Express save buffer\n");
3431 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
3433 pci_err(dev
, "unable to preallocate PCI-X save buffer\n");
3435 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_LTR
,
3438 pci_err(dev
, "unable to allocate suspend buffer for LTR\n");
3440 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_L1SS
,
3443 pci_err(dev
, "unable to allocate suspend buffer for ASPM-L1SS\n");
3445 pci_allocate_vc_save_buffers(dev
);
3448 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
3450 struct pci_cap_saved_state
*tmp
;
3451 struct hlist_node
*n
;
3453 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
3458 * pci_configure_ari - enable or disable ARI forwarding
3459 * @dev: the PCI device
3461 * If @dev and its upstream bridge both support ARI, enable ARI in the
3462 * bridge. Otherwise, disable ARI in the bridge.
3464 void pci_configure_ari(struct pci_dev
*dev
)
3467 struct pci_dev
*bridge
;
3469 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
3472 bridge
= dev
->bus
->self
;
3476 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3477 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
3480 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
3481 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
3482 PCI_EXP_DEVCTL2_ARI
);
3483 bridge
->ari_enabled
= 1;
3485 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
3486 PCI_EXP_DEVCTL2_ARI
);
3487 bridge
->ari_enabled
= 0;
3491 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3496 pos
= pdev
->acs_cap
;
3501 * Except for egress control, capabilities are either required
3502 * or only required if controllable. Features missing from the
3503 * capability field can therefore be assumed as hard-wired enabled.
3505 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
3506 acs_flags
&= (cap
| PCI_ACS_EC
);
3508 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
3509 return (ctrl
& acs_flags
) == acs_flags
;
3513 * pci_acs_enabled - test ACS against required flags for a given device
3514 * @pdev: device to test
3515 * @acs_flags: required PCI ACS flags
3517 * Return true if the device supports the provided flags. Automatically
3518 * filters out flags that are not implemented on multifunction devices.
3520 * Note that this interface checks the effective ACS capabilities of the
3521 * device rather than the actual capabilities. For instance, most single
3522 * function endpoints are not required to support ACS because they have no
3523 * opportunity for peer-to-peer access. We therefore return 'true'
3524 * regardless of whether the device exposes an ACS capability. This makes
3525 * it much easier for callers of this function to ignore the actual type
3526 * or topology of the device when testing ACS support.
3528 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3532 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
3537 * Conventional PCI and PCI-X devices never support ACS, either
3538 * effectively or actually. The shared bus topology implies that
3539 * any device on the bus can receive or snoop DMA.
3541 if (!pci_is_pcie(pdev
))
3544 switch (pci_pcie_type(pdev
)) {
3546 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3547 * but since their primary interface is PCI/X, we conservatively
3548 * handle them as we would a non-PCIe device.
3550 case PCI_EXP_TYPE_PCIE_BRIDGE
:
3552 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3553 * applicable... must never implement an ACS Extended Capability...".
3554 * This seems arbitrary, but we take a conservative interpretation
3555 * of this statement.
3557 case PCI_EXP_TYPE_PCI_BRIDGE
:
3558 case PCI_EXP_TYPE_RC_EC
:
3561 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3562 * implement ACS in order to indicate their peer-to-peer capabilities,
3563 * regardless of whether they are single- or multi-function devices.
3565 case PCI_EXP_TYPE_DOWNSTREAM
:
3566 case PCI_EXP_TYPE_ROOT_PORT
:
3567 return pci_acs_flags_enabled(pdev
, acs_flags
);
3569 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3570 * implemented by the remaining PCIe types to indicate peer-to-peer
3571 * capabilities, but only when they are part of a multifunction
3572 * device. The footnote for section 6.12 indicates the specific
3573 * PCIe types included here.
3575 case PCI_EXP_TYPE_ENDPOINT
:
3576 case PCI_EXP_TYPE_UPSTREAM
:
3577 case PCI_EXP_TYPE_LEG_END
:
3578 case PCI_EXP_TYPE_RC_END
:
3579 if (!pdev
->multifunction
)
3582 return pci_acs_flags_enabled(pdev
, acs_flags
);
3586 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3587 * to single function devices with the exception of downstream ports.
3593 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3594 * @start: starting downstream device
3595 * @end: ending upstream device or NULL to search to the root bus
3596 * @acs_flags: required flags
3598 * Walk up a device tree from start to end testing PCI ACS support. If
3599 * any step along the way does not support the required flags, return false.
3601 bool pci_acs_path_enabled(struct pci_dev
*start
,
3602 struct pci_dev
*end
, u16 acs_flags
)
3604 struct pci_dev
*pdev
, *parent
= start
;
3609 if (!pci_acs_enabled(pdev
, acs_flags
))
3612 if (pci_is_root_bus(pdev
->bus
))
3613 return (end
== NULL
);
3615 parent
= pdev
->bus
->self
;
3616 } while (pdev
!= end
);
3622 * pci_acs_init - Initialize ACS if hardware supports it
3623 * @dev: the PCI device
3625 void pci_acs_init(struct pci_dev
*dev
)
3627 dev
->acs_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
3630 * Attempt to enable ACS regardless of capability because some Root
3631 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3632 * the standard ACS capability but still support ACS via those
3635 pci_enable_acs(dev
);
3639 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3643 * Helper to find the position of the ctrl register for a BAR.
3644 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3645 * Returns -ENOENT if no ctrl register for the BAR could be found.
3647 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3649 unsigned int pos
, nbars
, i
;
3652 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3656 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3657 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3658 PCI_REBAR_CTRL_NBAR_SHIFT
;
3660 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3663 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3664 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3673 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3675 * @bar: BAR to query
3677 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3678 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3680 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3685 pos
= pci_rebar_find_pos(pdev
, bar
);
3689 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3690 cap
&= PCI_REBAR_CAP_SIZES
;
3692 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3693 if (pdev
->vendor
== PCI_VENDOR_ID_ATI
&& pdev
->device
== 0x731f &&
3694 bar
== 0 && cap
== 0x7000)
3699 EXPORT_SYMBOL(pci_rebar_get_possible_sizes
);
3702 * pci_rebar_get_current_size - get the current size of a BAR
3704 * @bar: BAR to set size to
3706 * Read the size of a BAR from the resizable BAR config.
3707 * Returns size if found or negative error code.
3709 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3714 pos
= pci_rebar_find_pos(pdev
, bar
);
3718 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3719 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> PCI_REBAR_CTRL_BAR_SHIFT
;
3723 * pci_rebar_set_size - set a new size for a BAR
3725 * @bar: BAR to set size to
3726 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3728 * Set the new size of a BAR as defined in the spec.
3729 * Returns zero if resizing was successful, error code otherwise.
3731 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3736 pos
= pci_rebar_find_pos(pdev
, bar
);
3740 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3741 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3742 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
3743 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3748 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3749 * @dev: the PCI device
3750 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3751 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3752 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3753 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3755 * Return 0 if all upstream bridges support AtomicOp routing, egress
3756 * blocking is disabled on all upstream ports, and the root port supports
3757 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3758 * AtomicOp completion), or negative otherwise.
3760 int pci_enable_atomic_ops_to_root(struct pci_dev
*dev
, u32 cap_mask
)
3762 struct pci_bus
*bus
= dev
->bus
;
3763 struct pci_dev
*bridge
;
3767 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3768 * in Device Control 2 is reserved in VFs and the PF value applies
3769 * to all associated VFs.
3774 if (!pci_is_pcie(dev
))
3778 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3779 * AtomicOp requesters. For now, we only support endpoints as
3780 * requesters and root ports as completers. No endpoints as
3781 * completers, and no peer-to-peer.
3784 switch (pci_pcie_type(dev
)) {
3785 case PCI_EXP_TYPE_ENDPOINT
:
3786 case PCI_EXP_TYPE_LEG_END
:
3787 case PCI_EXP_TYPE_RC_END
:
3793 while (bus
->parent
) {
3796 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3798 switch (pci_pcie_type(bridge
)) {
3799 /* Ensure switch ports support AtomicOp routing */
3800 case PCI_EXP_TYPE_UPSTREAM
:
3801 case PCI_EXP_TYPE_DOWNSTREAM
:
3802 if (!(cap
& PCI_EXP_DEVCAP2_ATOMIC_ROUTE
))
3806 /* Ensure root port supports all the sizes we care about */
3807 case PCI_EXP_TYPE_ROOT_PORT
:
3808 if ((cap
& cap_mask
) != cap_mask
)
3813 /* Ensure upstream ports don't block AtomicOps on egress */
3814 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
) {
3815 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
,
3817 if (ctl2
& PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
)
3824 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
3825 PCI_EXP_DEVCTL2_ATOMIC_REQ
);
3828 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root
);
3831 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3832 * @dev: the PCI device
3833 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3835 * Perform INTx swizzling for a device behind one level of bridge. This is
3836 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3837 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3838 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3839 * the PCI Express Base Specification, Revision 2.1)
3841 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3845 if (pci_ari_enabled(dev
->bus
))
3848 slot
= PCI_SLOT(dev
->devfn
);
3850 return (((pin
- 1) + slot
) % 4) + 1;
3853 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3861 while (!pci_is_root_bus(dev
->bus
)) {
3862 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3863 dev
= dev
->bus
->self
;
3870 * pci_common_swizzle - swizzle INTx all the way to root bridge
3871 * @dev: the PCI device
3872 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3874 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3875 * bridges all the way up to a PCI root bus.
3877 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3881 while (!pci_is_root_bus(dev
->bus
)) {
3882 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3883 dev
= dev
->bus
->self
;
3886 return PCI_SLOT(dev
->devfn
);
3888 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3891 * pci_release_region - Release a PCI bar
3892 * @pdev: PCI device whose resources were previously reserved by
3893 * pci_request_region()
3894 * @bar: BAR to release
3896 * Releases the PCI I/O and memory resources previously reserved by a
3897 * successful call to pci_request_region(). Call this function only
3898 * after all use of the PCI regions has ceased.
3900 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3902 struct pci_devres
*dr
;
3904 if (pci_resource_len(pdev
, bar
) == 0)
3906 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3907 release_region(pci_resource_start(pdev
, bar
),
3908 pci_resource_len(pdev
, bar
));
3909 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3910 release_mem_region(pci_resource_start(pdev
, bar
),
3911 pci_resource_len(pdev
, bar
));
3913 dr
= find_pci_dr(pdev
);
3915 dr
->region_mask
&= ~(1 << bar
);
3917 EXPORT_SYMBOL(pci_release_region
);
3920 * __pci_request_region - Reserved PCI I/O and memory resource
3921 * @pdev: PCI device whose resources are to be reserved
3922 * @bar: BAR to be reserved
3923 * @res_name: Name to be associated with resource.
3924 * @exclusive: whether the region access is exclusive or not
3926 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3927 * being reserved by owner @res_name. Do not access any
3928 * address inside the PCI regions unless this call returns
3931 * If @exclusive is set, then the region is marked so that userspace
3932 * is explicitly not allowed to map the resource via /dev/mem or
3933 * sysfs MMIO access.
3935 * Returns 0 on success, or %EBUSY on error. A warning
3936 * message is also printed on failure.
3938 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3939 const char *res_name
, int exclusive
)
3941 struct pci_devres
*dr
;
3943 if (pci_resource_len(pdev
, bar
) == 0)
3946 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3947 if (!request_region(pci_resource_start(pdev
, bar
),
3948 pci_resource_len(pdev
, bar
), res_name
))
3950 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3951 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3952 pci_resource_len(pdev
, bar
), res_name
,
3957 dr
= find_pci_dr(pdev
);
3959 dr
->region_mask
|= 1 << bar
;
3964 pci_warn(pdev
, "BAR %d: can't reserve %pR\n", bar
,
3965 &pdev
->resource
[bar
]);
3970 * pci_request_region - Reserve PCI I/O and memory resource
3971 * @pdev: PCI device whose resources are to be reserved
3972 * @bar: BAR to be reserved
3973 * @res_name: Name to be associated with resource
3975 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3976 * being reserved by owner @res_name. Do not access any
3977 * address inside the PCI regions unless this call returns
3980 * Returns 0 on success, or %EBUSY on error. A warning
3981 * message is also printed on failure.
3983 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3985 return __pci_request_region(pdev
, bar
, res_name
, 0);
3987 EXPORT_SYMBOL(pci_request_region
);
3990 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3991 * @pdev: PCI device whose resources were previously reserved
3992 * @bars: Bitmask of BARs to be released
3994 * Release selected PCI I/O and memory resources previously reserved.
3995 * Call this function only after all use of the PCI regions has ceased.
3997 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
4001 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
4002 if (bars
& (1 << i
))
4003 pci_release_region(pdev
, i
);
4005 EXPORT_SYMBOL(pci_release_selected_regions
);
4007 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
4008 const char *res_name
, int excl
)
4012 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
4013 if (bars
& (1 << i
))
4014 if (__pci_request_region(pdev
, i
, res_name
, excl
))
4020 if (bars
& (1 << i
))
4021 pci_release_region(pdev
, i
);
4028 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4029 * @pdev: PCI device whose resources are to be reserved
4030 * @bars: Bitmask of BARs to be requested
4031 * @res_name: Name to be associated with resource
4033 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
4034 const char *res_name
)
4036 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
4038 EXPORT_SYMBOL(pci_request_selected_regions
);
4040 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
4041 const char *res_name
)
4043 return __pci_request_selected_regions(pdev
, bars
, res_name
,
4044 IORESOURCE_EXCLUSIVE
);
4046 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
4049 * pci_release_regions - Release reserved PCI I/O and memory resources
4050 * @pdev: PCI device whose resources were previously reserved by
4051 * pci_request_regions()
4053 * Releases all PCI I/O and memory resources previously reserved by a
4054 * successful call to pci_request_regions(). Call this function only
4055 * after all use of the PCI regions has ceased.
4058 void pci_release_regions(struct pci_dev
*pdev
)
4060 pci_release_selected_regions(pdev
, (1 << PCI_STD_NUM_BARS
) - 1);
4062 EXPORT_SYMBOL(pci_release_regions
);
4065 * pci_request_regions - Reserve PCI I/O and memory resources
4066 * @pdev: PCI device whose resources are to be reserved
4067 * @res_name: Name to be associated with resource.
4069 * Mark all PCI regions associated with PCI device @pdev as
4070 * being reserved by owner @res_name. Do not access any
4071 * address inside the PCI regions unless this call returns
4074 * Returns 0 on success, or %EBUSY on error. A warning
4075 * message is also printed on failure.
4077 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
4079 return pci_request_selected_regions(pdev
,
4080 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4082 EXPORT_SYMBOL(pci_request_regions
);
4085 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4086 * @pdev: PCI device whose resources are to be reserved
4087 * @res_name: Name to be associated with resource.
4089 * Mark all PCI regions associated with PCI device @pdev as being reserved
4090 * by owner @res_name. Do not access any address inside the PCI regions
4091 * unless this call returns successfully.
4093 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4094 * and the sysfs MMIO access will not be allowed.
4096 * Returns 0 on success, or %EBUSY on error. A warning message is also
4097 * printed on failure.
4099 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
4101 return pci_request_selected_regions_exclusive(pdev
,
4102 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4104 EXPORT_SYMBOL(pci_request_regions_exclusive
);
4107 * Record the PCI IO range (expressed as CPU physical address + size).
4108 * Return a negative value if an error has occurred, zero otherwise
4110 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
4111 resource_size_t size
)
4115 struct logic_pio_hwaddr
*range
;
4117 if (!size
|| addr
+ size
< addr
)
4120 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
4124 range
->fwnode
= fwnode
;
4126 range
->hw_start
= addr
;
4127 range
->flags
= LOGIC_PIO_CPU_MMIO
;
4129 ret
= logic_pio_register_range(range
);
4133 /* Ignore duplicates due to deferred probing */
4141 phys_addr_t
pci_pio_to_address(unsigned long pio
)
4143 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
4146 if (pio
>= MMIO_UPPER_LIMIT
)
4149 address
= logic_pio_to_hwaddr(pio
);
4154 EXPORT_SYMBOL_GPL(pci_pio_to_address
);
4156 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
4159 return logic_pio_trans_cpuaddr(address
);
4161 if (address
> IO_SPACE_LIMIT
)
4162 return (unsigned long)-1;
4164 return (unsigned long) address
;
4169 * pci_remap_iospace - Remap the memory mapped I/O space
4170 * @res: Resource describing the I/O space
4171 * @phys_addr: physical address of range to be mapped
4173 * Remap the memory mapped I/O space described by the @res and the CPU
4174 * physical address @phys_addr into virtual address space. Only
4175 * architectures that have memory mapped IO functions defined (and the
4176 * PCI_IOBASE value defined) should call this function.
4178 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
4180 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4181 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4183 if (!(res
->flags
& IORESOURCE_IO
))
4186 if (res
->end
> IO_SPACE_LIMIT
)
4189 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
4190 pgprot_device(PAGE_KERNEL
));
4193 * This architecture does not have memory mapped I/O space,
4194 * so this function should never be called
4196 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4200 EXPORT_SYMBOL(pci_remap_iospace
);
4203 * pci_unmap_iospace - Unmap the memory mapped I/O space
4204 * @res: resource to be unmapped
4206 * Unmap the CPU virtual address @res from virtual address space. Only
4207 * architectures that have memory mapped IO functions defined (and the
4208 * PCI_IOBASE value defined) should call this function.
4210 void pci_unmap_iospace(struct resource
*res
)
4212 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4213 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4215 vunmap_range(vaddr
, vaddr
+ resource_size(res
));
4218 EXPORT_SYMBOL(pci_unmap_iospace
);
4220 static void devm_pci_unmap_iospace(struct device
*dev
, void *ptr
)
4222 struct resource
**res
= ptr
;
4224 pci_unmap_iospace(*res
);
4228 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4229 * @dev: Generic device to remap IO address for
4230 * @res: Resource describing the I/O space
4231 * @phys_addr: physical address of range to be mapped
4233 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4236 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
4237 phys_addr_t phys_addr
)
4239 const struct resource
**ptr
;
4242 ptr
= devres_alloc(devm_pci_unmap_iospace
, sizeof(*ptr
), GFP_KERNEL
);
4246 error
= pci_remap_iospace(res
, phys_addr
);
4251 devres_add(dev
, ptr
);
4256 EXPORT_SYMBOL(devm_pci_remap_iospace
);
4259 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4260 * @dev: Generic device to remap IO address for
4261 * @offset: Resource address to map
4262 * @size: Size of map
4264 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4267 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
4268 resource_size_t offset
,
4269 resource_size_t size
)
4271 void __iomem
**ptr
, *addr
;
4273 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
4277 addr
= pci_remap_cfgspace(offset
, size
);
4280 devres_add(dev
, ptr
);
4286 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
4289 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4290 * @dev: generic device to handle the resource for
4291 * @res: configuration space resource to be handled
4293 * Checks that a resource is a valid memory region, requests the memory
4294 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4295 * proper PCI configuration space memory attributes are guaranteed.
4297 * All operations are managed and will be undone on driver detach.
4299 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4300 * on failure. Usage example::
4302 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4303 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4305 * return PTR_ERR(base);
4307 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
4308 struct resource
*res
)
4310 resource_size_t size
;
4312 void __iomem
*dest_ptr
;
4316 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
4317 dev_err(dev
, "invalid resource\n");
4318 return IOMEM_ERR_PTR(-EINVAL
);
4321 size
= resource_size(res
);
4324 name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s %s", dev_name(dev
),
4327 name
= devm_kstrdup(dev
, dev_name(dev
), GFP_KERNEL
);
4329 return IOMEM_ERR_PTR(-ENOMEM
);
4331 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
4332 dev_err(dev
, "can't request region for resource %pR\n", res
);
4333 return IOMEM_ERR_PTR(-EBUSY
);
4336 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
4338 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
4339 devm_release_mem_region(dev
, res
->start
, size
);
4340 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
4345 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
4347 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
4351 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
4353 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
4355 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
4356 if (cmd
!= old_cmd
) {
4357 pci_dbg(dev
, "%s bus mastering\n",
4358 enable
? "enabling" : "disabling");
4359 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4361 dev
->is_busmaster
= enable
;
4365 * pcibios_setup - process "pci=" kernel boot arguments
4366 * @str: string used to pass in "pci=" kernel boot arguments
4368 * Process kernel boot arguments. This is the default implementation.
4369 * Architecture specific implementations can override this as necessary.
4371 char * __weak __init
pcibios_setup(char *str
)
4377 * pcibios_set_master - enable PCI bus-mastering for device dev
4378 * @dev: the PCI device to enable
4380 * Enables PCI bus-mastering for the device. This is the default
4381 * implementation. Architecture specific implementations can override
4382 * this if necessary.
4384 void __weak
pcibios_set_master(struct pci_dev
*dev
)
4388 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4389 if (pci_is_pcie(dev
))
4392 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
4394 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
4395 else if (lat
> pcibios_max_latency
)
4396 lat
= pcibios_max_latency
;
4400 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
4404 * pci_set_master - enables bus-mastering for device dev
4405 * @dev: the PCI device to enable
4407 * Enables bus-mastering on the device and calls pcibios_set_master()
4408 * to do the needed arch specific settings.
4410 void pci_set_master(struct pci_dev
*dev
)
4412 __pci_set_master(dev
, true);
4413 pcibios_set_master(dev
);
4415 EXPORT_SYMBOL(pci_set_master
);
4418 * pci_clear_master - disables bus-mastering for device dev
4419 * @dev: the PCI device to disable
4421 void pci_clear_master(struct pci_dev
*dev
)
4423 __pci_set_master(dev
, false);
4425 EXPORT_SYMBOL(pci_clear_master
);
4428 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4429 * @dev: the PCI device for which MWI is to be enabled
4431 * Helper function for pci_set_mwi.
4432 * Originally copied from drivers/net/acenic.c.
4433 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4435 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4437 int pci_set_cacheline_size(struct pci_dev
*dev
)
4441 if (!pci_cache_line_size
)
4444 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4445 equal to or multiple of the right value. */
4446 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4447 if (cacheline_size
>= pci_cache_line_size
&&
4448 (cacheline_size
% pci_cache_line_size
) == 0)
4451 /* Write the correct value. */
4452 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
4454 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4455 if (cacheline_size
== pci_cache_line_size
)
4458 pci_dbg(dev
, "cache line size of %d is not supported\n",
4459 pci_cache_line_size
<< 2);
4463 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
4466 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4467 * @dev: the PCI device for which MWI is enabled
4469 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4471 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4473 int pci_set_mwi(struct pci_dev
*dev
)
4475 #ifdef PCI_DISABLE_MWI
4481 rc
= pci_set_cacheline_size(dev
);
4485 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4486 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
4487 pci_dbg(dev
, "enabling Mem-Wr-Inval\n");
4488 cmd
|= PCI_COMMAND_INVALIDATE
;
4489 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4494 EXPORT_SYMBOL(pci_set_mwi
);
4497 * pcim_set_mwi - a device-managed pci_set_mwi()
4498 * @dev: the PCI device for which MWI is enabled
4500 * Managed pci_set_mwi().
4502 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4504 int pcim_set_mwi(struct pci_dev
*dev
)
4506 struct pci_devres
*dr
;
4508 dr
= find_pci_dr(dev
);
4513 return pci_set_mwi(dev
);
4515 EXPORT_SYMBOL(pcim_set_mwi
);
4518 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4519 * @dev: the PCI device for which MWI is enabled
4521 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4522 * Callers are not required to check the return value.
4524 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4526 int pci_try_set_mwi(struct pci_dev
*dev
)
4528 #ifdef PCI_DISABLE_MWI
4531 return pci_set_mwi(dev
);
4534 EXPORT_SYMBOL(pci_try_set_mwi
);
4537 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4538 * @dev: the PCI device to disable
4540 * Disables PCI Memory-Write-Invalidate transaction on the device
4542 void pci_clear_mwi(struct pci_dev
*dev
)
4544 #ifndef PCI_DISABLE_MWI
4547 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4548 if (cmd
& PCI_COMMAND_INVALIDATE
) {
4549 cmd
&= ~PCI_COMMAND_INVALIDATE
;
4550 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4554 EXPORT_SYMBOL(pci_clear_mwi
);
4557 * pci_disable_parity - disable parity checking for device
4558 * @dev: the PCI device to operate on
4560 * Disable parity checking for device @dev
4562 void pci_disable_parity(struct pci_dev
*dev
)
4566 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4567 if (cmd
& PCI_COMMAND_PARITY
) {
4568 cmd
&= ~PCI_COMMAND_PARITY
;
4569 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4574 * pci_intx - enables/disables PCI INTx for device dev
4575 * @pdev: the PCI device to operate on
4576 * @enable: boolean: whether to enable or disable PCI INTx
4578 * Enables/disables PCI INTx for device @pdev
4580 void pci_intx(struct pci_dev
*pdev
, int enable
)
4582 u16 pci_command
, new;
4584 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
4587 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
4589 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
4591 if (new != pci_command
) {
4592 struct pci_devres
*dr
;
4594 pci_write_config_word(pdev
, PCI_COMMAND
, new);
4596 dr
= find_pci_dr(pdev
);
4597 if (dr
&& !dr
->restore_intx
) {
4598 dr
->restore_intx
= 1;
4599 dr
->orig_intx
= !enable
;
4603 EXPORT_SYMBOL_GPL(pci_intx
);
4605 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
4607 struct pci_bus
*bus
= dev
->bus
;
4608 bool mask_updated
= true;
4609 u32 cmd_status_dword
;
4610 u16 origcmd
, newcmd
;
4611 unsigned long flags
;
4615 * We do a single dword read to retrieve both command and status.
4616 * Document assumptions that make this possible.
4618 BUILD_BUG_ON(PCI_COMMAND
% 4);
4619 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
4621 raw_spin_lock_irqsave(&pci_lock
, flags
);
4623 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
4625 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
4628 * Check interrupt status register to see whether our device
4629 * triggered the interrupt (when masking) or the next IRQ is
4630 * already pending (when unmasking).
4632 if (mask
!= irq_pending
) {
4633 mask_updated
= false;
4637 origcmd
= cmd_status_dword
;
4638 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
4640 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
4641 if (newcmd
!= origcmd
)
4642 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
4645 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
4647 return mask_updated
;
4651 * pci_check_and_mask_intx - mask INTx on pending interrupt
4652 * @dev: the PCI device to operate on
4654 * Check if the device dev has its INTx line asserted, mask it and return
4655 * true in that case. False is returned if no interrupt was pending.
4657 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
4659 return pci_check_and_set_intx_mask(dev
, true);
4661 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
4664 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4665 * @dev: the PCI device to operate on
4667 * Check if the device dev has its INTx line asserted, unmask it if not and
4668 * return true. False is returned and the mask remains active if there was
4669 * still an interrupt pending.
4671 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
4673 return pci_check_and_set_intx_mask(dev
, false);
4675 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
4678 * pci_wait_for_pending_transaction - wait for pending transaction
4679 * @dev: the PCI device to operate on
4681 * Return 0 if transaction is pending 1 otherwise.
4683 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
4685 if (!pci_is_pcie(dev
))
4688 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
4689 PCI_EXP_DEVSTA_TRPND
);
4691 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
4694 * pcie_flr - initiate a PCIe function level reset
4695 * @dev: device to reset
4697 * Initiate a function level reset unconditionally on @dev without
4698 * checking any flags and DEVCAP
4700 int pcie_flr(struct pci_dev
*dev
)
4702 if (!pci_wait_for_pending_transaction(dev
))
4703 pci_err(dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
4705 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
4711 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4712 * 100ms, but may silently discard requests while the FLR is in
4713 * progress. Wait 100ms before trying to access the device.
4717 return pci_dev_wait(dev
, "FLR", PCIE_RESET_READY_POLL_MS
);
4719 EXPORT_SYMBOL_GPL(pcie_flr
);
4722 * pcie_reset_flr - initiate a PCIe function level reset
4723 * @dev: device to reset
4724 * @probe: if true, return 0 if device can be reset this way
4726 * Initiate a function level reset on @dev.
4728 int pcie_reset_flr(struct pci_dev
*dev
, bool probe
)
4730 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4733 if (!(dev
->devcap
& PCI_EXP_DEVCAP_FLR
))
4739 return pcie_flr(dev
);
4741 EXPORT_SYMBOL_GPL(pcie_reset_flr
);
4743 static int pci_af_flr(struct pci_dev
*dev
, bool probe
)
4748 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4752 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4755 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4756 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4763 * Wait for Transaction Pending bit to clear. A word-aligned test
4764 * is used, so we use the control offset rather than status and shift
4765 * the test bit to match.
4767 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4768 PCI_AF_STATUS_TP
<< 8))
4769 pci_err(dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4771 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4777 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4778 * updated 27 July 2006; a device must complete an FLR within
4779 * 100ms, but may silently discard requests while the FLR is in
4780 * progress. Wait 100ms before trying to access the device.
4784 return pci_dev_wait(dev
, "AF_FLR", PCIE_RESET_READY_POLL_MS
);
4788 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4789 * @dev: Device to reset.
4790 * @probe: if true, return 0 if the device can be reset this way.
4792 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4793 * unset, it will be reinitialized internally when going from PCI_D3hot to
4794 * PCI_D0. If that's the case and the device is not in a low-power state
4795 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4797 * NOTE: This causes the caller to sleep for twice the device power transition
4798 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4799 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4800 * Moreover, only devices in D0 can be reset by this function.
4802 static int pci_pm_reset(struct pci_dev
*dev
, bool probe
)
4806 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4809 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4810 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4816 if (dev
->current_state
!= PCI_D0
)
4819 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4821 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4822 pci_dev_d3_sleep(dev
);
4824 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4826 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4827 pci_dev_d3_sleep(dev
);
4829 return pci_dev_wait(dev
, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS
);
4833 * pcie_wait_for_link_delay - Wait until link is active or inactive
4834 * @pdev: Bridge device
4835 * @active: waiting for active or inactive?
4836 * @delay: Delay to wait after link has become active (in ms)
4838 * Use this to wait till link becomes active or inactive.
4840 static bool pcie_wait_for_link_delay(struct pci_dev
*pdev
, bool active
,
4848 * Some controllers might not implement link active reporting. In this
4849 * case, we wait for 1000 ms + any delay requested by the caller.
4851 if (!pdev
->link_active_reporting
) {
4852 msleep(timeout
+ delay
);
4857 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4858 * after which we should expect an link active if the reset was
4859 * successful. If so, software must wait a minimum 100ms before sending
4860 * configuration requests to devices downstream this port.
4862 * If the link fails to activate, either the device was physically
4863 * removed or the link is permanently failed.
4868 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
4869 ret
= !!(lnk_status
& PCI_EXP_LNKSTA_DLLLA
);
4880 return ret
== active
;
4884 * pcie_wait_for_link - Wait until link is active or inactive
4885 * @pdev: Bridge device
4886 * @active: waiting for active or inactive?
4888 * Use this to wait till link becomes active or inactive.
4890 bool pcie_wait_for_link(struct pci_dev
*pdev
, bool active
)
4892 return pcie_wait_for_link_delay(pdev
, active
, 100);
4896 * Find maximum D3cold delay required by all the devices on the bus. The
4897 * spec says 100 ms, but firmware can lower it and we allow drivers to
4898 * increase it as well.
4900 * Called with @pci_bus_sem locked for reading.
4902 static int pci_bus_max_d3cold_delay(const struct pci_bus
*bus
)
4904 const struct pci_dev
*pdev
;
4905 int min_delay
= 100;
4908 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
4909 if (pdev
->d3cold_delay
< min_delay
)
4910 min_delay
= pdev
->d3cold_delay
;
4911 if (pdev
->d3cold_delay
> max_delay
)
4912 max_delay
= pdev
->d3cold_delay
;
4915 return max(min_delay
, max_delay
);
4919 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4922 * Handle necessary delays before access to the devices on the secondary
4923 * side of the bridge are permitted after D3cold to D0 transition.
4925 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4926 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4929 void pci_bridge_wait_for_secondary_bus(struct pci_dev
*dev
)
4931 struct pci_dev
*child
;
4934 if (pci_dev_is_disconnected(dev
))
4937 if (!pci_is_bridge(dev
) || !dev
->bridge_d3
)
4940 down_read(&pci_bus_sem
);
4943 * We only deal with devices that are present currently on the bus.
4944 * For any hot-added devices the access delay is handled in pciehp
4945 * board_added(). In case of ACPI hotplug the firmware is expected
4946 * to configure the devices before OS is notified.
4948 if (!dev
->subordinate
|| list_empty(&dev
->subordinate
->devices
)) {
4949 up_read(&pci_bus_sem
);
4953 /* Take d3cold_delay requirements into account */
4954 delay
= pci_bus_max_d3cold_delay(dev
->subordinate
);
4956 up_read(&pci_bus_sem
);
4960 child
= list_first_entry(&dev
->subordinate
->devices
, struct pci_dev
,
4962 up_read(&pci_bus_sem
);
4965 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4966 * accessing the device after reset (that is 1000 ms + 100 ms). In
4967 * practice this should not be needed because we don't do power
4968 * management for them (see pci_bridge_d3_possible()).
4970 if (!pci_is_pcie(dev
)) {
4971 pci_dbg(dev
, "waiting %d ms for secondary bus\n", 1000 + delay
);
4972 msleep(1000 + delay
);
4977 * For PCIe downstream and root ports that do not support speeds
4978 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4979 * speeds (gen3) we need to wait first for the data link layer to
4982 * However, 100 ms is the minimum and the PCIe spec says the
4983 * software must allow at least 1s before it can determine that the
4984 * device that did not respond is a broken device. There is
4985 * evidence that 100 ms is not always enough, for example certain
4986 * Titan Ridge xHCI controller does not always respond to
4987 * configuration requests if we only wait for 100 ms (see
4988 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4990 * Therefore we wait for 100 ms and check for the device presence.
4991 * If it is still not present give it an additional 100 ms.
4993 if (!pcie_downstream_port(dev
))
4996 if (pcie_get_speed_cap(dev
) <= PCIE_SPEED_5_0GT
) {
4997 pci_dbg(dev
, "waiting %d ms for downstream link\n", delay
);
5000 pci_dbg(dev
, "waiting %d ms for downstream link, after activation\n",
5002 if (!pcie_wait_for_link_delay(dev
, true, delay
)) {
5003 /* Did not train, no need to wait any further */
5004 pci_info(dev
, "Data Link Layer Link Active not set in 1000 msec\n");
5009 if (!pci_device_is_present(child
)) {
5010 pci_dbg(child
, "waiting additional %d ms to become accessible\n", delay
);
5015 void pci_reset_secondary_bus(struct pci_dev
*dev
)
5019 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
5020 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
5021 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5024 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5025 * this to 2ms to ensure that we meet the minimum requirement.
5029 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
5030 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5033 * Trhfa for conventional PCI is 2^25 clock cycles.
5034 * Assuming a minimum 33MHz clock this results in a 1s
5035 * delay before we can consider subordinate devices to
5036 * be re-initialized. PCIe has some ways to shorten this,
5037 * but we don't make use of them yet.
5042 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
5044 pci_reset_secondary_bus(dev
);
5048 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5049 * @dev: Bridge device
5051 * Use the bridge control register to assert reset on the secondary bus.
5052 * Devices on the secondary bus are left in power-on state.
5054 int pci_bridge_secondary_bus_reset(struct pci_dev
*dev
)
5056 pcibios_reset_secondary_bus(dev
);
5058 return pci_dev_wait(dev
, "bus reset", PCIE_RESET_READY_POLL_MS
);
5060 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset
);
5062 static int pci_parent_bus_reset(struct pci_dev
*dev
, bool probe
)
5064 struct pci_dev
*pdev
;
5066 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
5067 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5070 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
5077 return pci_bridge_secondary_bus_reset(dev
->bus
->self
);
5080 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, bool probe
)
5084 if (!hotplug
|| !try_module_get(hotplug
->owner
))
5087 if (hotplug
->ops
->reset_slot
)
5088 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
5090 module_put(hotplug
->owner
);
5095 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, bool probe
)
5097 if (dev
->multifunction
|| dev
->subordinate
|| !dev
->slot
||
5098 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5101 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
5104 static int pci_reset_bus_function(struct pci_dev
*dev
, bool probe
)
5108 rc
= pci_dev_reset_slot_function(dev
, probe
);
5111 return pci_parent_bus_reset(dev
, probe
);
5114 void pci_dev_lock(struct pci_dev
*dev
)
5116 /* block PM suspend, driver probe, etc. */
5117 device_lock(&dev
->dev
);
5118 pci_cfg_access_lock(dev
);
5120 EXPORT_SYMBOL_GPL(pci_dev_lock
);
5122 /* Return 1 on successful lock, 0 on contention */
5123 int pci_dev_trylock(struct pci_dev
*dev
)
5125 if (device_trylock(&dev
->dev
)) {
5126 if (pci_cfg_access_trylock(dev
))
5128 device_unlock(&dev
->dev
);
5133 EXPORT_SYMBOL_GPL(pci_dev_trylock
);
5135 void pci_dev_unlock(struct pci_dev
*dev
)
5137 pci_cfg_access_unlock(dev
);
5138 device_unlock(&dev
->dev
);
5140 EXPORT_SYMBOL_GPL(pci_dev_unlock
);
5142 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
5144 const struct pci_error_handlers
*err_handler
=
5145 dev
->driver
? dev
->driver
->err_handler
: NULL
;
5148 * dev->driver->err_handler->reset_prepare() is protected against
5149 * races with ->remove() by the device lock, which must be held by
5152 if (err_handler
&& err_handler
->reset_prepare
)
5153 err_handler
->reset_prepare(dev
);
5156 * Wake-up device prior to save. PM registers default to D0 after
5157 * reset and a simple register restore doesn't reliably return
5158 * to a non-D0 state anyway.
5160 pci_set_power_state(dev
, PCI_D0
);
5162 pci_save_state(dev
);
5164 * Disable the device by clearing the Command register, except for
5165 * INTx-disable which is set. This not only disables MMIO and I/O port
5166 * BARs, but also prevents the device from being Bus Master, preventing
5167 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5168 * compliant devices, INTx-disable prevents legacy interrupts.
5170 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
5173 static void pci_dev_restore(struct pci_dev
*dev
)
5175 const struct pci_error_handlers
*err_handler
=
5176 dev
->driver
? dev
->driver
->err_handler
: NULL
;
5178 pci_restore_state(dev
);
5181 * dev->driver->err_handler->reset_done() is protected against
5182 * races with ->remove() by the device lock, which must be held by
5185 if (err_handler
&& err_handler
->reset_done
)
5186 err_handler
->reset_done(dev
);
5189 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5190 static const struct pci_reset_fn_method pci_reset_fn_methods
[] = {
5192 { pci_dev_specific_reset
, .name
= "device_specific" },
5193 { pci_dev_acpi_reset
, .name
= "acpi" },
5194 { pcie_reset_flr
, .name
= "flr" },
5195 { pci_af_flr
, .name
= "af_flr" },
5196 { pci_pm_reset
, .name
= "pm" },
5197 { pci_reset_bus_function
, .name
= "bus" },
5200 static ssize_t
reset_method_show(struct device
*dev
,
5201 struct device_attribute
*attr
, char *buf
)
5203 struct pci_dev
*pdev
= to_pci_dev(dev
);
5207 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5208 m
= pdev
->reset_methods
[i
];
5212 len
+= sysfs_emit_at(buf
, len
, "%s%s", len
? " " : "",
5213 pci_reset_fn_methods
[m
].name
);
5217 len
+= sysfs_emit_at(buf
, len
, "\n");
5222 static int reset_method_lookup(const char *name
)
5226 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5227 if (sysfs_streq(name
, pci_reset_fn_methods
[m
].name
))
5231 return 0; /* not found */
5234 static ssize_t
reset_method_store(struct device
*dev
,
5235 struct device_attribute
*attr
,
5236 const char *buf
, size_t count
)
5238 struct pci_dev
*pdev
= to_pci_dev(dev
);
5239 char *options
, *name
;
5241 u8 reset_methods
[PCI_NUM_RESET_METHODS
] = { 0 };
5243 if (sysfs_streq(buf
, "")) {
5244 pdev
->reset_methods
[0] = 0;
5245 pci_warn(pdev
, "All device reset methods disabled by user");
5249 if (sysfs_streq(buf
, "default")) {
5250 pci_init_reset_methods(pdev
);
5254 options
= kstrndup(buf
, count
, GFP_KERNEL
);
5259 while ((name
= strsep(&options
, " ")) != NULL
) {
5260 if (sysfs_streq(name
, ""))
5265 m
= reset_method_lookup(name
);
5267 pci_err(pdev
, "Invalid reset method '%s'", name
);
5271 if (pci_reset_fn_methods
[m
].reset_fn(pdev
, PCI_RESET_PROBE
)) {
5272 pci_err(pdev
, "Unsupported reset method '%s'", name
);
5276 if (n
== PCI_NUM_RESET_METHODS
- 1) {
5277 pci_err(pdev
, "Too many reset methods\n");
5281 reset_methods
[n
++] = m
;
5284 reset_methods
[n
] = 0;
5286 /* Warn if dev-specific supported but not highest priority */
5287 if (pci_reset_fn_methods
[1].reset_fn(pdev
, PCI_RESET_PROBE
) == 0 &&
5288 reset_methods
[0] != 1)
5289 pci_warn(pdev
, "Device-specific reset disabled/de-prioritized by user");
5290 memcpy(pdev
->reset_methods
, reset_methods
, sizeof(pdev
->reset_methods
));
5295 /* Leave previous methods unchanged */
5299 static DEVICE_ATTR_RW(reset_method
);
5301 static struct attribute
*pci_dev_reset_method_attrs
[] = {
5302 &dev_attr_reset_method
.attr
,
5306 static umode_t
pci_dev_reset_method_attr_is_visible(struct kobject
*kobj
,
5307 struct attribute
*a
, int n
)
5309 struct pci_dev
*pdev
= to_pci_dev(kobj_to_dev(kobj
));
5311 if (!pci_reset_supported(pdev
))
5317 const struct attribute_group pci_dev_reset_method_attr_group
= {
5318 .attrs
= pci_dev_reset_method_attrs
,
5319 .is_visible
= pci_dev_reset_method_attr_is_visible
,
5323 * __pci_reset_function_locked - reset a PCI device function while holding
5324 * the @dev mutex lock.
5325 * @dev: PCI device to reset
5327 * Some devices allow an individual function to be reset without affecting
5328 * other functions in the same device. The PCI device must be responsive
5329 * to PCI config space in order to use this function.
5331 * The device function is presumed to be unused and the caller is holding
5332 * the device mutex lock when this function is called.
5334 * Resetting the device will make the contents of PCI configuration space
5335 * random, so any caller of this must be prepared to reinitialise the
5336 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5339 * Returns 0 if the device function was successfully reset or negative if the
5340 * device doesn't support resetting a single function.
5342 int __pci_reset_function_locked(struct pci_dev
*dev
)
5344 int i
, m
, rc
= -ENOTTY
;
5349 * A reset method returns -ENOTTY if it doesn't support this device and
5350 * we should try the next method.
5352 * If it returns 0 (success), we're finished. If it returns any other
5353 * error, we're also finished: this indicates that further reset
5354 * mechanisms might be broken on the device.
5356 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5357 m
= dev
->reset_methods
[i
];
5361 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_DO_RESET
);
5370 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
5373 * pci_init_reset_methods - check whether device can be safely reset
5374 * and store supported reset mechanisms.
5375 * @dev: PCI device to check for reset mechanisms
5377 * Some devices allow an individual function to be reset without affecting
5378 * other functions in the same device. The PCI device must be in D0-D3hot
5381 * Stores reset mechanisms supported by device in reset_methods byte array
5382 * which is a member of struct pci_dev.
5384 void pci_init_reset_methods(struct pci_dev
*dev
)
5388 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods
) != PCI_NUM_RESET_METHODS
);
5393 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5394 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_PROBE
);
5396 dev
->reset_methods
[i
++] = m
;
5397 else if (rc
!= -ENOTTY
)
5401 dev
->reset_methods
[i
] = 0;
5405 * pci_reset_function - quiesce and reset a PCI device function
5406 * @dev: PCI device to reset
5408 * Some devices allow an individual function to be reset without affecting
5409 * other functions in the same device. The PCI device must be responsive
5410 * to PCI config space in order to use this function.
5412 * This function does not just reset the PCI portion of a device, but
5413 * clears all the state associated with the device. This function differs
5414 * from __pci_reset_function_locked() in that it saves and restores device state
5415 * over the reset and takes the PCI device lock.
5417 * Returns 0 if the device function was successfully reset or negative if the
5418 * device doesn't support resetting a single function.
5420 int pci_reset_function(struct pci_dev
*dev
)
5424 if (!pci_reset_supported(dev
))
5428 pci_dev_save_and_disable(dev
);
5430 rc
= __pci_reset_function_locked(dev
);
5432 pci_dev_restore(dev
);
5433 pci_dev_unlock(dev
);
5437 EXPORT_SYMBOL_GPL(pci_reset_function
);
5440 * pci_reset_function_locked - quiesce and reset a PCI device function
5441 * @dev: PCI device to reset
5443 * Some devices allow an individual function to be reset without affecting
5444 * other functions in the same device. The PCI device must be responsive
5445 * to PCI config space in order to use this function.
5447 * This function does not just reset the PCI portion of a device, but
5448 * clears all the state associated with the device. This function differs
5449 * from __pci_reset_function_locked() in that it saves and restores device state
5450 * over the reset. It also differs from pci_reset_function() in that it
5451 * requires the PCI device lock to be held.
5453 * Returns 0 if the device function was successfully reset or negative if the
5454 * device doesn't support resetting a single function.
5456 int pci_reset_function_locked(struct pci_dev
*dev
)
5460 if (!pci_reset_supported(dev
))
5463 pci_dev_save_and_disable(dev
);
5465 rc
= __pci_reset_function_locked(dev
);
5467 pci_dev_restore(dev
);
5471 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
5474 * pci_try_reset_function - quiesce and reset a PCI device function
5475 * @dev: PCI device to reset
5477 * Same as above, except return -EAGAIN if unable to lock device.
5479 int pci_try_reset_function(struct pci_dev
*dev
)
5483 if (!pci_reset_supported(dev
))
5486 if (!pci_dev_trylock(dev
))
5489 pci_dev_save_and_disable(dev
);
5490 rc
= __pci_reset_function_locked(dev
);
5491 pci_dev_restore(dev
);
5492 pci_dev_unlock(dev
);
5496 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
5498 /* Do any devices on or below this bus prevent a bus reset? */
5499 static bool pci_bus_resetable(struct pci_bus
*bus
)
5501 struct pci_dev
*dev
;
5504 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5507 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5508 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5509 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5516 /* Lock devices from the top of the tree down */
5517 static void pci_bus_lock(struct pci_bus
*bus
)
5519 struct pci_dev
*dev
;
5521 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5523 if (dev
->subordinate
)
5524 pci_bus_lock(dev
->subordinate
);
5528 /* Unlock devices from the bottom of the tree up */
5529 static void pci_bus_unlock(struct pci_bus
*bus
)
5531 struct pci_dev
*dev
;
5533 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5534 if (dev
->subordinate
)
5535 pci_bus_unlock(dev
->subordinate
);
5536 pci_dev_unlock(dev
);
5540 /* Return 1 on successful lock, 0 on contention */
5541 static int pci_bus_trylock(struct pci_bus
*bus
)
5543 struct pci_dev
*dev
;
5545 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5546 if (!pci_dev_trylock(dev
))
5548 if (dev
->subordinate
) {
5549 if (!pci_bus_trylock(dev
->subordinate
)) {
5550 pci_dev_unlock(dev
);
5558 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
5559 if (dev
->subordinate
)
5560 pci_bus_unlock(dev
->subordinate
);
5561 pci_dev_unlock(dev
);
5566 /* Do any devices on or below this slot prevent a bus reset? */
5567 static bool pci_slot_resetable(struct pci_slot
*slot
)
5569 struct pci_dev
*dev
;
5571 if (slot
->bus
->self
&&
5572 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5575 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5576 if (!dev
->slot
|| dev
->slot
!= slot
)
5578 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5579 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5586 /* Lock devices from the top of the tree down */
5587 static void pci_slot_lock(struct pci_slot
*slot
)
5589 struct pci_dev
*dev
;
5591 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5592 if (!dev
->slot
|| dev
->slot
!= slot
)
5595 if (dev
->subordinate
)
5596 pci_bus_lock(dev
->subordinate
);
5600 /* Unlock devices from the bottom of the tree up */
5601 static void pci_slot_unlock(struct pci_slot
*slot
)
5603 struct pci_dev
*dev
;
5605 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5606 if (!dev
->slot
|| dev
->slot
!= slot
)
5608 if (dev
->subordinate
)
5609 pci_bus_unlock(dev
->subordinate
);
5610 pci_dev_unlock(dev
);
5614 /* Return 1 on successful lock, 0 on contention */
5615 static int pci_slot_trylock(struct pci_slot
*slot
)
5617 struct pci_dev
*dev
;
5619 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5620 if (!dev
->slot
|| dev
->slot
!= slot
)
5622 if (!pci_dev_trylock(dev
))
5624 if (dev
->subordinate
) {
5625 if (!pci_bus_trylock(dev
->subordinate
)) {
5626 pci_dev_unlock(dev
);
5634 list_for_each_entry_continue_reverse(dev
,
5635 &slot
->bus
->devices
, bus_list
) {
5636 if (!dev
->slot
|| dev
->slot
!= slot
)
5638 if (dev
->subordinate
)
5639 pci_bus_unlock(dev
->subordinate
);
5640 pci_dev_unlock(dev
);
5646 * Save and disable devices from the top of the tree down while holding
5647 * the @dev mutex lock for the entire tree.
5649 static void pci_bus_save_and_disable_locked(struct pci_bus
*bus
)
5651 struct pci_dev
*dev
;
5653 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5654 pci_dev_save_and_disable(dev
);
5655 if (dev
->subordinate
)
5656 pci_bus_save_and_disable_locked(dev
->subordinate
);
5661 * Restore devices from top of the tree down while holding @dev mutex lock
5662 * for the entire tree. Parent bridges need to be restored before we can
5663 * get to subordinate devices.
5665 static void pci_bus_restore_locked(struct pci_bus
*bus
)
5667 struct pci_dev
*dev
;
5669 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5670 pci_dev_restore(dev
);
5671 if (dev
->subordinate
)
5672 pci_bus_restore_locked(dev
->subordinate
);
5677 * Save and disable devices from the top of the tree down while holding
5678 * the @dev mutex lock for the entire tree.
5680 static void pci_slot_save_and_disable_locked(struct pci_slot
*slot
)
5682 struct pci_dev
*dev
;
5684 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5685 if (!dev
->slot
|| dev
->slot
!= slot
)
5687 pci_dev_save_and_disable(dev
);
5688 if (dev
->subordinate
)
5689 pci_bus_save_and_disable_locked(dev
->subordinate
);
5694 * Restore devices from top of the tree down while holding @dev mutex lock
5695 * for the entire tree. Parent bridges need to be restored before we can
5696 * get to subordinate devices.
5698 static void pci_slot_restore_locked(struct pci_slot
*slot
)
5700 struct pci_dev
*dev
;
5702 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5703 if (!dev
->slot
|| dev
->slot
!= slot
)
5705 pci_dev_restore(dev
);
5706 if (dev
->subordinate
)
5707 pci_bus_restore_locked(dev
->subordinate
);
5711 static int pci_slot_reset(struct pci_slot
*slot
, bool probe
)
5715 if (!slot
|| !pci_slot_resetable(slot
))
5719 pci_slot_lock(slot
);
5723 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
5726 pci_slot_unlock(slot
);
5732 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5733 * @slot: PCI slot to probe
5735 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5737 int pci_probe_reset_slot(struct pci_slot
*slot
)
5739 return pci_slot_reset(slot
, PCI_RESET_PROBE
);
5741 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
5744 * __pci_reset_slot - Try to reset a PCI slot
5745 * @slot: PCI slot to reset
5747 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5748 * independent of other slots. For instance, some slots may support slot power
5749 * control. In the case of a 1:1 bus to slot architecture, this function may
5750 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5751 * Generally a slot reset should be attempted before a bus reset. All of the
5752 * function of the slot and any subordinate buses behind the slot are reset
5753 * through this function. PCI config space of all devices in the slot and
5754 * behind the slot is saved before and restored after reset.
5756 * Same as above except return -EAGAIN if the slot cannot be locked
5758 static int __pci_reset_slot(struct pci_slot
*slot
)
5762 rc
= pci_slot_reset(slot
, PCI_RESET_PROBE
);
5766 if (pci_slot_trylock(slot
)) {
5767 pci_slot_save_and_disable_locked(slot
);
5769 rc
= pci_reset_hotplug_slot(slot
->hotplug
, PCI_RESET_DO_RESET
);
5770 pci_slot_restore_locked(slot
);
5771 pci_slot_unlock(slot
);
5778 static int pci_bus_reset(struct pci_bus
*bus
, bool probe
)
5782 if (!bus
->self
|| !pci_bus_resetable(bus
))
5792 ret
= pci_bridge_secondary_bus_reset(bus
->self
);
5794 pci_bus_unlock(bus
);
5800 * pci_bus_error_reset - reset the bridge's subordinate bus
5801 * @bridge: The parent device that connects to the bus to reset
5803 * This function will first try to reset the slots on this bus if the method is
5804 * available. If slot reset fails or is not available, this will fall back to a
5805 * secondary bus reset.
5807 int pci_bus_error_reset(struct pci_dev
*bridge
)
5809 struct pci_bus
*bus
= bridge
->subordinate
;
5810 struct pci_slot
*slot
;
5815 mutex_lock(&pci_slot_mutex
);
5816 if (list_empty(&bus
->slots
))
5819 list_for_each_entry(slot
, &bus
->slots
, list
)
5820 if (pci_probe_reset_slot(slot
))
5823 list_for_each_entry(slot
, &bus
->slots
, list
)
5824 if (pci_slot_reset(slot
, PCI_RESET_DO_RESET
))
5827 mutex_unlock(&pci_slot_mutex
);
5830 mutex_unlock(&pci_slot_mutex
);
5831 return pci_bus_reset(bridge
->subordinate
, PCI_RESET_DO_RESET
);
5835 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5836 * @bus: PCI bus to probe
5838 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5840 int pci_probe_reset_bus(struct pci_bus
*bus
)
5842 return pci_bus_reset(bus
, PCI_RESET_PROBE
);
5844 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
5847 * __pci_reset_bus - Try to reset a PCI bus
5848 * @bus: top level PCI bus to reset
5850 * Same as above except return -EAGAIN if the bus cannot be locked
5852 static int __pci_reset_bus(struct pci_bus
*bus
)
5856 rc
= pci_bus_reset(bus
, PCI_RESET_PROBE
);
5860 if (pci_bus_trylock(bus
)) {
5861 pci_bus_save_and_disable_locked(bus
);
5863 rc
= pci_bridge_secondary_bus_reset(bus
->self
);
5864 pci_bus_restore_locked(bus
);
5865 pci_bus_unlock(bus
);
5873 * pci_reset_bus - Try to reset a PCI bus
5874 * @pdev: top level PCI device to reset via slot/bus
5876 * Same as above except return -EAGAIN if the bus cannot be locked
5878 int pci_reset_bus(struct pci_dev
*pdev
)
5880 return (!pci_probe_reset_slot(pdev
->slot
)) ?
5881 __pci_reset_slot(pdev
->slot
) : __pci_reset_bus(pdev
->bus
);
5883 EXPORT_SYMBOL_GPL(pci_reset_bus
);
5886 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5887 * @dev: PCI device to query
5889 * Returns mmrbc: maximum designed memory read count in bytes or
5890 * appropriate error value.
5892 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
5897 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5901 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5904 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
5906 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
5909 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5910 * @dev: PCI device to query
5912 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5915 int pcix_get_mmrbc(struct pci_dev
*dev
)
5920 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5924 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5927 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
5929 EXPORT_SYMBOL(pcix_get_mmrbc
);
5932 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5933 * @dev: PCI device to query
5934 * @mmrbc: maximum memory read count in bytes
5935 * valid values are 512, 1024, 2048, 4096
5937 * If possible sets maximum memory read byte count, some bridges have errata
5938 * that prevent this.
5940 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
5946 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
5949 v
= ffs(mmrbc
) - 10;
5951 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5955 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5958 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
5961 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5964 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
5966 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
5969 cmd
&= ~PCI_X_CMD_MAX_READ
;
5971 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
5976 EXPORT_SYMBOL(pcix_set_mmrbc
);
5979 * pcie_get_readrq - get PCI Express read request size
5980 * @dev: PCI device to query
5982 * Returns maximum memory read request in bytes or appropriate error value.
5984 int pcie_get_readrq(struct pci_dev
*dev
)
5988 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
5990 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5992 EXPORT_SYMBOL(pcie_get_readrq
);
5995 * pcie_set_readrq - set PCI Express maximum memory read request
5996 * @dev: PCI device to query
5997 * @rq: maximum memory read count in bytes
5998 * valid values are 128, 256, 512, 1024, 2048, 4096
6000 * If possible sets maximum memory read request in bytes
6002 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
6007 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
6011 * If using the "performance" PCIe config, we clamp the read rq
6012 * size to the max packet size to keep the host bridge from
6013 * generating requests larger than we can cope with.
6015 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
6016 int mps
= pcie_get_mps(dev
);
6022 v
= (ffs(rq
) - 8) << 12;
6024 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6025 PCI_EXP_DEVCTL_READRQ
, v
);
6027 return pcibios_err_to_errno(ret
);
6029 EXPORT_SYMBOL(pcie_set_readrq
);
6032 * pcie_get_mps - get PCI Express maximum payload size
6033 * @dev: PCI device to query
6035 * Returns maximum payload size in bytes
6037 int pcie_get_mps(struct pci_dev
*dev
)
6041 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
6043 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6045 EXPORT_SYMBOL(pcie_get_mps
);
6048 * pcie_set_mps - set PCI Express maximum payload size
6049 * @dev: PCI device to query
6050 * @mps: maximum payload size in bytes
6051 * valid values are 128, 256, 512, 1024, 2048, 4096
6053 * If possible sets maximum payload size
6055 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
6060 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
6064 if (v
> dev
->pcie_mpss
)
6068 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6069 PCI_EXP_DEVCTL_PAYLOAD
, v
);
6071 return pcibios_err_to_errno(ret
);
6073 EXPORT_SYMBOL(pcie_set_mps
);
6076 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6077 * device and its bandwidth limitation
6078 * @dev: PCI device to query
6079 * @limiting_dev: storage for device causing the bandwidth limitation
6080 * @speed: storage for speed of limiting device
6081 * @width: storage for width of limiting device
6083 * Walk up the PCI device chain and find the point where the minimum
6084 * bandwidth is available. Return the bandwidth available there and (if
6085 * limiting_dev, speed, and width pointers are supplied) information about
6086 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6089 u32
pcie_bandwidth_available(struct pci_dev
*dev
, struct pci_dev
**limiting_dev
,
6090 enum pci_bus_speed
*speed
,
6091 enum pcie_link_width
*width
)
6094 enum pci_bus_speed next_speed
;
6095 enum pcie_link_width next_width
;
6099 *speed
= PCI_SPEED_UNKNOWN
;
6101 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
6106 pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
6108 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
6109 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
6110 PCI_EXP_LNKSTA_NLW_SHIFT
;
6112 next_bw
= next_width
* PCIE_SPEED2MBS_ENC(next_speed
);
6114 /* Check if current device limits the total bandwidth */
6115 if (!bw
|| next_bw
<= bw
) {
6119 *limiting_dev
= dev
;
6121 *speed
= next_speed
;
6123 *width
= next_width
;
6126 dev
= pci_upstream_bridge(dev
);
6131 EXPORT_SYMBOL(pcie_bandwidth_available
);
6134 * pcie_get_speed_cap - query for the PCI device's link speed capability
6135 * @dev: PCI device to query
6137 * Query the PCI device speed capability. Return the maximum link speed
6138 * supported by the device.
6140 enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev
*dev
)
6142 u32 lnkcap2
, lnkcap
;
6145 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6146 * implementation note there recommends using the Supported Link
6147 * Speeds Vector in Link Capabilities 2 when supported.
6149 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6150 * should use the Supported Link Speeds field in Link Capabilities,
6151 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6153 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
6155 /* PCIe r3.0-compliant */
6157 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2
);
6159 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6160 if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_5_0GB
)
6161 return PCIE_SPEED_5_0GT
;
6162 else if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_2_5GB
)
6163 return PCIE_SPEED_2_5GT
;
6165 return PCI_SPEED_UNKNOWN
;
6167 EXPORT_SYMBOL(pcie_get_speed_cap
);
6170 * pcie_get_width_cap - query for the PCI device's link width capability
6171 * @dev: PCI device to query
6173 * Query the PCI device width capability. Return the maximum link width
6174 * supported by the device.
6176 enum pcie_link_width
pcie_get_width_cap(struct pci_dev
*dev
)
6180 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6182 return (lnkcap
& PCI_EXP_LNKCAP_MLW
) >> 4;
6184 return PCIE_LNK_WIDTH_UNKNOWN
;
6186 EXPORT_SYMBOL(pcie_get_width_cap
);
6189 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6191 * @speed: storage for link speed
6192 * @width: storage for link width
6194 * Calculate a PCI device's link bandwidth by querying for its link speed
6195 * and width, multiplying them, and applying encoding overhead. The result
6196 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6198 u32
pcie_bandwidth_capable(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
6199 enum pcie_link_width
*width
)
6201 *speed
= pcie_get_speed_cap(dev
);
6202 *width
= pcie_get_width_cap(dev
);
6204 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
)
6207 return *width
* PCIE_SPEED2MBS_ENC(*speed
);
6211 * __pcie_print_link_status - Report the PCI device's link speed and width
6212 * @dev: PCI device to query
6213 * @verbose: Print info even when enough bandwidth is available
6215 * If the available bandwidth at the device is less than the device is
6216 * capable of, report the device's maximum possible bandwidth and the
6217 * upstream link that limits its performance. If @verbose, always print
6218 * the available bandwidth, even if the device isn't constrained.
6220 void __pcie_print_link_status(struct pci_dev
*dev
, bool verbose
)
6222 enum pcie_link_width width
, width_cap
;
6223 enum pci_bus_speed speed
, speed_cap
;
6224 struct pci_dev
*limiting_dev
= NULL
;
6225 u32 bw_avail
, bw_cap
;
6227 bw_cap
= pcie_bandwidth_capable(dev
, &speed_cap
, &width_cap
);
6228 bw_avail
= pcie_bandwidth_available(dev
, &limiting_dev
, &speed
, &width
);
6230 if (bw_avail
>= bw_cap
&& verbose
)
6231 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6232 bw_cap
/ 1000, bw_cap
% 1000,
6233 pci_speed_string(speed_cap
), width_cap
);
6234 else if (bw_avail
< bw_cap
)
6235 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6236 bw_avail
/ 1000, bw_avail
% 1000,
6237 pci_speed_string(speed
), width
,
6238 limiting_dev
? pci_name(limiting_dev
) : "<unknown>",
6239 bw_cap
/ 1000, bw_cap
% 1000,
6240 pci_speed_string(speed_cap
), width_cap
);
6244 * pcie_print_link_status - Report the PCI device's link speed and width
6245 * @dev: PCI device to query
6247 * Report the available bandwidth at the device.
6249 void pcie_print_link_status(struct pci_dev
*dev
)
6251 __pcie_print_link_status(dev
, true);
6253 EXPORT_SYMBOL(pcie_print_link_status
);
6256 * pci_select_bars - Make BAR mask from the type of resource
6257 * @dev: the PCI device for which BAR mask is made
6258 * @flags: resource type mask to be selected
6260 * This helper routine makes bar mask from the type of resource.
6262 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
6265 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
6266 if (pci_resource_flags(dev
, i
) & flags
)
6270 EXPORT_SYMBOL(pci_select_bars
);
6272 /* Some architectures require additional programming to enable VGA */
6273 static arch_set_vga_state_t arch_set_vga_state
;
6275 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
6277 arch_set_vga_state
= func
; /* NULL disables */
6280 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
6281 unsigned int command_bits
, u32 flags
)
6283 if (arch_set_vga_state
)
6284 return arch_set_vga_state(dev
, decode
, command_bits
,
6290 * pci_set_vga_state - set VGA decode state on device and parents if requested
6291 * @dev: the PCI device
6292 * @decode: true = enable decoding, false = disable decoding
6293 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6294 * @flags: traverse ancestors and change bridges
6295 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6297 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
6298 unsigned int command_bits
, u32 flags
)
6300 struct pci_bus
*bus
;
6301 struct pci_dev
*bridge
;
6305 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
6307 /* ARCH specific VGA enables */
6308 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
6312 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
6313 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
6315 cmd
|= command_bits
;
6317 cmd
&= ~command_bits
;
6318 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
6321 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
6328 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6331 cmd
|= PCI_BRIDGE_CTL_VGA
;
6333 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
6334 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6343 bool pci_pr3_present(struct pci_dev
*pdev
)
6345 struct acpi_device
*adev
;
6350 adev
= ACPI_COMPANION(&pdev
->dev
);
6354 return adev
->power
.flags
.power_resources
&&
6355 acpi_has_method(adev
->handle
, "_PR3");
6357 EXPORT_SYMBOL_GPL(pci_pr3_present
);
6361 * pci_add_dma_alias - Add a DMA devfn alias for a device
6362 * @dev: the PCI device for which alias is added
6363 * @devfn_from: alias slot and function
6364 * @nr_devfns: number of subsequent devfns to alias
6366 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6367 * which is used to program permissible bus-devfn source addresses for DMA
6368 * requests in an IOMMU. These aliases factor into IOMMU group creation
6369 * and are useful for devices generating DMA requests beyond or different
6370 * from their logical bus-devfn. Examples include device quirks where the
6371 * device simply uses the wrong devfn, as well as non-transparent bridges
6372 * where the alias may be a proxy for devices in another domain.
6374 * IOMMU group creation is performed during device discovery or addition,
6375 * prior to any potential DMA mapping and therefore prior to driver probing
6376 * (especially for userspace assigned devices where IOMMU group definition
6377 * cannot be left as a userspace activity). DMA aliases should therefore
6378 * be configured via quirks, such as the PCI fixup header quirk.
6380 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn_from
, unsigned nr_devfns
)
6384 nr_devfns
= min(nr_devfns
, (unsigned) MAX_NR_DEVFNS
- devfn_from
);
6385 devfn_to
= devfn_from
+ nr_devfns
- 1;
6387 if (!dev
->dma_alias_mask
)
6388 dev
->dma_alias_mask
= bitmap_zalloc(MAX_NR_DEVFNS
, GFP_KERNEL
);
6389 if (!dev
->dma_alias_mask
) {
6390 pci_warn(dev
, "Unable to allocate DMA alias mask\n");
6394 bitmap_set(dev
->dma_alias_mask
, devfn_from
, nr_devfns
);
6397 pci_info(dev
, "Enabling fixed DMA alias to %02x.%d\n",
6398 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
));
6399 else if (nr_devfns
> 1)
6400 pci_info(dev
, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6401 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
),
6402 PCI_SLOT(devfn_to
), PCI_FUNC(devfn_to
));
6405 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
6407 return (dev1
->dma_alias_mask
&&
6408 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
6409 (dev2
->dma_alias_mask
&&
6410 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
)) ||
6411 pci_real_dma_dev(dev1
) == dev2
||
6412 pci_real_dma_dev(dev2
) == dev1
;
6415 bool pci_device_is_present(struct pci_dev
*pdev
)
6419 if (pci_dev_is_disconnected(pdev
))
6421 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
6423 EXPORT_SYMBOL_GPL(pci_device_is_present
);
6425 void pci_ignore_hotplug(struct pci_dev
*dev
)
6427 struct pci_dev
*bridge
= dev
->bus
->self
;
6429 dev
->ignore_hotplug
= 1;
6430 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6432 bridge
->ignore_hotplug
= 1;
6434 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
6437 * pci_real_dma_dev - Get PCI DMA device for PCI device
6438 * @dev: the PCI device that may have a PCI DMA alias
6440 * Permits the platform to provide architecture-specific functionality to
6441 * devices needing to alias DMA to another PCI device on another PCI bus. If
6442 * the PCI device is on the same bus, it is recommended to use
6443 * pci_add_dma_alias(). This is the default implementation. Architecture
6444 * implementations can override this.
6446 struct pci_dev __weak
*pci_real_dma_dev(struct pci_dev
*dev
)
6451 resource_size_t __weak
pcibios_default_alignment(void)
6457 * Arches that don't want to expose struct resource to userland as-is in
6458 * sysfs and /proc can implement their own pci_resource_to_user().
6460 void __weak
pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
6461 const struct resource
*rsrc
,
6462 resource_size_t
*start
, resource_size_t
*end
)
6464 *start
= rsrc
->start
;
6468 static char *resource_alignment_param
;
6469 static DEFINE_SPINLOCK(resource_alignment_lock
);
6472 * pci_specified_resource_alignment - get resource alignment specified by user.
6473 * @dev: the PCI device to get
6474 * @resize: whether or not to change resources' size when reassigning alignment
6476 * RETURNS: Resource alignment if it is specified.
6477 * Zero if it is not specified.
6479 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
6482 int align_order
, count
;
6483 resource_size_t align
= pcibios_default_alignment();
6487 spin_lock(&resource_alignment_lock
);
6488 p
= resource_alignment_param
;
6491 if (pci_has_flag(PCI_PROBE_ONLY
)) {
6493 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6499 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
6502 if (align_order
> 63) {
6503 pr_err("PCI: Invalid requested alignment (order %d)\n",
6505 align_order
= PAGE_SHIFT
;
6508 align_order
= PAGE_SHIFT
;
6511 ret
= pci_dev_str_match(dev
, p
, &p
);
6514 align
= 1ULL << align_order
;
6516 } else if (ret
< 0) {
6517 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6522 if (*p
!= ';' && *p
!= ',') {
6523 /* End of param or invalid format */
6529 spin_unlock(&resource_alignment_lock
);
6533 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
6534 resource_size_t align
, bool resize
)
6536 struct resource
*r
= &dev
->resource
[bar
];
6537 resource_size_t size
;
6539 if (!(r
->flags
& IORESOURCE_MEM
))
6542 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
6543 pci_info(dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
6544 bar
, r
, (unsigned long long)align
);
6548 size
= resource_size(r
);
6553 * Increase the alignment of the resource. There are two ways we
6556 * 1) Increase the size of the resource. BARs are aligned on their
6557 * size, so when we reallocate space for this resource, we'll
6558 * allocate it with the larger alignment. This also prevents
6559 * assignment of any other BARs inside the alignment region, so
6560 * if we're requesting page alignment, this means no other BARs
6561 * will share the page.
6563 * The disadvantage is that this makes the resource larger than
6564 * the hardware BAR, which may break drivers that compute things
6565 * based on the resource size, e.g., to find registers at a
6566 * fixed offset before the end of the BAR.
6568 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6569 * set r->start to the desired alignment. By itself this
6570 * doesn't prevent other BARs being put inside the alignment
6571 * region, but if we realign *every* resource of every device in
6572 * the system, none of them will share an alignment region.
6574 * When the user has requested alignment for only some devices via
6575 * the "pci=resource_alignment" argument, "resize" is true and we
6576 * use the first method. Otherwise we assume we're aligning all
6577 * devices and we use the second.
6580 pci_info(dev
, "BAR%d %pR: requesting alignment to %#llx\n",
6581 bar
, r
, (unsigned long long)align
);
6587 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
6588 r
->flags
|= IORESOURCE_STARTALIGN
;
6590 r
->end
= r
->start
+ size
- 1;
6592 r
->flags
|= IORESOURCE_UNSET
;
6596 * This function disables memory decoding and releases memory resources
6597 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6598 * It also rounds up size to specified alignment.
6599 * Later on, the kernel will assign page-aligned memory resource back
6602 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
6606 resource_size_t align
;
6608 bool resize
= false;
6611 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6612 * 3.4.1.11. Their resources are allocated from the space
6613 * described by the VF BARx register in the PF's SR-IOV capability.
6614 * We can't influence their alignment here.
6619 /* check if specified PCI is target device to reassign */
6620 align
= pci_specified_resource_alignment(dev
, &resize
);
6624 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
6625 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
6626 pci_warn(dev
, "Can't reassign resources to host bridge\n");
6630 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
6631 command
&= ~PCI_COMMAND_MEMORY
;
6632 pci_write_config_word(dev
, PCI_COMMAND
, command
);
6634 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
6635 pci_request_resource_alignment(dev
, i
, align
, resize
);
6638 * Need to disable bridge's resource window,
6639 * to enable the kernel to reassign new resource
6642 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
6643 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
6644 r
= &dev
->resource
[i
];
6645 if (!(r
->flags
& IORESOURCE_MEM
))
6647 r
->flags
|= IORESOURCE_UNSET
;
6648 r
->end
= resource_size(r
) - 1;
6651 pci_disable_bridge_window(dev
);
6655 static ssize_t
resource_alignment_show(struct bus_type
*bus
, char *buf
)
6659 spin_lock(&resource_alignment_lock
);
6660 if (resource_alignment_param
)
6661 count
= sysfs_emit(buf
, "%s\n", resource_alignment_param
);
6662 spin_unlock(&resource_alignment_lock
);
6667 static ssize_t
resource_alignment_store(struct bus_type
*bus
,
6668 const char *buf
, size_t count
)
6670 char *param
, *old
, *end
;
6672 if (count
>= (PAGE_SIZE
- 1))
6675 param
= kstrndup(buf
, count
, GFP_KERNEL
);
6679 end
= strchr(param
, '\n');
6683 spin_lock(&resource_alignment_lock
);
6684 old
= resource_alignment_param
;
6685 if (strlen(param
)) {
6686 resource_alignment_param
= param
;
6689 resource_alignment_param
= NULL
;
6691 spin_unlock(&resource_alignment_lock
);
6698 static BUS_ATTR_RW(resource_alignment
);
6700 static int __init
pci_resource_alignment_sysfs_init(void)
6702 return bus_create_file(&pci_bus_type
,
6703 &bus_attr_resource_alignment
);
6705 late_initcall(pci_resource_alignment_sysfs_init
);
6707 static void pci_no_domains(void)
6709 #ifdef CONFIG_PCI_DOMAINS
6710 pci_domains_supported
= 0;
6714 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6715 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
6717 static int pci_get_new_domain_nr(void)
6719 return atomic_inc_return(&__domain_nr
);
6722 static int of_pci_bus_find_domain_nr(struct device
*parent
)
6724 static int use_dt_domains
= -1;
6728 domain
= of_get_pci_domain_nr(parent
->of_node
);
6731 * Check DT domain and use_dt_domains values.
6733 * If DT domain property is valid (domain >= 0) and
6734 * use_dt_domains != 0, the DT assignment is valid since this means
6735 * we have not previously allocated a domain number by using
6736 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6737 * 1, to indicate that we have just assigned a domain number from
6740 * If DT domain property value is not valid (ie domain < 0), and we
6741 * have not previously assigned a domain number from DT
6742 * (use_dt_domains != 1) we should assign a domain number by
6745 * pci_get_new_domain_nr()
6747 * API and update the use_dt_domains value to keep track of method we
6748 * are using to assign domain numbers (use_dt_domains = 0).
6750 * All other combinations imply we have a platform that is trying
6751 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6752 * which is a recipe for domain mishandling and it is prevented by
6753 * invalidating the domain value (domain = -1) and printing a
6754 * corresponding error.
6756 if (domain
>= 0 && use_dt_domains
) {
6758 } else if (domain
< 0 && use_dt_domains
!= 1) {
6760 domain
= pci_get_new_domain_nr();
6763 pr_err("Node %pOF has ", parent
->of_node
);
6764 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6771 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
6773 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
6774 acpi_pci_bus_find_domain_nr(bus
);
6779 * pci_ext_cfg_avail - can we access extended PCI config space?
6781 * Returns 1 if we can access PCI extended config space (offsets
6782 * greater than 0xff). This is the default implementation. Architecture
6783 * implementations can override this.
6785 int __weak
pci_ext_cfg_avail(void)
6790 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
6793 EXPORT_SYMBOL(pci_fixup_cardbus
);
6795 static int __init
pci_setup(char *str
)
6798 char *k
= strchr(str
, ',');
6801 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
6802 if (!strcmp(str
, "nomsi")) {
6804 } else if (!strncmp(str
, "noats", 5)) {
6805 pr_info("PCIe: ATS is disabled\n");
6806 pcie_ats_disabled
= true;
6807 } else if (!strcmp(str
, "noaer")) {
6809 } else if (!strcmp(str
, "earlydump")) {
6810 pci_early_dump
= true;
6811 } else if (!strncmp(str
, "realloc=", 8)) {
6812 pci_realloc_get_opt(str
+ 8);
6813 } else if (!strncmp(str
, "realloc", 7)) {
6814 pci_realloc_get_opt("on");
6815 } else if (!strcmp(str
, "nodomains")) {
6817 } else if (!strncmp(str
, "noari", 5)) {
6818 pcie_ari_disabled
= true;
6819 } else if (!strncmp(str
, "cbiosize=", 9)) {
6820 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
6821 } else if (!strncmp(str
, "cbmemsize=", 10)) {
6822 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
6823 } else if (!strncmp(str
, "resource_alignment=", 19)) {
6824 resource_alignment_param
= str
+ 19;
6825 } else if (!strncmp(str
, "ecrc=", 5)) {
6826 pcie_ecrc_get_policy(str
+ 5);
6827 } else if (!strncmp(str
, "hpiosize=", 9)) {
6828 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
6829 } else if (!strncmp(str
, "hpmmiosize=", 11)) {
6830 pci_hotplug_mmio_size
= memparse(str
+ 11, &str
);
6831 } else if (!strncmp(str
, "hpmmioprefsize=", 15)) {
6832 pci_hotplug_mmio_pref_size
= memparse(str
+ 15, &str
);
6833 } else if (!strncmp(str
, "hpmemsize=", 10)) {
6834 pci_hotplug_mmio_size
= memparse(str
+ 10, &str
);
6835 pci_hotplug_mmio_pref_size
= pci_hotplug_mmio_size
;
6836 } else if (!strncmp(str
, "hpbussize=", 10)) {
6837 pci_hotplug_bus_size
=
6838 simple_strtoul(str
+ 10, &str
, 0);
6839 if (pci_hotplug_bus_size
> 0xff)
6840 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
6841 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
6842 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
6843 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
6844 pcie_bus_config
= PCIE_BUS_SAFE
;
6845 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
6846 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
6847 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
6848 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
6849 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
6850 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
6851 } else if (!strncmp(str
, "disable_acs_redir=", 18)) {
6852 disable_acs_redir_param
= str
+ 18;
6854 pr_err("PCI: Unknown option `%s'\n", str
);
6861 early_param("pci", pci_setup
);
6864 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6865 * in pci_setup(), above, to point to data in the __initdata section which
6866 * will be freed after the init sequence is complete. We can't allocate memory
6867 * in pci_setup() because some architectures do not have any memory allocation
6868 * service available during an early_param() call. So we allocate memory and
6869 * copy the variable here before the init section is freed.
6872 static int __init
pci_realloc_setup_params(void)
6874 resource_alignment_param
= kstrdup(resource_alignment_param
,
6876 disable_acs_redir_param
= kstrdup(disable_acs_redir_param
, GFP_KERNEL
);
6880 pure_initcall(pci_realloc_setup_params
);