2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/logic_pio.h>
25 #include <linux/pci-aspm.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 const char *pci_power_names
[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names
);
43 int isa_dma_bridge_buggy
;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
47 EXPORT_SYMBOL(pci_pci_problems
);
49 unsigned int pci_pm_d3_delay
;
51 static void pci_pme_list_scan(struct work_struct
*work
);
53 static LIST_HEAD(pci_pme_list
);
54 static DEFINE_MUTEX(pci_pme_list_mutex
);
55 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
57 struct pci_pme_device
{
58 struct list_head list
;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
66 unsigned int delay
= dev
->d3_delay
;
68 if (delay
< pci_pm_d3_delay
)
69 delay
= pci_pm_d3_delay
;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported
= 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
83 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
89 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
94 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
103 u8 pci_cache_line_size
;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency
= 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled
;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable
;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force
;
119 static int __init
pcie_port_pm_setup(char *str
)
121 if (!strcmp(str
, "off"))
122 pci_bridge_d3_disable
= true;
123 else if (!strcmp(str
, "force"))
124 pci_bridge_d3_force
= true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup
);
130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
131 * @bus: pointer to PCI bus structure to search
133 * Given a PCI bus, returns the highest PCI bus number present in the set
134 * including the given PCI bus and its list of child PCI buses.
136 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
139 unsigned char max
, n
;
141 max
= bus
->busn_res
.end
;
142 list_for_each_entry(tmp
, &bus
->children
, node
) {
143 n
= pci_bus_max_busnr(tmp
);
149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
151 #ifdef CONFIG_HAS_IOMEM
152 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
154 struct resource
*res
= &pdev
->resource
[bar
];
157 * Make sure the BAR is actually a memory resource, not an IO resource
159 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
160 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
163 return ioremap_nocache(res
->start
, resource_size(res
));
165 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
167 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
170 * Make sure the BAR is actually a memory resource, not an IO resource
172 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
176 return ioremap_wc(pci_resource_start(pdev
, bar
),
177 pci_resource_len(pdev
, bar
));
179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
183 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
184 u8 pos
, int cap
, int *ttl
)
189 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
195 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
207 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
210 int ttl
= PCI_FIND_CAP_TTL
;
212 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
215 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
217 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
218 pos
+ PCI_CAP_LIST_NEXT
, cap
);
220 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
222 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
223 unsigned int devfn
, u8 hdr_type
)
227 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
228 if (!(status
& PCI_STATUS_CAP_LIST
))
232 case PCI_HEADER_TYPE_NORMAL
:
233 case PCI_HEADER_TYPE_BRIDGE
:
234 return PCI_CAPABILITY_LIST
;
235 case PCI_HEADER_TYPE_CARDBUS
:
236 return PCI_CB_CAPABILITY_LIST
;
243 * pci_find_capability - query for devices' capabilities
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Tell if a device supports a given PCI capability.
248 * Returns the address of the requested capability structure within the
249 * device's PCI configuration space or 0 in case the device does not
250 * support it. Possible values for @cap:
252 * %PCI_CAP_ID_PM Power Management
253 * %PCI_CAP_ID_AGP Accelerated Graphics Port
254 * %PCI_CAP_ID_VPD Vital Product Data
255 * %PCI_CAP_ID_SLOTID Slot Identification
256 * %PCI_CAP_ID_MSI Message Signalled Interrupts
257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
258 * %PCI_CAP_ID_PCIX PCI-X
259 * %PCI_CAP_ID_EXP PCI Express
261 int pci_find_capability(struct pci_dev
*dev
, int cap
)
265 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
267 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
271 EXPORT_SYMBOL(pci_find_capability
);
274 * pci_bus_find_capability - query for devices' capabilities
275 * @bus: the PCI bus to query
276 * @devfn: PCI device to query
277 * @cap: capability code
279 * Like pci_find_capability() but works for pci devices that do not have a
280 * pci_dev structure set up yet.
282 * Returns the address of the requested capability structure within the
283 * device's PCI configuration space or 0 in case the device does not
286 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
291 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
293 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
295 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
299 EXPORT_SYMBOL(pci_bus_find_capability
);
302 * pci_find_next_ext_capability - Find an extended capability
303 * @dev: PCI device to query
304 * @start: address at which to start looking (0 to start at beginning of list)
305 * @cap: capability code
307 * Returns the address of the next matching extended capability structure
308 * within the device's PCI configuration space or 0 if the device does
309 * not support it. Some capabilities can occur several times, e.g., the
310 * vendor-specific capability, and this provides a way to find them all.
312 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
316 int pos
= PCI_CFG_SPACE_SIZE
;
318 /* minimum 8 bytes per capability */
319 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
321 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
327 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
331 * If we have no capabilities, this is indicated by cap ID,
332 * cap version and next pointer all being 0.
338 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
341 pos
= PCI_EXT_CAP_NEXT(header
);
342 if (pos
< PCI_CFG_SPACE_SIZE
)
345 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
354 * pci_find_ext_capability - Find an extended capability
355 * @dev: PCI device to query
356 * @cap: capability code
358 * Returns the address of the requested extended capability structure
359 * within the device's PCI configuration space or 0 if the device does
360 * not support it. Possible values for @cap:
362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
363 * %PCI_EXT_CAP_ID_VC Virtual Channel
364 * %PCI_EXT_CAP_ID_DSN Device Serial Number
365 * %PCI_EXT_CAP_ID_PWR Power Budgeting
367 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
369 return pci_find_next_ext_capability(dev
, 0, cap
);
371 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
373 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
375 int rc
, ttl
= PCI_FIND_CAP_TTL
;
378 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
379 mask
= HT_3BIT_CAP_MASK
;
381 mask
= HT_5BIT_CAP_MASK
;
383 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
384 PCI_CAP_ID_HT
, &ttl
);
386 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
387 if (rc
!= PCIBIOS_SUCCESSFUL
)
390 if ((cap
& mask
) == ht_cap
)
393 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
394 pos
+ PCI_CAP_LIST_NEXT
,
395 PCI_CAP_ID_HT
, &ttl
);
401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
402 * @dev: PCI device to query
403 * @pos: Position from which to continue searching
404 * @ht_cap: Hypertransport capability code
406 * To be used in conjunction with pci_find_ht_capability() to search for
407 * all capabilities matching @ht_cap. @pos should always be a value returned
408 * from pci_find_ht_capability().
410 * NB. To be 100% safe against broken PCI devices, the caller should take
411 * steps to avoid an infinite loop.
413 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
415 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
420 * pci_find_ht_capability - query a device's Hypertransport capabilities
421 * @dev: PCI device to query
422 * @ht_cap: Hypertransport capability code
424 * Tell if a device supports a given Hypertransport capability.
425 * Returns an address within the device's PCI configuration space
426 * or 0 in case the device does not support the request capability.
427 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
428 * which has a Hypertransport capability matching @ht_cap.
430 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
434 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
436 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
440 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
443 * pci_find_parent_resource - return resource region of parent bus of given region
444 * @dev: PCI device structure contains resources to be searched
445 * @res: child resource record for which parent is sought
447 * For given resource region of given device, return the resource
448 * region of parent bus the given region is contained in.
450 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
451 struct resource
*res
)
453 const struct pci_bus
*bus
= dev
->bus
;
457 pci_bus_for_each_resource(bus
, r
, i
) {
460 if (resource_contains(r
, res
)) {
463 * If the window is prefetchable but the BAR is
464 * not, the allocator made a mistake.
466 if (r
->flags
& IORESOURCE_PREFETCH
&&
467 !(res
->flags
& IORESOURCE_PREFETCH
))
471 * If we're below a transparent bridge, there may
472 * be both a positively-decoded aperture and a
473 * subtractively-decoded region that contain the BAR.
474 * We want the positively-decoded one, so this depends
475 * on pci_bus_for_each_resource() giving us those
483 EXPORT_SYMBOL(pci_find_parent_resource
);
486 * pci_find_resource - Return matching PCI device resource
487 * @dev: PCI device to query
488 * @res: Resource to look for
490 * Goes over standard PCI resources (BARs) and checks if the given resource
491 * is partially or fully contained in any of them. In that case the
492 * matching resource is returned, %NULL otherwise.
494 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
498 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++) {
499 struct resource
*r
= &dev
->resource
[i
];
501 if (r
->start
&& resource_contains(r
, res
))
507 EXPORT_SYMBOL(pci_find_resource
);
510 * pci_find_pcie_root_port - return PCIe Root Port
511 * @dev: PCI device to query
513 * Traverse up the parent chain and return the PCIe Root Port PCI Device
514 * for a given PCI Device.
516 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
)
518 struct pci_dev
*bridge
, *highest_pcie_bridge
= dev
;
520 bridge
= pci_upstream_bridge(dev
);
521 while (bridge
&& pci_is_pcie(bridge
)) {
522 highest_pcie_bridge
= bridge
;
523 bridge
= pci_upstream_bridge(bridge
);
526 if (pci_pcie_type(highest_pcie_bridge
) != PCI_EXP_TYPE_ROOT_PORT
)
529 return highest_pcie_bridge
;
531 EXPORT_SYMBOL(pci_find_pcie_root_port
);
534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
535 * @dev: the PCI device to operate on
536 * @pos: config space offset of status word
537 * @mask: mask of bit(s) to care about in status word
539 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
541 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
545 /* Wait for Transaction Pending bit clean */
546 for (i
= 0; i
< 4; i
++) {
549 msleep((1 << (i
- 1)) * 100);
551 pci_read_config_word(dev
, pos
, &status
);
552 if (!(status
& mask
))
560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
561 * @dev: PCI device to have its BARs restored
563 * Restore the BAR values for a given device, so as to make it
564 * accessible by its driver.
566 static void pci_restore_bars(struct pci_dev
*dev
)
570 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
571 pci_update_resource(dev
, i
);
574 static const struct pci_platform_pm_ops
*pci_platform_pm
;
576 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
578 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
579 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
581 pci_platform_pm
= ops
;
585 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
587 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
590 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
593 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
596 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
598 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
601 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
603 return pci_platform_pm
?
604 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
607 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
609 return pci_platform_pm
?
610 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
613 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
615 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
621 * @dev: PCI device to handle.
622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
625 * -EINVAL if the requested state is invalid.
626 * -EIO if device does not support PCI PM or its PM capabilities register has a
627 * wrong version, or device doesn't support the requested state.
628 * 0 if device already is in the requested state.
629 * 0 if device's power state has been successfully changed.
631 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
634 bool need_restore
= false;
636 /* Check if we're already there */
637 if (dev
->current_state
== state
)
643 if (state
< PCI_D0
|| state
> PCI_D3hot
)
646 /* Validate current state:
647 * Can enter D0 from any state, but if we can only go deeper
648 * to sleep if we're already in a low power state
650 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
651 && dev
->current_state
> state
) {
652 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
653 dev
->current_state
, state
);
657 /* check if this device supports the desired state */
658 if ((state
== PCI_D1
&& !dev
->d1_support
)
659 || (state
== PCI_D2
&& !dev
->d2_support
))
662 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
664 /* If we're (effectively) in D3, force entire word to 0.
665 * This doesn't affect PME_Status, disables PME_En, and
666 * sets PowerState to 0.
668 switch (dev
->current_state
) {
672 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
677 case PCI_UNKNOWN
: /* Boot-up */
678 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
679 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
681 /* Fall-through: force to D0 */
687 /* enter specified state */
688 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
690 /* Mandatory power management transition delays */
691 /* see PCI PM 1.1 5.6.1 table 18 */
692 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
693 pci_dev_d3_sleep(dev
);
694 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
695 udelay(PCI_PM_D2_DELAY
);
697 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
698 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
699 if (dev
->current_state
!= state
&& printk_ratelimit())
700 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
706 * from D3hot to D0 _may_ perform an internal reset, thereby
707 * going to "D0 Uninitialized" rather than "D0 Initialized".
708 * For example, at least some versions of the 3c905B and the
709 * 3c556B exhibit this behaviour.
711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
712 * devices in a D3hot state at boot. Consequently, we need to
713 * restore at least the BARs so that the device will be
714 * accessible to its driver.
717 pci_restore_bars(dev
);
720 pcie_aspm_pm_state_change(dev
->bus
->self
);
726 * pci_update_current_state - Read power state of given device and cache it
727 * @dev: PCI device to handle.
728 * @state: State to cache in case the device doesn't have the PM capability
730 * The power state is read from the PMCSR register, which however is
731 * inaccessible in D3cold. The platform firmware is therefore queried first
732 * to detect accessibility of the register. In case the platform firmware
733 * reports an incorrect state or the device isn't power manageable by the
734 * platform at all, we try to detect D3cold by testing accessibility of the
735 * vendor ID in config space.
737 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
739 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
740 !pci_device_is_present(dev
)) {
741 dev
->current_state
= PCI_D3cold
;
742 } else if (dev
->pm_cap
) {
745 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
746 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
748 dev
->current_state
= state
;
753 * pci_power_up - Put the given device into D0 forcibly
754 * @dev: PCI device to power up
756 void pci_power_up(struct pci_dev
*dev
)
758 if (platform_pci_power_manageable(dev
))
759 platform_pci_set_power_state(dev
, PCI_D0
);
761 pci_raw_set_power_state(dev
, PCI_D0
);
762 pci_update_current_state(dev
, PCI_D0
);
766 * pci_platform_power_transition - Use platform to change device power state
767 * @dev: PCI device to handle.
768 * @state: State to put the device into.
770 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
774 if (platform_pci_power_manageable(dev
)) {
775 error
= platform_pci_set_power_state(dev
, state
);
777 pci_update_current_state(dev
, state
);
781 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
782 dev
->current_state
= PCI_D0
;
788 * pci_wakeup - Wake up a PCI device
789 * @pci_dev: Device to handle.
790 * @ign: ignored parameter
792 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
794 pci_wakeup_event(pci_dev
);
795 pm_request_resume(&pci_dev
->dev
);
800 * pci_wakeup_bus - Walk given bus and wake up devices on it
801 * @bus: Top bus of the subtree to walk.
803 static void pci_wakeup_bus(struct pci_bus
*bus
)
806 pci_walk_bus(bus
, pci_wakeup
, NULL
);
810 * __pci_start_power_transition - Start power transition of a PCI device
811 * @dev: PCI device to handle.
812 * @state: State to put the device into.
814 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
816 if (state
== PCI_D0
) {
817 pci_platform_power_transition(dev
, PCI_D0
);
819 * Mandatory power management transition delays, see
820 * PCI Express Base Specification Revision 2.0 Section
821 * 6.6.1: Conventional Reset. Do not delay for
822 * devices powered on/off by corresponding bridge,
823 * because have already delayed for the bridge.
825 if (dev
->runtime_d3cold
) {
826 if (dev
->d3cold_delay
)
827 msleep(dev
->d3cold_delay
);
829 * When powering on a bridge from D3cold, the
830 * whole hierarchy may be powered on into
831 * D0uninitialized state, resume them to give
832 * them a chance to suspend again
834 pci_wakeup_bus(dev
->subordinate
);
840 * __pci_dev_set_current_state - Set current state of a PCI device
841 * @dev: Device to handle
842 * @data: pointer to state to be set
844 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
846 pci_power_t state
= *(pci_power_t
*)data
;
848 dev
->current_state
= state
;
853 * __pci_bus_set_current_state - Walk given bus and set current state of devices
854 * @bus: Top bus of the subtree to walk.
855 * @state: state to be set
857 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
860 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
864 * __pci_complete_power_transition - Complete power transition of a PCI device
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 * This function should not be called directly by device drivers.
870 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
876 ret
= pci_platform_power_transition(dev
, state
);
877 /* Power off the bridge may power off the whole hierarchy */
878 if (!ret
&& state
== PCI_D3cold
)
879 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
885 * pci_set_power_state - Set the power state of a PCI device
886 * @dev: PCI device to handle.
887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
889 * Transition a device to a new power state, using the platform firmware and/or
890 * the device's PCI PM registers.
893 * -EINVAL if the requested state is invalid.
894 * -EIO if device does not support PCI PM or its PM capabilities register has a
895 * wrong version, or device doesn't support the requested state.
896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
897 * 0 if device already is in the requested state.
898 * 0 if the transition is to D3 but D3 is not supported.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
905 /* bound the state we're entering */
906 if (state
> PCI_D3cold
)
908 else if (state
< PCI_D0
)
910 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev
->current_state
== state
)
922 __pci_start_power_transition(dev
, state
);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
936 if (!__pci_complete_power_transition(dev
, state
))
941 EXPORT_SYMBOL(pci_set_power_state
);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
960 ret
= platform_pci_choose_state(dev
);
961 if (ret
!= PCI_POWER_ERROR
)
964 switch (state
.event
) {
967 case PM_EVENT_FREEZE
:
968 case PM_EVENT_PRETHAW
:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND
:
971 case PM_EVENT_HIBERNATE
:
974 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state
);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
985 u16 cap
, bool extended
)
987 struct pci_cap_saved_state
*tmp
;
989 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
990 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
996 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
998 return _pci_find_saved_cap(dev
, cap
, false);
1001 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1003 return _pci_find_saved_cap(dev
, cap
, true);
1006 static int pci_save_pcie_state(struct pci_dev
*dev
)
1009 struct pci_cap_saved_state
*save_state
;
1012 if (!pci_is_pcie(dev
))
1015 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1017 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1021 cap
= (u16
*)&save_state
->cap
.data
[0];
1022 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1023 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1024 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1025 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1026 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1027 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1028 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1033 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1036 struct pci_cap_saved_state
*save_state
;
1039 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1043 cap
= (u16
*)&save_state
->cap
.data
[0];
1044 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1045 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1046 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1047 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1048 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1049 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1050 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1054 static int pci_save_pcix_state(struct pci_dev
*dev
)
1057 struct pci_cap_saved_state
*save_state
;
1059 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1063 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1065 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1069 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1070 (u16
*)save_state
->cap
.data
);
1075 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1078 struct pci_cap_saved_state
*save_state
;
1081 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1082 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1083 if (!save_state
|| !pos
)
1085 cap
= (u16
*)&save_state
->cap
.data
[0];
1087 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev
*dev
)
1098 /* XXX: 100% dword access ok here? */
1099 for (i
= 0; i
< 16; i
++)
1100 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1101 dev
->state_saved
= true;
1103 i
= pci_save_pcie_state(dev
);
1107 i
= pci_save_pcix_state(dev
);
1111 return pci_save_vc_state(dev
);
1113 EXPORT_SYMBOL(pci_save_state
);
1115 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1116 u32 saved_val
, int retry
, bool force
)
1120 pci_read_config_dword(pdev
, offset
, &val
);
1121 if (!force
&& val
== saved_val
)
1125 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset
, val
, saved_val
);
1127 pci_write_config_dword(pdev
, offset
, saved_val
);
1131 pci_read_config_dword(pdev
, offset
, &val
);
1132 if (val
== saved_val
)
1139 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1140 int start
, int end
, int retry
,
1145 for (index
= end
; index
>= start
; index
--)
1146 pci_restore_config_dword(pdev
, 4 * index
,
1147 pdev
->saved_config_space
[index
],
1151 static void pci_restore_config_space(struct pci_dev
*pdev
)
1153 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1154 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1155 /* Restore BARs before the command register. */
1156 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1157 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1158 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1159 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1162 * Force rewriting of prefetch registers to avoid S3 resume
1163 * issues on Intel PCI bridges that occur when these
1164 * registers are not explicitly written.
1166 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1167 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1169 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1174 * pci_restore_state - Restore the saved state of a PCI device
1175 * @dev: - PCI device that we're dealing with
1177 void pci_restore_state(struct pci_dev
*dev
)
1179 if (!dev
->state_saved
)
1182 /* PCI Express register must be restored first */
1183 pci_restore_pcie_state(dev
);
1184 pci_restore_pasid_state(dev
);
1185 pci_restore_pri_state(dev
);
1186 pci_restore_ats_state(dev
);
1187 pci_restore_vc_state(dev
);
1189 pci_cleanup_aer_error_status_regs(dev
);
1191 pci_restore_config_space(dev
);
1193 pci_restore_pcix_state(dev
);
1194 pci_restore_msi_state(dev
);
1196 /* Restore ACS and IOV configuration state */
1197 pci_enable_acs(dev
);
1198 pci_restore_iov_state(dev
);
1200 dev
->state_saved
= false;
1202 EXPORT_SYMBOL(pci_restore_state
);
1204 struct pci_saved_state
{
1205 u32 config_space
[16];
1206 struct pci_cap_saved_data cap
[0];
1210 * pci_store_saved_state - Allocate and return an opaque struct containing
1211 * the device saved state.
1212 * @dev: PCI device that we're dealing with
1214 * Return NULL if no state or error.
1216 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1218 struct pci_saved_state
*state
;
1219 struct pci_cap_saved_state
*tmp
;
1220 struct pci_cap_saved_data
*cap
;
1223 if (!dev
->state_saved
)
1226 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1228 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1229 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1231 state
= kzalloc(size
, GFP_KERNEL
);
1235 memcpy(state
->config_space
, dev
->saved_config_space
,
1236 sizeof(state
->config_space
));
1239 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1240 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1241 memcpy(cap
, &tmp
->cap
, len
);
1242 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1244 /* Empty cap_save terminates list */
1248 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1251 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1252 * @dev: PCI device that we're dealing with
1253 * @state: Saved state returned from pci_store_saved_state()
1255 int pci_load_saved_state(struct pci_dev
*dev
,
1256 struct pci_saved_state
*state
)
1258 struct pci_cap_saved_data
*cap
;
1260 dev
->state_saved
= false;
1265 memcpy(dev
->saved_config_space
, state
->config_space
,
1266 sizeof(state
->config_space
));
1270 struct pci_cap_saved_state
*tmp
;
1272 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1273 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1276 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1277 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1278 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1281 dev
->state_saved
= true;
1284 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1287 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1288 * and free the memory allocated for it.
1289 * @dev: PCI device that we're dealing with
1290 * @state: Pointer to saved state returned from pci_store_saved_state()
1292 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1293 struct pci_saved_state
**state
)
1295 int ret
= pci_load_saved_state(dev
, *state
);
1300 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1302 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1304 return pci_enable_resources(dev
, bars
);
1307 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1310 struct pci_dev
*bridge
;
1314 err
= pci_set_power_state(dev
, PCI_D0
);
1315 if (err
< 0 && err
!= -EIO
)
1318 bridge
= pci_upstream_bridge(dev
);
1320 pcie_aspm_powersave_config_link(bridge
);
1322 err
= pcibios_enable_device(dev
, bars
);
1325 pci_fixup_device(pci_fixup_enable
, dev
);
1327 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1330 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1332 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1333 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1334 pci_write_config_word(dev
, PCI_COMMAND
,
1335 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1342 * pci_reenable_device - Resume abandoned device
1343 * @dev: PCI device to be resumed
1345 * Note this function is a backend of pci_default_resume and is not supposed
1346 * to be called by normal code, write proper resume handler and use it instead.
1348 int pci_reenable_device(struct pci_dev
*dev
)
1350 if (pci_is_enabled(dev
))
1351 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1354 EXPORT_SYMBOL(pci_reenable_device
);
1356 static void pci_enable_bridge(struct pci_dev
*dev
)
1358 struct pci_dev
*bridge
;
1361 bridge
= pci_upstream_bridge(dev
);
1363 pci_enable_bridge(bridge
);
1365 if (pci_is_enabled(dev
)) {
1366 if (!dev
->is_busmaster
)
1367 pci_set_master(dev
);
1371 retval
= pci_enable_device(dev
);
1373 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1375 pci_set_master(dev
);
1378 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1380 struct pci_dev
*bridge
;
1385 * Power state could be unknown at this point, either due to a fresh
1386 * boot or a device removal call. So get the current power state
1387 * so that things like MSI message writing will behave as expected
1388 * (e.g. if the device really is in D0 at enable time).
1392 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1393 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1396 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1397 return 0; /* already enabled */
1399 bridge
= pci_upstream_bridge(dev
);
1401 pci_enable_bridge(bridge
);
1403 /* only skip sriov related */
1404 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1405 if (dev
->resource
[i
].flags
& flags
)
1407 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1408 if (dev
->resource
[i
].flags
& flags
)
1411 err
= do_pci_enable_device(dev
, bars
);
1413 atomic_dec(&dev
->enable_cnt
);
1418 * pci_enable_device_io - Initialize a device for use with IO space
1419 * @dev: PCI device to be initialized
1421 * Initialize device before it's used by a driver. Ask low-level code
1422 * to enable I/O resources. Wake up the device if it was suspended.
1423 * Beware, this function can fail.
1425 int pci_enable_device_io(struct pci_dev
*dev
)
1427 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1429 EXPORT_SYMBOL(pci_enable_device_io
);
1432 * pci_enable_device_mem - Initialize a device for use with Memory space
1433 * @dev: PCI device to be initialized
1435 * Initialize device before it's used by a driver. Ask low-level code
1436 * to enable Memory resources. Wake up the device if it was suspended.
1437 * Beware, this function can fail.
1439 int pci_enable_device_mem(struct pci_dev
*dev
)
1441 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1443 EXPORT_SYMBOL(pci_enable_device_mem
);
1446 * pci_enable_device - Initialize device before it's used by a driver.
1447 * @dev: PCI device to be initialized
1449 * Initialize device before it's used by a driver. Ask low-level code
1450 * to enable I/O and memory. Wake up the device if it was suspended.
1451 * Beware, this function can fail.
1453 * Note we don't actually enable the device many times if we call
1454 * this function repeatedly (we just increment the count).
1456 int pci_enable_device(struct pci_dev
*dev
)
1458 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1460 EXPORT_SYMBOL(pci_enable_device
);
1463 * Managed PCI resources. This manages device on/off, intx/msi/msix
1464 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1465 * there's no need to track it separately. pci_devres is initialized
1466 * when a device is enabled using managed PCI device enable interface.
1469 unsigned int enabled
:1;
1470 unsigned int pinned
:1;
1471 unsigned int orig_intx
:1;
1472 unsigned int restore_intx
:1;
1477 static void pcim_release(struct device
*gendev
, void *res
)
1479 struct pci_dev
*dev
= to_pci_dev(gendev
);
1480 struct pci_devres
*this = res
;
1483 if (dev
->msi_enabled
)
1484 pci_disable_msi(dev
);
1485 if (dev
->msix_enabled
)
1486 pci_disable_msix(dev
);
1488 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1489 if (this->region_mask
& (1 << i
))
1490 pci_release_region(dev
, i
);
1495 if (this->restore_intx
)
1496 pci_intx(dev
, this->orig_intx
);
1498 if (this->enabled
&& !this->pinned
)
1499 pci_disable_device(dev
);
1502 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1504 struct pci_devres
*dr
, *new_dr
;
1506 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1510 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1513 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1516 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1518 if (pci_is_managed(pdev
))
1519 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1524 * pcim_enable_device - Managed pci_enable_device()
1525 * @pdev: PCI device to be initialized
1527 * Managed pci_enable_device().
1529 int pcim_enable_device(struct pci_dev
*pdev
)
1531 struct pci_devres
*dr
;
1534 dr
= get_pci_dr(pdev
);
1540 rc
= pci_enable_device(pdev
);
1542 pdev
->is_managed
= 1;
1547 EXPORT_SYMBOL(pcim_enable_device
);
1550 * pcim_pin_device - Pin managed PCI device
1551 * @pdev: PCI device to pin
1553 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1554 * driver detach. @pdev must have been enabled with
1555 * pcim_enable_device().
1557 void pcim_pin_device(struct pci_dev
*pdev
)
1559 struct pci_devres
*dr
;
1561 dr
= find_pci_dr(pdev
);
1562 WARN_ON(!dr
|| !dr
->enabled
);
1566 EXPORT_SYMBOL(pcim_pin_device
);
1569 * pcibios_add_device - provide arch specific hooks when adding device dev
1570 * @dev: the PCI device being added
1572 * Permits the platform to provide architecture specific functionality when
1573 * devices are added. This is the default implementation. Architecture
1574 * implementations can override this.
1576 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1582 * pcibios_release_device - provide arch specific hooks when releasing device dev
1583 * @dev: the PCI device being released
1585 * Permits the platform to provide architecture specific functionality when
1586 * devices are released. This is the default implementation. Architecture
1587 * implementations can override this.
1589 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1592 * pcibios_disable_device - disable arch specific PCI resources for device dev
1593 * @dev: the PCI device to disable
1595 * Disables architecture specific PCI resources for the device. This
1596 * is the default implementation. Architecture implementations can
1599 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
1602 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1603 * @irq: ISA IRQ to penalize
1604 * @active: IRQ active or not
1606 * Permits the platform to provide architecture-specific functionality when
1607 * penalizing ISA IRQs. This is the default implementation. Architecture
1608 * implementations can override this.
1610 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1612 static void do_pci_disable_device(struct pci_dev
*dev
)
1616 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1617 if (pci_command
& PCI_COMMAND_MASTER
) {
1618 pci_command
&= ~PCI_COMMAND_MASTER
;
1619 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1622 pcibios_disable_device(dev
);
1626 * pci_disable_enabled_device - Disable device without updating enable_cnt
1627 * @dev: PCI device to disable
1629 * NOTE: This function is a backend of PCI power management routines and is
1630 * not supposed to be called drivers.
1632 void pci_disable_enabled_device(struct pci_dev
*dev
)
1634 if (pci_is_enabled(dev
))
1635 do_pci_disable_device(dev
);
1639 * pci_disable_device - Disable PCI device after use
1640 * @dev: PCI device to be disabled
1642 * Signal to the system that the PCI device is not in use by the system
1643 * anymore. This only involves disabling PCI bus-mastering, if active.
1645 * Note we don't actually disable the device until all callers of
1646 * pci_enable_device() have called pci_disable_device().
1648 void pci_disable_device(struct pci_dev
*dev
)
1650 struct pci_devres
*dr
;
1652 dr
= find_pci_dr(dev
);
1656 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1657 "disabling already-disabled device");
1659 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1662 do_pci_disable_device(dev
);
1664 dev
->is_busmaster
= 0;
1666 EXPORT_SYMBOL(pci_disable_device
);
1669 * pcibios_set_pcie_reset_state - set reset state for device dev
1670 * @dev: the PCIe device reset
1671 * @state: Reset state to enter into
1674 * Sets the PCIe reset state for the device. This is the default
1675 * implementation. Architecture implementations can override this.
1677 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1678 enum pcie_reset_state state
)
1684 * pci_set_pcie_reset_state - set reset state for device dev
1685 * @dev: the PCIe device reset
1686 * @state: Reset state to enter into
1689 * Sets the PCI reset state for the device.
1691 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1693 return pcibios_set_pcie_reset_state(dev
, state
);
1695 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1698 * pci_check_pme_status - Check if given device has generated PME.
1699 * @dev: Device to check.
1701 * Check the PME status of the device and if set, clear it and clear PME enable
1702 * (if set). Return 'true' if PME status and PME enable were both set or
1703 * 'false' otherwise.
1705 bool pci_check_pme_status(struct pci_dev
*dev
)
1714 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1715 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1716 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1719 /* Clear PME status. */
1720 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1721 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1722 /* Disable PME to avoid interrupt flood. */
1723 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1727 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1733 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1734 * @dev: Device to handle.
1735 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1737 * Check if @dev has generated PME and queue a resume request for it in that
1740 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1742 if (pme_poll_reset
&& dev
->pme_poll
)
1743 dev
->pme_poll
= false;
1745 if (pci_check_pme_status(dev
)) {
1746 pci_wakeup_event(dev
);
1747 pm_request_resume(&dev
->dev
);
1753 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1754 * @bus: Top bus of the subtree to walk.
1756 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1759 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1764 * pci_pme_capable - check the capability of PCI device to generate PME#
1765 * @dev: PCI device to handle.
1766 * @state: PCI state from which device will issue PME#.
1768 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1773 return !!(dev
->pme_support
& (1 << state
));
1775 EXPORT_SYMBOL(pci_pme_capable
);
1777 static void pci_pme_list_scan(struct work_struct
*work
)
1779 struct pci_pme_device
*pme_dev
, *n
;
1781 mutex_lock(&pci_pme_list_mutex
);
1782 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1783 if (pme_dev
->dev
->pme_poll
) {
1784 struct pci_dev
*bridge
;
1786 bridge
= pme_dev
->dev
->bus
->self
;
1788 * If bridge is in low power state, the
1789 * configuration space of subordinate devices
1790 * may be not accessible
1792 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1794 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1796 list_del(&pme_dev
->list
);
1800 if (!list_empty(&pci_pme_list
))
1801 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
1802 msecs_to_jiffies(PME_TIMEOUT
));
1803 mutex_unlock(&pci_pme_list_mutex
);
1806 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
1810 if (!dev
->pme_support
)
1813 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1814 /* Clear PME_Status by writing 1 to it and enable PME# */
1815 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1817 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1819 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1823 * pci_pme_restore - Restore PME configuration after config space restore.
1824 * @dev: PCI device to update.
1826 void pci_pme_restore(struct pci_dev
*dev
)
1830 if (!dev
->pme_support
)
1833 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1834 if (dev
->wakeup_prepared
) {
1835 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
1836 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
1838 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1839 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1841 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1845 * pci_pme_active - enable or disable PCI device's PME# function
1846 * @dev: PCI device to handle.
1847 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1849 * The caller must verify that the device is capable of generating PME# before
1850 * calling this function with @enable equal to 'true'.
1852 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1854 __pci_pme_active(dev
, enable
);
1857 * PCI (as opposed to PCIe) PME requires that the device have
1858 * its PME# line hooked up correctly. Not all hardware vendors
1859 * do this, so the PME never gets delivered and the device
1860 * remains asleep. The easiest way around this is to
1861 * periodically walk the list of suspended devices and check
1862 * whether any have their PME flag set. The assumption is that
1863 * we'll wake up often enough anyway that this won't be a huge
1864 * hit, and the power savings from the devices will still be a
1867 * Although PCIe uses in-band PME message instead of PME# line
1868 * to report PME, PME does not work for some PCIe devices in
1869 * reality. For example, there are devices that set their PME
1870 * status bits, but don't really bother to send a PME message;
1871 * there are PCI Express Root Ports that don't bother to
1872 * trigger interrupts when they receive PME messages from the
1873 * devices below. So PME poll is used for PCIe devices too.
1876 if (dev
->pme_poll
) {
1877 struct pci_pme_device
*pme_dev
;
1879 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1882 dev_warn(&dev
->dev
, "can't enable PME#\n");
1886 mutex_lock(&pci_pme_list_mutex
);
1887 list_add(&pme_dev
->list
, &pci_pme_list
);
1888 if (list_is_singular(&pci_pme_list
))
1889 queue_delayed_work(system_freezable_wq
,
1891 msecs_to_jiffies(PME_TIMEOUT
));
1892 mutex_unlock(&pci_pme_list_mutex
);
1894 mutex_lock(&pci_pme_list_mutex
);
1895 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1896 if (pme_dev
->dev
== dev
) {
1897 list_del(&pme_dev
->list
);
1902 mutex_unlock(&pci_pme_list_mutex
);
1906 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1908 EXPORT_SYMBOL(pci_pme_active
);
1911 * __pci_enable_wake - enable PCI device as wakeup event source
1912 * @dev: PCI device affected
1913 * @state: PCI state from which device will issue wakeup events
1914 * @enable: True to enable event generation; false to disable
1916 * This enables the device as a wakeup event source, or disables it.
1917 * When such events involves platform-specific hooks, those hooks are
1918 * called automatically by this routine.
1920 * Devices with legacy power management (no standard PCI PM capabilities)
1921 * always require such platform hooks.
1924 * 0 is returned on success
1925 * -EINVAL is returned if device is not supposed to wake up the system
1926 * Error code depending on the platform is returned if both the platform and
1927 * the native mechanism fail to enable the generation of wake-up events
1929 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
1934 * Bridges can only signal wakeup on behalf of subordinate devices,
1935 * but that is set up elsewhere, so skip them.
1937 if (pci_has_subordinate(dev
))
1940 /* Don't do the same thing twice in a row for one device. */
1941 if (!!enable
== !!dev
->wakeup_prepared
)
1945 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1946 * Anderson we should be doing PME# wake enable followed by ACPI wake
1947 * enable. To disable wake-up we call the platform first, for symmetry.
1953 if (pci_pme_capable(dev
, state
))
1954 pci_pme_active(dev
, true);
1957 error
= platform_pci_set_wakeup(dev
, true);
1961 dev
->wakeup_prepared
= true;
1963 platform_pci_set_wakeup(dev
, false);
1964 pci_pme_active(dev
, false);
1965 dev
->wakeup_prepared
= false;
1972 * pci_enable_wake - change wakeup settings for a PCI device
1973 * @pci_dev: Target device
1974 * @state: PCI state from which device will issue wakeup events
1975 * @enable: Whether or not to enable event generation
1977 * If @enable is set, check device_may_wakeup() for the device before calling
1978 * __pci_enable_wake() for it.
1980 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
1982 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
1985 return __pci_enable_wake(pci_dev
, state
, enable
);
1987 EXPORT_SYMBOL(pci_enable_wake
);
1990 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1991 * @dev: PCI device to prepare
1992 * @enable: True to enable wake-up event generation; false to disable
1994 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1995 * and this function allows them to set that up cleanly - pci_enable_wake()
1996 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1997 * ordering constraints.
1999 * This function only returns error code if the device is not allowed to wake
2000 * up the system from sleep or it is not capable of generating PME# from both
2001 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2003 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2005 return pci_pme_capable(dev
, PCI_D3cold
) ?
2006 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2007 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2009 EXPORT_SYMBOL(pci_wake_from_d3
);
2012 * pci_target_state - find an appropriate low power state for a given PCI dev
2014 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2016 * Use underlying platform code to find a supported low power state for @dev.
2017 * If the platform can't manage @dev, return the deepest state from which it
2018 * can generate wake events, based on any available PME info.
2020 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2022 pci_power_t target_state
= PCI_D3hot
;
2024 if (platform_pci_power_manageable(dev
)) {
2026 * Call the platform to choose the target state of the device
2027 * and enable wake-up from this state if supported.
2029 pci_power_t state
= platform_pci_choose_state(dev
);
2032 case PCI_POWER_ERROR
:
2037 if (pci_no_d1d2(dev
))
2040 target_state
= state
;
2043 return target_state
;
2047 target_state
= PCI_D0
;
2050 * If the device is in D3cold even though it's not power-manageable by
2051 * the platform, it may have been powered down by non-standard means.
2052 * Best to let it slumber.
2054 if (dev
->current_state
== PCI_D3cold
)
2055 target_state
= PCI_D3cold
;
2059 * Find the deepest state from which the device can generate
2060 * wake-up events, make it the target state and enable device
2063 if (dev
->pme_support
) {
2065 && !(dev
->pme_support
& (1 << target_state
)))
2070 return target_state
;
2074 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2075 * @dev: Device to handle.
2077 * Choose the power state appropriate for the device depending on whether
2078 * it can wake up the system and/or is power manageable by the platform
2079 * (PCI_D3hot is the default) and put the device into that state.
2081 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2083 bool wakeup
= device_may_wakeup(&dev
->dev
);
2084 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2087 if (target_state
== PCI_POWER_ERROR
)
2090 pci_enable_wake(dev
, target_state
, wakeup
);
2092 error
= pci_set_power_state(dev
, target_state
);
2095 pci_enable_wake(dev
, target_state
, false);
2099 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2102 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2103 * @dev: Device to handle.
2105 * Disable device's system wake-up capability and put it into D0.
2107 int pci_back_from_sleep(struct pci_dev
*dev
)
2109 pci_enable_wake(dev
, PCI_D0
, false);
2110 return pci_set_power_state(dev
, PCI_D0
);
2112 EXPORT_SYMBOL(pci_back_from_sleep
);
2115 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2116 * @dev: PCI device being suspended.
2118 * Prepare @dev to generate wake-up events at run time and put it into a low
2121 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2123 pci_power_t target_state
;
2126 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2127 if (target_state
== PCI_POWER_ERROR
)
2130 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2132 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2134 error
= pci_set_power_state(dev
, target_state
);
2137 pci_enable_wake(dev
, target_state
, false);
2138 dev
->runtime_d3cold
= false;
2145 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2146 * @dev: Device to check.
2148 * Return true if the device itself is capable of generating wake-up events
2149 * (through the platform or using the native PCIe PME) or if the device supports
2150 * PME and one of its upstream bridges can generate wake-up events.
2152 bool pci_dev_run_wake(struct pci_dev
*dev
)
2154 struct pci_bus
*bus
= dev
->bus
;
2156 if (!dev
->pme_support
)
2159 /* PME-capable in principle, but not from the target power state */
2160 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2163 if (device_can_wakeup(&dev
->dev
))
2166 while (bus
->parent
) {
2167 struct pci_dev
*bridge
= bus
->self
;
2169 if (device_can_wakeup(&bridge
->dev
))
2175 /* We have reached the root bus. */
2177 return device_can_wakeup(bus
->bridge
);
2181 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2184 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2185 * @pci_dev: Device to check.
2187 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2188 * reconfigured due to wakeup settings difference between system and runtime
2189 * suspend and the current power state of it is suitable for the upcoming
2190 * (system) transition.
2192 * If the device is not configured for system wakeup, disable PME for it before
2193 * returning 'true' to prevent it from waking up the system unnecessarily.
2195 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2197 struct device
*dev
= &pci_dev
->dev
;
2198 bool wakeup
= device_may_wakeup(dev
);
2200 if (!pm_runtime_suspended(dev
)
2201 || pci_target_state(pci_dev
, wakeup
) != pci_dev
->current_state
2202 || platform_pci_need_resume(pci_dev
))
2206 * At this point the device is good to go unless it's been configured
2207 * to generate PME at the runtime suspend time, but it is not supposed
2208 * to wake up the system. In that case, simply disable PME for it
2209 * (it will have to be re-enabled on exit from system resume).
2211 * If the device's power state is D3cold and the platform check above
2212 * hasn't triggered, the device's configuration is suitable and we don't
2213 * need to manipulate it at all.
2215 spin_lock_irq(&dev
->power
.lock
);
2217 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
&&
2219 __pci_pme_active(pci_dev
, false);
2221 spin_unlock_irq(&dev
->power
.lock
);
2226 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2227 * @pci_dev: Device to handle.
2229 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2230 * it might have been disabled during the prepare phase of system suspend if
2231 * the device was not configured for system wakeup.
2233 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2235 struct device
*dev
= &pci_dev
->dev
;
2237 if (!pci_dev_run_wake(pci_dev
))
2240 spin_lock_irq(&dev
->power
.lock
);
2242 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2243 __pci_pme_active(pci_dev
, true);
2245 spin_unlock_irq(&dev
->power
.lock
);
2248 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2250 struct device
*dev
= &pdev
->dev
;
2251 struct device
*parent
= dev
->parent
;
2254 pm_runtime_get_sync(parent
);
2255 pm_runtime_get_noresume(dev
);
2257 * pdev->current_state is set to PCI_D3cold during suspending,
2258 * so wait until suspending completes
2260 pm_runtime_barrier(dev
);
2262 * Only need to resume devices in D3cold, because config
2263 * registers are still accessible for devices suspended but
2266 if (pdev
->current_state
== PCI_D3cold
)
2267 pm_runtime_resume(dev
);
2270 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2272 struct device
*dev
= &pdev
->dev
;
2273 struct device
*parent
= dev
->parent
;
2275 pm_runtime_put(dev
);
2277 pm_runtime_put_sync(parent
);
2281 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2282 * @bridge: Bridge to check
2284 * This function checks if it is possible to move the bridge to D3.
2285 * Currently we only allow D3 for recent enough PCIe ports.
2287 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2291 if (!pci_is_pcie(bridge
))
2294 switch (pci_pcie_type(bridge
)) {
2295 case PCI_EXP_TYPE_ROOT_PORT
:
2296 case PCI_EXP_TYPE_UPSTREAM
:
2297 case PCI_EXP_TYPE_DOWNSTREAM
:
2298 if (pci_bridge_d3_disable
)
2302 * Hotplug interrupts cannot be delivered if the link is down,
2303 * so parents of a hotplug port must stay awake. In addition,
2304 * hotplug ports handled by firmware in System Management Mode
2305 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2306 * For simplicity, disallow in general for now.
2308 if (bridge
->is_hotplug_bridge
)
2311 if (pci_bridge_d3_force
)
2315 * It should be safe to put PCIe ports from 2015 or newer
2318 if (dmi_get_date(DMI_BIOS_DATE
, &year
, NULL
, NULL
) &&
2328 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2330 bool *d3cold_ok
= data
;
2332 if (/* The device needs to be allowed to go D3cold ... */
2333 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
2335 /* ... and if it is wakeup capable to do so from D3cold. */
2336 (device_may_wakeup(&dev
->dev
) &&
2337 !pci_pme_capable(dev
, PCI_D3cold
)) ||
2339 /* If it is a bridge it must be allowed to go to D3. */
2340 !pci_power_manageable(dev
))
2348 * pci_bridge_d3_update - Update bridge D3 capabilities
2349 * @dev: PCI device which is changed
2351 * Update upstream bridge PM capabilities accordingly depending on if the
2352 * device PM configuration was changed or the device is being removed. The
2353 * change is also propagated upstream.
2355 void pci_bridge_d3_update(struct pci_dev
*dev
)
2357 bool remove
= !device_is_registered(&dev
->dev
);
2358 struct pci_dev
*bridge
;
2359 bool d3cold_ok
= true;
2361 bridge
= pci_upstream_bridge(dev
);
2362 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
2366 * If D3 is currently allowed for the bridge, removing one of its
2367 * children won't change that.
2369 if (remove
&& bridge
->bridge_d3
)
2373 * If D3 is currently allowed for the bridge and a child is added or
2374 * changed, disallowance of D3 can only be caused by that child, so
2375 * we only need to check that single device, not any of its siblings.
2377 * If D3 is currently not allowed for the bridge, checking the device
2378 * first may allow us to skip checking its siblings.
2381 pci_dev_check_d3cold(dev
, &d3cold_ok
);
2384 * If D3 is currently not allowed for the bridge, this may be caused
2385 * either by the device being changed/removed or any of its siblings,
2386 * so we need to go through all children to find out if one of them
2387 * continues to block D3.
2389 if (d3cold_ok
&& !bridge
->bridge_d3
)
2390 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
2393 if (bridge
->bridge_d3
!= d3cold_ok
) {
2394 bridge
->bridge_d3
= d3cold_ok
;
2395 /* Propagate change to upstream bridges */
2396 pci_bridge_d3_update(bridge
);
2401 * pci_d3cold_enable - Enable D3cold for device
2402 * @dev: PCI device to handle
2404 * This function can be used in drivers to enable D3cold from the device
2405 * they handle. It also updates upstream PCI bridge PM capabilities
2408 void pci_d3cold_enable(struct pci_dev
*dev
)
2410 if (dev
->no_d3cold
) {
2411 dev
->no_d3cold
= false;
2412 pci_bridge_d3_update(dev
);
2415 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
2418 * pci_d3cold_disable - Disable D3cold for device
2419 * @dev: PCI device to handle
2421 * This function can be used in drivers to disable D3cold from the device
2422 * they handle. It also updates upstream PCI bridge PM capabilities
2425 void pci_d3cold_disable(struct pci_dev
*dev
)
2427 if (!dev
->no_d3cold
) {
2428 dev
->no_d3cold
= true;
2429 pci_bridge_d3_update(dev
);
2432 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
2435 * pci_pm_init - Initialize PM functions of given PCI device
2436 * @dev: PCI device to handle.
2438 void pci_pm_init(struct pci_dev
*dev
)
2443 pm_runtime_forbid(&dev
->dev
);
2444 pm_runtime_set_active(&dev
->dev
);
2445 pm_runtime_enable(&dev
->dev
);
2446 device_enable_async_suspend(&dev
->dev
);
2447 dev
->wakeup_prepared
= false;
2450 dev
->pme_support
= 0;
2452 /* find PCI PM capability in list */
2453 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2456 /* Check device's ability to generate PME# */
2457 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2459 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2460 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2461 pmc
& PCI_PM_CAP_VER_MASK
);
2466 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2467 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2468 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
2469 dev
->d3cold_allowed
= true;
2471 dev
->d1_support
= false;
2472 dev
->d2_support
= false;
2473 if (!pci_no_d1d2(dev
)) {
2474 if (pmc
& PCI_PM_CAP_D1
)
2475 dev
->d1_support
= true;
2476 if (pmc
& PCI_PM_CAP_D2
)
2477 dev
->d2_support
= true;
2479 if (dev
->d1_support
|| dev
->d2_support
)
2480 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2481 dev
->d1_support
? " D1" : "",
2482 dev
->d2_support
? " D2" : "");
2485 pmc
&= PCI_PM_CAP_PME_MASK
;
2487 dev_printk(KERN_DEBUG
, &dev
->dev
,
2488 "PME# supported from%s%s%s%s%s\n",
2489 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2490 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2491 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2492 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2493 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2494 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2495 dev
->pme_poll
= true;
2497 * Make device's PM flags reflect the wake-up capability, but
2498 * let the user space enable it to wake up the system as needed.
2500 device_set_wakeup_capable(&dev
->dev
, true);
2501 /* Disable the PME# generation functionality */
2502 pci_pme_active(dev
, false);
2506 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
2508 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
2512 case PCI_EA_P_VF_MEM
:
2513 flags
|= IORESOURCE_MEM
;
2515 case PCI_EA_P_MEM_PREFETCH
:
2516 case PCI_EA_P_VF_MEM_PREFETCH
:
2517 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
2520 flags
|= IORESOURCE_IO
;
2529 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
2532 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
2533 return &dev
->resource
[bei
];
2534 #ifdef CONFIG_PCI_IOV
2535 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
2536 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
2537 return &dev
->resource
[PCI_IOV_RESOURCES
+
2538 bei
- PCI_EA_BEI_VF_BAR0
];
2540 else if (bei
== PCI_EA_BEI_ROM
)
2541 return &dev
->resource
[PCI_ROM_RESOURCE
];
2546 /* Read an Enhanced Allocation (EA) entry */
2547 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
2549 struct resource
*res
;
2550 int ent_size
, ent_offset
= offset
;
2551 resource_size_t start
, end
;
2552 unsigned long flags
;
2553 u32 dw0
, bei
, base
, max_offset
;
2555 bool support_64
= (sizeof(resource_size_t
) >= 8);
2557 pci_read_config_dword(dev
, ent_offset
, &dw0
);
2560 /* Entry size field indicates DWORDs after 1st */
2561 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
2563 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
2566 bei
= (dw0
& PCI_EA_BEI
) >> 4;
2567 prop
= (dw0
& PCI_EA_PP
) >> 8;
2570 * If the Property is in the reserved range, try the Secondary
2573 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
2574 prop
= (dw0
& PCI_EA_SP
) >> 16;
2575 if (prop
> PCI_EA_P_BRIDGE_IO
)
2578 res
= pci_ea_get_resource(dev
, bei
, prop
);
2580 dev_err(&dev
->dev
, "Unsupported EA entry BEI: %u\n", bei
);
2584 flags
= pci_ea_flags(dev
, prop
);
2586 dev_err(&dev
->dev
, "Unsupported EA properties: %#x\n", prop
);
2591 pci_read_config_dword(dev
, ent_offset
, &base
);
2592 start
= (base
& PCI_EA_FIELD_MASK
);
2595 /* Read MaxOffset */
2596 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
2599 /* Read Base MSBs (if 64-bit entry) */
2600 if (base
& PCI_EA_IS_64
) {
2603 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
2606 flags
|= IORESOURCE_MEM_64
;
2608 /* entry starts above 32-bit boundary, can't use */
2609 if (!support_64
&& base_upper
)
2613 start
|= ((u64
)base_upper
<< 32);
2616 end
= start
+ (max_offset
| 0x03);
2618 /* Read MaxOffset MSBs (if 64-bit entry) */
2619 if (max_offset
& PCI_EA_IS_64
) {
2620 u32 max_offset_upper
;
2622 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
2625 flags
|= IORESOURCE_MEM_64
;
2627 /* entry too big, can't use */
2628 if (!support_64
&& max_offset_upper
)
2632 end
+= ((u64
)max_offset_upper
<< 32);
2636 dev_err(&dev
->dev
, "EA Entry crosses address boundary\n");
2640 if (ent_size
!= ent_offset
- offset
) {
2642 "EA Entry Size (%d) does not match length read (%d)\n",
2643 ent_size
, ent_offset
- offset
);
2647 res
->name
= pci_name(dev
);
2652 if (bei
<= PCI_EA_BEI_BAR5
)
2653 dev_printk(KERN_DEBUG
, &dev
->dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2655 else if (bei
== PCI_EA_BEI_ROM
)
2656 dev_printk(KERN_DEBUG
, &dev
->dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2658 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
2659 dev_printk(KERN_DEBUG
, &dev
->dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2660 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
2662 dev_printk(KERN_DEBUG
, &dev
->dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2666 return offset
+ ent_size
;
2669 /* Enhanced Allocation Initialization */
2670 void pci_ea_init(struct pci_dev
*dev
)
2677 /* find PCI EA capability in list */
2678 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
2682 /* determine the number of entries */
2683 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
2685 num_ent
&= PCI_EA_NUM_ENT_MASK
;
2687 offset
= ea
+ PCI_EA_FIRST_ENT
;
2689 /* Skip DWORD 2 for type 1 functions */
2690 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2693 /* parse each EA entry */
2694 for (i
= 0; i
< num_ent
; ++i
)
2695 offset
= pci_ea_read(dev
, offset
);
2698 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2699 struct pci_cap_saved_state
*new_cap
)
2701 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2705 * _pci_add_cap_save_buffer - allocate buffer for saving given
2706 * capability registers
2707 * @dev: the PCI device
2708 * @cap: the capability to allocate the buffer for
2709 * @extended: Standard or Extended capability ID
2710 * @size: requested size of the buffer
2712 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2713 bool extended
, unsigned int size
)
2716 struct pci_cap_saved_state
*save_state
;
2719 pos
= pci_find_ext_capability(dev
, cap
);
2721 pos
= pci_find_capability(dev
, cap
);
2726 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2730 save_state
->cap
.cap_nr
= cap
;
2731 save_state
->cap
.cap_extended
= extended
;
2732 save_state
->cap
.size
= size
;
2733 pci_add_saved_cap(dev
, save_state
);
2738 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2740 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2743 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2745 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2749 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2750 * @dev: the PCI device
2752 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2756 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2757 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2760 "unable to preallocate PCI Express save buffer\n");
2762 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2765 "unable to preallocate PCI-X save buffer\n");
2767 pci_allocate_vc_save_buffers(dev
);
2770 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2772 struct pci_cap_saved_state
*tmp
;
2773 struct hlist_node
*n
;
2775 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2780 * pci_configure_ari - enable or disable ARI forwarding
2781 * @dev: the PCI device
2783 * If @dev and its upstream bridge both support ARI, enable ARI in the
2784 * bridge. Otherwise, disable ARI in the bridge.
2786 void pci_configure_ari(struct pci_dev
*dev
)
2789 struct pci_dev
*bridge
;
2791 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2794 bridge
= dev
->bus
->self
;
2798 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2799 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2802 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2803 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2804 PCI_EXP_DEVCTL2_ARI
);
2805 bridge
->ari_enabled
= 1;
2807 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2808 PCI_EXP_DEVCTL2_ARI
);
2809 bridge
->ari_enabled
= 0;
2813 static int pci_acs_enable
;
2816 * pci_request_acs - ask for ACS to be enabled if supported
2818 void pci_request_acs(void)
2824 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2825 * @dev: the PCI device
2827 static void pci_std_enable_acs(struct pci_dev
*dev
)
2833 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2837 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2838 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2840 /* Source Validation */
2841 ctrl
|= (cap
& PCI_ACS_SV
);
2843 /* P2P Request Redirect */
2844 ctrl
|= (cap
& PCI_ACS_RR
);
2846 /* P2P Completion Redirect */
2847 ctrl
|= (cap
& PCI_ACS_CR
);
2849 /* Upstream Forwarding */
2850 ctrl
|= (cap
& PCI_ACS_UF
);
2852 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2856 * pci_enable_acs - enable ACS if hardware support it
2857 * @dev: the PCI device
2859 void pci_enable_acs(struct pci_dev
*dev
)
2861 if (!pci_acs_enable
)
2864 if (!pci_dev_specific_enable_acs(dev
))
2867 pci_std_enable_acs(dev
);
2870 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2875 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2880 * Except for egress control, capabilities are either required
2881 * or only required if controllable. Features missing from the
2882 * capability field can therefore be assumed as hard-wired enabled.
2884 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2885 acs_flags
&= (cap
| PCI_ACS_EC
);
2887 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2888 return (ctrl
& acs_flags
) == acs_flags
;
2892 * pci_acs_enabled - test ACS against required flags for a given device
2893 * @pdev: device to test
2894 * @acs_flags: required PCI ACS flags
2896 * Return true if the device supports the provided flags. Automatically
2897 * filters out flags that are not implemented on multifunction devices.
2899 * Note that this interface checks the effective ACS capabilities of the
2900 * device rather than the actual capabilities. For instance, most single
2901 * function endpoints are not required to support ACS because they have no
2902 * opportunity for peer-to-peer access. We therefore return 'true'
2903 * regardless of whether the device exposes an ACS capability. This makes
2904 * it much easier for callers of this function to ignore the actual type
2905 * or topology of the device when testing ACS support.
2907 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2911 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2916 * Conventional PCI and PCI-X devices never support ACS, either
2917 * effectively or actually. The shared bus topology implies that
2918 * any device on the bus can receive or snoop DMA.
2920 if (!pci_is_pcie(pdev
))
2923 switch (pci_pcie_type(pdev
)) {
2925 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2926 * but since their primary interface is PCI/X, we conservatively
2927 * handle them as we would a non-PCIe device.
2929 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2931 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2932 * applicable... must never implement an ACS Extended Capability...".
2933 * This seems arbitrary, but we take a conservative interpretation
2934 * of this statement.
2936 case PCI_EXP_TYPE_PCI_BRIDGE
:
2937 case PCI_EXP_TYPE_RC_EC
:
2940 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2941 * implement ACS in order to indicate their peer-to-peer capabilities,
2942 * regardless of whether they are single- or multi-function devices.
2944 case PCI_EXP_TYPE_DOWNSTREAM
:
2945 case PCI_EXP_TYPE_ROOT_PORT
:
2946 return pci_acs_flags_enabled(pdev
, acs_flags
);
2948 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2949 * implemented by the remaining PCIe types to indicate peer-to-peer
2950 * capabilities, but only when they are part of a multifunction
2951 * device. The footnote for section 6.12 indicates the specific
2952 * PCIe types included here.
2954 case PCI_EXP_TYPE_ENDPOINT
:
2955 case PCI_EXP_TYPE_UPSTREAM
:
2956 case PCI_EXP_TYPE_LEG_END
:
2957 case PCI_EXP_TYPE_RC_END
:
2958 if (!pdev
->multifunction
)
2961 return pci_acs_flags_enabled(pdev
, acs_flags
);
2965 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2966 * to single function devices with the exception of downstream ports.
2972 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2973 * @start: starting downstream device
2974 * @end: ending upstream device or NULL to search to the root bus
2975 * @acs_flags: required flags
2977 * Walk up a device tree from start to end testing PCI ACS support. If
2978 * any step along the way does not support the required flags, return false.
2980 bool pci_acs_path_enabled(struct pci_dev
*start
,
2981 struct pci_dev
*end
, u16 acs_flags
)
2983 struct pci_dev
*pdev
, *parent
= start
;
2988 if (!pci_acs_enabled(pdev
, acs_flags
))
2991 if (pci_is_root_bus(pdev
->bus
))
2992 return (end
== NULL
);
2994 parent
= pdev
->bus
->self
;
2995 } while (pdev
!= end
);
3001 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3005 * Helper to find the position of the ctrl register for a BAR.
3006 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3007 * Returns -ENOENT if no ctrl register for the BAR could be found.
3009 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3011 unsigned int pos
, nbars
, i
;
3014 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3018 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3019 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3020 PCI_REBAR_CTRL_NBAR_SHIFT
;
3022 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3025 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3026 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3035 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3037 * @bar: BAR to query
3039 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3040 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3042 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3047 pos
= pci_rebar_find_pos(pdev
, bar
);
3051 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3052 return (cap
& PCI_REBAR_CAP_SIZES
) >> 4;
3056 * pci_rebar_get_current_size - get the current size of a BAR
3058 * @bar: BAR to set size to
3060 * Read the size of a BAR from the resizable BAR config.
3061 * Returns size if found or negative error code.
3063 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3068 pos
= pci_rebar_find_pos(pdev
, bar
);
3072 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3073 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> 8;
3077 * pci_rebar_set_size - set a new size for a BAR
3079 * @bar: BAR to set size to
3080 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3082 * Set the new size of a BAR as defined in the spec.
3083 * Returns zero if resizing was successful, error code otherwise.
3085 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3090 pos
= pci_rebar_find_pos(pdev
, bar
);
3094 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3095 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3097 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3102 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3103 * @dev: the PCI device
3104 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3106 * Perform INTx swizzling for a device behind one level of bridge. This is
3107 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3108 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3109 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3110 * the PCI Express Base Specification, Revision 2.1)
3112 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3116 if (pci_ari_enabled(dev
->bus
))
3119 slot
= PCI_SLOT(dev
->devfn
);
3121 return (((pin
- 1) + slot
) % 4) + 1;
3124 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3132 while (!pci_is_root_bus(dev
->bus
)) {
3133 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3134 dev
= dev
->bus
->self
;
3141 * pci_common_swizzle - swizzle INTx all the way to root bridge
3142 * @dev: the PCI device
3143 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3145 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3146 * bridges all the way up to a PCI root bus.
3148 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3152 while (!pci_is_root_bus(dev
->bus
)) {
3153 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3154 dev
= dev
->bus
->self
;
3157 return PCI_SLOT(dev
->devfn
);
3159 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3162 * pci_release_region - Release a PCI bar
3163 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3164 * @bar: BAR to release
3166 * Releases the PCI I/O and memory resources previously reserved by a
3167 * successful call to pci_request_region. Call this function only
3168 * after all use of the PCI regions has ceased.
3170 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3172 struct pci_devres
*dr
;
3174 if (pci_resource_len(pdev
, bar
) == 0)
3176 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3177 release_region(pci_resource_start(pdev
, bar
),
3178 pci_resource_len(pdev
, bar
));
3179 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3180 release_mem_region(pci_resource_start(pdev
, bar
),
3181 pci_resource_len(pdev
, bar
));
3183 dr
= find_pci_dr(pdev
);
3185 dr
->region_mask
&= ~(1 << bar
);
3187 EXPORT_SYMBOL(pci_release_region
);
3190 * __pci_request_region - Reserved PCI I/O and memory resource
3191 * @pdev: PCI device whose resources are to be reserved
3192 * @bar: BAR to be reserved
3193 * @res_name: Name to be associated with resource.
3194 * @exclusive: whether the region access is exclusive or not
3196 * Mark the PCI region associated with PCI device @pdev BR @bar as
3197 * being reserved by owner @res_name. Do not access any
3198 * address inside the PCI regions unless this call returns
3201 * If @exclusive is set, then the region is marked so that userspace
3202 * is explicitly not allowed to map the resource via /dev/mem or
3203 * sysfs MMIO access.
3205 * Returns 0 on success, or %EBUSY on error. A warning
3206 * message is also printed on failure.
3208 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3209 const char *res_name
, int exclusive
)
3211 struct pci_devres
*dr
;
3213 if (pci_resource_len(pdev
, bar
) == 0)
3216 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3217 if (!request_region(pci_resource_start(pdev
, bar
),
3218 pci_resource_len(pdev
, bar
), res_name
))
3220 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3221 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3222 pci_resource_len(pdev
, bar
), res_name
,
3227 dr
= find_pci_dr(pdev
);
3229 dr
->region_mask
|= 1 << bar
;
3234 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
3235 &pdev
->resource
[bar
]);
3240 * pci_request_region - Reserve PCI I/O and memory resource
3241 * @pdev: PCI device whose resources are to be reserved
3242 * @bar: BAR to be reserved
3243 * @res_name: Name to be associated with resource
3245 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3246 * being reserved by owner @res_name. Do not access any
3247 * address inside the PCI regions unless this call returns
3250 * Returns 0 on success, or %EBUSY on error. A warning
3251 * message is also printed on failure.
3253 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3255 return __pci_request_region(pdev
, bar
, res_name
, 0);
3257 EXPORT_SYMBOL(pci_request_region
);
3260 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3261 * @pdev: PCI device whose resources are to be reserved
3262 * @bar: BAR to be reserved
3263 * @res_name: Name to be associated with resource.
3265 * Mark the PCI region associated with PCI device @pdev BR @bar as
3266 * being reserved by owner @res_name. Do not access any
3267 * address inside the PCI regions unless this call returns
3270 * Returns 0 on success, or %EBUSY on error. A warning
3271 * message is also printed on failure.
3273 * The key difference that _exclusive makes it that userspace is
3274 * explicitly not allowed to map the resource via /dev/mem or
3277 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
3278 const char *res_name
)
3280 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
3282 EXPORT_SYMBOL(pci_request_region_exclusive
);
3285 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3286 * @pdev: PCI device whose resources were previously reserved
3287 * @bars: Bitmask of BARs to be released
3289 * Release selected PCI I/O and memory resources previously reserved.
3290 * Call this function only after all use of the PCI regions has ceased.
3292 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
3296 for (i
= 0; i
< 6; i
++)
3297 if (bars
& (1 << i
))
3298 pci_release_region(pdev
, i
);
3300 EXPORT_SYMBOL(pci_release_selected_regions
);
3302 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3303 const char *res_name
, int excl
)
3307 for (i
= 0; i
< 6; i
++)
3308 if (bars
& (1 << i
))
3309 if (__pci_request_region(pdev
, i
, res_name
, excl
))
3315 if (bars
& (1 << i
))
3316 pci_release_region(pdev
, i
);
3323 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3324 * @pdev: PCI device whose resources are to be reserved
3325 * @bars: Bitmask of BARs to be requested
3326 * @res_name: Name to be associated with resource
3328 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3329 const char *res_name
)
3331 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
3333 EXPORT_SYMBOL(pci_request_selected_regions
);
3335 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
3336 const char *res_name
)
3338 return __pci_request_selected_regions(pdev
, bars
, res_name
,
3339 IORESOURCE_EXCLUSIVE
);
3341 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3344 * pci_release_regions - Release reserved PCI I/O and memory resources
3345 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3347 * Releases all PCI I/O and memory resources previously reserved by a
3348 * successful call to pci_request_regions. Call this function only
3349 * after all use of the PCI regions has ceased.
3352 void pci_release_regions(struct pci_dev
*pdev
)
3354 pci_release_selected_regions(pdev
, (1 << 6) - 1);
3356 EXPORT_SYMBOL(pci_release_regions
);
3359 * pci_request_regions - Reserved PCI I/O and memory resources
3360 * @pdev: PCI device whose resources are to be reserved
3361 * @res_name: Name to be associated with resource.
3363 * Mark all PCI regions associated with PCI device @pdev as
3364 * being reserved by owner @res_name. Do not access any
3365 * address inside the PCI regions unless this call returns
3368 * Returns 0 on success, or %EBUSY on error. A warning
3369 * message is also printed on failure.
3371 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
3373 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
3375 EXPORT_SYMBOL(pci_request_regions
);
3378 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3379 * @pdev: PCI device whose resources are to be reserved
3380 * @res_name: Name to be associated with resource.
3382 * Mark all PCI regions associated with PCI device @pdev as
3383 * being reserved by owner @res_name. Do not access any
3384 * address inside the PCI regions unless this call returns
3387 * pci_request_regions_exclusive() will mark the region so that
3388 * /dev/mem and the sysfs MMIO access will not be allowed.
3390 * Returns 0 on success, or %EBUSY on error. A warning
3391 * message is also printed on failure.
3393 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
3395 return pci_request_selected_regions_exclusive(pdev
,
3396 ((1 << 6) - 1), res_name
);
3398 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3401 * Record the PCI IO range (expressed as CPU physical address + size).
3402 * Return a negative value if an error has occured, zero otherwise
3404 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
3405 resource_size_t size
)
3409 struct logic_pio_hwaddr
*range
;
3411 if (!size
|| addr
+ size
< addr
)
3414 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
3418 range
->fwnode
= fwnode
;
3420 range
->hw_start
= addr
;
3421 range
->flags
= LOGIC_PIO_CPU_MMIO
;
3423 ret
= logic_pio_register_range(range
);
3431 phys_addr_t
pci_pio_to_address(unsigned long pio
)
3433 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
3436 if (pio
>= MMIO_UPPER_LIMIT
)
3439 address
= logic_pio_to_hwaddr(pio
);
3445 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
3448 return logic_pio_trans_cpuaddr(address
);
3450 if (address
> IO_SPACE_LIMIT
)
3451 return (unsigned long)-1;
3453 return (unsigned long) address
;
3458 * pci_remap_iospace - Remap the memory mapped I/O space
3459 * @res: Resource describing the I/O space
3460 * @phys_addr: physical address of range to be mapped
3462 * Remap the memory mapped I/O space described by the @res
3463 * and the CPU physical address @phys_addr into virtual address space.
3464 * Only architectures that have memory mapped IO functions defined
3465 * (and the PCI_IOBASE value defined) should call this function.
3467 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
3469 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3470 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3472 if (!(res
->flags
& IORESOURCE_IO
))
3475 if (res
->end
> IO_SPACE_LIMIT
)
3478 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
3479 pgprot_device(PAGE_KERNEL
));
3481 /* this architecture does not have memory mapped I/O space,
3482 so this function should never be called */
3483 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3487 EXPORT_SYMBOL(pci_remap_iospace
);
3490 * pci_unmap_iospace - Unmap the memory mapped I/O space
3491 * @res: resource to be unmapped
3493 * Unmap the CPU virtual address @res from virtual address space.
3494 * Only architectures that have memory mapped IO functions defined
3495 * (and the PCI_IOBASE value defined) should call this function.
3497 void pci_unmap_iospace(struct resource
*res
)
3499 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3500 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3502 unmap_kernel_range(vaddr
, resource_size(res
));
3505 EXPORT_SYMBOL(pci_unmap_iospace
);
3508 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3509 * @dev: Generic device to remap IO address for
3510 * @offset: Resource address to map
3511 * @size: Size of map
3513 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3516 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
3517 resource_size_t offset
,
3518 resource_size_t size
)
3520 void __iomem
**ptr
, *addr
;
3522 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
3526 addr
= pci_remap_cfgspace(offset
, size
);
3529 devres_add(dev
, ptr
);
3535 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
3538 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3539 * @dev: generic device to handle the resource for
3540 * @res: configuration space resource to be handled
3542 * Checks that a resource is a valid memory region, requests the memory
3543 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3544 * proper PCI configuration space memory attributes are guaranteed.
3546 * All operations are managed and will be undone on driver detach.
3548 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3549 * on failure. Usage example::
3551 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3552 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3554 * return PTR_ERR(base);
3556 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
3557 struct resource
*res
)
3559 resource_size_t size
;
3561 void __iomem
*dest_ptr
;
3565 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
3566 dev_err(dev
, "invalid resource\n");
3567 return IOMEM_ERR_PTR(-EINVAL
);
3570 size
= resource_size(res
);
3571 name
= res
->name
?: dev_name(dev
);
3573 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
3574 dev_err(dev
, "can't request region for resource %pR\n", res
);
3575 return IOMEM_ERR_PTR(-EBUSY
);
3578 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
3580 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
3581 devm_release_mem_region(dev
, res
->start
, size
);
3582 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
3587 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
3589 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
3593 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
3595 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
3597 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
3598 if (cmd
!= old_cmd
) {
3599 dev_dbg(&dev
->dev
, "%s bus mastering\n",
3600 enable
? "enabling" : "disabling");
3601 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3603 dev
->is_busmaster
= enable
;
3607 * pcibios_setup - process "pci=" kernel boot arguments
3608 * @str: string used to pass in "pci=" kernel boot arguments
3610 * Process kernel boot arguments. This is the default implementation.
3611 * Architecture specific implementations can override this as necessary.
3613 char * __weak __init
pcibios_setup(char *str
)
3619 * pcibios_set_master - enable PCI bus-mastering for device dev
3620 * @dev: the PCI device to enable
3622 * Enables PCI bus-mastering for the device. This is the default
3623 * implementation. Architecture specific implementations can override
3624 * this if necessary.
3626 void __weak
pcibios_set_master(struct pci_dev
*dev
)
3630 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3631 if (pci_is_pcie(dev
))
3634 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
3636 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
3637 else if (lat
> pcibios_max_latency
)
3638 lat
= pcibios_max_latency
;
3642 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
3646 * pci_set_master - enables bus-mastering for device dev
3647 * @dev: the PCI device to enable
3649 * Enables bus-mastering on the device and calls pcibios_set_master()
3650 * to do the needed arch specific settings.
3652 void pci_set_master(struct pci_dev
*dev
)
3654 __pci_set_master(dev
, true);
3655 pcibios_set_master(dev
);
3657 EXPORT_SYMBOL(pci_set_master
);
3660 * pci_clear_master - disables bus-mastering for device dev
3661 * @dev: the PCI device to disable
3663 void pci_clear_master(struct pci_dev
*dev
)
3665 __pci_set_master(dev
, false);
3667 EXPORT_SYMBOL(pci_clear_master
);
3670 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3671 * @dev: the PCI device for which MWI is to be enabled
3673 * Helper function for pci_set_mwi.
3674 * Originally copied from drivers/net/acenic.c.
3675 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3677 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3679 int pci_set_cacheline_size(struct pci_dev
*dev
)
3683 if (!pci_cache_line_size
)
3686 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3687 equal to or multiple of the right value. */
3688 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3689 if (cacheline_size
>= pci_cache_line_size
&&
3690 (cacheline_size
% pci_cache_line_size
) == 0)
3693 /* Write the correct value. */
3694 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
3696 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3697 if (cacheline_size
== pci_cache_line_size
)
3700 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
3701 pci_cache_line_size
<< 2);
3705 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
3708 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3709 * @dev: the PCI device for which MWI is enabled
3711 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3713 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3715 int pci_set_mwi(struct pci_dev
*dev
)
3717 #ifdef PCI_DISABLE_MWI
3723 rc
= pci_set_cacheline_size(dev
);
3727 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3728 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
3729 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
3730 cmd
|= PCI_COMMAND_INVALIDATE
;
3731 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3736 EXPORT_SYMBOL(pci_set_mwi
);
3739 * pcim_set_mwi - a device-managed pci_set_mwi()
3740 * @dev: the PCI device for which MWI is enabled
3742 * Managed pci_set_mwi().
3744 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3746 int pcim_set_mwi(struct pci_dev
*dev
)
3748 struct pci_devres
*dr
;
3750 dr
= find_pci_dr(dev
);
3755 return pci_set_mwi(dev
);
3757 EXPORT_SYMBOL(pcim_set_mwi
);
3760 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3761 * @dev: the PCI device for which MWI is enabled
3763 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3764 * Callers are not required to check the return value.
3766 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3768 int pci_try_set_mwi(struct pci_dev
*dev
)
3770 #ifdef PCI_DISABLE_MWI
3773 return pci_set_mwi(dev
);
3776 EXPORT_SYMBOL(pci_try_set_mwi
);
3779 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3780 * @dev: the PCI device to disable
3782 * Disables PCI Memory-Write-Invalidate transaction on the device
3784 void pci_clear_mwi(struct pci_dev
*dev
)
3786 #ifndef PCI_DISABLE_MWI
3789 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3790 if (cmd
& PCI_COMMAND_INVALIDATE
) {
3791 cmd
&= ~PCI_COMMAND_INVALIDATE
;
3792 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3796 EXPORT_SYMBOL(pci_clear_mwi
);
3799 * pci_intx - enables/disables PCI INTx for device dev
3800 * @pdev: the PCI device to operate on
3801 * @enable: boolean: whether to enable or disable PCI INTx
3803 * Enables/disables PCI INTx for device dev
3805 void pci_intx(struct pci_dev
*pdev
, int enable
)
3807 u16 pci_command
, new;
3809 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
3812 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
3814 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
3816 if (new != pci_command
) {
3817 struct pci_devres
*dr
;
3819 pci_write_config_word(pdev
, PCI_COMMAND
, new);
3821 dr
= find_pci_dr(pdev
);
3822 if (dr
&& !dr
->restore_intx
) {
3823 dr
->restore_intx
= 1;
3824 dr
->orig_intx
= !enable
;
3828 EXPORT_SYMBOL_GPL(pci_intx
);
3830 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3832 struct pci_bus
*bus
= dev
->bus
;
3833 bool mask_updated
= true;
3834 u32 cmd_status_dword
;
3835 u16 origcmd
, newcmd
;
3836 unsigned long flags
;
3840 * We do a single dword read to retrieve both command and status.
3841 * Document assumptions that make this possible.
3843 BUILD_BUG_ON(PCI_COMMAND
% 4);
3844 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3846 raw_spin_lock_irqsave(&pci_lock
, flags
);
3848 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3850 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3853 * Check interrupt status register to see whether our device
3854 * triggered the interrupt (when masking) or the next IRQ is
3855 * already pending (when unmasking).
3857 if (mask
!= irq_pending
) {
3858 mask_updated
= false;
3862 origcmd
= cmd_status_dword
;
3863 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3865 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3866 if (newcmd
!= origcmd
)
3867 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3870 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3872 return mask_updated
;
3876 * pci_check_and_mask_intx - mask INTx on pending interrupt
3877 * @dev: the PCI device to operate on
3879 * Check if the device dev has its INTx line asserted, mask it and
3880 * return true in that case. False is returned if no interrupt was
3883 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3885 return pci_check_and_set_intx_mask(dev
, true);
3887 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3890 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3891 * @dev: the PCI device to operate on
3893 * Check if the device dev has its INTx line asserted, unmask it if not
3894 * and return true. False is returned and the mask remains active if
3895 * there was still an interrupt pending.
3897 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3899 return pci_check_and_set_intx_mask(dev
, false);
3901 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3904 * pci_wait_for_pending_transaction - waits for pending transaction
3905 * @dev: the PCI device to operate on
3907 * Return 0 if transaction is pending 1 otherwise.
3909 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3911 if (!pci_is_pcie(dev
))
3914 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3915 PCI_EXP_DEVSTA_TRPND
);
3917 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3919 static void pci_flr_wait(struct pci_dev
*dev
)
3921 int delay
= 1, timeout
= 60000;
3925 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3926 * 100ms, but may silently discard requests while the FLR is in
3927 * progress. Wait 100ms before trying to access the device.
3932 * After 100ms, the device should not silently discard config
3933 * requests, but it may still indicate that it needs more time by
3934 * responding to them with CRS completions. The Root Port will
3935 * generally synthesize ~0 data to complete the read (except when
3936 * CRS SV is enabled and the read was for the Vendor ID; in that
3937 * case it synthesizes 0x0001 data).
3939 * Wait for the device to return a non-CRS completion. Read the
3940 * Command register instead of Vendor ID so we don't have to
3941 * contend with the CRS SV value.
3943 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3945 if (delay
> timeout
) {
3946 dev_warn(&dev
->dev
, "not ready %dms after FLR; giving up\n",
3952 dev_info(&dev
->dev
, "not ready %dms after FLR; waiting\n",
3957 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3961 dev_info(&dev
->dev
, "ready %dms after FLR\n", 100 + delay
- 1);
3965 * pcie_has_flr - check if a device supports function level resets
3966 * @dev: device to check
3968 * Returns true if the device advertises support for PCIe function level
3971 static bool pcie_has_flr(struct pci_dev
*dev
)
3975 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
3978 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3979 return cap
& PCI_EXP_DEVCAP_FLR
;
3983 * pcie_flr - initiate a PCIe function level reset
3984 * @dev: device to reset
3986 * Initiate a function level reset on @dev. The caller should ensure the
3987 * device supports FLR before calling this function, e.g. by using the
3988 * pcie_has_flr() helper.
3990 void pcie_flr(struct pci_dev
*dev
)
3992 if (!pci_wait_for_pending_transaction(dev
))
3993 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
3995 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3998 EXPORT_SYMBOL_GPL(pcie_flr
);
4000 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
4005 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4009 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4012 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4013 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4020 * Wait for Transaction Pending bit to clear. A word-aligned test
4021 * is used, so we use the conrol offset rather than status and shift
4022 * the test bit to match.
4024 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4025 PCI_AF_STATUS_TP
<< 8))
4026 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4028 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4034 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4035 * @dev: Device to reset.
4036 * @probe: If set, only check if the device can be reset this way.
4038 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4039 * unset, it will be reinitialized internally when going from PCI_D3hot to
4040 * PCI_D0. If that's the case and the device is not in a low-power state
4041 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4043 * NOTE: This causes the caller to sleep for twice the device power transition
4044 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4045 * by default (i.e. unless the @dev's d3_delay field has a different value).
4046 * Moreover, only devices in D0 can be reset by this function.
4048 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
4052 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4055 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4056 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4062 if (dev
->current_state
!= PCI_D0
)
4065 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4067 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4068 pci_dev_d3_sleep(dev
);
4070 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4072 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4073 pci_dev_d3_sleep(dev
);
4078 void pci_reset_secondary_bus(struct pci_dev
*dev
)
4082 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
4083 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
4084 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4086 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4087 * this to 2ms to ensure that we meet the minimum requirement.
4091 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
4092 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4095 * Trhfa for conventional PCI is 2^25 clock cycles.
4096 * Assuming a minimum 33MHz clock this results in a 1s
4097 * delay before we can consider subordinate devices to
4098 * be re-initialized. PCIe has some ways to shorten this,
4099 * but we don't make use of them yet.
4104 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
4106 pci_reset_secondary_bus(dev
);
4110 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4111 * @dev: Bridge device
4113 * Use the bridge control register to assert reset on the secondary bus.
4114 * Devices on the secondary bus are left in power-on state.
4116 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
4118 pcibios_reset_secondary_bus(dev
);
4120 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
4122 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
4124 struct pci_dev
*pdev
;
4126 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
4127 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4130 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4137 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
4142 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
4146 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
4149 if (hotplug
->ops
->reset_slot
)
4150 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
4152 module_put(hotplug
->ops
->owner
);
4157 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
4159 struct pci_dev
*pdev
;
4161 if (dev
->subordinate
|| !dev
->slot
||
4162 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4165 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4166 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
4169 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
4172 static void pci_dev_lock(struct pci_dev
*dev
)
4174 pci_cfg_access_lock(dev
);
4175 /* block PM suspend, driver probe, etc. */
4176 device_lock(&dev
->dev
);
4179 /* Return 1 on successful lock, 0 on contention */
4180 static int pci_dev_trylock(struct pci_dev
*dev
)
4182 if (pci_cfg_access_trylock(dev
)) {
4183 if (device_trylock(&dev
->dev
))
4185 pci_cfg_access_unlock(dev
);
4191 static void pci_dev_unlock(struct pci_dev
*dev
)
4193 device_unlock(&dev
->dev
);
4194 pci_cfg_access_unlock(dev
);
4197 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
4199 const struct pci_error_handlers
*err_handler
=
4200 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4203 * dev->driver->err_handler->reset_prepare() is protected against
4204 * races with ->remove() by the device lock, which must be held by
4207 if (err_handler
&& err_handler
->reset_prepare
)
4208 err_handler
->reset_prepare(dev
);
4211 * Wake-up device prior to save. PM registers default to D0 after
4212 * reset and a simple register restore doesn't reliably return
4213 * to a non-D0 state anyway.
4215 pci_set_power_state(dev
, PCI_D0
);
4217 pci_save_state(dev
);
4219 * Disable the device by clearing the Command register, except for
4220 * INTx-disable which is set. This not only disables MMIO and I/O port
4221 * BARs, but also prevents the device from being Bus Master, preventing
4222 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4223 * compliant devices, INTx-disable prevents legacy interrupts.
4225 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
4228 static void pci_dev_restore(struct pci_dev
*dev
)
4230 const struct pci_error_handlers
*err_handler
=
4231 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4233 pci_restore_state(dev
);
4236 * dev->driver->err_handler->reset_done() is protected against
4237 * races with ->remove() by the device lock, which must be held by
4240 if (err_handler
&& err_handler
->reset_done
)
4241 err_handler
->reset_done(dev
);
4245 * __pci_reset_function_locked - reset a PCI device function while holding
4246 * the @dev mutex lock.
4247 * @dev: PCI device to reset
4249 * Some devices allow an individual function to be reset without affecting
4250 * other functions in the same device. The PCI device must be responsive
4251 * to PCI config space in order to use this function.
4253 * The device function is presumed to be unused and the caller is holding
4254 * the device mutex lock when this function is called.
4255 * Resetting the device will make the contents of PCI configuration space
4256 * random, so any caller of this must be prepared to reinitialise the
4257 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4260 * Returns 0 if the device function was successfully reset or negative if the
4261 * device doesn't support resetting a single function.
4263 int __pci_reset_function_locked(struct pci_dev
*dev
)
4270 * A reset method returns -ENOTTY if it doesn't support this device
4271 * and we should try the next method.
4273 * If it returns 0 (success), we're finished. If it returns any
4274 * other error, we're also finished: this indicates that further
4275 * reset mechanisms might be broken on the device.
4277 rc
= pci_dev_specific_reset(dev
, 0);
4280 if (pcie_has_flr(dev
)) {
4284 rc
= pci_af_flr(dev
, 0);
4287 rc
= pci_pm_reset(dev
, 0);
4290 rc
= pci_dev_reset_slot_function(dev
, 0);
4293 return pci_parent_bus_reset(dev
, 0);
4295 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
4298 * pci_probe_reset_function - check whether the device can be safely reset
4299 * @dev: PCI device to reset
4301 * Some devices allow an individual function to be reset without affecting
4302 * other functions in the same device. The PCI device must be responsive
4303 * to PCI config space in order to use this function.
4305 * Returns 0 if the device function can be reset or negative if the
4306 * device doesn't support resetting a single function.
4308 int pci_probe_reset_function(struct pci_dev
*dev
)
4314 rc
= pci_dev_specific_reset(dev
, 1);
4317 if (pcie_has_flr(dev
))
4319 rc
= pci_af_flr(dev
, 1);
4322 rc
= pci_pm_reset(dev
, 1);
4325 rc
= pci_dev_reset_slot_function(dev
, 1);
4329 return pci_parent_bus_reset(dev
, 1);
4333 * pci_reset_function - quiesce and reset a PCI device function
4334 * @dev: PCI device to reset
4336 * Some devices allow an individual function to be reset without affecting
4337 * other functions in the same device. The PCI device must be responsive
4338 * to PCI config space in order to use this function.
4340 * This function does not just reset the PCI portion of a device, but
4341 * clears all the state associated with the device. This function differs
4342 * from __pci_reset_function_locked() in that it saves and restores device state
4343 * over the reset and takes the PCI device lock.
4345 * Returns 0 if the device function was successfully reset or negative if the
4346 * device doesn't support resetting a single function.
4348 int pci_reset_function(struct pci_dev
*dev
)
4352 rc
= pci_probe_reset_function(dev
);
4357 pci_dev_save_and_disable(dev
);
4359 rc
= __pci_reset_function_locked(dev
);
4361 pci_dev_restore(dev
);
4362 pci_dev_unlock(dev
);
4366 EXPORT_SYMBOL_GPL(pci_reset_function
);
4369 * pci_reset_function_locked - quiesce and reset a PCI device function
4370 * @dev: PCI device to reset
4372 * Some devices allow an individual function to be reset without affecting
4373 * other functions in the same device. The PCI device must be responsive
4374 * to PCI config space in order to use this function.
4376 * This function does not just reset the PCI portion of a device, but
4377 * clears all the state associated with the device. This function differs
4378 * from __pci_reset_function_locked() in that it saves and restores device state
4379 * over the reset. It also differs from pci_reset_function() in that it
4380 * requires the PCI device lock to be held.
4382 * Returns 0 if the device function was successfully reset or negative if the
4383 * device doesn't support resetting a single function.
4385 int pci_reset_function_locked(struct pci_dev
*dev
)
4389 rc
= pci_probe_reset_function(dev
);
4393 pci_dev_save_and_disable(dev
);
4395 rc
= __pci_reset_function_locked(dev
);
4397 pci_dev_restore(dev
);
4401 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
4404 * pci_try_reset_function - quiesce and reset a PCI device function
4405 * @dev: PCI device to reset
4407 * Same as above, except return -EAGAIN if unable to lock device.
4409 int pci_try_reset_function(struct pci_dev
*dev
)
4413 rc
= pci_probe_reset_function(dev
);
4417 if (!pci_dev_trylock(dev
))
4420 pci_dev_save_and_disable(dev
);
4421 rc
= __pci_reset_function_locked(dev
);
4422 pci_dev_unlock(dev
);
4424 pci_dev_restore(dev
);
4427 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
4429 /* Do any devices on or below this bus prevent a bus reset? */
4430 static bool pci_bus_resetable(struct pci_bus
*bus
)
4432 struct pci_dev
*dev
;
4435 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4438 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4439 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4440 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4447 /* Lock devices from the top of the tree down */
4448 static void pci_bus_lock(struct pci_bus
*bus
)
4450 struct pci_dev
*dev
;
4452 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4454 if (dev
->subordinate
)
4455 pci_bus_lock(dev
->subordinate
);
4459 /* Unlock devices from the bottom of the tree up */
4460 static void pci_bus_unlock(struct pci_bus
*bus
)
4462 struct pci_dev
*dev
;
4464 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4465 if (dev
->subordinate
)
4466 pci_bus_unlock(dev
->subordinate
);
4467 pci_dev_unlock(dev
);
4471 /* Return 1 on successful lock, 0 on contention */
4472 static int pci_bus_trylock(struct pci_bus
*bus
)
4474 struct pci_dev
*dev
;
4476 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4477 if (!pci_dev_trylock(dev
))
4479 if (dev
->subordinate
) {
4480 if (!pci_bus_trylock(dev
->subordinate
)) {
4481 pci_dev_unlock(dev
);
4489 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
4490 if (dev
->subordinate
)
4491 pci_bus_unlock(dev
->subordinate
);
4492 pci_dev_unlock(dev
);
4497 /* Do any devices on or below this slot prevent a bus reset? */
4498 static bool pci_slot_resetable(struct pci_slot
*slot
)
4500 struct pci_dev
*dev
;
4502 if (slot
->bus
->self
&&
4503 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4506 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4507 if (!dev
->slot
|| dev
->slot
!= slot
)
4509 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4510 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4517 /* Lock devices from the top of the tree down */
4518 static void pci_slot_lock(struct pci_slot
*slot
)
4520 struct pci_dev
*dev
;
4522 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4523 if (!dev
->slot
|| dev
->slot
!= slot
)
4526 if (dev
->subordinate
)
4527 pci_bus_lock(dev
->subordinate
);
4531 /* Unlock devices from the bottom of the tree up */
4532 static void pci_slot_unlock(struct pci_slot
*slot
)
4534 struct pci_dev
*dev
;
4536 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4537 if (!dev
->slot
|| dev
->slot
!= slot
)
4539 if (dev
->subordinate
)
4540 pci_bus_unlock(dev
->subordinate
);
4541 pci_dev_unlock(dev
);
4545 /* Return 1 on successful lock, 0 on contention */
4546 static int pci_slot_trylock(struct pci_slot
*slot
)
4548 struct pci_dev
*dev
;
4550 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4551 if (!dev
->slot
|| dev
->slot
!= slot
)
4553 if (!pci_dev_trylock(dev
))
4555 if (dev
->subordinate
) {
4556 if (!pci_bus_trylock(dev
->subordinate
)) {
4557 pci_dev_unlock(dev
);
4565 list_for_each_entry_continue_reverse(dev
,
4566 &slot
->bus
->devices
, bus_list
) {
4567 if (!dev
->slot
|| dev
->slot
!= slot
)
4569 if (dev
->subordinate
)
4570 pci_bus_unlock(dev
->subordinate
);
4571 pci_dev_unlock(dev
);
4576 /* Save and disable devices from the top of the tree down */
4577 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
4579 struct pci_dev
*dev
;
4581 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4583 pci_dev_save_and_disable(dev
);
4584 pci_dev_unlock(dev
);
4585 if (dev
->subordinate
)
4586 pci_bus_save_and_disable(dev
->subordinate
);
4591 * Restore devices from top of the tree down - parent bridges need to be
4592 * restored before we can get to subordinate devices.
4594 static void pci_bus_restore(struct pci_bus
*bus
)
4596 struct pci_dev
*dev
;
4598 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4600 pci_dev_restore(dev
);
4601 pci_dev_unlock(dev
);
4602 if (dev
->subordinate
)
4603 pci_bus_restore(dev
->subordinate
);
4607 /* Save and disable devices from the top of the tree down */
4608 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
4610 struct pci_dev
*dev
;
4612 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4613 if (!dev
->slot
|| dev
->slot
!= slot
)
4615 pci_dev_save_and_disable(dev
);
4616 if (dev
->subordinate
)
4617 pci_bus_save_and_disable(dev
->subordinate
);
4622 * Restore devices from top of the tree down - parent bridges need to be
4623 * restored before we can get to subordinate devices.
4625 static void pci_slot_restore(struct pci_slot
*slot
)
4627 struct pci_dev
*dev
;
4629 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4630 if (!dev
->slot
|| dev
->slot
!= slot
)
4632 pci_dev_restore(dev
);
4633 if (dev
->subordinate
)
4634 pci_bus_restore(dev
->subordinate
);
4638 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
4642 if (!slot
|| !pci_slot_resetable(slot
))
4646 pci_slot_lock(slot
);
4650 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
4653 pci_slot_unlock(slot
);
4659 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4660 * @slot: PCI slot to probe
4662 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4664 int pci_probe_reset_slot(struct pci_slot
*slot
)
4666 return pci_slot_reset(slot
, 1);
4668 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
4671 * pci_reset_slot - reset a PCI slot
4672 * @slot: PCI slot to reset
4674 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4675 * independent of other slots. For instance, some slots may support slot power
4676 * control. In the case of a 1:1 bus to slot architecture, this function may
4677 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4678 * Generally a slot reset should be attempted before a bus reset. All of the
4679 * function of the slot and any subordinate buses behind the slot are reset
4680 * through this function. PCI config space of all devices in the slot and
4681 * behind the slot is saved before and restored after reset.
4683 * Return 0 on success, non-zero on error.
4685 int pci_reset_slot(struct pci_slot
*slot
)
4689 rc
= pci_slot_reset(slot
, 1);
4693 pci_slot_save_and_disable(slot
);
4695 rc
= pci_slot_reset(slot
, 0);
4697 pci_slot_restore(slot
);
4701 EXPORT_SYMBOL_GPL(pci_reset_slot
);
4704 * pci_try_reset_slot - Try to reset a PCI slot
4705 * @slot: PCI slot to reset
4707 * Same as above except return -EAGAIN if the slot cannot be locked
4709 int pci_try_reset_slot(struct pci_slot
*slot
)
4713 rc
= pci_slot_reset(slot
, 1);
4717 pci_slot_save_and_disable(slot
);
4719 if (pci_slot_trylock(slot
)) {
4721 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
4722 pci_slot_unlock(slot
);
4726 pci_slot_restore(slot
);
4730 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
4732 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
4734 if (!bus
->self
|| !pci_bus_resetable(bus
))
4744 pci_reset_bridge_secondary_bus(bus
->self
);
4746 pci_bus_unlock(bus
);
4752 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4753 * @bus: PCI bus to probe
4755 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4757 int pci_probe_reset_bus(struct pci_bus
*bus
)
4759 return pci_bus_reset(bus
, 1);
4761 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
4764 * pci_reset_bus - reset a PCI bus
4765 * @bus: top level PCI bus to reset
4767 * Do a bus reset on the given bus and any subordinate buses, saving
4768 * and restoring state of all devices.
4770 * Return 0 on success, non-zero on error.
4772 int pci_reset_bus(struct pci_bus
*bus
)
4776 rc
= pci_bus_reset(bus
, 1);
4780 pci_bus_save_and_disable(bus
);
4782 rc
= pci_bus_reset(bus
, 0);
4784 pci_bus_restore(bus
);
4788 EXPORT_SYMBOL_GPL(pci_reset_bus
);
4791 * pci_try_reset_bus - Try to reset a PCI bus
4792 * @bus: top level PCI bus to reset
4794 * Same as above except return -EAGAIN if the bus cannot be locked
4796 int pci_try_reset_bus(struct pci_bus
*bus
)
4800 rc
= pci_bus_reset(bus
, 1);
4804 pci_bus_save_and_disable(bus
);
4806 if (pci_bus_trylock(bus
)) {
4808 pci_reset_bridge_secondary_bus(bus
->self
);
4809 pci_bus_unlock(bus
);
4813 pci_bus_restore(bus
);
4817 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
4820 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4821 * @dev: PCI device to query
4823 * Returns mmrbc: maximum designed memory read count in bytes
4824 * or appropriate error value.
4826 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
4831 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4835 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4838 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
4840 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
4843 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4844 * @dev: PCI device to query
4846 * Returns mmrbc: maximum memory read count in bytes
4847 * or appropriate error value.
4849 int pcix_get_mmrbc(struct pci_dev
*dev
)
4854 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4858 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4861 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
4863 EXPORT_SYMBOL(pcix_get_mmrbc
);
4866 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4867 * @dev: PCI device to query
4868 * @mmrbc: maximum memory read count in bytes
4869 * valid values are 512, 1024, 2048, 4096
4871 * If possible sets maximum memory read byte count, some bridges have erratas
4872 * that prevent this.
4874 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4880 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4883 v
= ffs(mmrbc
) - 10;
4885 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4889 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4892 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4895 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4898 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4900 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4903 cmd
&= ~PCI_X_CMD_MAX_READ
;
4905 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4910 EXPORT_SYMBOL(pcix_set_mmrbc
);
4913 * pcie_get_readrq - get PCI Express read request size
4914 * @dev: PCI device to query
4916 * Returns maximum memory read request in bytes
4917 * or appropriate error value.
4919 int pcie_get_readrq(struct pci_dev
*dev
)
4923 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4925 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4927 EXPORT_SYMBOL(pcie_get_readrq
);
4930 * pcie_set_readrq - set PCI Express maximum memory read request
4931 * @dev: PCI device to query
4932 * @rq: maximum memory read count in bytes
4933 * valid values are 128, 256, 512, 1024, 2048, 4096
4935 * If possible sets maximum memory read request in bytes
4937 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4941 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4945 * If using the "performance" PCIe config, we clamp the
4946 * read rq size to the max packet size to prevent the
4947 * host bridge generating requests larger than we can
4950 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4951 int mps
= pcie_get_mps(dev
);
4957 v
= (ffs(rq
) - 8) << 12;
4959 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4960 PCI_EXP_DEVCTL_READRQ
, v
);
4962 EXPORT_SYMBOL(pcie_set_readrq
);
4965 * pcie_get_mps - get PCI Express maximum payload size
4966 * @dev: PCI device to query
4968 * Returns maximum payload size in bytes
4970 int pcie_get_mps(struct pci_dev
*dev
)
4974 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4976 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
4978 EXPORT_SYMBOL(pcie_get_mps
);
4981 * pcie_set_mps - set PCI Express maximum payload size
4982 * @dev: PCI device to query
4983 * @mps: maximum payload size in bytes
4984 * valid values are 128, 256, 512, 1024, 2048, 4096
4986 * If possible sets maximum payload size
4988 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
4992 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
4996 if (v
> dev
->pcie_mpss
)
5000 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
5001 PCI_EXP_DEVCTL_PAYLOAD
, v
);
5003 EXPORT_SYMBOL(pcie_set_mps
);
5006 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5007 * @dev: PCI device to query
5008 * @speed: storage for minimum speed
5009 * @width: storage for minimum width
5011 * This function will walk up the PCI device chain and determine the minimum
5012 * link width and speed of the device.
5014 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
5015 enum pcie_link_width
*width
)
5019 *speed
= PCI_SPEED_UNKNOWN
;
5020 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
5024 enum pci_bus_speed next_speed
;
5025 enum pcie_link_width next_width
;
5027 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
5031 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
5032 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
5033 PCI_EXP_LNKSTA_NLW_SHIFT
;
5035 if (next_speed
< *speed
)
5036 *speed
= next_speed
;
5038 if (next_width
< *width
)
5039 *width
= next_width
;
5041 dev
= dev
->bus
->self
;
5046 EXPORT_SYMBOL(pcie_get_minimum_link
);
5049 * pci_select_bars - Make BAR mask from the type of resource
5050 * @dev: the PCI device for which BAR mask is made
5051 * @flags: resource type mask to be selected
5053 * This helper routine makes bar mask from the type of resource.
5055 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
5058 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
5059 if (pci_resource_flags(dev
, i
) & flags
)
5063 EXPORT_SYMBOL(pci_select_bars
);
5065 /* Some architectures require additional programming to enable VGA */
5066 static arch_set_vga_state_t arch_set_vga_state
;
5068 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
5070 arch_set_vga_state
= func
; /* NULL disables */
5073 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
5074 unsigned int command_bits
, u32 flags
)
5076 if (arch_set_vga_state
)
5077 return arch_set_vga_state(dev
, decode
, command_bits
,
5083 * pci_set_vga_state - set VGA decode state on device and parents if requested
5084 * @dev: the PCI device
5085 * @decode: true = enable decoding, false = disable decoding
5086 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5087 * @flags: traverse ancestors and change bridges
5088 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5090 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
5091 unsigned int command_bits
, u32 flags
)
5093 struct pci_bus
*bus
;
5094 struct pci_dev
*bridge
;
5098 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
5100 /* ARCH specific VGA enables */
5101 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
5105 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
5106 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
5108 cmd
|= command_bits
;
5110 cmd
&= ~command_bits
;
5111 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
5114 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
5121 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5124 cmd
|= PCI_BRIDGE_CTL_VGA
;
5126 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
5127 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5136 * pci_add_dma_alias - Add a DMA devfn alias for a device
5137 * @dev: the PCI device for which alias is added
5138 * @devfn: alias slot and function
5140 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5141 * It should be called early, preferably as PCI fixup header quirk.
5143 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
)
5145 if (!dev
->dma_alias_mask
)
5146 dev
->dma_alias_mask
= kcalloc(BITS_TO_LONGS(U8_MAX
),
5147 sizeof(long), GFP_KERNEL
);
5148 if (!dev
->dma_alias_mask
) {
5149 dev_warn(&dev
->dev
, "Unable to allocate DMA alias mask\n");
5153 set_bit(devfn
, dev
->dma_alias_mask
);
5154 dev_info(&dev
->dev
, "Enabling fixed DMA alias to %02x.%d\n",
5155 PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5158 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
5160 return (dev1
->dma_alias_mask
&&
5161 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
5162 (dev2
->dma_alias_mask
&&
5163 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
));
5166 bool pci_device_is_present(struct pci_dev
*pdev
)
5170 if (pci_dev_is_disconnected(pdev
))
5172 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
5174 EXPORT_SYMBOL_GPL(pci_device_is_present
);
5176 void pci_ignore_hotplug(struct pci_dev
*dev
)
5178 struct pci_dev
*bridge
= dev
->bus
->self
;
5180 dev
->ignore_hotplug
= 1;
5181 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5183 bridge
->ignore_hotplug
= 1;
5185 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
5187 resource_size_t __weak
pcibios_default_alignment(void)
5192 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5193 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
5194 static DEFINE_SPINLOCK(resource_alignment_lock
);
5197 * pci_specified_resource_alignment - get resource alignment specified by user.
5198 * @dev: the PCI device to get
5199 * @resize: whether or not to change resources' size when reassigning alignment
5201 * RETURNS: Resource alignment if it is specified.
5202 * Zero if it is not specified.
5204 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
5207 int seg
, bus
, slot
, func
, align_order
, count
;
5208 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
5209 resource_size_t align
= pcibios_default_alignment();
5212 spin_lock(&resource_alignment_lock
);
5213 p
= resource_alignment_param
;
5216 if (pci_has_flag(PCI_PROBE_ONLY
)) {
5218 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5224 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
5230 if (strncmp(p
, "pci:", 4) == 0) {
5231 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5233 if (sscanf(p
, "%hx:%hx:%hx:%hx%n",
5234 &vendor
, &device
, &subsystem_vendor
, &subsystem_device
, &count
) != 4) {
5235 if (sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
) != 2) {
5236 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: pci:%s\n",
5240 subsystem_vendor
= subsystem_device
= 0;
5243 if ((!vendor
|| (vendor
== dev
->vendor
)) &&
5244 (!device
|| (device
== dev
->device
)) &&
5245 (!subsystem_vendor
|| (subsystem_vendor
== dev
->subsystem_vendor
)) &&
5246 (!subsystem_device
|| (subsystem_device
== dev
->subsystem_device
))) {
5248 if (align_order
== -1)
5251 align
= 1 << align_order
;
5257 if (sscanf(p
, "%x:%x:%x.%x%n",
5258 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
5260 if (sscanf(p
, "%x:%x.%x%n",
5261 &bus
, &slot
, &func
, &count
) != 3) {
5262 /* Invalid format */
5263 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
5269 if (seg
== pci_domain_nr(dev
->bus
) &&
5270 bus
== dev
->bus
->number
&&
5271 slot
== PCI_SLOT(dev
->devfn
) &&
5272 func
== PCI_FUNC(dev
->devfn
)) {
5274 if (align_order
== -1)
5277 align
= 1 << align_order
;
5282 if (*p
!= ';' && *p
!= ',') {
5283 /* End of param or invalid format */
5289 spin_unlock(&resource_alignment_lock
);
5293 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
5294 resource_size_t align
, bool resize
)
5296 struct resource
*r
= &dev
->resource
[bar
];
5297 resource_size_t size
;
5299 if (!(r
->flags
& IORESOURCE_MEM
))
5302 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
5303 dev_info(&dev
->dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
5304 bar
, r
, (unsigned long long)align
);
5308 size
= resource_size(r
);
5313 * Increase the alignment of the resource. There are two ways we
5316 * 1) Increase the size of the resource. BARs are aligned on their
5317 * size, so when we reallocate space for this resource, we'll
5318 * allocate it with the larger alignment. This also prevents
5319 * assignment of any other BARs inside the alignment region, so
5320 * if we're requesting page alignment, this means no other BARs
5321 * will share the page.
5323 * The disadvantage is that this makes the resource larger than
5324 * the hardware BAR, which may break drivers that compute things
5325 * based on the resource size, e.g., to find registers at a
5326 * fixed offset before the end of the BAR.
5328 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5329 * set r->start to the desired alignment. By itself this
5330 * doesn't prevent other BARs being put inside the alignment
5331 * region, but if we realign *every* resource of every device in
5332 * the system, none of them will share an alignment region.
5334 * When the user has requested alignment for only some devices via
5335 * the "pci=resource_alignment" argument, "resize" is true and we
5336 * use the first method. Otherwise we assume we're aligning all
5337 * devices and we use the second.
5340 dev_info(&dev
->dev
, "BAR%d %pR: requesting alignment to %#llx\n",
5341 bar
, r
, (unsigned long long)align
);
5347 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
5348 r
->flags
|= IORESOURCE_STARTALIGN
;
5350 r
->end
= r
->start
+ size
- 1;
5352 r
->flags
|= IORESOURCE_UNSET
;
5356 * This function disables memory decoding and releases memory resources
5357 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5358 * It also rounds up size to specified alignment.
5359 * Later on, the kernel will assign page-aligned memory resource back
5362 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
5366 resource_size_t align
;
5368 bool resize
= false;
5371 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5372 * 3.4.1.11. Their resources are allocated from the space
5373 * described by the VF BARx register in the PF's SR-IOV capability.
5374 * We can't influence their alignment here.
5379 /* check if specified PCI is target device to reassign */
5380 align
= pci_specified_resource_alignment(dev
, &resize
);
5384 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
5385 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
5387 "Can't reassign resources to host bridge.\n");
5392 "Disabling memory decoding and releasing memory resources.\n");
5393 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
5394 command
&= ~PCI_COMMAND_MEMORY
;
5395 pci_write_config_word(dev
, PCI_COMMAND
, command
);
5397 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
5398 pci_request_resource_alignment(dev
, i
, align
, resize
);
5401 * Need to disable bridge's resource window,
5402 * to enable the kernel to reassign new resource
5405 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
5406 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
5407 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
5408 r
= &dev
->resource
[i
];
5409 if (!(r
->flags
& IORESOURCE_MEM
))
5411 r
->flags
|= IORESOURCE_UNSET
;
5412 r
->end
= resource_size(r
) - 1;
5415 pci_disable_bridge_window(dev
);
5419 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
5421 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
5422 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
5423 spin_lock(&resource_alignment_lock
);
5424 strncpy(resource_alignment_param
, buf
, count
);
5425 resource_alignment_param
[count
] = '\0';
5426 spin_unlock(&resource_alignment_lock
);
5430 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
5433 spin_lock(&resource_alignment_lock
);
5434 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
5435 spin_unlock(&resource_alignment_lock
);
5439 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
5441 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
5444 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
5445 const char *buf
, size_t count
)
5447 return pci_set_resource_alignment_param(buf
, count
);
5450 static BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
5451 pci_resource_alignment_store
);
5453 static int __init
pci_resource_alignment_sysfs_init(void)
5455 return bus_create_file(&pci_bus_type
,
5456 &bus_attr_resource_alignment
);
5458 late_initcall(pci_resource_alignment_sysfs_init
);
5460 static void pci_no_domains(void)
5462 #ifdef CONFIG_PCI_DOMAINS
5463 pci_domains_supported
= 0;
5467 #ifdef CONFIG_PCI_DOMAINS
5468 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
5470 int pci_get_new_domain_nr(void)
5472 return atomic_inc_return(&__domain_nr
);
5475 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5476 static int of_pci_bus_find_domain_nr(struct device
*parent
)
5478 static int use_dt_domains
= -1;
5482 domain
= of_get_pci_domain_nr(parent
->of_node
);
5484 * Check DT domain and use_dt_domains values.
5486 * If DT domain property is valid (domain >= 0) and
5487 * use_dt_domains != 0, the DT assignment is valid since this means
5488 * we have not previously allocated a domain number by using
5489 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5490 * 1, to indicate that we have just assigned a domain number from
5493 * If DT domain property value is not valid (ie domain < 0), and we
5494 * have not previously assigned a domain number from DT
5495 * (use_dt_domains != 1) we should assign a domain number by
5498 * pci_get_new_domain_nr()
5500 * API and update the use_dt_domains value to keep track of method we
5501 * are using to assign domain numbers (use_dt_domains = 0).
5503 * All other combinations imply we have a platform that is trying
5504 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5505 * which is a recipe for domain mishandling and it is prevented by
5506 * invalidating the domain value (domain = -1) and printing a
5507 * corresponding error.
5509 if (domain
>= 0 && use_dt_domains
) {
5511 } else if (domain
< 0 && use_dt_domains
!= 1) {
5513 domain
= pci_get_new_domain_nr();
5515 dev_err(parent
, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5523 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
5525 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
5526 acpi_pci_bus_find_domain_nr(bus
);
5532 * pci_ext_cfg_avail - can we access extended PCI config space?
5534 * Returns 1 if we can access PCI extended config space (offsets
5535 * greater than 0xff). This is the default implementation. Architecture
5536 * implementations can override this.
5538 int __weak
pci_ext_cfg_avail(void)
5543 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
5546 EXPORT_SYMBOL(pci_fixup_cardbus
);
5548 static int __init
pci_setup(char *str
)
5551 char *k
= strchr(str
, ',');
5554 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
5555 if (!strcmp(str
, "nomsi")) {
5557 } else if (!strcmp(str
, "noaer")) {
5559 } else if (!strncmp(str
, "realloc=", 8)) {
5560 pci_realloc_get_opt(str
+ 8);
5561 } else if (!strncmp(str
, "realloc", 7)) {
5562 pci_realloc_get_opt("on");
5563 } else if (!strcmp(str
, "nodomains")) {
5565 } else if (!strncmp(str
, "noari", 5)) {
5566 pcie_ari_disabled
= true;
5567 } else if (!strncmp(str
, "cbiosize=", 9)) {
5568 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
5569 } else if (!strncmp(str
, "cbmemsize=", 10)) {
5570 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
5571 } else if (!strncmp(str
, "resource_alignment=", 19)) {
5572 pci_set_resource_alignment_param(str
+ 19,
5574 } else if (!strncmp(str
, "ecrc=", 5)) {
5575 pcie_ecrc_get_policy(str
+ 5);
5576 } else if (!strncmp(str
, "hpiosize=", 9)) {
5577 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
5578 } else if (!strncmp(str
, "hpmemsize=", 10)) {
5579 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
5580 } else if (!strncmp(str
, "hpbussize=", 10)) {
5581 pci_hotplug_bus_size
=
5582 simple_strtoul(str
+ 10, &str
, 0);
5583 if (pci_hotplug_bus_size
> 0xff)
5584 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
5585 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
5586 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
5587 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
5588 pcie_bus_config
= PCIE_BUS_SAFE
;
5589 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
5590 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
5591 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
5592 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
5593 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
5594 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
5596 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
5604 early_param("pci", pci_setup
);