1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex
);
39 const char *pci_power_names
[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names
);
44 int isa_dma_bridge_buggy
;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
48 EXPORT_SYMBOL(pci_pci_problems
);
50 unsigned int pci_pm_d3hot_delay
;
52 static void pci_pme_list_scan(struct work_struct
*work
);
54 static LIST_HEAD(pci_pme_list
);
55 static DEFINE_MUTEX(pci_pme_list_mutex
);
56 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
58 struct pci_pme_device
{
59 struct list_head list
;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
67 unsigned int delay
= dev
->d3hot_delay
;
69 if (delay
< pci_pm_d3hot_delay
)
70 delay
= pci_pm_d3hot_delay
;
76 bool pci_reset_supported(struct pci_dev
*dev
)
78 return dev
->reset_methods
[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported
= 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
89 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size
= DEFAULT_HOTPLUG_MMIO_SIZE
;
102 unsigned long pci_hotplug_mmio_pref_size
= DEFAULT_HOTPLUG_MMIO_PREF_SIZE
;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_SAFE
;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PEER2PEER
;
118 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
128 u8 pci_cache_line_size
;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency
= 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled
;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled
;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled
;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled
);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable
;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force
;
156 static int __init
pcie_port_pm_setup(char *str
)
158 if (!strcmp(str
, "off"))
159 pci_bridge_d3_disable
= true;
160 else if (!strcmp(str
, "force"))
161 pci_bridge_d3_force
= true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup
);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
169 static const struct dmi_system_id aspm_fix_whitelist
[] = {
171 .ident
= "LENOVO Stealth Thinkstation",
173 DMI_MATCH(DMI_BIOS_VERSION
, "S07K"),
177 .ident
= "Dell Inc. Precision 7960 Tower",
179 DMI_MATCH(DMI_SYS_VENDOR
, "Dell Inc."),
180 DMI_MATCH(DMI_PRODUCT_NAME
, "Precision 7960 Tower"),
187 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
188 * @bus: pointer to PCI bus structure to search
190 * Given a PCI bus, returns the highest PCI bus number present in the set
191 * including the given PCI bus and its list of child PCI buses.
193 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
196 unsigned char max
, n
;
198 max
= bus
->busn_res
.end
;
199 list_for_each_entry(tmp
, &bus
->children
, node
) {
200 n
= pci_bus_max_busnr(tmp
);
206 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
209 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
210 * @pdev: the PCI device
212 * Returns error bits set in PCI_STATUS and clears them.
214 int pci_status_get_and_clear_errors(struct pci_dev
*pdev
)
219 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
220 if (ret
!= PCIBIOS_SUCCESSFUL
)
223 status
&= PCI_STATUS_ERROR_BITS
;
225 pci_write_config_word(pdev
, PCI_STATUS
, status
);
229 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors
);
231 #ifdef CONFIG_HAS_IOMEM
232 static void __iomem
*__pci_ioremap_resource(struct pci_dev
*pdev
, int bar
,
235 struct resource
*res
= &pdev
->resource
[bar
];
236 resource_size_t start
= res
->start
;
237 resource_size_t size
= resource_size(res
);
240 * Make sure the BAR is actually a memory resource, not an IO resource
242 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
243 pci_err(pdev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
248 return ioremap_wc(start
, size
);
250 return ioremap(start
, size
);
253 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
255 return __pci_ioremap_resource(pdev
, bar
, false);
257 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
259 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
261 return __pci_ioremap_resource(pdev
, bar
, true);
263 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
267 * pci_dev_str_match_path - test if a path string matches a device
268 * @dev: the PCI device to test
269 * @path: string to match the device against
270 * @endptr: pointer to the string after the match
272 * Test if a string (typically from a kernel parameter) formatted as a
273 * path of device/function addresses matches a PCI device. The string must
276 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
278 * A path for a device can be obtained using 'lspci -t'. Using a path
279 * is more robust against bus renumbering than using only a single bus,
280 * device and function address.
282 * Returns 1 if the string matches the device, 0 if it does not and
283 * a negative error code if it fails to parse the string.
285 static int pci_dev_str_match_path(struct pci_dev
*dev
, const char *path
,
289 int seg
, bus
, slot
, func
;
293 *endptr
= strchrnul(path
, ';');
295 wpath
= kmemdup_nul(path
, *endptr
- path
, GFP_ATOMIC
);
300 p
= strrchr(wpath
, '/');
303 ret
= sscanf(p
, "/%x.%x%c", &slot
, &func
, &end
);
309 if (dev
->devfn
!= PCI_DEVFN(slot
, func
)) {
315 * Note: we don't need to get a reference to the upstream
316 * bridge because we hold a reference to the top level
317 * device which should hold a reference to the bridge,
320 dev
= pci_upstream_bridge(dev
);
329 ret
= sscanf(wpath
, "%x:%x:%x.%x%c", &seg
, &bus
, &slot
,
333 ret
= sscanf(wpath
, "%x:%x.%x%c", &bus
, &slot
, &func
, &end
);
340 ret
= (seg
== pci_domain_nr(dev
->bus
) &&
341 bus
== dev
->bus
->number
&&
342 dev
->devfn
== PCI_DEVFN(slot
, func
));
350 * pci_dev_str_match - test if a string matches a device
351 * @dev: the PCI device to test
352 * @p: string to match the device against
353 * @endptr: pointer to the string after the match
355 * Test if a string (typically from a kernel parameter) matches a specified
356 * PCI device. The string may be of one of the following formats:
358 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
359 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
361 * The first format specifies a PCI bus/device/function address which
362 * may change if new hardware is inserted, if motherboard firmware changes,
363 * or due to changes caused in kernel parameters. If the domain is
364 * left unspecified, it is taken to be 0. In order to be robust against
365 * bus renumbering issues, a path of PCI device/function numbers may be used
366 * to address the specific device. The path for a device can be determined
367 * through the use of 'lspci -t'.
369 * The second format matches devices using IDs in the configuration
370 * space which may match multiple devices in the system. A value of 0
371 * for any field will match all devices. (Note: this differs from
372 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
373 * legacy reasons and convenience so users don't have to specify
374 * FFFFFFFFs on the command line.)
376 * Returns 1 if the string matches the device, 0 if it does not and
377 * a negative error code if the string cannot be parsed.
379 static int pci_dev_str_match(struct pci_dev
*dev
, const char *p
,
384 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
386 if (strncmp(p
, "pci:", 4) == 0) {
387 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
389 ret
= sscanf(p
, "%hx:%hx:%hx:%hx%n", &vendor
, &device
,
390 &subsystem_vendor
, &subsystem_device
, &count
);
392 ret
= sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
);
396 subsystem_vendor
= 0;
397 subsystem_device
= 0;
402 if ((!vendor
|| vendor
== dev
->vendor
) &&
403 (!device
|| device
== dev
->device
) &&
404 (!subsystem_vendor
||
405 subsystem_vendor
== dev
->subsystem_vendor
) &&
406 (!subsystem_device
||
407 subsystem_device
== dev
->subsystem_device
))
411 * PCI Bus, Device, Function IDs are specified
412 * (optionally, may include a path of devfns following it)
414 ret
= pci_dev_str_match_path(dev
, p
, &p
);
429 static u8
__pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
430 u8 pos
, int cap
, int *ttl
)
435 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
441 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
453 static u8
__pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
456 int ttl
= PCI_FIND_CAP_TTL
;
458 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
461 u8
pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
463 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
464 pos
+ PCI_CAP_LIST_NEXT
, cap
);
466 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
468 static u8
__pci_bus_find_cap_start(struct pci_bus
*bus
,
469 unsigned int devfn
, u8 hdr_type
)
473 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
474 if (!(status
& PCI_STATUS_CAP_LIST
))
478 case PCI_HEADER_TYPE_NORMAL
:
479 case PCI_HEADER_TYPE_BRIDGE
:
480 return PCI_CAPABILITY_LIST
;
481 case PCI_HEADER_TYPE_CARDBUS
:
482 return PCI_CB_CAPABILITY_LIST
;
489 * pci_find_capability - query for devices' capabilities
490 * @dev: PCI device to query
491 * @cap: capability code
493 * Tell if a device supports a given PCI capability.
494 * Returns the address of the requested capability structure within the
495 * device's PCI configuration space or 0 in case the device does not
496 * support it. Possible values for @cap include:
498 * %PCI_CAP_ID_PM Power Management
499 * %PCI_CAP_ID_AGP Accelerated Graphics Port
500 * %PCI_CAP_ID_VPD Vital Product Data
501 * %PCI_CAP_ID_SLOTID Slot Identification
502 * %PCI_CAP_ID_MSI Message Signalled Interrupts
503 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
504 * %PCI_CAP_ID_PCIX PCI-X
505 * %PCI_CAP_ID_EXP PCI Express
507 u8
pci_find_capability(struct pci_dev
*dev
, int cap
)
511 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
513 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
517 EXPORT_SYMBOL(pci_find_capability
);
520 * pci_bus_find_capability - query for devices' capabilities
521 * @bus: the PCI bus to query
522 * @devfn: PCI device to query
523 * @cap: capability code
525 * Like pci_find_capability() but works for PCI devices that do not have a
526 * pci_dev structure set up yet.
528 * Returns the address of the requested capability structure within the
529 * device's PCI configuration space or 0 in case the device does not
532 u8
pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
536 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
538 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
540 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
544 EXPORT_SYMBOL(pci_bus_find_capability
);
547 * pci_find_next_ext_capability - Find an extended capability
548 * @dev: PCI device to query
549 * @start: address at which to start looking (0 to start at beginning of list)
550 * @cap: capability code
552 * Returns the address of the next matching extended capability structure
553 * within the device's PCI configuration space or 0 if the device does
554 * not support it. Some capabilities can occur several times, e.g., the
555 * vendor-specific capability, and this provides a way to find them all.
557 u16
pci_find_next_ext_capability(struct pci_dev
*dev
, u16 start
, int cap
)
561 u16 pos
= PCI_CFG_SPACE_SIZE
;
563 /* minimum 8 bytes per capability */
564 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
566 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
572 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
576 * If we have no capabilities, this is indicated by cap ID,
577 * cap version and next pointer all being 0.
583 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
586 pos
= PCI_EXT_CAP_NEXT(header
);
587 if (pos
< PCI_CFG_SPACE_SIZE
)
590 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
596 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
599 * pci_find_ext_capability - Find an extended capability
600 * @dev: PCI device to query
601 * @cap: capability code
603 * Returns the address of the requested extended capability structure
604 * within the device's PCI configuration space or 0 if the device does
605 * not support it. Possible values for @cap include:
607 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
608 * %PCI_EXT_CAP_ID_VC Virtual Channel
609 * %PCI_EXT_CAP_ID_DSN Device Serial Number
610 * %PCI_EXT_CAP_ID_PWR Power Budgeting
612 u16
pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
614 return pci_find_next_ext_capability(dev
, 0, cap
);
616 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
619 * pci_get_dsn - Read and return the 8-byte Device Serial Number
620 * @dev: PCI device to query
622 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
625 * Returns the DSN, or zero if the capability does not exist.
627 u64
pci_get_dsn(struct pci_dev
*dev
)
633 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_DSN
);
638 * The Device Serial Number is two dwords offset 4 bytes from the
639 * capability position. The specification says that the first dword is
640 * the lower half, and the second dword is the upper half.
643 pci_read_config_dword(dev
, pos
, &dword
);
645 pci_read_config_dword(dev
, pos
+ 4, &dword
);
646 dsn
|= ((u64
)dword
) << 32;
650 EXPORT_SYMBOL_GPL(pci_get_dsn
);
652 static u8
__pci_find_next_ht_cap(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
654 int rc
, ttl
= PCI_FIND_CAP_TTL
;
657 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
658 mask
= HT_3BIT_CAP_MASK
;
660 mask
= HT_5BIT_CAP_MASK
;
662 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
663 PCI_CAP_ID_HT
, &ttl
);
665 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
666 if (rc
!= PCIBIOS_SUCCESSFUL
)
669 if ((cap
& mask
) == ht_cap
)
672 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
673 pos
+ PCI_CAP_LIST_NEXT
,
674 PCI_CAP_ID_HT
, &ttl
);
681 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
682 * @dev: PCI device to query
683 * @pos: Position from which to continue searching
684 * @ht_cap: HyperTransport capability code
686 * To be used in conjunction with pci_find_ht_capability() to search for
687 * all capabilities matching @ht_cap. @pos should always be a value returned
688 * from pci_find_ht_capability().
690 * NB. To be 100% safe against broken PCI devices, the caller should take
691 * steps to avoid an infinite loop.
693 u8
pci_find_next_ht_capability(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
695 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
697 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
700 * pci_find_ht_capability - query a device's HyperTransport capabilities
701 * @dev: PCI device to query
702 * @ht_cap: HyperTransport capability code
704 * Tell if a device supports a given HyperTransport capability.
705 * Returns an address within the device's PCI configuration space
706 * or 0 in case the device does not support the request capability.
707 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
708 * which has a HyperTransport capability matching @ht_cap.
710 u8
pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
714 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
716 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
720 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
723 * pci_find_vsec_capability - Find a vendor-specific extended capability
724 * @dev: PCI device to query
725 * @vendor: Vendor ID for which capability is defined
726 * @cap: Vendor-specific capability ID
728 * If @dev has Vendor ID @vendor, search for a VSEC capability with
729 * VSEC ID @cap. If found, return the capability offset in
730 * config space; otherwise return 0.
732 u16
pci_find_vsec_capability(struct pci_dev
*dev
, u16 vendor
, int cap
)
737 if (vendor
!= dev
->vendor
)
740 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
741 PCI_EXT_CAP_ID_VNDR
))) {
742 if (pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
,
743 &header
) == PCIBIOS_SUCCESSFUL
&&
744 PCI_VNDR_HEADER_ID(header
) == cap
)
750 EXPORT_SYMBOL_GPL(pci_find_vsec_capability
);
753 * pci_find_parent_resource - return resource region of parent bus of given
755 * @dev: PCI device structure contains resources to be searched
756 * @res: child resource record for which parent is sought
758 * For given resource region of given device, return the resource region of
759 * parent bus the given region is contained in.
761 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
762 struct resource
*res
)
764 const struct pci_bus
*bus
= dev
->bus
;
768 pci_bus_for_each_resource(bus
, r
, i
) {
771 if (resource_contains(r
, res
)) {
774 * If the window is prefetchable but the BAR is
775 * not, the allocator made a mistake.
777 if (r
->flags
& IORESOURCE_PREFETCH
&&
778 !(res
->flags
& IORESOURCE_PREFETCH
))
782 * If we're below a transparent bridge, there may
783 * be both a positively-decoded aperture and a
784 * subtractively-decoded region that contain the BAR.
785 * We want the positively-decoded one, so this depends
786 * on pci_bus_for_each_resource() giving us those
794 EXPORT_SYMBOL(pci_find_parent_resource
);
797 * pci_find_resource - Return matching PCI device resource
798 * @dev: PCI device to query
799 * @res: Resource to look for
801 * Goes over standard PCI resources (BARs) and checks if the given resource
802 * is partially or fully contained in any of them. In that case the
803 * matching resource is returned, %NULL otherwise.
805 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
809 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
810 struct resource
*r
= &dev
->resource
[i
];
812 if (r
->start
&& resource_contains(r
, res
))
818 EXPORT_SYMBOL(pci_find_resource
);
821 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
822 * @dev: the PCI device to operate on
823 * @pos: config space offset of status word
824 * @mask: mask of bit(s) to care about in status word
826 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
828 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
832 /* Wait for Transaction Pending bit clean */
833 for (i
= 0; i
< 4; i
++) {
836 msleep((1 << (i
- 1)) * 100);
838 pci_read_config_word(dev
, pos
, &status
);
839 if (!(status
& mask
))
846 static int pci_acs_enable
;
849 * pci_request_acs - ask for ACS to be enabled if supported
851 void pci_request_acs(void)
856 static const char *disable_acs_redir_param
;
859 * pci_disable_acs_redir - disable ACS redirect capabilities
860 * @dev: the PCI device
862 * For only devices specified in the disable_acs_redir parameter.
864 static void pci_disable_acs_redir(struct pci_dev
*dev
)
871 if (!disable_acs_redir_param
)
874 p
= disable_acs_redir_param
;
876 ret
= pci_dev_str_match(dev
, p
, &p
);
878 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
879 disable_acs_redir_param
);
882 } else if (ret
== 1) {
887 if (*p
!= ';' && *p
!= ',') {
888 /* End of param or invalid format */
897 if (!pci_dev_specific_disable_acs_redir(dev
))
902 pci_warn(dev
, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
906 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
908 /* P2P Request & Completion Redirect */
909 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
911 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
913 pci_info(dev
, "disabled ACS redirect\n");
917 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
918 * @dev: the PCI device
920 static void pci_std_enable_acs(struct pci_dev
*dev
)
930 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
931 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
933 /* Source Validation */
934 ctrl
|= (cap
& PCI_ACS_SV
);
936 /* P2P Request Redirect */
937 ctrl
|= (cap
& PCI_ACS_RR
);
939 /* P2P Completion Redirect */
940 ctrl
|= (cap
& PCI_ACS_CR
);
942 /* Upstream Forwarding */
943 ctrl
|= (cap
& PCI_ACS_UF
);
945 /* Enable Translation Blocking for external devices and noats */
946 if (pci_ats_disabled() || dev
->external_facing
|| dev
->untrusted
)
947 ctrl
|= (cap
& PCI_ACS_TB
);
949 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
953 * pci_enable_acs - enable ACS if hardware support it
954 * @dev: the PCI device
956 static void pci_enable_acs(struct pci_dev
*dev
)
959 goto disable_acs_redir
;
961 if (!pci_dev_specific_enable_acs(dev
))
962 goto disable_acs_redir
;
964 pci_std_enable_acs(dev
);
968 * Note: pci_disable_acs_redir() must be called even if ACS was not
969 * enabled by the kernel because it may have been enabled by
970 * platform firmware. So if we are told to disable it, we should
971 * always disable it after setting the kernel's default
974 pci_disable_acs_redir(dev
);
978 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
979 * @dev: PCI device to have its BARs restored
981 * Restore the BAR values for a given device, so as to make it
982 * accessible by its driver.
984 static void pci_restore_bars(struct pci_dev
*dev
)
988 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
989 pci_update_resource(dev
, i
);
992 static const struct pci_platform_pm_ops
*pci_platform_pm
;
994 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
996 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
997 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
999 pci_platform_pm
= ops
;
1003 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
1005 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
1008 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
1011 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
1014 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
1016 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
1019 static inline void platform_pci_refresh_power_state(struct pci_dev
*dev
)
1021 if (pci_platform_pm
&& pci_platform_pm
->refresh_state
)
1022 pci_platform_pm
->refresh_state(dev
);
1025 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
1027 return pci_platform_pm
?
1028 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
1031 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
1033 return pci_platform_pm
?
1034 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
1037 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
1039 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
1042 static inline bool platform_pci_bridge_d3(struct pci_dev
*dev
)
1044 if (pci_platform_pm
&& pci_platform_pm
->bridge_d3
)
1045 return pci_platform_pm
->bridge_d3(dev
);
1050 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1052 * @dev: PCI device to handle.
1053 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1056 * -EINVAL if the requested state is invalid.
1057 * -EIO if device does not support PCI PM or its PM capabilities register has a
1058 * wrong version, or device doesn't support the requested state.
1059 * 0 if device already is in the requested state.
1060 * 0 if device's power state has been successfully changed.
1062 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1065 bool need_restore
= false;
1067 /* Check if we're already there */
1068 if (dev
->current_state
== state
)
1074 if (state
< PCI_D0
|| state
> PCI_D3hot
)
1078 * Validate transition: We can enter D0 from any state, but if
1079 * we're already in a low-power state, we can only go deeper. E.g.,
1080 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1081 * we'd have to go from D3 to D0, then to D1.
1083 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
1084 && dev
->current_state
> state
) {
1085 pci_err(dev
, "invalid power transition (from %s to %s)\n",
1086 pci_power_name(dev
->current_state
),
1087 pci_power_name(state
));
1091 /* Check if this device supports the desired state */
1092 if ((state
== PCI_D1
&& !dev
->d1_support
)
1093 || (state
== PCI_D2
&& !dev
->d2_support
))
1096 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1097 if (pmcsr
== (u16
) ~0) {
1098 pci_err(dev
, "can't change power state from %s to %s (config space inaccessible)\n",
1099 pci_power_name(dev
->current_state
),
1100 pci_power_name(state
));
1105 * If we're (effectively) in D3, force entire word to 0.
1106 * This doesn't affect PME_Status, disables PME_En, and
1107 * sets PowerState to 0.
1109 switch (dev
->current_state
) {
1113 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
1118 case PCI_UNKNOWN
: /* Boot-up */
1119 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
1120 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
1121 need_restore
= true;
1122 fallthrough
; /* force to D0 */
1128 /* Enter specified state */
1129 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1132 * Mandatory power management transition delays; see PCI PM 1.1
1135 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
1136 pci_dev_d3_sleep(dev
);
1137 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
1138 udelay(PCI_PM_D2_DELAY
);
1140 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1141 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1142 if (dev
->current_state
!= state
)
1143 pci_info_ratelimited(dev
, "refused to change power state from %s to %s\n",
1144 pci_power_name(dev
->current_state
),
1145 pci_power_name(state
));
1148 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1149 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1150 * from D3hot to D0 _may_ perform an internal reset, thereby
1151 * going to "D0 Uninitialized" rather than "D0 Initialized".
1152 * For example, at least some versions of the 3c905B and the
1153 * 3c556B exhibit this behaviour.
1155 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1156 * devices in a D3hot state at boot. Consequently, we need to
1157 * restore at least the BARs so that the device will be
1158 * accessible to its driver.
1161 pci_restore_bars(dev
);
1163 if (dev
->bus
->self
&& !dmi_check_system(aspm_fix_whitelist
))
1164 pcie_aspm_pm_state_change(dev
->bus
->self
);
1170 * pci_update_current_state - Read power state of given device and cache it
1171 * @dev: PCI device to handle.
1172 * @state: State to cache in case the device doesn't have the PM capability
1174 * The power state is read from the PMCSR register, which however is
1175 * inaccessible in D3cold. The platform firmware is therefore queried first
1176 * to detect accessibility of the register. In case the platform firmware
1177 * reports an incorrect state or the device isn't power manageable by the
1178 * platform at all, we try to detect D3cold by testing accessibility of the
1179 * vendor ID in config space.
1181 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
1183 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
1184 !pci_device_is_present(dev
)) {
1185 dev
->current_state
= PCI_D3cold
;
1186 } else if (dev
->pm_cap
) {
1189 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1190 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1192 dev
->current_state
= state
;
1197 * pci_refresh_power_state - Refresh the given device's power state data
1198 * @dev: Target PCI device.
1200 * Ask the platform to refresh the devices power state information and invoke
1201 * pci_update_current_state() to update its current PCI power state.
1203 void pci_refresh_power_state(struct pci_dev
*dev
)
1205 if (platform_pci_power_manageable(dev
))
1206 platform_pci_refresh_power_state(dev
);
1208 pci_update_current_state(dev
, dev
->current_state
);
1212 * pci_platform_power_transition - Use platform to change device power state
1213 * @dev: PCI device to handle.
1214 * @state: State to put the device into.
1216 int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
1220 if (platform_pci_power_manageable(dev
)) {
1221 error
= platform_pci_set_power_state(dev
, state
);
1223 pci_update_current_state(dev
, state
);
1227 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
1228 dev
->current_state
= PCI_D0
;
1232 EXPORT_SYMBOL_GPL(pci_platform_power_transition
);
1234 static int pci_resume_one(struct pci_dev
*pci_dev
, void *ign
)
1236 pm_request_resume(&pci_dev
->dev
);
1241 * pci_resume_bus - Walk given bus and runtime resume devices on it
1242 * @bus: Top bus of the subtree to walk.
1244 void pci_resume_bus(struct pci_bus
*bus
)
1247 pci_walk_bus(bus
, pci_resume_one
, NULL
);
1250 static int pci_dev_wait(struct pci_dev
*dev
, char *reset_type
, int timeout
)
1256 * After reset, the device should not silently discard config
1257 * requests, but it may still indicate that it needs more time by
1258 * responding to them with CRS completions. The Root Port will
1259 * generally synthesize ~0 data to complete the read (except when
1260 * CRS SV is enabled and the read was for the Vendor ID; in that
1261 * case it synthesizes 0x0001 data).
1263 * Wait for the device to return a non-CRS completion. Read the
1264 * Command register instead of Vendor ID so we don't have to
1265 * contend with the CRS SV value.
1267 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1269 if (delay
> timeout
) {
1270 pci_warn(dev
, "not ready %dms after %s; giving up\n",
1271 delay
- 1, reset_type
);
1276 pci_info(dev
, "not ready %dms after %s; waiting\n",
1277 delay
- 1, reset_type
);
1281 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1285 pci_info(dev
, "ready %dms after %s\n", delay
- 1,
1292 * pci_power_up - Put the given device into D0
1293 * @dev: PCI device to power up
1295 int pci_power_up(struct pci_dev
*dev
)
1297 pci_platform_power_transition(dev
, PCI_D0
);
1300 * Mandatory power management transition delays are handled in
1301 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1302 * corresponding bridge.
1304 if (dev
->runtime_d3cold
) {
1306 * When powering on a bridge from D3cold, the whole hierarchy
1307 * may be powered on into D0uninitialized state, resume them to
1308 * give them a chance to suspend again
1310 pci_resume_bus(dev
->subordinate
);
1313 return pci_raw_set_power_state(dev
, PCI_D0
);
1317 * __pci_dev_set_current_state - Set current state of a PCI device
1318 * @dev: Device to handle
1319 * @data: pointer to state to be set
1321 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
1323 pci_power_t state
= *(pci_power_t
*)data
;
1325 dev
->current_state
= state
;
1330 * pci_bus_set_current_state - Walk given bus and set current state of devices
1331 * @bus: Top bus of the subtree to walk.
1332 * @state: state to be set
1334 void pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
1337 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
1341 * pci_set_power_state - Set the power state of a PCI device
1342 * @dev: PCI device to handle.
1343 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1345 * Transition a device to a new power state, using the platform firmware and/or
1346 * the device's PCI PM registers.
1349 * -EINVAL if the requested state is invalid.
1350 * -EIO if device does not support PCI PM or its PM capabilities register has a
1351 * wrong version, or device doesn't support the requested state.
1352 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1353 * 0 if device already is in the requested state.
1354 * 0 if the transition is to D3 but D3 is not supported.
1355 * 0 if device's power state has been successfully changed.
1357 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1361 /* Bound the state we're entering */
1362 if (state
> PCI_D3cold
)
1364 else if (state
< PCI_D0
)
1366 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
1369 * If the device or the parent bridge do not support PCI
1370 * PM, ignore the request if we're doing anything other
1371 * than putting it into D0 (which would only happen on
1376 /* Check if we're already there */
1377 if (dev
->current_state
== state
)
1380 if (state
== PCI_D0
)
1381 return pci_power_up(dev
);
1384 * This device is quirked not to be put into D3, so don't put it in
1387 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
1391 * To put device in D3cold, we put device into D3hot in native
1392 * way, then put device into D3cold with platform ops
1394 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
1397 if (pci_platform_power_transition(dev
, state
))
1400 /* Powering off a bridge may power off the whole hierarchy */
1401 if (state
== PCI_D3cold
)
1402 pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
1406 EXPORT_SYMBOL(pci_set_power_state
);
1409 * pci_choose_state - Choose the power state of a PCI device
1410 * @dev: PCI device to be suspended
1411 * @state: target sleep state for the whole system. This is the value
1412 * that is passed to suspend() function.
1414 * Returns PCI power state suitable for given device and given system
1417 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
1424 ret
= platform_pci_choose_state(dev
);
1425 if (ret
!= PCI_POWER_ERROR
)
1428 switch (state
.event
) {
1431 case PM_EVENT_FREEZE
:
1432 case PM_EVENT_PRETHAW
:
1433 /* REVISIT both freeze and pre-thaw "should" use D0 */
1434 case PM_EVENT_SUSPEND
:
1435 case PM_EVENT_HIBERNATE
:
1438 pci_info(dev
, "unrecognized suspend event %d\n",
1444 EXPORT_SYMBOL(pci_choose_state
);
1446 #define PCI_EXP_SAVE_REGS 7
1448 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
1449 u16 cap
, bool extended
)
1451 struct pci_cap_saved_state
*tmp
;
1453 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
1454 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
1460 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
1462 return _pci_find_saved_cap(dev
, cap
, false);
1465 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1467 return _pci_find_saved_cap(dev
, cap
, true);
1470 static int pci_save_pcie_state(struct pci_dev
*dev
)
1473 struct pci_cap_saved_state
*save_state
;
1476 if (!pci_is_pcie(dev
))
1479 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1481 pci_err(dev
, "buffer not found in %s\n", __func__
);
1485 cap
= (u16
*)&save_state
->cap
.data
[0];
1486 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1487 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1488 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1489 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1490 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1491 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1492 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1497 void pci_bridge_reconfigure_ltr(struct pci_dev
*dev
)
1499 #ifdef CONFIG_PCIEASPM
1500 struct pci_dev
*bridge
;
1503 bridge
= pci_upstream_bridge(dev
);
1504 if (bridge
&& bridge
->ltr_path
) {
1505 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
, &ctl
);
1506 if (!(ctl
& PCI_EXP_DEVCTL2_LTR_EN
)) {
1507 pci_dbg(bridge
, "re-enabling LTR\n");
1508 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
1509 PCI_EXP_DEVCTL2_LTR_EN
);
1515 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1518 struct pci_cap_saved_state
*save_state
;
1521 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1526 * Downstream ports reset the LTR enable bit when link goes down.
1527 * Check and re-configure the bit here before restoring device.
1528 * PCIe r5.0, sec 7.5.3.16.
1530 pci_bridge_reconfigure_ltr(dev
);
1532 cap
= (u16
*)&save_state
->cap
.data
[0];
1533 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1534 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1535 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1536 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1537 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1538 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1539 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1542 static int pci_save_pcix_state(struct pci_dev
*dev
)
1545 struct pci_cap_saved_state
*save_state
;
1547 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1551 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1553 pci_err(dev
, "buffer not found in %s\n", __func__
);
1557 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1558 (u16
*)save_state
->cap
.data
);
1563 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1566 struct pci_cap_saved_state
*save_state
;
1569 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1570 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1571 if (!save_state
|| !pos
)
1573 cap
= (u16
*)&save_state
->cap
.data
[0];
1575 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1578 static void pci_save_ltr_state(struct pci_dev
*dev
)
1581 struct pci_cap_saved_state
*save_state
;
1584 if (!pci_is_pcie(dev
))
1587 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1591 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1593 pci_err(dev
, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1597 cap
= (u16
*)&save_state
->cap
.data
[0];
1598 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, cap
++);
1599 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, cap
++);
1602 static void pci_restore_ltr_state(struct pci_dev
*dev
)
1604 struct pci_cap_saved_state
*save_state
;
1608 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1609 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1610 if (!save_state
|| !ltr
)
1613 cap
= (u16
*)&save_state
->cap
.data
[0];
1614 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, *cap
++);
1615 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, *cap
++);
1619 * pci_save_state - save the PCI configuration space of a device before
1621 * @dev: PCI device that we're dealing with
1623 int pci_save_state(struct pci_dev
*dev
)
1626 /* XXX: 100% dword access ok here? */
1627 for (i
= 0; i
< 16; i
++) {
1628 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1629 pci_dbg(dev
, "saving config space at offset %#x (reading %#x)\n",
1630 i
* 4, dev
->saved_config_space
[i
]);
1632 dev
->state_saved
= true;
1634 i
= pci_save_pcie_state(dev
);
1638 i
= pci_save_pcix_state(dev
);
1642 pci_save_ltr_state(dev
);
1643 if (dmi_check_system(aspm_fix_whitelist
))
1644 pci_save_aspm_l1ss_state(dev
);
1645 pci_save_dpc_state(dev
);
1646 pci_save_aer_state(dev
);
1647 pci_save_ptm_state(dev
);
1648 return pci_save_vc_state(dev
);
1650 EXPORT_SYMBOL(pci_save_state
);
1652 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1653 u32 saved_val
, int retry
, bool force
)
1657 pci_read_config_dword(pdev
, offset
, &val
);
1658 if (!force
&& val
== saved_val
)
1662 pci_dbg(pdev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1663 offset
, val
, saved_val
);
1664 pci_write_config_dword(pdev
, offset
, saved_val
);
1668 pci_read_config_dword(pdev
, offset
, &val
);
1669 if (val
== saved_val
)
1676 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1677 int start
, int end
, int retry
,
1682 for (index
= end
; index
>= start
; index
--)
1683 pci_restore_config_dword(pdev
, 4 * index
,
1684 pdev
->saved_config_space
[index
],
1688 static void pci_restore_config_space(struct pci_dev
*pdev
)
1690 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1691 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1692 /* Restore BARs before the command register. */
1693 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1694 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1695 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1696 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1699 * Force rewriting of prefetch registers to avoid S3 resume
1700 * issues on Intel PCI bridges that occur when these
1701 * registers are not explicitly written.
1703 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1704 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1706 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1710 static void pci_restore_rebar_state(struct pci_dev
*pdev
)
1712 unsigned int pos
, nbars
, i
;
1715 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
1719 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1720 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
1721 PCI_REBAR_CTRL_NBAR_SHIFT
;
1723 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
1724 struct resource
*res
;
1727 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1728 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
1729 res
= pdev
->resource
+ bar_idx
;
1730 size
= pci_rebar_bytes_to_size(resource_size(res
));
1731 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
1732 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
1733 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
1738 * pci_restore_state - Restore the saved state of a PCI device
1739 * @dev: PCI device that we're dealing with
1741 void pci_restore_state(struct pci_dev
*dev
)
1743 if (!dev
->state_saved
)
1747 * Restore max latencies (in the LTR capability) before enabling
1748 * LTR itself (in the PCIe capability).
1750 pci_restore_ltr_state(dev
);
1751 if (dmi_check_system(aspm_fix_whitelist
))
1752 pci_restore_aspm_l1ss_state(dev
);
1754 pci_restore_pcie_state(dev
);
1755 pci_restore_pasid_state(dev
);
1756 pci_restore_pri_state(dev
);
1757 pci_restore_ats_state(dev
);
1758 pci_restore_vc_state(dev
);
1759 pci_restore_rebar_state(dev
);
1760 pci_restore_dpc_state(dev
);
1761 pci_restore_ptm_state(dev
);
1763 pci_aer_clear_status(dev
);
1764 pci_restore_aer_state(dev
);
1766 pci_restore_config_space(dev
);
1768 pci_restore_pcix_state(dev
);
1769 pci_restore_msi_state(dev
);
1771 /* Restore ACS and IOV configuration state */
1772 pci_enable_acs(dev
);
1773 pci_restore_iov_state(dev
);
1775 dev
->state_saved
= false;
1777 EXPORT_SYMBOL(pci_restore_state
);
1779 struct pci_saved_state
{
1780 u32 config_space
[16];
1781 struct pci_cap_saved_data cap
[];
1785 * pci_store_saved_state - Allocate and return an opaque struct containing
1786 * the device saved state.
1787 * @dev: PCI device that we're dealing with
1789 * Return NULL if no state or error.
1791 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1793 struct pci_saved_state
*state
;
1794 struct pci_cap_saved_state
*tmp
;
1795 struct pci_cap_saved_data
*cap
;
1798 if (!dev
->state_saved
)
1801 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1803 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1804 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1806 state
= kzalloc(size
, GFP_KERNEL
);
1810 memcpy(state
->config_space
, dev
->saved_config_space
,
1811 sizeof(state
->config_space
));
1814 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1815 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1816 memcpy(cap
, &tmp
->cap
, len
);
1817 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1819 /* Empty cap_save terminates list */
1823 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1826 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1827 * @dev: PCI device that we're dealing with
1828 * @state: Saved state returned from pci_store_saved_state()
1830 int pci_load_saved_state(struct pci_dev
*dev
,
1831 struct pci_saved_state
*state
)
1833 struct pci_cap_saved_data
*cap
;
1835 dev
->state_saved
= false;
1840 memcpy(dev
->saved_config_space
, state
->config_space
,
1841 sizeof(state
->config_space
));
1845 struct pci_cap_saved_state
*tmp
;
1847 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1848 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1851 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1852 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1853 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1856 dev
->state_saved
= true;
1859 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1862 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1863 * and free the memory allocated for it.
1864 * @dev: PCI device that we're dealing with
1865 * @state: Pointer to saved state returned from pci_store_saved_state()
1867 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1868 struct pci_saved_state
**state
)
1870 int ret
= pci_load_saved_state(dev
, *state
);
1875 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1877 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1879 return pci_enable_resources(dev
, bars
);
1882 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1885 struct pci_dev
*bridge
;
1889 err
= pci_set_power_state(dev
, PCI_D0
);
1890 if (err
< 0 && err
!= -EIO
)
1893 bridge
= pci_upstream_bridge(dev
);
1895 pcie_aspm_powersave_config_link(bridge
);
1897 err
= pcibios_enable_device(dev
, bars
);
1900 pci_fixup_device(pci_fixup_enable
, dev
);
1902 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1905 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1907 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1908 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1909 pci_write_config_word(dev
, PCI_COMMAND
,
1910 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1917 * pci_reenable_device - Resume abandoned device
1918 * @dev: PCI device to be resumed
1920 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1921 * to be called by normal code, write proper resume handler and use it instead.
1923 int pci_reenable_device(struct pci_dev
*dev
)
1925 if (pci_is_enabled(dev
))
1926 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1929 EXPORT_SYMBOL(pci_reenable_device
);
1931 static void pci_enable_bridge(struct pci_dev
*dev
)
1933 struct pci_dev
*bridge
;
1936 bridge
= pci_upstream_bridge(dev
);
1938 pci_enable_bridge(bridge
);
1940 if (pci_is_enabled(dev
)) {
1941 if (!dev
->is_busmaster
)
1942 pci_set_master(dev
);
1946 retval
= pci_enable_device(dev
);
1948 pci_err(dev
, "Error enabling bridge (%d), continuing\n",
1950 pci_set_master(dev
);
1953 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1955 struct pci_dev
*bridge
;
1960 * Power state could be unknown at this point, either due to a fresh
1961 * boot or a device removal call. So get the current power state
1962 * so that things like MSI message writing will behave as expected
1963 * (e.g. if the device really is in D0 at enable time).
1965 pci_update_current_state(dev
, dev
->current_state
);
1967 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1968 return 0; /* already enabled */
1970 bridge
= pci_upstream_bridge(dev
);
1972 pci_enable_bridge(bridge
);
1974 /* only skip sriov related */
1975 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1976 if (dev
->resource
[i
].flags
& flags
)
1978 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1979 if (dev
->resource
[i
].flags
& flags
)
1982 err
= do_pci_enable_device(dev
, bars
);
1984 atomic_dec(&dev
->enable_cnt
);
1989 * pci_enable_device_io - Initialize a device for use with IO space
1990 * @dev: PCI device to be initialized
1992 * Initialize device before it's used by a driver. Ask low-level code
1993 * to enable I/O resources. Wake up the device if it was suspended.
1994 * Beware, this function can fail.
1996 int pci_enable_device_io(struct pci_dev
*dev
)
1998 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
2000 EXPORT_SYMBOL(pci_enable_device_io
);
2003 * pci_enable_device_mem - Initialize a device for use with Memory space
2004 * @dev: PCI device to be initialized
2006 * Initialize device before it's used by a driver. Ask low-level code
2007 * to enable Memory resources. Wake up the device if it was suspended.
2008 * Beware, this function can fail.
2010 int pci_enable_device_mem(struct pci_dev
*dev
)
2012 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
2014 EXPORT_SYMBOL(pci_enable_device_mem
);
2017 * pci_enable_device - Initialize device before it's used by a driver.
2018 * @dev: PCI device to be initialized
2020 * Initialize device before it's used by a driver. Ask low-level code
2021 * to enable I/O and memory. Wake up the device if it was suspended.
2022 * Beware, this function can fail.
2024 * Note we don't actually enable the device many times if we call
2025 * this function repeatedly (we just increment the count).
2027 int pci_enable_device(struct pci_dev
*dev
)
2029 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
2031 EXPORT_SYMBOL(pci_enable_device
);
2034 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2035 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2036 * there's no need to track it separately. pci_devres is initialized
2037 * when a device is enabled using managed PCI device enable interface.
2040 unsigned int enabled
:1;
2041 unsigned int pinned
:1;
2042 unsigned int orig_intx
:1;
2043 unsigned int restore_intx
:1;
2048 static void pcim_release(struct device
*gendev
, void *res
)
2050 struct pci_dev
*dev
= to_pci_dev(gendev
);
2051 struct pci_devres
*this = res
;
2054 if (dev
->msi_enabled
)
2055 pci_disable_msi(dev
);
2056 if (dev
->msix_enabled
)
2057 pci_disable_msix(dev
);
2059 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
2060 if (this->region_mask
& (1 << i
))
2061 pci_release_region(dev
, i
);
2066 if (this->restore_intx
)
2067 pci_intx(dev
, this->orig_intx
);
2069 if (this->enabled
&& !this->pinned
)
2070 pci_disable_device(dev
);
2073 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
2075 struct pci_devres
*dr
, *new_dr
;
2077 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2081 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
2084 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
2087 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
2089 if (pci_is_managed(pdev
))
2090 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2095 * pcim_enable_device - Managed pci_enable_device()
2096 * @pdev: PCI device to be initialized
2098 * Managed pci_enable_device().
2100 int pcim_enable_device(struct pci_dev
*pdev
)
2102 struct pci_devres
*dr
;
2105 dr
= get_pci_dr(pdev
);
2111 rc
= pci_enable_device(pdev
);
2113 pdev
->is_managed
= 1;
2118 EXPORT_SYMBOL(pcim_enable_device
);
2121 * pcim_pin_device - Pin managed PCI device
2122 * @pdev: PCI device to pin
2124 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2125 * driver detach. @pdev must have been enabled with
2126 * pcim_enable_device().
2128 void pcim_pin_device(struct pci_dev
*pdev
)
2130 struct pci_devres
*dr
;
2132 dr
= find_pci_dr(pdev
);
2133 WARN_ON(!dr
|| !dr
->enabled
);
2137 EXPORT_SYMBOL(pcim_pin_device
);
2140 * pcibios_add_device - provide arch specific hooks when adding device dev
2141 * @dev: the PCI device being added
2143 * Permits the platform to provide architecture specific functionality when
2144 * devices are added. This is the default implementation. Architecture
2145 * implementations can override this.
2147 int __weak
pcibios_add_device(struct pci_dev
*dev
)
2153 * pcibios_release_device - provide arch specific hooks when releasing
2155 * @dev: the PCI device being released
2157 * Permits the platform to provide architecture specific functionality when
2158 * devices are released. This is the default implementation. Architecture
2159 * implementations can override this.
2161 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
2164 * pcibios_disable_device - disable arch specific PCI resources for device dev
2165 * @dev: the PCI device to disable
2167 * Disables architecture specific PCI resources for the device. This
2168 * is the default implementation. Architecture implementations can
2171 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
2174 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2175 * @irq: ISA IRQ to penalize
2176 * @active: IRQ active or not
2178 * Permits the platform to provide architecture-specific functionality when
2179 * penalizing ISA IRQs. This is the default implementation. Architecture
2180 * implementations can override this.
2182 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
2184 static void do_pci_disable_device(struct pci_dev
*dev
)
2188 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
2189 if (pci_command
& PCI_COMMAND_MASTER
) {
2190 pci_command
&= ~PCI_COMMAND_MASTER
;
2191 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
2194 pcibios_disable_device(dev
);
2198 * pci_disable_enabled_device - Disable device without updating enable_cnt
2199 * @dev: PCI device to disable
2201 * NOTE: This function is a backend of PCI power management routines and is
2202 * not supposed to be called drivers.
2204 void pci_disable_enabled_device(struct pci_dev
*dev
)
2206 if (pci_is_enabled(dev
))
2207 do_pci_disable_device(dev
);
2211 * pci_disable_device - Disable PCI device after use
2212 * @dev: PCI device to be disabled
2214 * Signal to the system that the PCI device is not in use by the system
2215 * anymore. This only involves disabling PCI bus-mastering, if active.
2217 * Note we don't actually disable the device until all callers of
2218 * pci_enable_device() have called pci_disable_device().
2220 void pci_disable_device(struct pci_dev
*dev
)
2222 struct pci_devres
*dr
;
2224 dr
= find_pci_dr(dev
);
2228 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
2229 "disabling already-disabled device");
2231 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
2234 do_pci_disable_device(dev
);
2236 dev
->is_busmaster
= 0;
2238 EXPORT_SYMBOL(pci_disable_device
);
2241 * pcibios_set_pcie_reset_state - set reset state for device dev
2242 * @dev: the PCIe device reset
2243 * @state: Reset state to enter into
2245 * Set the PCIe reset state for the device. This is the default
2246 * implementation. Architecture implementations can override this.
2248 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
2249 enum pcie_reset_state state
)
2255 * pci_set_pcie_reset_state - set reset state for device dev
2256 * @dev: the PCIe device reset
2257 * @state: Reset state to enter into
2259 * Sets the PCI reset state for the device.
2261 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
2263 return pcibios_set_pcie_reset_state(dev
, state
);
2265 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
2267 void pcie_clear_device_status(struct pci_dev
*dev
)
2271 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
2272 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
2276 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2277 * @dev: PCIe root port or event collector.
2279 void pcie_clear_root_pme_status(struct pci_dev
*dev
)
2281 pcie_capability_set_dword(dev
, PCI_EXP_RTSTA
, PCI_EXP_RTSTA_PME
);
2285 * pci_check_pme_status - Check if given device has generated PME.
2286 * @dev: Device to check.
2288 * Check the PME status of the device and if set, clear it and clear PME enable
2289 * (if set). Return 'true' if PME status and PME enable were both set or
2290 * 'false' otherwise.
2292 bool pci_check_pme_status(struct pci_dev
*dev
)
2301 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
2302 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
2303 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
2306 /* Clear PME status. */
2307 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2308 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
2309 /* Disable PME to avoid interrupt flood. */
2310 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2314 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
2320 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2321 * @dev: Device to handle.
2322 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2324 * Check if @dev has generated PME and queue a resume request for it in that
2327 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
2329 if (pme_poll_reset
&& dev
->pme_poll
)
2330 dev
->pme_poll
= false;
2332 if (pci_check_pme_status(dev
)) {
2333 pci_wakeup_event(dev
);
2334 pm_request_resume(&dev
->dev
);
2340 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2341 * @bus: Top bus of the subtree to walk.
2343 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
2346 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
2351 * pci_pme_capable - check the capability of PCI device to generate PME#
2352 * @dev: PCI device to handle.
2353 * @state: PCI state from which device will issue PME#.
2355 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
2360 return !!(dev
->pme_support
& (1 << state
));
2362 EXPORT_SYMBOL(pci_pme_capable
);
2364 static void pci_pme_list_scan(struct work_struct
*work
)
2366 struct pci_pme_device
*pme_dev
, *n
;
2368 mutex_lock(&pci_pme_list_mutex
);
2369 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
2370 if (pme_dev
->dev
->pme_poll
) {
2371 struct pci_dev
*bridge
;
2373 bridge
= pme_dev
->dev
->bus
->self
;
2375 * If bridge is in low power state, the
2376 * configuration space of subordinate devices
2377 * may be not accessible
2379 if (bridge
&& bridge
->current_state
!= PCI_D0
)
2382 * If the device is in D3cold it should not be
2385 if (pme_dev
->dev
->current_state
== PCI_D3cold
)
2388 pci_pme_wakeup(pme_dev
->dev
, NULL
);
2390 list_del(&pme_dev
->list
);
2394 if (!list_empty(&pci_pme_list
))
2395 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
2396 msecs_to_jiffies(PME_TIMEOUT
));
2397 mutex_unlock(&pci_pme_list_mutex
);
2400 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
2404 if (!dev
->pme_support
)
2407 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2408 /* Clear PME_Status by writing 1 to it and enable PME# */
2409 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
2411 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2413 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2417 * pci_pme_restore - Restore PME configuration after config space restore.
2418 * @dev: PCI device to update.
2420 void pci_pme_restore(struct pci_dev
*dev
)
2424 if (!dev
->pme_support
)
2427 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2428 if (dev
->wakeup_prepared
) {
2429 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
2430 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
2432 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2433 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2435 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2439 * pci_pme_active - enable or disable PCI device's PME# function
2440 * @dev: PCI device to handle.
2441 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2443 * The caller must verify that the device is capable of generating PME# before
2444 * calling this function with @enable equal to 'true'.
2446 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
2448 __pci_pme_active(dev
, enable
);
2451 * PCI (as opposed to PCIe) PME requires that the device have
2452 * its PME# line hooked up correctly. Not all hardware vendors
2453 * do this, so the PME never gets delivered and the device
2454 * remains asleep. The easiest way around this is to
2455 * periodically walk the list of suspended devices and check
2456 * whether any have their PME flag set. The assumption is that
2457 * we'll wake up often enough anyway that this won't be a huge
2458 * hit, and the power savings from the devices will still be a
2461 * Although PCIe uses in-band PME message instead of PME# line
2462 * to report PME, PME does not work for some PCIe devices in
2463 * reality. For example, there are devices that set their PME
2464 * status bits, but don't really bother to send a PME message;
2465 * there are PCI Express Root Ports that don't bother to
2466 * trigger interrupts when they receive PME messages from the
2467 * devices below. So PME poll is used for PCIe devices too.
2470 if (dev
->pme_poll
) {
2471 struct pci_pme_device
*pme_dev
;
2473 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
2476 pci_warn(dev
, "can't enable PME#\n");
2480 mutex_lock(&pci_pme_list_mutex
);
2481 list_add(&pme_dev
->list
, &pci_pme_list
);
2482 if (list_is_singular(&pci_pme_list
))
2483 queue_delayed_work(system_freezable_wq
,
2485 msecs_to_jiffies(PME_TIMEOUT
));
2486 mutex_unlock(&pci_pme_list_mutex
);
2488 mutex_lock(&pci_pme_list_mutex
);
2489 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
2490 if (pme_dev
->dev
== dev
) {
2491 list_del(&pme_dev
->list
);
2496 mutex_unlock(&pci_pme_list_mutex
);
2500 pci_dbg(dev
, "PME# %s\n", enable
? "enabled" : "disabled");
2502 EXPORT_SYMBOL(pci_pme_active
);
2505 * __pci_enable_wake - enable PCI device as wakeup event source
2506 * @dev: PCI device affected
2507 * @state: PCI state from which device will issue wakeup events
2508 * @enable: True to enable event generation; false to disable
2510 * This enables the device as a wakeup event source, or disables it.
2511 * When such events involves platform-specific hooks, those hooks are
2512 * called automatically by this routine.
2514 * Devices with legacy power management (no standard PCI PM capabilities)
2515 * always require such platform hooks.
2518 * 0 is returned on success
2519 * -EINVAL is returned if device is not supposed to wake up the system
2520 * Error code depending on the platform is returned if both the platform and
2521 * the native mechanism fail to enable the generation of wake-up events
2523 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
2528 * Bridges that are not power-manageable directly only signal
2529 * wakeup on behalf of subordinate devices which is set up
2530 * elsewhere, so skip them. However, bridges that are
2531 * power-manageable may signal wakeup for themselves (for example,
2532 * on a hotplug event) and they need to be covered here.
2534 if (!pci_power_manageable(dev
))
2537 /* Don't do the same thing twice in a row for one device. */
2538 if (!!enable
== !!dev
->wakeup_prepared
)
2542 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2543 * Anderson we should be doing PME# wake enable followed by ACPI wake
2544 * enable. To disable wake-up we call the platform first, for symmetry.
2551 * Enable PME signaling if the device can signal PME from
2552 * D3cold regardless of whether or not it can signal PME from
2553 * the current target state, because that will allow it to
2554 * signal PME when the hierarchy above it goes into D3cold and
2555 * the device itself ends up in D3cold as a result of that.
2557 if (pci_pme_capable(dev
, state
) || pci_pme_capable(dev
, PCI_D3cold
))
2558 pci_pme_active(dev
, true);
2561 error
= platform_pci_set_wakeup(dev
, true);
2565 dev
->wakeup_prepared
= true;
2567 platform_pci_set_wakeup(dev
, false);
2568 pci_pme_active(dev
, false);
2569 dev
->wakeup_prepared
= false;
2576 * pci_enable_wake - change wakeup settings for a PCI device
2577 * @pci_dev: Target device
2578 * @state: PCI state from which device will issue wakeup events
2579 * @enable: Whether or not to enable event generation
2581 * If @enable is set, check device_may_wakeup() for the device before calling
2582 * __pci_enable_wake() for it.
2584 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
2586 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
2589 return __pci_enable_wake(pci_dev
, state
, enable
);
2591 EXPORT_SYMBOL(pci_enable_wake
);
2594 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2595 * @dev: PCI device to prepare
2596 * @enable: True to enable wake-up event generation; false to disable
2598 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2599 * and this function allows them to set that up cleanly - pci_enable_wake()
2600 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2601 * ordering constraints.
2603 * This function only returns error code if the device is not allowed to wake
2604 * up the system from sleep or it is not capable of generating PME# from both
2605 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2607 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2609 return pci_pme_capable(dev
, PCI_D3cold
) ?
2610 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2611 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2613 EXPORT_SYMBOL(pci_wake_from_d3
);
2616 * pci_target_state - find an appropriate low power state for a given PCI dev
2618 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2620 * Use underlying platform code to find a supported low power state for @dev.
2621 * If the platform can't manage @dev, return the deepest state from which it
2622 * can generate wake events, based on any available PME info.
2624 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2626 pci_power_t target_state
= PCI_D3hot
;
2628 if (platform_pci_power_manageable(dev
)) {
2630 * Call the platform to find the target state for the device.
2632 pci_power_t state
= platform_pci_choose_state(dev
);
2635 case PCI_POWER_ERROR
:
2640 if (pci_no_d1d2(dev
))
2644 target_state
= state
;
2647 return target_state
;
2651 target_state
= PCI_D0
;
2654 * If the device is in D3cold even though it's not power-manageable by
2655 * the platform, it may have been powered down by non-standard means.
2656 * Best to let it slumber.
2658 if (dev
->current_state
== PCI_D3cold
)
2659 target_state
= PCI_D3cold
;
2661 if (wakeup
&& dev
->pme_support
) {
2662 pci_power_t state
= target_state
;
2665 * Find the deepest state from which the device can generate
2668 while (state
&& !(dev
->pme_support
& (1 << state
)))
2673 else if (dev
->pme_support
& 1)
2677 return target_state
;
2681 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2682 * into a sleep state
2683 * @dev: Device to handle.
2685 * Choose the power state appropriate for the device depending on whether
2686 * it can wake up the system and/or is power manageable by the platform
2687 * (PCI_D3hot is the default) and put the device into that state.
2689 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2691 bool wakeup
= device_may_wakeup(&dev
->dev
);
2692 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2695 if (target_state
== PCI_POWER_ERROR
)
2699 * There are systems (for example, Intel mobile chips since Coffee
2700 * Lake) where the power drawn while suspended can be significantly
2701 * reduced by disabling PTM on PCIe root ports as this allows the
2702 * port to enter a lower-power PM state and the SoC to reach a
2703 * lower-power idle state as a whole.
2705 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2706 pci_disable_ptm(dev
);
2708 pci_enable_wake(dev
, target_state
, wakeup
);
2710 error
= pci_set_power_state(dev
, target_state
);
2713 pci_enable_wake(dev
, target_state
, false);
2714 pci_restore_ptm_state(dev
);
2719 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2722 * pci_back_from_sleep - turn PCI device on during system-wide transition
2723 * into working state
2724 * @dev: Device to handle.
2726 * Disable device's system wake-up capability and put it into D0.
2728 int pci_back_from_sleep(struct pci_dev
*dev
)
2730 pci_enable_wake(dev
, PCI_D0
, false);
2731 return pci_set_power_state(dev
, PCI_D0
);
2733 EXPORT_SYMBOL(pci_back_from_sleep
);
2736 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2737 * @dev: PCI device being suspended.
2739 * Prepare @dev to generate wake-up events at run time and put it into a low
2742 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2744 pci_power_t target_state
;
2747 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2748 if (target_state
== PCI_POWER_ERROR
)
2751 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2754 * There are systems (for example, Intel mobile chips since Coffee
2755 * Lake) where the power drawn while suspended can be significantly
2756 * reduced by disabling PTM on PCIe root ports as this allows the
2757 * port to enter a lower-power PM state and the SoC to reach a
2758 * lower-power idle state as a whole.
2760 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2761 pci_disable_ptm(dev
);
2763 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2765 error
= pci_set_power_state(dev
, target_state
);
2768 pci_enable_wake(dev
, target_state
, false);
2769 pci_restore_ptm_state(dev
);
2770 dev
->runtime_d3cold
= false;
2777 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2778 * @dev: Device to check.
2780 * Return true if the device itself is capable of generating wake-up events
2781 * (through the platform or using the native PCIe PME) or if the device supports
2782 * PME and one of its upstream bridges can generate wake-up events.
2784 bool pci_dev_run_wake(struct pci_dev
*dev
)
2786 struct pci_bus
*bus
= dev
->bus
;
2788 if (!dev
->pme_support
)
2791 /* PME-capable in principle, but not from the target power state */
2792 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2795 if (device_can_wakeup(&dev
->dev
))
2798 while (bus
->parent
) {
2799 struct pci_dev
*bridge
= bus
->self
;
2801 if (device_can_wakeup(&bridge
->dev
))
2807 /* We have reached the root bus. */
2809 return device_can_wakeup(bus
->bridge
);
2813 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2816 * pci_dev_need_resume - Check if it is necessary to resume the device.
2817 * @pci_dev: Device to check.
2819 * Return 'true' if the device is not runtime-suspended or it has to be
2820 * reconfigured due to wakeup settings difference between system and runtime
2821 * suspend, or the current power state of it is not suitable for the upcoming
2822 * (system-wide) transition.
2824 bool pci_dev_need_resume(struct pci_dev
*pci_dev
)
2826 struct device
*dev
= &pci_dev
->dev
;
2827 pci_power_t target_state
;
2829 if (!pm_runtime_suspended(dev
) || platform_pci_need_resume(pci_dev
))
2832 target_state
= pci_target_state(pci_dev
, device_may_wakeup(dev
));
2835 * If the earlier platform check has not triggered, D3cold is just power
2836 * removal on top of D3hot, so no need to resume the device in that
2839 return target_state
!= pci_dev
->current_state
&&
2840 target_state
!= PCI_D3cold
&&
2841 pci_dev
->current_state
!= PCI_D3hot
;
2845 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2846 * @pci_dev: Device to check.
2848 * If the device is suspended and it is not configured for system wakeup,
2849 * disable PME for it to prevent it from waking up the system unnecessarily.
2851 * Note that if the device's power state is D3cold and the platform check in
2852 * pci_dev_need_resume() has not triggered, the device's configuration need not
2855 void pci_dev_adjust_pme(struct pci_dev
*pci_dev
)
2857 struct device
*dev
= &pci_dev
->dev
;
2859 spin_lock_irq(&dev
->power
.lock
);
2861 if (pm_runtime_suspended(dev
) && !device_may_wakeup(dev
) &&
2862 pci_dev
->current_state
< PCI_D3cold
)
2863 __pci_pme_active(pci_dev
, false);
2865 spin_unlock_irq(&dev
->power
.lock
);
2869 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2870 * @pci_dev: Device to handle.
2872 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2873 * it might have been disabled during the prepare phase of system suspend if
2874 * the device was not configured for system wakeup.
2876 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2878 struct device
*dev
= &pci_dev
->dev
;
2880 if (!pci_dev_run_wake(pci_dev
))
2883 spin_lock_irq(&dev
->power
.lock
);
2885 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2886 __pci_pme_active(pci_dev
, true);
2888 spin_unlock_irq(&dev
->power
.lock
);
2891 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2893 struct device
*dev
= &pdev
->dev
;
2894 struct device
*parent
= dev
->parent
;
2897 pm_runtime_get_sync(parent
);
2898 pm_runtime_get_noresume(dev
);
2900 * pdev->current_state is set to PCI_D3cold during suspending,
2901 * so wait until suspending completes
2903 pm_runtime_barrier(dev
);
2905 * Only need to resume devices in D3cold, because config
2906 * registers are still accessible for devices suspended but
2909 if (pdev
->current_state
== PCI_D3cold
)
2910 pm_runtime_resume(dev
);
2913 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2915 struct device
*dev
= &pdev
->dev
;
2916 struct device
*parent
= dev
->parent
;
2918 pm_runtime_put(dev
);
2920 pm_runtime_put_sync(parent
);
2923 static const struct dmi_system_id bridge_d3_blacklist
[] = {
2927 * Gigabyte X299 root port is not marked as hotplug capable
2928 * which allows Linux to power manage it. However, this
2929 * confuses the BIOS SMI handler so don't power manage root
2930 * ports on that system.
2932 .ident
= "X299 DESIGNARE EX-CF",
2934 DMI_MATCH(DMI_BOARD_VENDOR
, "Gigabyte Technology Co., Ltd."),
2935 DMI_MATCH(DMI_BOARD_NAME
, "X299 DESIGNARE EX-CF"),
2940 * Downstream device is not accessible after putting a root port
2941 * into D3cold and back into D0 on Elo i2.
2945 DMI_MATCH(DMI_SYS_VENDOR
, "Elo Touch Solutions"),
2946 DMI_MATCH(DMI_PRODUCT_NAME
, "Elo i2"),
2947 DMI_MATCH(DMI_PRODUCT_VERSION
, "RevB"),
2955 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2956 * @bridge: Bridge to check
2958 * This function checks if it is possible to move the bridge to D3.
2959 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2961 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2963 if (!pci_is_pcie(bridge
))
2966 switch (pci_pcie_type(bridge
)) {
2967 case PCI_EXP_TYPE_ROOT_PORT
:
2968 case PCI_EXP_TYPE_UPSTREAM
:
2969 case PCI_EXP_TYPE_DOWNSTREAM
:
2970 if (pci_bridge_d3_disable
)
2974 * Hotplug ports handled by firmware in System Management Mode
2975 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2977 if (bridge
->is_hotplug_bridge
&& !pciehp_is_native(bridge
))
2980 if (pci_bridge_d3_force
)
2983 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2984 if (bridge
->is_thunderbolt
)
2987 /* Platform might know better if the bridge supports D3 */
2988 if (platform_pci_bridge_d3(bridge
))
2992 * Hotplug ports handled natively by the OS were not validated
2993 * by vendors for runtime D3 at least until 2018 because there
2994 * was no OS support.
2996 if (bridge
->is_hotplug_bridge
)
2999 if (dmi_check_system(bridge_d3_blacklist
))
3003 * It should be safe to put PCIe ports from 2015 or newer
3006 if (dmi_get_bios_year() >= 2015)
3014 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
3016 bool *d3cold_ok
= data
;
3018 if (/* The device needs to be allowed to go D3cold ... */
3019 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
3021 /* ... and if it is wakeup capable to do so from D3cold. */
3022 (device_may_wakeup(&dev
->dev
) &&
3023 !pci_pme_capable(dev
, PCI_D3cold
)) ||
3025 /* If it is a bridge it must be allowed to go to D3. */
3026 !pci_power_manageable(dev
))
3034 * pci_bridge_d3_update - Update bridge D3 capabilities
3035 * @dev: PCI device which is changed
3037 * Update upstream bridge PM capabilities accordingly depending on if the
3038 * device PM configuration was changed or the device is being removed. The
3039 * change is also propagated upstream.
3041 void pci_bridge_d3_update(struct pci_dev
*dev
)
3043 bool remove
= !device_is_registered(&dev
->dev
);
3044 struct pci_dev
*bridge
;
3045 bool d3cold_ok
= true;
3047 bridge
= pci_upstream_bridge(dev
);
3048 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
3052 * If D3 is currently allowed for the bridge, removing one of its
3053 * children won't change that.
3055 if (remove
&& bridge
->bridge_d3
)
3059 * If D3 is currently allowed for the bridge and a child is added or
3060 * changed, disallowance of D3 can only be caused by that child, so
3061 * we only need to check that single device, not any of its siblings.
3063 * If D3 is currently not allowed for the bridge, checking the device
3064 * first may allow us to skip checking its siblings.
3067 pci_dev_check_d3cold(dev
, &d3cold_ok
);
3070 * If D3 is currently not allowed for the bridge, this may be caused
3071 * either by the device being changed/removed or any of its siblings,
3072 * so we need to go through all children to find out if one of them
3073 * continues to block D3.
3075 if (d3cold_ok
&& !bridge
->bridge_d3
)
3076 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
3079 if (bridge
->bridge_d3
!= d3cold_ok
) {
3080 bridge
->bridge_d3
= d3cold_ok
;
3081 /* Propagate change to upstream bridges */
3082 pci_bridge_d3_update(bridge
);
3087 * pci_d3cold_enable - Enable D3cold for device
3088 * @dev: PCI device to handle
3090 * This function can be used in drivers to enable D3cold from the device
3091 * they handle. It also updates upstream PCI bridge PM capabilities
3094 void pci_d3cold_enable(struct pci_dev
*dev
)
3096 if (dev
->no_d3cold
) {
3097 dev
->no_d3cold
= false;
3098 pci_bridge_d3_update(dev
);
3101 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
3104 * pci_d3cold_disable - Disable D3cold for device
3105 * @dev: PCI device to handle
3107 * This function can be used in drivers to disable D3cold from the device
3108 * they handle. It also updates upstream PCI bridge PM capabilities
3111 void pci_d3cold_disable(struct pci_dev
*dev
)
3113 if (!dev
->no_d3cold
) {
3114 dev
->no_d3cold
= true;
3115 pci_bridge_d3_update(dev
);
3118 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
3121 * pci_pm_init - Initialize PM functions of given PCI device
3122 * @dev: PCI device to handle.
3124 void pci_pm_init(struct pci_dev
*dev
)
3130 pm_runtime_forbid(&dev
->dev
);
3131 pm_runtime_set_active(&dev
->dev
);
3132 pm_runtime_enable(&dev
->dev
);
3133 device_enable_async_suspend(&dev
->dev
);
3134 dev
->wakeup_prepared
= false;
3137 dev
->pme_support
= 0;
3139 /* find PCI PM capability in list */
3140 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3143 /* Check device's ability to generate PME# */
3144 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
3146 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
3147 pci_err(dev
, "unsupported PM cap regs version (%u)\n",
3148 pmc
& PCI_PM_CAP_VER_MASK
);
3153 dev
->d3hot_delay
= PCI_PM_D3HOT_WAIT
;
3154 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
3155 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
3156 dev
->d3cold_allowed
= true;
3158 dev
->d1_support
= false;
3159 dev
->d2_support
= false;
3160 if (!pci_no_d1d2(dev
)) {
3161 if (pmc
& PCI_PM_CAP_D1
)
3162 dev
->d1_support
= true;
3163 if (pmc
& PCI_PM_CAP_D2
)
3164 dev
->d2_support
= true;
3166 if (dev
->d1_support
|| dev
->d2_support
)
3167 pci_info(dev
, "supports%s%s\n",
3168 dev
->d1_support
? " D1" : "",
3169 dev
->d2_support
? " D2" : "");
3172 pmc
&= PCI_PM_CAP_PME_MASK
;
3174 pci_info(dev
, "PME# supported from%s%s%s%s%s\n",
3175 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
3176 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
3177 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
3178 (pmc
& PCI_PM_CAP_PME_D3hot
) ? " D3hot" : "",
3179 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
3180 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
3181 dev
->pme_poll
= true;
3183 * Make device's PM flags reflect the wake-up capability, but
3184 * let the user space enable it to wake up the system as needed.
3186 device_set_wakeup_capable(&dev
->dev
, true);
3187 /* Disable the PME# generation functionality */
3188 pci_pme_active(dev
, false);
3191 pci_read_config_word(dev
, PCI_STATUS
, &status
);
3192 if (status
& PCI_STATUS_IMM_READY
)
3196 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
3198 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
3202 case PCI_EA_P_VF_MEM
:
3203 flags
|= IORESOURCE_MEM
;
3205 case PCI_EA_P_MEM_PREFETCH
:
3206 case PCI_EA_P_VF_MEM_PREFETCH
:
3207 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
3210 flags
|= IORESOURCE_IO
;
3219 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
3222 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
3223 return &dev
->resource
[bei
];
3224 #ifdef CONFIG_PCI_IOV
3225 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
3226 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
3227 return &dev
->resource
[PCI_IOV_RESOURCES
+
3228 bei
- PCI_EA_BEI_VF_BAR0
];
3230 else if (bei
== PCI_EA_BEI_ROM
)
3231 return &dev
->resource
[PCI_ROM_RESOURCE
];
3236 /* Read an Enhanced Allocation (EA) entry */
3237 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
3239 struct resource
*res
;
3240 int ent_size
, ent_offset
= offset
;
3241 resource_size_t start
, end
;
3242 unsigned long flags
;
3243 u32 dw0
, bei
, base
, max_offset
;
3245 bool support_64
= (sizeof(resource_size_t
) >= 8);
3247 pci_read_config_dword(dev
, ent_offset
, &dw0
);
3250 /* Entry size field indicates DWORDs after 1st */
3251 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
3253 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
3256 bei
= (dw0
& PCI_EA_BEI
) >> 4;
3257 prop
= (dw0
& PCI_EA_PP
) >> 8;
3260 * If the Property is in the reserved range, try the Secondary
3263 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
3264 prop
= (dw0
& PCI_EA_SP
) >> 16;
3265 if (prop
> PCI_EA_P_BRIDGE_IO
)
3268 res
= pci_ea_get_resource(dev
, bei
, prop
);
3270 pci_err(dev
, "Unsupported EA entry BEI: %u\n", bei
);
3274 flags
= pci_ea_flags(dev
, prop
);
3276 pci_err(dev
, "Unsupported EA properties: %#x\n", prop
);
3281 pci_read_config_dword(dev
, ent_offset
, &base
);
3282 start
= (base
& PCI_EA_FIELD_MASK
);
3285 /* Read MaxOffset */
3286 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
3289 /* Read Base MSBs (if 64-bit entry) */
3290 if (base
& PCI_EA_IS_64
) {
3293 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
3296 flags
|= IORESOURCE_MEM_64
;
3298 /* entry starts above 32-bit boundary, can't use */
3299 if (!support_64
&& base_upper
)
3303 start
|= ((u64
)base_upper
<< 32);
3306 end
= start
+ (max_offset
| 0x03);
3308 /* Read MaxOffset MSBs (if 64-bit entry) */
3309 if (max_offset
& PCI_EA_IS_64
) {
3310 u32 max_offset_upper
;
3312 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
3315 flags
|= IORESOURCE_MEM_64
;
3317 /* entry too big, can't use */
3318 if (!support_64
&& max_offset_upper
)
3322 end
+= ((u64
)max_offset_upper
<< 32);
3326 pci_err(dev
, "EA Entry crosses address boundary\n");
3330 if (ent_size
!= ent_offset
- offset
) {
3331 pci_err(dev
, "EA Entry Size (%d) does not match length read (%d)\n",
3332 ent_size
, ent_offset
- offset
);
3336 res
->name
= pci_name(dev
);
3341 if (bei
<= PCI_EA_BEI_BAR5
)
3342 pci_info(dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3344 else if (bei
== PCI_EA_BEI_ROM
)
3345 pci_info(dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3347 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
3348 pci_info(dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3349 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
3351 pci_info(dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3355 return offset
+ ent_size
;
3358 /* Enhanced Allocation Initialization */
3359 void pci_ea_init(struct pci_dev
*dev
)
3366 /* find PCI EA capability in list */
3367 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
3371 /* determine the number of entries */
3372 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
3374 num_ent
&= PCI_EA_NUM_ENT_MASK
;
3376 offset
= ea
+ PCI_EA_FIRST_ENT
;
3378 /* Skip DWORD 2 for type 1 functions */
3379 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
3382 /* parse each EA entry */
3383 for (i
= 0; i
< num_ent
; ++i
)
3384 offset
= pci_ea_read(dev
, offset
);
3387 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
3388 struct pci_cap_saved_state
*new_cap
)
3390 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
3394 * _pci_add_cap_save_buffer - allocate buffer for saving given
3395 * capability registers
3396 * @dev: the PCI device
3397 * @cap: the capability to allocate the buffer for
3398 * @extended: Standard or Extended capability ID
3399 * @size: requested size of the buffer
3401 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
3402 bool extended
, unsigned int size
)
3405 struct pci_cap_saved_state
*save_state
;
3408 pos
= pci_find_ext_capability(dev
, cap
);
3410 pos
= pci_find_capability(dev
, cap
);
3415 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
3419 save_state
->cap
.cap_nr
= cap
;
3420 save_state
->cap
.cap_extended
= extended
;
3421 save_state
->cap
.size
= size
;
3422 pci_add_saved_cap(dev
, save_state
);
3427 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
3429 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
3432 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
3434 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
3438 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3439 * @dev: the PCI device
3441 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
3445 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
3446 PCI_EXP_SAVE_REGS
* sizeof(u16
));
3448 pci_err(dev
, "unable to preallocate PCI Express save buffer\n");
3450 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
3452 pci_err(dev
, "unable to preallocate PCI-X save buffer\n");
3454 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_LTR
,
3457 pci_err(dev
, "unable to allocate suspend buffer for LTR\n");
3459 if (dmi_check_system(aspm_fix_whitelist
)) {
3460 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_L1SS
,
3463 pci_err(dev
, "unable to allocate suspend buffer for ASPM-L1SS\n");
3466 pci_allocate_vc_save_buffers(dev
);
3469 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
3471 struct pci_cap_saved_state
*tmp
;
3472 struct hlist_node
*n
;
3474 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
3479 * pci_configure_ari - enable or disable ARI forwarding
3480 * @dev: the PCI device
3482 * If @dev and its upstream bridge both support ARI, enable ARI in the
3483 * bridge. Otherwise, disable ARI in the bridge.
3485 void pci_configure_ari(struct pci_dev
*dev
)
3488 struct pci_dev
*bridge
;
3490 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
3493 bridge
= dev
->bus
->self
;
3497 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3498 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
3501 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
3502 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
3503 PCI_EXP_DEVCTL2_ARI
);
3504 bridge
->ari_enabled
= 1;
3506 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
3507 PCI_EXP_DEVCTL2_ARI
);
3508 bridge
->ari_enabled
= 0;
3512 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3517 pos
= pdev
->acs_cap
;
3522 * Except for egress control, capabilities are either required
3523 * or only required if controllable. Features missing from the
3524 * capability field can therefore be assumed as hard-wired enabled.
3526 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
3527 acs_flags
&= (cap
| PCI_ACS_EC
);
3529 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
3530 return (ctrl
& acs_flags
) == acs_flags
;
3534 * pci_acs_enabled - test ACS against required flags for a given device
3535 * @pdev: device to test
3536 * @acs_flags: required PCI ACS flags
3538 * Return true if the device supports the provided flags. Automatically
3539 * filters out flags that are not implemented on multifunction devices.
3541 * Note that this interface checks the effective ACS capabilities of the
3542 * device rather than the actual capabilities. For instance, most single
3543 * function endpoints are not required to support ACS because they have no
3544 * opportunity for peer-to-peer access. We therefore return 'true'
3545 * regardless of whether the device exposes an ACS capability. This makes
3546 * it much easier for callers of this function to ignore the actual type
3547 * or topology of the device when testing ACS support.
3549 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3553 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
3558 * Conventional PCI and PCI-X devices never support ACS, either
3559 * effectively or actually. The shared bus topology implies that
3560 * any device on the bus can receive or snoop DMA.
3562 if (!pci_is_pcie(pdev
))
3565 switch (pci_pcie_type(pdev
)) {
3567 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3568 * but since their primary interface is PCI/X, we conservatively
3569 * handle them as we would a non-PCIe device.
3571 case PCI_EXP_TYPE_PCIE_BRIDGE
:
3573 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3574 * applicable... must never implement an ACS Extended Capability...".
3575 * This seems arbitrary, but we take a conservative interpretation
3576 * of this statement.
3578 case PCI_EXP_TYPE_PCI_BRIDGE
:
3579 case PCI_EXP_TYPE_RC_EC
:
3582 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3583 * implement ACS in order to indicate their peer-to-peer capabilities,
3584 * regardless of whether they are single- or multi-function devices.
3586 case PCI_EXP_TYPE_DOWNSTREAM
:
3587 case PCI_EXP_TYPE_ROOT_PORT
:
3588 return pci_acs_flags_enabled(pdev
, acs_flags
);
3590 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3591 * implemented by the remaining PCIe types to indicate peer-to-peer
3592 * capabilities, but only when they are part of a multifunction
3593 * device. The footnote for section 6.12 indicates the specific
3594 * PCIe types included here.
3596 case PCI_EXP_TYPE_ENDPOINT
:
3597 case PCI_EXP_TYPE_UPSTREAM
:
3598 case PCI_EXP_TYPE_LEG_END
:
3599 case PCI_EXP_TYPE_RC_END
:
3600 if (!pdev
->multifunction
)
3603 return pci_acs_flags_enabled(pdev
, acs_flags
);
3607 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3608 * to single function devices with the exception of downstream ports.
3614 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3615 * @start: starting downstream device
3616 * @end: ending upstream device or NULL to search to the root bus
3617 * @acs_flags: required flags
3619 * Walk up a device tree from start to end testing PCI ACS support. If
3620 * any step along the way does not support the required flags, return false.
3622 bool pci_acs_path_enabled(struct pci_dev
*start
,
3623 struct pci_dev
*end
, u16 acs_flags
)
3625 struct pci_dev
*pdev
, *parent
= start
;
3630 if (!pci_acs_enabled(pdev
, acs_flags
))
3633 if (pci_is_root_bus(pdev
->bus
))
3634 return (end
== NULL
);
3636 parent
= pdev
->bus
->self
;
3637 } while (pdev
!= end
);
3643 * pci_acs_init - Initialize ACS if hardware supports it
3644 * @dev: the PCI device
3646 void pci_acs_init(struct pci_dev
*dev
)
3648 dev
->acs_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
3651 * Attempt to enable ACS regardless of capability because some Root
3652 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3653 * the standard ACS capability but still support ACS via those
3656 pci_enable_acs(dev
);
3660 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3664 * Helper to find the position of the ctrl register for a BAR.
3665 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3666 * Returns -ENOENT if no ctrl register for the BAR could be found.
3668 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3670 unsigned int pos
, nbars
, i
;
3673 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3677 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3678 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3679 PCI_REBAR_CTRL_NBAR_SHIFT
;
3681 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3684 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3685 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3694 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3696 * @bar: BAR to query
3698 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3699 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3701 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3706 pos
= pci_rebar_find_pos(pdev
, bar
);
3710 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3711 cap
&= PCI_REBAR_CAP_SIZES
;
3713 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3714 if (pdev
->vendor
== PCI_VENDOR_ID_ATI
&& pdev
->device
== 0x731f &&
3715 bar
== 0 && cap
== 0x7000)
3720 EXPORT_SYMBOL(pci_rebar_get_possible_sizes
);
3723 * pci_rebar_get_current_size - get the current size of a BAR
3725 * @bar: BAR to set size to
3727 * Read the size of a BAR from the resizable BAR config.
3728 * Returns size if found or negative error code.
3730 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3735 pos
= pci_rebar_find_pos(pdev
, bar
);
3739 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3740 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> PCI_REBAR_CTRL_BAR_SHIFT
;
3744 * pci_rebar_set_size - set a new size for a BAR
3746 * @bar: BAR to set size to
3747 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3749 * Set the new size of a BAR as defined in the spec.
3750 * Returns zero if resizing was successful, error code otherwise.
3752 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3757 pos
= pci_rebar_find_pos(pdev
, bar
);
3761 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3762 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3763 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
3764 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3769 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3770 * @dev: the PCI device
3771 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3772 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3773 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3774 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3776 * Return 0 if all upstream bridges support AtomicOp routing, egress
3777 * blocking is disabled on all upstream ports, and the root port supports
3778 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3779 * AtomicOp completion), or negative otherwise.
3781 int pci_enable_atomic_ops_to_root(struct pci_dev
*dev
, u32 cap_mask
)
3783 struct pci_bus
*bus
= dev
->bus
;
3784 struct pci_dev
*bridge
;
3788 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3789 * in Device Control 2 is reserved in VFs and the PF value applies
3790 * to all associated VFs.
3795 if (!pci_is_pcie(dev
))
3799 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3800 * AtomicOp requesters. For now, we only support endpoints as
3801 * requesters and root ports as completers. No endpoints as
3802 * completers, and no peer-to-peer.
3805 switch (pci_pcie_type(dev
)) {
3806 case PCI_EXP_TYPE_ENDPOINT
:
3807 case PCI_EXP_TYPE_LEG_END
:
3808 case PCI_EXP_TYPE_RC_END
:
3814 while (bus
->parent
) {
3817 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3819 switch (pci_pcie_type(bridge
)) {
3820 /* Ensure switch ports support AtomicOp routing */
3821 case PCI_EXP_TYPE_UPSTREAM
:
3822 case PCI_EXP_TYPE_DOWNSTREAM
:
3823 if (!(cap
& PCI_EXP_DEVCAP2_ATOMIC_ROUTE
))
3827 /* Ensure root port supports all the sizes we care about */
3828 case PCI_EXP_TYPE_ROOT_PORT
:
3829 if ((cap
& cap_mask
) != cap_mask
)
3834 /* Ensure upstream ports don't block AtomicOps on egress */
3835 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
) {
3836 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
,
3838 if (ctl2
& PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
)
3845 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
3846 PCI_EXP_DEVCTL2_ATOMIC_REQ
);
3849 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root
);
3852 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3853 * @dev: the PCI device
3854 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3856 * Perform INTx swizzling for a device behind one level of bridge. This is
3857 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3858 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3859 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3860 * the PCI Express Base Specification, Revision 2.1)
3862 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3866 if (pci_ari_enabled(dev
->bus
))
3869 slot
= PCI_SLOT(dev
->devfn
);
3871 return (((pin
- 1) + slot
) % 4) + 1;
3874 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3882 while (!pci_is_root_bus(dev
->bus
)) {
3883 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3884 dev
= dev
->bus
->self
;
3891 * pci_common_swizzle - swizzle INTx all the way to root bridge
3892 * @dev: the PCI device
3893 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3895 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3896 * bridges all the way up to a PCI root bus.
3898 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3902 while (!pci_is_root_bus(dev
->bus
)) {
3903 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3904 dev
= dev
->bus
->self
;
3907 return PCI_SLOT(dev
->devfn
);
3909 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3912 * pci_release_region - Release a PCI bar
3913 * @pdev: PCI device whose resources were previously reserved by
3914 * pci_request_region()
3915 * @bar: BAR to release
3917 * Releases the PCI I/O and memory resources previously reserved by a
3918 * successful call to pci_request_region(). Call this function only
3919 * after all use of the PCI regions has ceased.
3921 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3923 struct pci_devres
*dr
;
3925 if (pci_resource_len(pdev
, bar
) == 0)
3927 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3928 release_region(pci_resource_start(pdev
, bar
),
3929 pci_resource_len(pdev
, bar
));
3930 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3931 release_mem_region(pci_resource_start(pdev
, bar
),
3932 pci_resource_len(pdev
, bar
));
3934 dr
= find_pci_dr(pdev
);
3936 dr
->region_mask
&= ~(1 << bar
);
3938 EXPORT_SYMBOL(pci_release_region
);
3941 * __pci_request_region - Reserved PCI I/O and memory resource
3942 * @pdev: PCI device whose resources are to be reserved
3943 * @bar: BAR to be reserved
3944 * @res_name: Name to be associated with resource.
3945 * @exclusive: whether the region access is exclusive or not
3947 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3948 * being reserved by owner @res_name. Do not access any
3949 * address inside the PCI regions unless this call returns
3952 * If @exclusive is set, then the region is marked so that userspace
3953 * is explicitly not allowed to map the resource via /dev/mem or
3954 * sysfs MMIO access.
3956 * Returns 0 on success, or %EBUSY on error. A warning
3957 * message is also printed on failure.
3959 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3960 const char *res_name
, int exclusive
)
3962 struct pci_devres
*dr
;
3964 if (pci_resource_len(pdev
, bar
) == 0)
3967 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3968 if (!request_region(pci_resource_start(pdev
, bar
),
3969 pci_resource_len(pdev
, bar
), res_name
))
3971 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3972 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3973 pci_resource_len(pdev
, bar
), res_name
,
3978 dr
= find_pci_dr(pdev
);
3980 dr
->region_mask
|= 1 << bar
;
3985 pci_warn(pdev
, "BAR %d: can't reserve %pR\n", bar
,
3986 &pdev
->resource
[bar
]);
3991 * pci_request_region - Reserve PCI I/O and memory resource
3992 * @pdev: PCI device whose resources are to be reserved
3993 * @bar: BAR to be reserved
3994 * @res_name: Name to be associated with resource
3996 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3997 * being reserved by owner @res_name. Do not access any
3998 * address inside the PCI regions unless this call returns
4001 * Returns 0 on success, or %EBUSY on error. A warning
4002 * message is also printed on failure.
4004 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
4006 return __pci_request_region(pdev
, bar
, res_name
, 0);
4008 EXPORT_SYMBOL(pci_request_region
);
4011 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4012 * @pdev: PCI device whose resources were previously reserved
4013 * @bars: Bitmask of BARs to be released
4015 * Release selected PCI I/O and memory resources previously reserved.
4016 * Call this function only after all use of the PCI regions has ceased.
4018 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
4022 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
4023 if (bars
& (1 << i
))
4024 pci_release_region(pdev
, i
);
4026 EXPORT_SYMBOL(pci_release_selected_regions
);
4028 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
4029 const char *res_name
, int excl
)
4033 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
4034 if (bars
& (1 << i
))
4035 if (__pci_request_region(pdev
, i
, res_name
, excl
))
4041 if (bars
& (1 << i
))
4042 pci_release_region(pdev
, i
);
4049 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4050 * @pdev: PCI device whose resources are to be reserved
4051 * @bars: Bitmask of BARs to be requested
4052 * @res_name: Name to be associated with resource
4054 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
4055 const char *res_name
)
4057 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
4059 EXPORT_SYMBOL(pci_request_selected_regions
);
4061 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
4062 const char *res_name
)
4064 return __pci_request_selected_regions(pdev
, bars
, res_name
,
4065 IORESOURCE_EXCLUSIVE
);
4067 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
4070 * pci_release_regions - Release reserved PCI I/O and memory resources
4071 * @pdev: PCI device whose resources were previously reserved by
4072 * pci_request_regions()
4074 * Releases all PCI I/O and memory resources previously reserved by a
4075 * successful call to pci_request_regions(). Call this function only
4076 * after all use of the PCI regions has ceased.
4079 void pci_release_regions(struct pci_dev
*pdev
)
4081 pci_release_selected_regions(pdev
, (1 << PCI_STD_NUM_BARS
) - 1);
4083 EXPORT_SYMBOL(pci_release_regions
);
4086 * pci_request_regions - Reserve PCI I/O and memory resources
4087 * @pdev: PCI device whose resources are to be reserved
4088 * @res_name: Name to be associated with resource.
4090 * Mark all PCI regions associated with PCI device @pdev as
4091 * being reserved by owner @res_name. Do not access any
4092 * address inside the PCI regions unless this call returns
4095 * Returns 0 on success, or %EBUSY on error. A warning
4096 * message is also printed on failure.
4098 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
4100 return pci_request_selected_regions(pdev
,
4101 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4103 EXPORT_SYMBOL(pci_request_regions
);
4106 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4107 * @pdev: PCI device whose resources are to be reserved
4108 * @res_name: Name to be associated with resource.
4110 * Mark all PCI regions associated with PCI device @pdev as being reserved
4111 * by owner @res_name. Do not access any address inside the PCI regions
4112 * unless this call returns successfully.
4114 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4115 * and the sysfs MMIO access will not be allowed.
4117 * Returns 0 on success, or %EBUSY on error. A warning message is also
4118 * printed on failure.
4120 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
4122 return pci_request_selected_regions_exclusive(pdev
,
4123 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4125 EXPORT_SYMBOL(pci_request_regions_exclusive
);
4128 * Record the PCI IO range (expressed as CPU physical address + size).
4129 * Return a negative value if an error has occurred, zero otherwise
4131 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
4132 resource_size_t size
)
4136 struct logic_pio_hwaddr
*range
;
4138 if (!size
|| addr
+ size
< addr
)
4141 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
4145 range
->fwnode
= fwnode
;
4147 range
->hw_start
= addr
;
4148 range
->flags
= LOGIC_PIO_CPU_MMIO
;
4150 ret
= logic_pio_register_range(range
);
4154 /* Ignore duplicates due to deferred probing */
4162 phys_addr_t
pci_pio_to_address(unsigned long pio
)
4164 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
4167 if (pio
>= MMIO_UPPER_LIMIT
)
4170 address
= logic_pio_to_hwaddr(pio
);
4175 EXPORT_SYMBOL_GPL(pci_pio_to_address
);
4177 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
4180 return logic_pio_trans_cpuaddr(address
);
4182 if (address
> IO_SPACE_LIMIT
)
4183 return (unsigned long)-1;
4185 return (unsigned long) address
;
4190 * pci_remap_iospace - Remap the memory mapped I/O space
4191 * @res: Resource describing the I/O space
4192 * @phys_addr: physical address of range to be mapped
4194 * Remap the memory mapped I/O space described by the @res and the CPU
4195 * physical address @phys_addr into virtual address space. Only
4196 * architectures that have memory mapped IO functions defined (and the
4197 * PCI_IOBASE value defined) should call this function.
4199 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
4201 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4202 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4204 if (!(res
->flags
& IORESOURCE_IO
))
4207 if (res
->end
> IO_SPACE_LIMIT
)
4210 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
4211 pgprot_device(PAGE_KERNEL
));
4214 * This architecture does not have memory mapped I/O space,
4215 * so this function should never be called
4217 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4221 EXPORT_SYMBOL(pci_remap_iospace
);
4224 * pci_unmap_iospace - Unmap the memory mapped I/O space
4225 * @res: resource to be unmapped
4227 * Unmap the CPU virtual address @res from virtual address space. Only
4228 * architectures that have memory mapped IO functions defined (and the
4229 * PCI_IOBASE value defined) should call this function.
4231 void pci_unmap_iospace(struct resource
*res
)
4233 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4234 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4236 vunmap_range(vaddr
, vaddr
+ resource_size(res
));
4239 EXPORT_SYMBOL(pci_unmap_iospace
);
4241 static void devm_pci_unmap_iospace(struct device
*dev
, void *ptr
)
4243 struct resource
**res
= ptr
;
4245 pci_unmap_iospace(*res
);
4249 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4250 * @dev: Generic device to remap IO address for
4251 * @res: Resource describing the I/O space
4252 * @phys_addr: physical address of range to be mapped
4254 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4257 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
4258 phys_addr_t phys_addr
)
4260 const struct resource
**ptr
;
4263 ptr
= devres_alloc(devm_pci_unmap_iospace
, sizeof(*ptr
), GFP_KERNEL
);
4267 error
= pci_remap_iospace(res
, phys_addr
);
4272 devres_add(dev
, ptr
);
4277 EXPORT_SYMBOL(devm_pci_remap_iospace
);
4280 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4281 * @dev: Generic device to remap IO address for
4282 * @offset: Resource address to map
4283 * @size: Size of map
4285 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4288 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
4289 resource_size_t offset
,
4290 resource_size_t size
)
4292 void __iomem
**ptr
, *addr
;
4294 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
4298 addr
= pci_remap_cfgspace(offset
, size
);
4301 devres_add(dev
, ptr
);
4307 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
4310 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4311 * @dev: generic device to handle the resource for
4312 * @res: configuration space resource to be handled
4314 * Checks that a resource is a valid memory region, requests the memory
4315 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4316 * proper PCI configuration space memory attributes are guaranteed.
4318 * All operations are managed and will be undone on driver detach.
4320 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4321 * on failure. Usage example::
4323 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4324 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4326 * return PTR_ERR(base);
4328 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
4329 struct resource
*res
)
4331 resource_size_t size
;
4333 void __iomem
*dest_ptr
;
4337 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
4338 dev_err(dev
, "invalid resource\n");
4339 return IOMEM_ERR_PTR(-EINVAL
);
4342 size
= resource_size(res
);
4345 name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s %s", dev_name(dev
),
4348 name
= devm_kstrdup(dev
, dev_name(dev
), GFP_KERNEL
);
4350 return IOMEM_ERR_PTR(-ENOMEM
);
4352 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
4353 dev_err(dev
, "can't request region for resource %pR\n", res
);
4354 return IOMEM_ERR_PTR(-EBUSY
);
4357 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
4359 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
4360 devm_release_mem_region(dev
, res
->start
, size
);
4361 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
4366 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
4368 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
4372 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
4374 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
4376 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
4377 if (cmd
!= old_cmd
) {
4378 pci_dbg(dev
, "%s bus mastering\n",
4379 enable
? "enabling" : "disabling");
4380 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4382 dev
->is_busmaster
= enable
;
4386 * pcibios_setup - process "pci=" kernel boot arguments
4387 * @str: string used to pass in "pci=" kernel boot arguments
4389 * Process kernel boot arguments. This is the default implementation.
4390 * Architecture specific implementations can override this as necessary.
4392 char * __weak __init
pcibios_setup(char *str
)
4398 * pcibios_set_master - enable PCI bus-mastering for device dev
4399 * @dev: the PCI device to enable
4401 * Enables PCI bus-mastering for the device. This is the default
4402 * implementation. Architecture specific implementations can override
4403 * this if necessary.
4405 void __weak
pcibios_set_master(struct pci_dev
*dev
)
4409 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4410 if (pci_is_pcie(dev
))
4413 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
4415 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
4416 else if (lat
> pcibios_max_latency
)
4417 lat
= pcibios_max_latency
;
4421 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
4425 * pci_set_master - enables bus-mastering for device dev
4426 * @dev: the PCI device to enable
4428 * Enables bus-mastering on the device and calls pcibios_set_master()
4429 * to do the needed arch specific settings.
4431 void pci_set_master(struct pci_dev
*dev
)
4433 __pci_set_master(dev
, true);
4434 pcibios_set_master(dev
);
4436 EXPORT_SYMBOL(pci_set_master
);
4439 * pci_clear_master - disables bus-mastering for device dev
4440 * @dev: the PCI device to disable
4442 void pci_clear_master(struct pci_dev
*dev
)
4444 __pci_set_master(dev
, false);
4446 EXPORT_SYMBOL(pci_clear_master
);
4449 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4450 * @dev: the PCI device for which MWI is to be enabled
4452 * Helper function for pci_set_mwi.
4453 * Originally copied from drivers/net/acenic.c.
4454 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4456 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4458 int pci_set_cacheline_size(struct pci_dev
*dev
)
4462 if (!pci_cache_line_size
)
4465 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4466 equal to or multiple of the right value. */
4467 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4468 if (cacheline_size
>= pci_cache_line_size
&&
4469 (cacheline_size
% pci_cache_line_size
) == 0)
4472 /* Write the correct value. */
4473 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
4475 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4476 if (cacheline_size
== pci_cache_line_size
)
4479 pci_dbg(dev
, "cache line size of %d is not supported\n",
4480 pci_cache_line_size
<< 2);
4484 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
4487 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4488 * @dev: the PCI device for which MWI is enabled
4490 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4492 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4494 int pci_set_mwi(struct pci_dev
*dev
)
4496 #ifdef PCI_DISABLE_MWI
4502 rc
= pci_set_cacheline_size(dev
);
4506 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4507 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
4508 pci_dbg(dev
, "enabling Mem-Wr-Inval\n");
4509 cmd
|= PCI_COMMAND_INVALIDATE
;
4510 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4515 EXPORT_SYMBOL(pci_set_mwi
);
4518 * pcim_set_mwi - a device-managed pci_set_mwi()
4519 * @dev: the PCI device for which MWI is enabled
4521 * Managed pci_set_mwi().
4523 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4525 int pcim_set_mwi(struct pci_dev
*dev
)
4527 struct pci_devres
*dr
;
4529 dr
= find_pci_dr(dev
);
4534 return pci_set_mwi(dev
);
4536 EXPORT_SYMBOL(pcim_set_mwi
);
4539 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4540 * @dev: the PCI device for which MWI is enabled
4542 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4543 * Callers are not required to check the return value.
4545 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4547 int pci_try_set_mwi(struct pci_dev
*dev
)
4549 #ifdef PCI_DISABLE_MWI
4552 return pci_set_mwi(dev
);
4555 EXPORT_SYMBOL(pci_try_set_mwi
);
4558 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4559 * @dev: the PCI device to disable
4561 * Disables PCI Memory-Write-Invalidate transaction on the device
4563 void pci_clear_mwi(struct pci_dev
*dev
)
4565 #ifndef PCI_DISABLE_MWI
4568 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4569 if (cmd
& PCI_COMMAND_INVALIDATE
) {
4570 cmd
&= ~PCI_COMMAND_INVALIDATE
;
4571 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4575 EXPORT_SYMBOL(pci_clear_mwi
);
4578 * pci_disable_parity - disable parity checking for device
4579 * @dev: the PCI device to operate on
4581 * Disable parity checking for device @dev
4583 void pci_disable_parity(struct pci_dev
*dev
)
4587 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4588 if (cmd
& PCI_COMMAND_PARITY
) {
4589 cmd
&= ~PCI_COMMAND_PARITY
;
4590 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4595 * pci_intx - enables/disables PCI INTx for device dev
4596 * @pdev: the PCI device to operate on
4597 * @enable: boolean: whether to enable or disable PCI INTx
4599 * Enables/disables PCI INTx for device @pdev
4601 void pci_intx(struct pci_dev
*pdev
, int enable
)
4603 u16 pci_command
, new;
4605 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
4608 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
4610 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
4612 if (new != pci_command
) {
4613 struct pci_devres
*dr
;
4615 pci_write_config_word(pdev
, PCI_COMMAND
, new);
4617 dr
= find_pci_dr(pdev
);
4618 if (dr
&& !dr
->restore_intx
) {
4619 dr
->restore_intx
= 1;
4620 dr
->orig_intx
= !enable
;
4624 EXPORT_SYMBOL_GPL(pci_intx
);
4626 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
4628 struct pci_bus
*bus
= dev
->bus
;
4629 bool mask_updated
= true;
4630 u32 cmd_status_dword
;
4631 u16 origcmd
, newcmd
;
4632 unsigned long flags
;
4636 * We do a single dword read to retrieve both command and status.
4637 * Document assumptions that make this possible.
4639 BUILD_BUG_ON(PCI_COMMAND
% 4);
4640 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
4642 raw_spin_lock_irqsave(&pci_lock
, flags
);
4644 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
4646 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
4649 * Check interrupt status register to see whether our device
4650 * triggered the interrupt (when masking) or the next IRQ is
4651 * already pending (when unmasking).
4653 if (mask
!= irq_pending
) {
4654 mask_updated
= false;
4658 origcmd
= cmd_status_dword
;
4659 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
4661 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
4662 if (newcmd
!= origcmd
)
4663 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
4666 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
4668 return mask_updated
;
4672 * pci_check_and_mask_intx - mask INTx on pending interrupt
4673 * @dev: the PCI device to operate on
4675 * Check if the device dev has its INTx line asserted, mask it and return
4676 * true in that case. False is returned if no interrupt was pending.
4678 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
4680 return pci_check_and_set_intx_mask(dev
, true);
4682 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
4685 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4686 * @dev: the PCI device to operate on
4688 * Check if the device dev has its INTx line asserted, unmask it if not and
4689 * return true. False is returned and the mask remains active if there was
4690 * still an interrupt pending.
4692 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
4694 return pci_check_and_set_intx_mask(dev
, false);
4696 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
4699 * pci_wait_for_pending_transaction - wait for pending transaction
4700 * @dev: the PCI device to operate on
4702 * Return 0 if transaction is pending 1 otherwise.
4704 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
4706 if (!pci_is_pcie(dev
))
4709 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
4710 PCI_EXP_DEVSTA_TRPND
);
4712 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
4715 * pcie_flr - initiate a PCIe function level reset
4716 * @dev: device to reset
4718 * Initiate a function level reset unconditionally on @dev without
4719 * checking any flags and DEVCAP
4721 int pcie_flr(struct pci_dev
*dev
)
4723 if (!pci_wait_for_pending_transaction(dev
))
4724 pci_err(dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
4726 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
4732 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4733 * 100ms, but may silently discard requests while the FLR is in
4734 * progress. Wait 100ms before trying to access the device.
4738 return pci_dev_wait(dev
, "FLR", PCIE_RESET_READY_POLL_MS
);
4740 EXPORT_SYMBOL_GPL(pcie_flr
);
4743 * pcie_reset_flr - initiate a PCIe function level reset
4744 * @dev: device to reset
4745 * @probe: if true, return 0 if device can be reset this way
4747 * Initiate a function level reset on @dev.
4749 int pcie_reset_flr(struct pci_dev
*dev
, bool probe
)
4751 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4754 if (!(dev
->devcap
& PCI_EXP_DEVCAP_FLR
))
4760 return pcie_flr(dev
);
4762 EXPORT_SYMBOL_GPL(pcie_reset_flr
);
4764 static int pci_af_flr(struct pci_dev
*dev
, bool probe
)
4769 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4773 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4776 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4777 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4784 * Wait for Transaction Pending bit to clear. A word-aligned test
4785 * is used, so we use the control offset rather than status and shift
4786 * the test bit to match.
4788 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4789 PCI_AF_STATUS_TP
<< 8))
4790 pci_err(dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4792 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4798 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4799 * updated 27 July 2006; a device must complete an FLR within
4800 * 100ms, but may silently discard requests while the FLR is in
4801 * progress. Wait 100ms before trying to access the device.
4805 return pci_dev_wait(dev
, "AF_FLR", PCIE_RESET_READY_POLL_MS
);
4809 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4810 * @dev: Device to reset.
4811 * @probe: if true, return 0 if the device can be reset this way.
4813 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4814 * unset, it will be reinitialized internally when going from PCI_D3hot to
4815 * PCI_D0. If that's the case and the device is not in a low-power state
4816 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4818 * NOTE: This causes the caller to sleep for twice the device power transition
4819 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4820 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4821 * Moreover, only devices in D0 can be reset by this function.
4823 static int pci_pm_reset(struct pci_dev
*dev
, bool probe
)
4827 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4830 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4831 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4837 if (dev
->current_state
!= PCI_D0
)
4840 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4842 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4843 pci_dev_d3_sleep(dev
);
4845 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4847 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4848 pci_dev_d3_sleep(dev
);
4850 return pci_dev_wait(dev
, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS
);
4854 * pcie_wait_for_link_delay - Wait until link is active or inactive
4855 * @pdev: Bridge device
4856 * @active: waiting for active or inactive?
4857 * @delay: Delay to wait after link has become active (in ms)
4859 * Use this to wait till link becomes active or inactive.
4861 static bool pcie_wait_for_link_delay(struct pci_dev
*pdev
, bool active
,
4869 * Some controllers might not implement link active reporting. In this
4870 * case, we wait for 1000 ms + any delay requested by the caller.
4872 if (!pdev
->link_active_reporting
) {
4873 msleep(timeout
+ delay
);
4878 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4879 * after which we should expect an link active if the reset was
4880 * successful. If so, software must wait a minimum 100ms before sending
4881 * configuration requests to devices downstream this port.
4883 * If the link fails to activate, either the device was physically
4884 * removed or the link is permanently failed.
4889 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
4890 ret
= !!(lnk_status
& PCI_EXP_LNKSTA_DLLLA
);
4901 return ret
== active
;
4905 * pcie_wait_for_link - Wait until link is active or inactive
4906 * @pdev: Bridge device
4907 * @active: waiting for active or inactive?
4909 * Use this to wait till link becomes active or inactive.
4911 bool pcie_wait_for_link(struct pci_dev
*pdev
, bool active
)
4913 return pcie_wait_for_link_delay(pdev
, active
, 100);
4917 * Find maximum D3cold delay required by all the devices on the bus. The
4918 * spec says 100 ms, but firmware can lower it and we allow drivers to
4919 * increase it as well.
4921 * Called with @pci_bus_sem locked for reading.
4923 static int pci_bus_max_d3cold_delay(const struct pci_bus
*bus
)
4925 const struct pci_dev
*pdev
;
4926 int min_delay
= 100;
4929 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
4930 if (pdev
->d3cold_delay
< min_delay
)
4931 min_delay
= pdev
->d3cold_delay
;
4932 if (pdev
->d3cold_delay
> max_delay
)
4933 max_delay
= pdev
->d3cold_delay
;
4936 return max(min_delay
, max_delay
);
4940 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4943 * Handle necessary delays before access to the devices on the secondary
4944 * side of the bridge are permitted after D3cold to D0 transition.
4946 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4947 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4950 void pci_bridge_wait_for_secondary_bus(struct pci_dev
*dev
)
4952 struct pci_dev
*child
;
4955 if (pci_dev_is_disconnected(dev
))
4958 if (!pci_is_bridge(dev
) || !dev
->bridge_d3
)
4961 down_read(&pci_bus_sem
);
4964 * We only deal with devices that are present currently on the bus.
4965 * For any hot-added devices the access delay is handled in pciehp
4966 * board_added(). In case of ACPI hotplug the firmware is expected
4967 * to configure the devices before OS is notified.
4969 if (!dev
->subordinate
|| list_empty(&dev
->subordinate
->devices
)) {
4970 up_read(&pci_bus_sem
);
4974 /* Take d3cold_delay requirements into account */
4975 delay
= pci_bus_max_d3cold_delay(dev
->subordinate
);
4977 up_read(&pci_bus_sem
);
4981 child
= list_first_entry(&dev
->subordinate
->devices
, struct pci_dev
,
4983 up_read(&pci_bus_sem
);
4986 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4987 * accessing the device after reset (that is 1000 ms + 100 ms). In
4988 * practice this should not be needed because we don't do power
4989 * management for them (see pci_bridge_d3_possible()).
4991 if (!pci_is_pcie(dev
)) {
4992 pci_dbg(dev
, "waiting %d ms for secondary bus\n", 1000 + delay
);
4993 msleep(1000 + delay
);
4998 * For PCIe downstream and root ports that do not support speeds
4999 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5000 * speeds (gen3) we need to wait first for the data link layer to
5003 * However, 100 ms is the minimum and the PCIe spec says the
5004 * software must allow at least 1s before it can determine that the
5005 * device that did not respond is a broken device. There is
5006 * evidence that 100 ms is not always enough, for example certain
5007 * Titan Ridge xHCI controller does not always respond to
5008 * configuration requests if we only wait for 100 ms (see
5009 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
5011 * Therefore we wait for 100 ms and check for the device presence.
5012 * If it is still not present give it an additional 100 ms.
5014 if (!pcie_downstream_port(dev
))
5017 if (pcie_get_speed_cap(dev
) <= PCIE_SPEED_5_0GT
) {
5018 pci_dbg(dev
, "waiting %d ms for downstream link\n", delay
);
5021 pci_dbg(dev
, "waiting %d ms for downstream link, after activation\n",
5023 if (!pcie_wait_for_link_delay(dev
, true, delay
)) {
5024 /* Did not train, no need to wait any further */
5025 pci_info(dev
, "Data Link Layer Link Active not set in 1000 msec\n");
5030 if (!pci_device_is_present(child
)) {
5031 pci_dbg(child
, "waiting additional %d ms to become accessible\n", delay
);
5036 void pci_reset_secondary_bus(struct pci_dev
*dev
)
5040 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
5041 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
5042 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5045 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5046 * this to 2ms to ensure that we meet the minimum requirement.
5050 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
5051 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5054 * Trhfa for conventional PCI is 2^25 clock cycles.
5055 * Assuming a minimum 33MHz clock this results in a 1s
5056 * delay before we can consider subordinate devices to
5057 * be re-initialized. PCIe has some ways to shorten this,
5058 * but we don't make use of them yet.
5063 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
5065 pci_reset_secondary_bus(dev
);
5069 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5070 * @dev: Bridge device
5072 * Use the bridge control register to assert reset on the secondary bus.
5073 * Devices on the secondary bus are left in power-on state.
5075 int pci_bridge_secondary_bus_reset(struct pci_dev
*dev
)
5077 pcibios_reset_secondary_bus(dev
);
5079 return pci_dev_wait(dev
, "bus reset", PCIE_RESET_READY_POLL_MS
);
5081 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset
);
5083 static int pci_parent_bus_reset(struct pci_dev
*dev
, bool probe
)
5085 struct pci_dev
*pdev
;
5087 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
5088 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5091 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
5098 return pci_bridge_secondary_bus_reset(dev
->bus
->self
);
5101 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, bool probe
)
5105 if (!hotplug
|| !try_module_get(hotplug
->owner
))
5108 if (hotplug
->ops
->reset_slot
)
5109 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
5111 module_put(hotplug
->owner
);
5116 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, bool probe
)
5118 if (dev
->multifunction
|| dev
->subordinate
|| !dev
->slot
||
5119 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5122 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
5125 static int pci_reset_bus_function(struct pci_dev
*dev
, bool probe
)
5129 rc
= pci_dev_reset_slot_function(dev
, probe
);
5132 return pci_parent_bus_reset(dev
, probe
);
5135 void pci_dev_lock(struct pci_dev
*dev
)
5137 /* block PM suspend, driver probe, etc. */
5138 device_lock(&dev
->dev
);
5139 pci_cfg_access_lock(dev
);
5141 EXPORT_SYMBOL_GPL(pci_dev_lock
);
5143 /* Return 1 on successful lock, 0 on contention */
5144 int pci_dev_trylock(struct pci_dev
*dev
)
5146 if (device_trylock(&dev
->dev
)) {
5147 if (pci_cfg_access_trylock(dev
))
5149 device_unlock(&dev
->dev
);
5154 EXPORT_SYMBOL_GPL(pci_dev_trylock
);
5156 void pci_dev_unlock(struct pci_dev
*dev
)
5158 pci_cfg_access_unlock(dev
);
5159 device_unlock(&dev
->dev
);
5161 EXPORT_SYMBOL_GPL(pci_dev_unlock
);
5163 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
5165 const struct pci_error_handlers
*err_handler
=
5166 dev
->driver
? dev
->driver
->err_handler
: NULL
;
5169 * dev->driver->err_handler->reset_prepare() is protected against
5170 * races with ->remove() by the device lock, which must be held by
5173 if (err_handler
&& err_handler
->reset_prepare
)
5174 err_handler
->reset_prepare(dev
);
5177 * Wake-up device prior to save. PM registers default to D0 after
5178 * reset and a simple register restore doesn't reliably return
5179 * to a non-D0 state anyway.
5181 pci_set_power_state(dev
, PCI_D0
);
5183 pci_save_state(dev
);
5185 * Disable the device by clearing the Command register, except for
5186 * INTx-disable which is set. This not only disables MMIO and I/O port
5187 * BARs, but also prevents the device from being Bus Master, preventing
5188 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5189 * compliant devices, INTx-disable prevents legacy interrupts.
5191 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
5194 static void pci_dev_restore(struct pci_dev
*dev
)
5196 const struct pci_error_handlers
*err_handler
=
5197 dev
->driver
? dev
->driver
->err_handler
: NULL
;
5199 pci_restore_state(dev
);
5202 * dev->driver->err_handler->reset_done() is protected against
5203 * races with ->remove() by the device lock, which must be held by
5206 if (err_handler
&& err_handler
->reset_done
)
5207 err_handler
->reset_done(dev
);
5210 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5211 static const struct pci_reset_fn_method pci_reset_fn_methods
[] = {
5213 { pci_dev_specific_reset
, .name
= "device_specific" },
5214 { pci_dev_acpi_reset
, .name
= "acpi" },
5215 { pcie_reset_flr
, .name
= "flr" },
5216 { pci_af_flr
, .name
= "af_flr" },
5217 { pci_pm_reset
, .name
= "pm" },
5218 { pci_reset_bus_function
, .name
= "bus" },
5221 static ssize_t
reset_method_show(struct device
*dev
,
5222 struct device_attribute
*attr
, char *buf
)
5224 struct pci_dev
*pdev
= to_pci_dev(dev
);
5228 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5229 m
= pdev
->reset_methods
[i
];
5233 len
+= sysfs_emit_at(buf
, len
, "%s%s", len
? " " : "",
5234 pci_reset_fn_methods
[m
].name
);
5238 len
+= sysfs_emit_at(buf
, len
, "\n");
5243 static int reset_method_lookup(const char *name
)
5247 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5248 if (sysfs_streq(name
, pci_reset_fn_methods
[m
].name
))
5252 return 0; /* not found */
5255 static ssize_t
reset_method_store(struct device
*dev
,
5256 struct device_attribute
*attr
,
5257 const char *buf
, size_t count
)
5259 struct pci_dev
*pdev
= to_pci_dev(dev
);
5260 char *options
, *name
;
5262 u8 reset_methods
[PCI_NUM_RESET_METHODS
] = { 0 };
5264 if (sysfs_streq(buf
, "")) {
5265 pdev
->reset_methods
[0] = 0;
5266 pci_warn(pdev
, "All device reset methods disabled by user");
5270 if (sysfs_streq(buf
, "default")) {
5271 pci_init_reset_methods(pdev
);
5275 options
= kstrndup(buf
, count
, GFP_KERNEL
);
5280 while ((name
= strsep(&options
, " ")) != NULL
) {
5281 if (sysfs_streq(name
, ""))
5286 m
= reset_method_lookup(name
);
5288 pci_err(pdev
, "Invalid reset method '%s'", name
);
5292 if (pci_reset_fn_methods
[m
].reset_fn(pdev
, PCI_RESET_PROBE
)) {
5293 pci_err(pdev
, "Unsupported reset method '%s'", name
);
5297 if (n
== PCI_NUM_RESET_METHODS
- 1) {
5298 pci_err(pdev
, "Too many reset methods\n");
5302 reset_methods
[n
++] = m
;
5305 reset_methods
[n
] = 0;
5307 /* Warn if dev-specific supported but not highest priority */
5308 if (pci_reset_fn_methods
[1].reset_fn(pdev
, PCI_RESET_PROBE
) == 0 &&
5309 reset_methods
[0] != 1)
5310 pci_warn(pdev
, "Device-specific reset disabled/de-prioritized by user");
5311 memcpy(pdev
->reset_methods
, reset_methods
, sizeof(pdev
->reset_methods
));
5316 /* Leave previous methods unchanged */
5320 static DEVICE_ATTR_RW(reset_method
);
5322 static struct attribute
*pci_dev_reset_method_attrs
[] = {
5323 &dev_attr_reset_method
.attr
,
5327 static umode_t
pci_dev_reset_method_attr_is_visible(struct kobject
*kobj
,
5328 struct attribute
*a
, int n
)
5330 struct pci_dev
*pdev
= to_pci_dev(kobj_to_dev(kobj
));
5332 if (!pci_reset_supported(pdev
))
5338 const struct attribute_group pci_dev_reset_method_attr_group
= {
5339 .attrs
= pci_dev_reset_method_attrs
,
5340 .is_visible
= pci_dev_reset_method_attr_is_visible
,
5344 * __pci_reset_function_locked - reset a PCI device function while holding
5345 * the @dev mutex lock.
5346 * @dev: PCI device to reset
5348 * Some devices allow an individual function to be reset without affecting
5349 * other functions in the same device. The PCI device must be responsive
5350 * to PCI config space in order to use this function.
5352 * The device function is presumed to be unused and the caller is holding
5353 * the device mutex lock when this function is called.
5355 * Resetting the device will make the contents of PCI configuration space
5356 * random, so any caller of this must be prepared to reinitialise the
5357 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5360 * Returns 0 if the device function was successfully reset or negative if the
5361 * device doesn't support resetting a single function.
5363 int __pci_reset_function_locked(struct pci_dev
*dev
)
5365 int i
, m
, rc
= -ENOTTY
;
5370 * A reset method returns -ENOTTY if it doesn't support this device and
5371 * we should try the next method.
5373 * If it returns 0 (success), we're finished. If it returns any other
5374 * error, we're also finished: this indicates that further reset
5375 * mechanisms might be broken on the device.
5377 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5378 m
= dev
->reset_methods
[i
];
5382 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_DO_RESET
);
5391 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
5394 * pci_init_reset_methods - check whether device can be safely reset
5395 * and store supported reset mechanisms.
5396 * @dev: PCI device to check for reset mechanisms
5398 * Some devices allow an individual function to be reset without affecting
5399 * other functions in the same device. The PCI device must be in D0-D3hot
5402 * Stores reset mechanisms supported by device in reset_methods byte array
5403 * which is a member of struct pci_dev.
5405 void pci_init_reset_methods(struct pci_dev
*dev
)
5409 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods
) != PCI_NUM_RESET_METHODS
);
5414 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5415 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_PROBE
);
5417 dev
->reset_methods
[i
++] = m
;
5418 else if (rc
!= -ENOTTY
)
5422 dev
->reset_methods
[i
] = 0;
5426 * pci_reset_function - quiesce and reset a PCI device function
5427 * @dev: PCI device to reset
5429 * Some devices allow an individual function to be reset without affecting
5430 * other functions in the same device. The PCI device must be responsive
5431 * to PCI config space in order to use this function.
5433 * This function does not just reset the PCI portion of a device, but
5434 * clears all the state associated with the device. This function differs
5435 * from __pci_reset_function_locked() in that it saves and restores device state
5436 * over the reset and takes the PCI device lock.
5438 * Returns 0 if the device function was successfully reset or negative if the
5439 * device doesn't support resetting a single function.
5441 int pci_reset_function(struct pci_dev
*dev
)
5445 if (!pci_reset_supported(dev
))
5449 pci_dev_save_and_disable(dev
);
5451 rc
= __pci_reset_function_locked(dev
);
5453 pci_dev_restore(dev
);
5454 pci_dev_unlock(dev
);
5458 EXPORT_SYMBOL_GPL(pci_reset_function
);
5461 * pci_reset_function_locked - quiesce and reset a PCI device function
5462 * @dev: PCI device to reset
5464 * Some devices allow an individual function to be reset without affecting
5465 * other functions in the same device. The PCI device must be responsive
5466 * to PCI config space in order to use this function.
5468 * This function does not just reset the PCI portion of a device, but
5469 * clears all the state associated with the device. This function differs
5470 * from __pci_reset_function_locked() in that it saves and restores device state
5471 * over the reset. It also differs from pci_reset_function() in that it
5472 * requires the PCI device lock to be held.
5474 * Returns 0 if the device function was successfully reset or negative if the
5475 * device doesn't support resetting a single function.
5477 int pci_reset_function_locked(struct pci_dev
*dev
)
5481 if (!pci_reset_supported(dev
))
5484 pci_dev_save_and_disable(dev
);
5486 rc
= __pci_reset_function_locked(dev
);
5488 pci_dev_restore(dev
);
5492 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
5495 * pci_try_reset_function - quiesce and reset a PCI device function
5496 * @dev: PCI device to reset
5498 * Same as above, except return -EAGAIN if unable to lock device.
5500 int pci_try_reset_function(struct pci_dev
*dev
)
5504 if (!pci_reset_supported(dev
))
5507 if (!pci_dev_trylock(dev
))
5510 pci_dev_save_and_disable(dev
);
5511 rc
= __pci_reset_function_locked(dev
);
5512 pci_dev_restore(dev
);
5513 pci_dev_unlock(dev
);
5517 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
5519 /* Do any devices on or below this bus prevent a bus reset? */
5520 static bool pci_bus_resetable(struct pci_bus
*bus
)
5522 struct pci_dev
*dev
;
5525 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5528 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5529 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5530 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5537 /* Lock devices from the top of the tree down */
5538 static void pci_bus_lock(struct pci_bus
*bus
)
5540 struct pci_dev
*dev
;
5542 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5544 if (dev
->subordinate
)
5545 pci_bus_lock(dev
->subordinate
);
5549 /* Unlock devices from the bottom of the tree up */
5550 static void pci_bus_unlock(struct pci_bus
*bus
)
5552 struct pci_dev
*dev
;
5554 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5555 if (dev
->subordinate
)
5556 pci_bus_unlock(dev
->subordinate
);
5557 pci_dev_unlock(dev
);
5561 /* Return 1 on successful lock, 0 on contention */
5562 static int pci_bus_trylock(struct pci_bus
*bus
)
5564 struct pci_dev
*dev
;
5566 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5567 if (!pci_dev_trylock(dev
))
5569 if (dev
->subordinate
) {
5570 if (!pci_bus_trylock(dev
->subordinate
)) {
5571 pci_dev_unlock(dev
);
5579 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
5580 if (dev
->subordinate
)
5581 pci_bus_unlock(dev
->subordinate
);
5582 pci_dev_unlock(dev
);
5587 /* Do any devices on or below this slot prevent a bus reset? */
5588 static bool pci_slot_resetable(struct pci_slot
*slot
)
5590 struct pci_dev
*dev
;
5592 if (slot
->bus
->self
&&
5593 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5596 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5597 if (!dev
->slot
|| dev
->slot
!= slot
)
5599 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5600 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5607 /* Lock devices from the top of the tree down */
5608 static void pci_slot_lock(struct pci_slot
*slot
)
5610 struct pci_dev
*dev
;
5612 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5613 if (!dev
->slot
|| dev
->slot
!= slot
)
5616 if (dev
->subordinate
)
5617 pci_bus_lock(dev
->subordinate
);
5621 /* Unlock devices from the bottom of the tree up */
5622 static void pci_slot_unlock(struct pci_slot
*slot
)
5624 struct pci_dev
*dev
;
5626 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5627 if (!dev
->slot
|| dev
->slot
!= slot
)
5629 if (dev
->subordinate
)
5630 pci_bus_unlock(dev
->subordinate
);
5631 pci_dev_unlock(dev
);
5635 /* Return 1 on successful lock, 0 on contention */
5636 static int pci_slot_trylock(struct pci_slot
*slot
)
5638 struct pci_dev
*dev
;
5640 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5641 if (!dev
->slot
|| dev
->slot
!= slot
)
5643 if (!pci_dev_trylock(dev
))
5645 if (dev
->subordinate
) {
5646 if (!pci_bus_trylock(dev
->subordinate
)) {
5647 pci_dev_unlock(dev
);
5655 list_for_each_entry_continue_reverse(dev
,
5656 &slot
->bus
->devices
, bus_list
) {
5657 if (!dev
->slot
|| dev
->slot
!= slot
)
5659 if (dev
->subordinate
)
5660 pci_bus_unlock(dev
->subordinate
);
5661 pci_dev_unlock(dev
);
5667 * Save and disable devices from the top of the tree down while holding
5668 * the @dev mutex lock for the entire tree.
5670 static void pci_bus_save_and_disable_locked(struct pci_bus
*bus
)
5672 struct pci_dev
*dev
;
5674 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5675 pci_dev_save_and_disable(dev
);
5676 if (dev
->subordinate
)
5677 pci_bus_save_and_disable_locked(dev
->subordinate
);
5682 * Restore devices from top of the tree down while holding @dev mutex lock
5683 * for the entire tree. Parent bridges need to be restored before we can
5684 * get to subordinate devices.
5686 static void pci_bus_restore_locked(struct pci_bus
*bus
)
5688 struct pci_dev
*dev
;
5690 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5691 pci_dev_restore(dev
);
5692 if (dev
->subordinate
)
5693 pci_bus_restore_locked(dev
->subordinate
);
5698 * Save and disable devices from the top of the tree down while holding
5699 * the @dev mutex lock for the entire tree.
5701 static void pci_slot_save_and_disable_locked(struct pci_slot
*slot
)
5703 struct pci_dev
*dev
;
5705 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5706 if (!dev
->slot
|| dev
->slot
!= slot
)
5708 pci_dev_save_and_disable(dev
);
5709 if (dev
->subordinate
)
5710 pci_bus_save_and_disable_locked(dev
->subordinate
);
5715 * Restore devices from top of the tree down while holding @dev mutex lock
5716 * for the entire tree. Parent bridges need to be restored before we can
5717 * get to subordinate devices.
5719 static void pci_slot_restore_locked(struct pci_slot
*slot
)
5721 struct pci_dev
*dev
;
5723 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5724 if (!dev
->slot
|| dev
->slot
!= slot
)
5726 pci_dev_restore(dev
);
5727 if (dev
->subordinate
)
5728 pci_bus_restore_locked(dev
->subordinate
);
5732 static int pci_slot_reset(struct pci_slot
*slot
, bool probe
)
5736 if (!slot
|| !pci_slot_resetable(slot
))
5740 pci_slot_lock(slot
);
5744 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
5747 pci_slot_unlock(slot
);
5753 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5754 * @slot: PCI slot to probe
5756 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5758 int pci_probe_reset_slot(struct pci_slot
*slot
)
5760 return pci_slot_reset(slot
, PCI_RESET_PROBE
);
5762 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
5765 * __pci_reset_slot - Try to reset a PCI slot
5766 * @slot: PCI slot to reset
5768 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5769 * independent of other slots. For instance, some slots may support slot power
5770 * control. In the case of a 1:1 bus to slot architecture, this function may
5771 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5772 * Generally a slot reset should be attempted before a bus reset. All of the
5773 * function of the slot and any subordinate buses behind the slot are reset
5774 * through this function. PCI config space of all devices in the slot and
5775 * behind the slot is saved before and restored after reset.
5777 * Same as above except return -EAGAIN if the slot cannot be locked
5779 static int __pci_reset_slot(struct pci_slot
*slot
)
5783 rc
= pci_slot_reset(slot
, PCI_RESET_PROBE
);
5787 if (pci_slot_trylock(slot
)) {
5788 pci_slot_save_and_disable_locked(slot
);
5790 rc
= pci_reset_hotplug_slot(slot
->hotplug
, PCI_RESET_DO_RESET
);
5791 pci_slot_restore_locked(slot
);
5792 pci_slot_unlock(slot
);
5799 static int pci_bus_reset(struct pci_bus
*bus
, bool probe
)
5803 if (!bus
->self
|| !pci_bus_resetable(bus
))
5813 ret
= pci_bridge_secondary_bus_reset(bus
->self
);
5815 pci_bus_unlock(bus
);
5821 * pci_bus_error_reset - reset the bridge's subordinate bus
5822 * @bridge: The parent device that connects to the bus to reset
5824 * This function will first try to reset the slots on this bus if the method is
5825 * available. If slot reset fails or is not available, this will fall back to a
5826 * secondary bus reset.
5828 int pci_bus_error_reset(struct pci_dev
*bridge
)
5830 struct pci_bus
*bus
= bridge
->subordinate
;
5831 struct pci_slot
*slot
;
5836 mutex_lock(&pci_slot_mutex
);
5837 if (list_empty(&bus
->slots
))
5840 list_for_each_entry(slot
, &bus
->slots
, list
)
5841 if (pci_probe_reset_slot(slot
))
5844 list_for_each_entry(slot
, &bus
->slots
, list
)
5845 if (pci_slot_reset(slot
, PCI_RESET_DO_RESET
))
5848 mutex_unlock(&pci_slot_mutex
);
5851 mutex_unlock(&pci_slot_mutex
);
5852 return pci_bus_reset(bridge
->subordinate
, PCI_RESET_DO_RESET
);
5856 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5857 * @bus: PCI bus to probe
5859 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5861 int pci_probe_reset_bus(struct pci_bus
*bus
)
5863 return pci_bus_reset(bus
, PCI_RESET_PROBE
);
5865 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
5868 * __pci_reset_bus - Try to reset a PCI bus
5869 * @bus: top level PCI bus to reset
5871 * Same as above except return -EAGAIN if the bus cannot be locked
5873 static int __pci_reset_bus(struct pci_bus
*bus
)
5877 rc
= pci_bus_reset(bus
, PCI_RESET_PROBE
);
5881 if (pci_bus_trylock(bus
)) {
5882 pci_bus_save_and_disable_locked(bus
);
5884 rc
= pci_bridge_secondary_bus_reset(bus
->self
);
5885 pci_bus_restore_locked(bus
);
5886 pci_bus_unlock(bus
);
5894 * pci_reset_bus - Try to reset a PCI bus
5895 * @pdev: top level PCI device to reset via slot/bus
5897 * Same as above except return -EAGAIN if the bus cannot be locked
5899 int pci_reset_bus(struct pci_dev
*pdev
)
5901 return (!pci_probe_reset_slot(pdev
->slot
)) ?
5902 __pci_reset_slot(pdev
->slot
) : __pci_reset_bus(pdev
->bus
);
5904 EXPORT_SYMBOL_GPL(pci_reset_bus
);
5907 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5908 * @dev: PCI device to query
5910 * Returns mmrbc: maximum designed memory read count in bytes or
5911 * appropriate error value.
5913 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
5918 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5922 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5925 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
5927 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
5930 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5931 * @dev: PCI device to query
5933 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5936 int pcix_get_mmrbc(struct pci_dev
*dev
)
5941 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5945 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5948 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
5950 EXPORT_SYMBOL(pcix_get_mmrbc
);
5953 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5954 * @dev: PCI device to query
5955 * @mmrbc: maximum memory read count in bytes
5956 * valid values are 512, 1024, 2048, 4096
5958 * If possible sets maximum memory read byte count, some bridges have errata
5959 * that prevent this.
5961 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
5967 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
5970 v
= ffs(mmrbc
) - 10;
5972 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5976 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5979 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
5982 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5985 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
5987 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
5990 cmd
&= ~PCI_X_CMD_MAX_READ
;
5992 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
5997 EXPORT_SYMBOL(pcix_set_mmrbc
);
6000 * pcie_get_readrq - get PCI Express read request size
6001 * @dev: PCI device to query
6003 * Returns maximum memory read request in bytes or appropriate error value.
6005 int pcie_get_readrq(struct pci_dev
*dev
)
6009 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
6011 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6013 EXPORT_SYMBOL(pcie_get_readrq
);
6016 * pcie_set_readrq - set PCI Express maximum memory read request
6017 * @dev: PCI device to query
6018 * @rq: maximum memory read count in bytes
6019 * valid values are 128, 256, 512, 1024, 2048, 4096
6021 * If possible sets maximum memory read request in bytes
6023 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
6028 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
6032 * If using the "performance" PCIe config, we clamp the read rq
6033 * size to the max packet size to keep the host bridge from
6034 * generating requests larger than we can cope with.
6036 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
6037 int mps
= pcie_get_mps(dev
);
6043 v
= (ffs(rq
) - 8) << 12;
6045 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6046 PCI_EXP_DEVCTL_READRQ
, v
);
6048 return pcibios_err_to_errno(ret
);
6050 EXPORT_SYMBOL(pcie_set_readrq
);
6053 * pcie_get_mps - get PCI Express maximum payload size
6054 * @dev: PCI device to query
6056 * Returns maximum payload size in bytes
6058 int pcie_get_mps(struct pci_dev
*dev
)
6062 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
6064 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6066 EXPORT_SYMBOL(pcie_get_mps
);
6069 * pcie_set_mps - set PCI Express maximum payload size
6070 * @dev: PCI device to query
6071 * @mps: maximum payload size in bytes
6072 * valid values are 128, 256, 512, 1024, 2048, 4096
6074 * If possible sets maximum payload size
6076 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
6081 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
6085 if (v
> dev
->pcie_mpss
)
6089 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6090 PCI_EXP_DEVCTL_PAYLOAD
, v
);
6092 return pcibios_err_to_errno(ret
);
6094 EXPORT_SYMBOL(pcie_set_mps
);
6097 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6098 * device and its bandwidth limitation
6099 * @dev: PCI device to query
6100 * @limiting_dev: storage for device causing the bandwidth limitation
6101 * @speed: storage for speed of limiting device
6102 * @width: storage for width of limiting device
6104 * Walk up the PCI device chain and find the point where the minimum
6105 * bandwidth is available. Return the bandwidth available there and (if
6106 * limiting_dev, speed, and width pointers are supplied) information about
6107 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6110 u32
pcie_bandwidth_available(struct pci_dev
*dev
, struct pci_dev
**limiting_dev
,
6111 enum pci_bus_speed
*speed
,
6112 enum pcie_link_width
*width
)
6115 enum pci_bus_speed next_speed
;
6116 enum pcie_link_width next_width
;
6120 *speed
= PCI_SPEED_UNKNOWN
;
6122 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
6127 pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
6129 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
6130 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
6131 PCI_EXP_LNKSTA_NLW_SHIFT
;
6133 next_bw
= next_width
* PCIE_SPEED2MBS_ENC(next_speed
);
6135 /* Check if current device limits the total bandwidth */
6136 if (!bw
|| next_bw
<= bw
) {
6140 *limiting_dev
= dev
;
6142 *speed
= next_speed
;
6144 *width
= next_width
;
6147 dev
= pci_upstream_bridge(dev
);
6152 EXPORT_SYMBOL(pcie_bandwidth_available
);
6155 * pcie_get_speed_cap - query for the PCI device's link speed capability
6156 * @dev: PCI device to query
6158 * Query the PCI device speed capability. Return the maximum link speed
6159 * supported by the device.
6161 enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev
*dev
)
6163 u32 lnkcap2
, lnkcap
;
6166 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6167 * implementation note there recommends using the Supported Link
6168 * Speeds Vector in Link Capabilities 2 when supported.
6170 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6171 * should use the Supported Link Speeds field in Link Capabilities,
6172 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6174 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
6176 /* PCIe r3.0-compliant */
6178 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2
);
6180 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6181 if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_5_0GB
)
6182 return PCIE_SPEED_5_0GT
;
6183 else if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_2_5GB
)
6184 return PCIE_SPEED_2_5GT
;
6186 return PCI_SPEED_UNKNOWN
;
6188 EXPORT_SYMBOL(pcie_get_speed_cap
);
6191 * pcie_get_width_cap - query for the PCI device's link width capability
6192 * @dev: PCI device to query
6194 * Query the PCI device width capability. Return the maximum link width
6195 * supported by the device.
6197 enum pcie_link_width
pcie_get_width_cap(struct pci_dev
*dev
)
6201 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6203 return (lnkcap
& PCI_EXP_LNKCAP_MLW
) >> 4;
6205 return PCIE_LNK_WIDTH_UNKNOWN
;
6207 EXPORT_SYMBOL(pcie_get_width_cap
);
6210 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6212 * @speed: storage for link speed
6213 * @width: storage for link width
6215 * Calculate a PCI device's link bandwidth by querying for its link speed
6216 * and width, multiplying them, and applying encoding overhead. The result
6217 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6219 u32
pcie_bandwidth_capable(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
6220 enum pcie_link_width
*width
)
6222 *speed
= pcie_get_speed_cap(dev
);
6223 *width
= pcie_get_width_cap(dev
);
6225 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
)
6228 return *width
* PCIE_SPEED2MBS_ENC(*speed
);
6232 * __pcie_print_link_status - Report the PCI device's link speed and width
6233 * @dev: PCI device to query
6234 * @verbose: Print info even when enough bandwidth is available
6236 * If the available bandwidth at the device is less than the device is
6237 * capable of, report the device's maximum possible bandwidth and the
6238 * upstream link that limits its performance. If @verbose, always print
6239 * the available bandwidth, even if the device isn't constrained.
6241 void __pcie_print_link_status(struct pci_dev
*dev
, bool verbose
)
6243 enum pcie_link_width width
, width_cap
;
6244 enum pci_bus_speed speed
, speed_cap
;
6245 struct pci_dev
*limiting_dev
= NULL
;
6246 u32 bw_avail
, bw_cap
;
6248 bw_cap
= pcie_bandwidth_capable(dev
, &speed_cap
, &width_cap
);
6249 bw_avail
= pcie_bandwidth_available(dev
, &limiting_dev
, &speed
, &width
);
6251 if (bw_avail
>= bw_cap
&& verbose
)
6252 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6253 bw_cap
/ 1000, bw_cap
% 1000,
6254 pci_speed_string(speed_cap
), width_cap
);
6255 else if (bw_avail
< bw_cap
)
6256 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6257 bw_avail
/ 1000, bw_avail
% 1000,
6258 pci_speed_string(speed
), width
,
6259 limiting_dev
? pci_name(limiting_dev
) : "<unknown>",
6260 bw_cap
/ 1000, bw_cap
% 1000,
6261 pci_speed_string(speed_cap
), width_cap
);
6265 * pcie_print_link_status - Report the PCI device's link speed and width
6266 * @dev: PCI device to query
6268 * Report the available bandwidth at the device.
6270 void pcie_print_link_status(struct pci_dev
*dev
)
6272 __pcie_print_link_status(dev
, true);
6274 EXPORT_SYMBOL(pcie_print_link_status
);
6277 * pci_select_bars - Make BAR mask from the type of resource
6278 * @dev: the PCI device for which BAR mask is made
6279 * @flags: resource type mask to be selected
6281 * This helper routine makes bar mask from the type of resource.
6283 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
6286 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
6287 if (pci_resource_flags(dev
, i
) & flags
)
6291 EXPORT_SYMBOL(pci_select_bars
);
6293 /* Some architectures require additional programming to enable VGA */
6294 static arch_set_vga_state_t arch_set_vga_state
;
6296 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
6298 arch_set_vga_state
= func
; /* NULL disables */
6301 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
6302 unsigned int command_bits
, u32 flags
)
6304 if (arch_set_vga_state
)
6305 return arch_set_vga_state(dev
, decode
, command_bits
,
6311 * pci_set_vga_state - set VGA decode state on device and parents if requested
6312 * @dev: the PCI device
6313 * @decode: true = enable decoding, false = disable decoding
6314 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6315 * @flags: traverse ancestors and change bridges
6316 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6318 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
6319 unsigned int command_bits
, u32 flags
)
6321 struct pci_bus
*bus
;
6322 struct pci_dev
*bridge
;
6326 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
6328 /* ARCH specific VGA enables */
6329 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
6333 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
6334 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
6336 cmd
|= command_bits
;
6338 cmd
&= ~command_bits
;
6339 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
6342 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
6349 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6352 cmd
|= PCI_BRIDGE_CTL_VGA
;
6354 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
6355 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6364 bool pci_pr3_present(struct pci_dev
*pdev
)
6366 struct acpi_device
*adev
;
6371 adev
= ACPI_COMPANION(&pdev
->dev
);
6375 return adev
->power
.flags
.power_resources
&&
6376 acpi_has_method(adev
->handle
, "_PR3");
6378 EXPORT_SYMBOL_GPL(pci_pr3_present
);
6382 * pci_add_dma_alias - Add a DMA devfn alias for a device
6383 * @dev: the PCI device for which alias is added
6384 * @devfn_from: alias slot and function
6385 * @nr_devfns: number of subsequent devfns to alias
6387 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6388 * which is used to program permissible bus-devfn source addresses for DMA
6389 * requests in an IOMMU. These aliases factor into IOMMU group creation
6390 * and are useful for devices generating DMA requests beyond or different
6391 * from their logical bus-devfn. Examples include device quirks where the
6392 * device simply uses the wrong devfn, as well as non-transparent bridges
6393 * where the alias may be a proxy for devices in another domain.
6395 * IOMMU group creation is performed during device discovery or addition,
6396 * prior to any potential DMA mapping and therefore prior to driver probing
6397 * (especially for userspace assigned devices where IOMMU group definition
6398 * cannot be left as a userspace activity). DMA aliases should therefore
6399 * be configured via quirks, such as the PCI fixup header quirk.
6401 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn_from
, unsigned nr_devfns
)
6405 nr_devfns
= min(nr_devfns
, (unsigned) MAX_NR_DEVFNS
- devfn_from
);
6406 devfn_to
= devfn_from
+ nr_devfns
- 1;
6408 if (!dev
->dma_alias_mask
)
6409 dev
->dma_alias_mask
= bitmap_zalloc(MAX_NR_DEVFNS
, GFP_KERNEL
);
6410 if (!dev
->dma_alias_mask
) {
6411 pci_warn(dev
, "Unable to allocate DMA alias mask\n");
6415 bitmap_set(dev
->dma_alias_mask
, devfn_from
, nr_devfns
);
6418 pci_info(dev
, "Enabling fixed DMA alias to %02x.%d\n",
6419 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
));
6420 else if (nr_devfns
> 1)
6421 pci_info(dev
, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6422 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
),
6423 PCI_SLOT(devfn_to
), PCI_FUNC(devfn_to
));
6426 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
6428 return (dev1
->dma_alias_mask
&&
6429 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
6430 (dev2
->dma_alias_mask
&&
6431 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
)) ||
6432 pci_real_dma_dev(dev1
) == dev2
||
6433 pci_real_dma_dev(dev2
) == dev1
;
6436 bool pci_device_is_present(struct pci_dev
*pdev
)
6440 if (pci_dev_is_disconnected(pdev
))
6442 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
6444 EXPORT_SYMBOL_GPL(pci_device_is_present
);
6446 void pci_ignore_hotplug(struct pci_dev
*dev
)
6448 struct pci_dev
*bridge
= dev
->bus
->self
;
6450 dev
->ignore_hotplug
= 1;
6451 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6453 bridge
->ignore_hotplug
= 1;
6455 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
6458 * pci_real_dma_dev - Get PCI DMA device for PCI device
6459 * @dev: the PCI device that may have a PCI DMA alias
6461 * Permits the platform to provide architecture-specific functionality to
6462 * devices needing to alias DMA to another PCI device on another PCI bus. If
6463 * the PCI device is on the same bus, it is recommended to use
6464 * pci_add_dma_alias(). This is the default implementation. Architecture
6465 * implementations can override this.
6467 struct pci_dev __weak
*pci_real_dma_dev(struct pci_dev
*dev
)
6472 resource_size_t __weak
pcibios_default_alignment(void)
6478 * Arches that don't want to expose struct resource to userland as-is in
6479 * sysfs and /proc can implement their own pci_resource_to_user().
6481 void __weak
pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
6482 const struct resource
*rsrc
,
6483 resource_size_t
*start
, resource_size_t
*end
)
6485 *start
= rsrc
->start
;
6489 static char *resource_alignment_param
;
6490 static DEFINE_SPINLOCK(resource_alignment_lock
);
6493 * pci_specified_resource_alignment - get resource alignment specified by user.
6494 * @dev: the PCI device to get
6495 * @resize: whether or not to change resources' size when reassigning alignment
6497 * RETURNS: Resource alignment if it is specified.
6498 * Zero if it is not specified.
6500 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
6503 int align_order
, count
;
6504 resource_size_t align
= pcibios_default_alignment();
6508 spin_lock(&resource_alignment_lock
);
6509 p
= resource_alignment_param
;
6512 if (pci_has_flag(PCI_PROBE_ONLY
)) {
6514 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6520 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
6523 if (align_order
> 63) {
6524 pr_err("PCI: Invalid requested alignment (order %d)\n",
6526 align_order
= PAGE_SHIFT
;
6529 align_order
= PAGE_SHIFT
;
6532 ret
= pci_dev_str_match(dev
, p
, &p
);
6535 align
= 1ULL << align_order
;
6537 } else if (ret
< 0) {
6538 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6543 if (*p
!= ';' && *p
!= ',') {
6544 /* End of param or invalid format */
6550 spin_unlock(&resource_alignment_lock
);
6554 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
6555 resource_size_t align
, bool resize
)
6557 struct resource
*r
= &dev
->resource
[bar
];
6558 resource_size_t size
;
6560 if (!(r
->flags
& IORESOURCE_MEM
))
6563 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
6564 pci_info(dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
6565 bar
, r
, (unsigned long long)align
);
6569 size
= resource_size(r
);
6574 * Increase the alignment of the resource. There are two ways we
6577 * 1) Increase the size of the resource. BARs are aligned on their
6578 * size, so when we reallocate space for this resource, we'll
6579 * allocate it with the larger alignment. This also prevents
6580 * assignment of any other BARs inside the alignment region, so
6581 * if we're requesting page alignment, this means no other BARs
6582 * will share the page.
6584 * The disadvantage is that this makes the resource larger than
6585 * the hardware BAR, which may break drivers that compute things
6586 * based on the resource size, e.g., to find registers at a
6587 * fixed offset before the end of the BAR.
6589 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6590 * set r->start to the desired alignment. By itself this
6591 * doesn't prevent other BARs being put inside the alignment
6592 * region, but if we realign *every* resource of every device in
6593 * the system, none of them will share an alignment region.
6595 * When the user has requested alignment for only some devices via
6596 * the "pci=resource_alignment" argument, "resize" is true and we
6597 * use the first method. Otherwise we assume we're aligning all
6598 * devices and we use the second.
6601 pci_info(dev
, "BAR%d %pR: requesting alignment to %#llx\n",
6602 bar
, r
, (unsigned long long)align
);
6608 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
6609 r
->flags
|= IORESOURCE_STARTALIGN
;
6611 r
->end
= r
->start
+ size
- 1;
6613 r
->flags
|= IORESOURCE_UNSET
;
6617 * This function disables memory decoding and releases memory resources
6618 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6619 * It also rounds up size to specified alignment.
6620 * Later on, the kernel will assign page-aligned memory resource back
6623 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
6627 resource_size_t align
;
6629 bool resize
= false;
6632 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6633 * 3.4.1.11. Their resources are allocated from the space
6634 * described by the VF BARx register in the PF's SR-IOV capability.
6635 * We can't influence their alignment here.
6640 /* check if specified PCI is target device to reassign */
6641 align
= pci_specified_resource_alignment(dev
, &resize
);
6645 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
6646 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
6647 pci_warn(dev
, "Can't reassign resources to host bridge\n");
6651 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
6652 command
&= ~PCI_COMMAND_MEMORY
;
6653 pci_write_config_word(dev
, PCI_COMMAND
, command
);
6655 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
6656 pci_request_resource_alignment(dev
, i
, align
, resize
);
6659 * Need to disable bridge's resource window,
6660 * to enable the kernel to reassign new resource
6663 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
6664 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
6665 r
= &dev
->resource
[i
];
6666 if (!(r
->flags
& IORESOURCE_MEM
))
6668 r
->flags
|= IORESOURCE_UNSET
;
6669 r
->end
= resource_size(r
) - 1;
6672 pci_disable_bridge_window(dev
);
6676 static ssize_t
resource_alignment_show(struct bus_type
*bus
, char *buf
)
6680 spin_lock(&resource_alignment_lock
);
6681 if (resource_alignment_param
)
6682 count
= sysfs_emit(buf
, "%s\n", resource_alignment_param
);
6683 spin_unlock(&resource_alignment_lock
);
6688 static ssize_t
resource_alignment_store(struct bus_type
*bus
,
6689 const char *buf
, size_t count
)
6691 char *param
, *old
, *end
;
6693 if (count
>= (PAGE_SIZE
- 1))
6696 param
= kstrndup(buf
, count
, GFP_KERNEL
);
6700 end
= strchr(param
, '\n');
6704 spin_lock(&resource_alignment_lock
);
6705 old
= resource_alignment_param
;
6706 if (strlen(param
)) {
6707 resource_alignment_param
= param
;
6710 resource_alignment_param
= NULL
;
6712 spin_unlock(&resource_alignment_lock
);
6719 static BUS_ATTR_RW(resource_alignment
);
6721 static int __init
pci_resource_alignment_sysfs_init(void)
6723 return bus_create_file(&pci_bus_type
,
6724 &bus_attr_resource_alignment
);
6726 late_initcall(pci_resource_alignment_sysfs_init
);
6728 static void pci_no_domains(void)
6730 #ifdef CONFIG_PCI_DOMAINS
6731 pci_domains_supported
= 0;
6735 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6736 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
6738 static int pci_get_new_domain_nr(void)
6740 return atomic_inc_return(&__domain_nr
);
6743 static int of_pci_bus_find_domain_nr(struct device
*parent
)
6745 static int use_dt_domains
= -1;
6749 domain
= of_get_pci_domain_nr(parent
->of_node
);
6752 * Check DT domain and use_dt_domains values.
6754 * If DT domain property is valid (domain >= 0) and
6755 * use_dt_domains != 0, the DT assignment is valid since this means
6756 * we have not previously allocated a domain number by using
6757 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6758 * 1, to indicate that we have just assigned a domain number from
6761 * If DT domain property value is not valid (ie domain < 0), and we
6762 * have not previously assigned a domain number from DT
6763 * (use_dt_domains != 1) we should assign a domain number by
6766 * pci_get_new_domain_nr()
6768 * API and update the use_dt_domains value to keep track of method we
6769 * are using to assign domain numbers (use_dt_domains = 0).
6771 * All other combinations imply we have a platform that is trying
6772 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6773 * which is a recipe for domain mishandling and it is prevented by
6774 * invalidating the domain value (domain = -1) and printing a
6775 * corresponding error.
6777 if (domain
>= 0 && use_dt_domains
) {
6779 } else if (domain
< 0 && use_dt_domains
!= 1) {
6781 domain
= pci_get_new_domain_nr();
6784 pr_err("Node %pOF has ", parent
->of_node
);
6785 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6792 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
6794 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
6795 acpi_pci_bus_find_domain_nr(bus
);
6800 * pci_ext_cfg_avail - can we access extended PCI config space?
6802 * Returns 1 if we can access PCI extended config space (offsets
6803 * greater than 0xff). This is the default implementation. Architecture
6804 * implementations can override this.
6806 int __weak
pci_ext_cfg_avail(void)
6811 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
6814 EXPORT_SYMBOL(pci_fixup_cardbus
);
6816 static int __init
pci_setup(char *str
)
6819 char *k
= strchr(str
, ',');
6822 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
6823 if (!strcmp(str
, "nomsi")) {
6825 } else if (!strncmp(str
, "noats", 5)) {
6826 pr_info("PCIe: ATS is disabled\n");
6827 pcie_ats_disabled
= true;
6828 } else if (!strcmp(str
, "noaer")) {
6830 } else if (!strcmp(str
, "earlydump")) {
6831 pci_early_dump
= true;
6832 } else if (!strncmp(str
, "realloc=", 8)) {
6833 pci_realloc_get_opt(str
+ 8);
6834 } else if (!strncmp(str
, "realloc", 7)) {
6835 pci_realloc_get_opt("on");
6836 } else if (!strcmp(str
, "nodomains")) {
6838 } else if (!strncmp(str
, "noari", 5)) {
6839 pcie_ari_disabled
= true;
6840 } else if (!strncmp(str
, "cbiosize=", 9)) {
6841 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
6842 } else if (!strncmp(str
, "cbmemsize=", 10)) {
6843 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
6844 } else if (!strncmp(str
, "resource_alignment=", 19)) {
6845 resource_alignment_param
= str
+ 19;
6846 } else if (!strncmp(str
, "ecrc=", 5)) {
6847 pcie_ecrc_get_policy(str
+ 5);
6848 } else if (!strncmp(str
, "hpiosize=", 9)) {
6849 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
6850 } else if (!strncmp(str
, "hpmmiosize=", 11)) {
6851 pci_hotplug_mmio_size
= memparse(str
+ 11, &str
);
6852 } else if (!strncmp(str
, "hpmmioprefsize=", 15)) {
6853 pci_hotplug_mmio_pref_size
= memparse(str
+ 15, &str
);
6854 } else if (!strncmp(str
, "hpmemsize=", 10)) {
6855 pci_hotplug_mmio_size
= memparse(str
+ 10, &str
);
6856 pci_hotplug_mmio_pref_size
= pci_hotplug_mmio_size
;
6857 } else if (!strncmp(str
, "hpbussize=", 10)) {
6858 pci_hotplug_bus_size
=
6859 simple_strtoul(str
+ 10, &str
, 0);
6860 if (pci_hotplug_bus_size
> 0xff)
6861 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
6862 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
6863 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
6864 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
6865 pcie_bus_config
= PCIE_BUS_SAFE
;
6866 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
6867 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
6868 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
6869 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
6870 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
6871 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
6872 } else if (!strncmp(str
, "disable_acs_redir=", 18)) {
6873 disable_acs_redir_param
= str
+ 18;
6875 pr_err("PCI: Unknown option `%s'\n", str
);
6882 early_param("pci", pci_setup
);
6885 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6886 * in pci_setup(), above, to point to data in the __initdata section which
6887 * will be freed after the init sequence is complete. We can't allocate memory
6888 * in pci_setup() because some architectures do not have any memory allocation
6889 * service available during an early_param() call. So we allocate memory and
6890 * copy the variable here before the init section is freed.
6893 static int __init
pci_realloc_setup_params(void)
6895 resource_alignment_param
= kstrdup(resource_alignment_param
,
6897 disable_acs_redir_param
= kstrdup(disable_acs_redir_param
, GFP_KERNEL
);
6901 pure_initcall(pci_realloc_setup_params
);