2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/logic_pio.h>
25 #include <linux/pci-aspm.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 const char *pci_power_names
[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names
);
43 int isa_dma_bridge_buggy
;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
47 EXPORT_SYMBOL(pci_pci_problems
);
49 unsigned int pci_pm_d3_delay
;
51 static void pci_pme_list_scan(struct work_struct
*work
);
53 static LIST_HEAD(pci_pme_list
);
54 static DEFINE_MUTEX(pci_pme_list_mutex
);
55 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
57 struct pci_pme_device
{
58 struct list_head list
;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
66 unsigned int delay
= dev
->d3_delay
;
68 if (delay
< pci_pm_d3_delay
)
69 delay
= pci_pm_d3_delay
;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported
= 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
83 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
89 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
94 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
103 u8 pci_cache_line_size
;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency
= 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled
;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable
;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force
;
119 static int __init
pcie_port_pm_setup(char *str
)
121 if (!strcmp(str
, "off"))
122 pci_bridge_d3_disable
= true;
123 else if (!strcmp(str
, "force"))
124 pci_bridge_d3_force
= true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup
);
130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
131 * @bus: pointer to PCI bus structure to search
133 * Given a PCI bus, returns the highest PCI bus number present in the set
134 * including the given PCI bus and its list of child PCI buses.
136 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
139 unsigned char max
, n
;
141 max
= bus
->busn_res
.end
;
142 list_for_each_entry(tmp
, &bus
->children
, node
) {
143 n
= pci_bus_max_busnr(tmp
);
149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
151 #ifdef CONFIG_HAS_IOMEM
152 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
154 struct resource
*res
= &pdev
->resource
[bar
];
157 * Make sure the BAR is actually a memory resource, not an IO resource
159 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
160 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
163 return ioremap_nocache(res
->start
, resource_size(res
));
165 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
167 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
170 * Make sure the BAR is actually a memory resource, not an IO resource
172 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
176 return ioremap_wc(pci_resource_start(pdev
, bar
),
177 pci_resource_len(pdev
, bar
));
179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
183 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
184 u8 pos
, int cap
, int *ttl
)
189 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
195 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
207 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
210 int ttl
= PCI_FIND_CAP_TTL
;
212 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
215 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
217 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
218 pos
+ PCI_CAP_LIST_NEXT
, cap
);
220 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
222 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
223 unsigned int devfn
, u8 hdr_type
)
227 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
228 if (!(status
& PCI_STATUS_CAP_LIST
))
232 case PCI_HEADER_TYPE_NORMAL
:
233 case PCI_HEADER_TYPE_BRIDGE
:
234 return PCI_CAPABILITY_LIST
;
235 case PCI_HEADER_TYPE_CARDBUS
:
236 return PCI_CB_CAPABILITY_LIST
;
243 * pci_find_capability - query for devices' capabilities
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Tell if a device supports a given PCI capability.
248 * Returns the address of the requested capability structure within the
249 * device's PCI configuration space or 0 in case the device does not
250 * support it. Possible values for @cap:
252 * %PCI_CAP_ID_PM Power Management
253 * %PCI_CAP_ID_AGP Accelerated Graphics Port
254 * %PCI_CAP_ID_VPD Vital Product Data
255 * %PCI_CAP_ID_SLOTID Slot Identification
256 * %PCI_CAP_ID_MSI Message Signalled Interrupts
257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
258 * %PCI_CAP_ID_PCIX PCI-X
259 * %PCI_CAP_ID_EXP PCI Express
261 int pci_find_capability(struct pci_dev
*dev
, int cap
)
265 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
267 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
271 EXPORT_SYMBOL(pci_find_capability
);
274 * pci_bus_find_capability - query for devices' capabilities
275 * @bus: the PCI bus to query
276 * @devfn: PCI device to query
277 * @cap: capability code
279 * Like pci_find_capability() but works for pci devices that do not have a
280 * pci_dev structure set up yet.
282 * Returns the address of the requested capability structure within the
283 * device's PCI configuration space or 0 in case the device does not
286 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
291 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
293 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
295 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
299 EXPORT_SYMBOL(pci_bus_find_capability
);
302 * pci_find_next_ext_capability - Find an extended capability
303 * @dev: PCI device to query
304 * @start: address at which to start looking (0 to start at beginning of list)
305 * @cap: capability code
307 * Returns the address of the next matching extended capability structure
308 * within the device's PCI configuration space or 0 if the device does
309 * not support it. Some capabilities can occur several times, e.g., the
310 * vendor-specific capability, and this provides a way to find them all.
312 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
316 int pos
= PCI_CFG_SPACE_SIZE
;
318 /* minimum 8 bytes per capability */
319 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
321 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
327 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
331 * If we have no capabilities, this is indicated by cap ID,
332 * cap version and next pointer all being 0.
338 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
341 pos
= PCI_EXT_CAP_NEXT(header
);
342 if (pos
< PCI_CFG_SPACE_SIZE
)
345 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
354 * pci_find_ext_capability - Find an extended capability
355 * @dev: PCI device to query
356 * @cap: capability code
358 * Returns the address of the requested extended capability structure
359 * within the device's PCI configuration space or 0 if the device does
360 * not support it. Possible values for @cap:
362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
363 * %PCI_EXT_CAP_ID_VC Virtual Channel
364 * %PCI_EXT_CAP_ID_DSN Device Serial Number
365 * %PCI_EXT_CAP_ID_PWR Power Budgeting
367 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
369 return pci_find_next_ext_capability(dev
, 0, cap
);
371 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
373 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
375 int rc
, ttl
= PCI_FIND_CAP_TTL
;
378 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
379 mask
= HT_3BIT_CAP_MASK
;
381 mask
= HT_5BIT_CAP_MASK
;
383 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
384 PCI_CAP_ID_HT
, &ttl
);
386 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
387 if (rc
!= PCIBIOS_SUCCESSFUL
)
390 if ((cap
& mask
) == ht_cap
)
393 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
394 pos
+ PCI_CAP_LIST_NEXT
,
395 PCI_CAP_ID_HT
, &ttl
);
401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
402 * @dev: PCI device to query
403 * @pos: Position from which to continue searching
404 * @ht_cap: Hypertransport capability code
406 * To be used in conjunction with pci_find_ht_capability() to search for
407 * all capabilities matching @ht_cap. @pos should always be a value returned
408 * from pci_find_ht_capability().
410 * NB. To be 100% safe against broken PCI devices, the caller should take
411 * steps to avoid an infinite loop.
413 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
415 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
420 * pci_find_ht_capability - query a device's Hypertransport capabilities
421 * @dev: PCI device to query
422 * @ht_cap: Hypertransport capability code
424 * Tell if a device supports a given Hypertransport capability.
425 * Returns an address within the device's PCI configuration space
426 * or 0 in case the device does not support the request capability.
427 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
428 * which has a Hypertransport capability matching @ht_cap.
430 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
434 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
436 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
440 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
443 * pci_find_parent_resource - return resource region of parent bus of given region
444 * @dev: PCI device structure contains resources to be searched
445 * @res: child resource record for which parent is sought
447 * For given resource region of given device, return the resource
448 * region of parent bus the given region is contained in.
450 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
451 struct resource
*res
)
453 const struct pci_bus
*bus
= dev
->bus
;
457 pci_bus_for_each_resource(bus
, r
, i
) {
460 if (resource_contains(r
, res
)) {
463 * If the window is prefetchable but the BAR is
464 * not, the allocator made a mistake.
466 if (r
->flags
& IORESOURCE_PREFETCH
&&
467 !(res
->flags
& IORESOURCE_PREFETCH
))
471 * If we're below a transparent bridge, there may
472 * be both a positively-decoded aperture and a
473 * subtractively-decoded region that contain the BAR.
474 * We want the positively-decoded one, so this depends
475 * on pci_bus_for_each_resource() giving us those
483 EXPORT_SYMBOL(pci_find_parent_resource
);
486 * pci_find_resource - Return matching PCI device resource
487 * @dev: PCI device to query
488 * @res: Resource to look for
490 * Goes over standard PCI resources (BARs) and checks if the given resource
491 * is partially or fully contained in any of them. In that case the
492 * matching resource is returned, %NULL otherwise.
494 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
498 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++) {
499 struct resource
*r
= &dev
->resource
[i
];
501 if (r
->start
&& resource_contains(r
, res
))
507 EXPORT_SYMBOL(pci_find_resource
);
510 * pci_find_pcie_root_port - return PCIe Root Port
511 * @dev: PCI device to query
513 * Traverse up the parent chain and return the PCIe Root Port PCI Device
514 * for a given PCI Device.
516 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
)
518 struct pci_dev
*bridge
, *highest_pcie_bridge
= dev
;
520 bridge
= pci_upstream_bridge(dev
);
521 while (bridge
&& pci_is_pcie(bridge
)) {
522 highest_pcie_bridge
= bridge
;
523 bridge
= pci_upstream_bridge(bridge
);
526 if (pci_pcie_type(highest_pcie_bridge
) != PCI_EXP_TYPE_ROOT_PORT
)
529 return highest_pcie_bridge
;
531 EXPORT_SYMBOL(pci_find_pcie_root_port
);
534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
535 * @dev: the PCI device to operate on
536 * @pos: config space offset of status word
537 * @mask: mask of bit(s) to care about in status word
539 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
541 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
545 /* Wait for Transaction Pending bit clean */
546 for (i
= 0; i
< 4; i
++) {
549 msleep((1 << (i
- 1)) * 100);
551 pci_read_config_word(dev
, pos
, &status
);
552 if (!(status
& mask
))
560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
561 * @dev: PCI device to have its BARs restored
563 * Restore the BAR values for a given device, so as to make it
564 * accessible by its driver.
566 static void pci_restore_bars(struct pci_dev
*dev
)
570 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
571 pci_update_resource(dev
, i
);
574 static const struct pci_platform_pm_ops
*pci_platform_pm
;
576 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
578 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
579 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
581 pci_platform_pm
= ops
;
585 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
587 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
590 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
593 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
596 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
598 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
601 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
603 return pci_platform_pm
?
604 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
607 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
609 return pci_platform_pm
?
610 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
613 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
615 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
621 * @dev: PCI device to handle.
622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
625 * -EINVAL if the requested state is invalid.
626 * -EIO if device does not support PCI PM or its PM capabilities register has a
627 * wrong version, or device doesn't support the requested state.
628 * 0 if device already is in the requested state.
629 * 0 if device's power state has been successfully changed.
631 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
634 bool need_restore
= false;
636 /* Check if we're already there */
637 if (dev
->current_state
== state
)
643 if (state
< PCI_D0
|| state
> PCI_D3hot
)
646 /* Validate current state:
647 * Can enter D0 from any state, but if we can only go deeper
648 * to sleep if we're already in a low power state
650 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
651 && dev
->current_state
> state
) {
652 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
653 dev
->current_state
, state
);
657 /* check if this device supports the desired state */
658 if ((state
== PCI_D1
&& !dev
->d1_support
)
659 || (state
== PCI_D2
&& !dev
->d2_support
))
662 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
664 /* If we're (effectively) in D3, force entire word to 0.
665 * This doesn't affect PME_Status, disables PME_En, and
666 * sets PowerState to 0.
668 switch (dev
->current_state
) {
672 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
677 case PCI_UNKNOWN
: /* Boot-up */
678 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
679 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
681 /* Fall-through: force to D0 */
687 /* enter specified state */
688 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
690 /* Mandatory power management transition delays */
691 /* see PCI PM 1.1 5.6.1 table 18 */
692 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
693 pci_dev_d3_sleep(dev
);
694 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
695 udelay(PCI_PM_D2_DELAY
);
697 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
698 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
699 if (dev
->current_state
!= state
&& printk_ratelimit())
700 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
706 * from D3hot to D0 _may_ perform an internal reset, thereby
707 * going to "D0 Uninitialized" rather than "D0 Initialized".
708 * For example, at least some versions of the 3c905B and the
709 * 3c556B exhibit this behaviour.
711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
712 * devices in a D3hot state at boot. Consequently, we need to
713 * restore at least the BARs so that the device will be
714 * accessible to its driver.
717 pci_restore_bars(dev
);
720 pcie_aspm_pm_state_change(dev
->bus
->self
);
726 * pci_update_current_state - Read power state of given device and cache it
727 * @dev: PCI device to handle.
728 * @state: State to cache in case the device doesn't have the PM capability
730 * The power state is read from the PMCSR register, which however is
731 * inaccessible in D3cold. The platform firmware is therefore queried first
732 * to detect accessibility of the register. In case the platform firmware
733 * reports an incorrect state or the device isn't power manageable by the
734 * platform at all, we try to detect D3cold by testing accessibility of the
735 * vendor ID in config space.
737 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
739 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
740 !pci_device_is_present(dev
)) {
741 dev
->current_state
= PCI_D3cold
;
742 } else if (dev
->pm_cap
) {
745 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
746 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
748 dev
->current_state
= state
;
753 * pci_power_up - Put the given device into D0 forcibly
754 * @dev: PCI device to power up
756 void pci_power_up(struct pci_dev
*dev
)
758 if (platform_pci_power_manageable(dev
))
759 platform_pci_set_power_state(dev
, PCI_D0
);
761 pci_raw_set_power_state(dev
, PCI_D0
);
762 pci_update_current_state(dev
, PCI_D0
);
766 * pci_platform_power_transition - Use platform to change device power state
767 * @dev: PCI device to handle.
768 * @state: State to put the device into.
770 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
774 if (platform_pci_power_manageable(dev
)) {
775 error
= platform_pci_set_power_state(dev
, state
);
777 pci_update_current_state(dev
, state
);
781 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
782 dev
->current_state
= PCI_D0
;
788 * pci_wakeup - Wake up a PCI device
789 * @pci_dev: Device to handle.
790 * @ign: ignored parameter
792 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
794 pci_wakeup_event(pci_dev
);
795 pm_request_resume(&pci_dev
->dev
);
800 * pci_wakeup_bus - Walk given bus and wake up devices on it
801 * @bus: Top bus of the subtree to walk.
803 static void pci_wakeup_bus(struct pci_bus
*bus
)
806 pci_walk_bus(bus
, pci_wakeup
, NULL
);
810 * __pci_start_power_transition - Start power transition of a PCI device
811 * @dev: PCI device to handle.
812 * @state: State to put the device into.
814 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
816 if (state
== PCI_D0
) {
817 pci_platform_power_transition(dev
, PCI_D0
);
819 * Mandatory power management transition delays, see
820 * PCI Express Base Specification Revision 2.0 Section
821 * 6.6.1: Conventional Reset. Do not delay for
822 * devices powered on/off by corresponding bridge,
823 * because have already delayed for the bridge.
825 if (dev
->runtime_d3cold
) {
826 if (dev
->d3cold_delay
)
827 msleep(dev
->d3cold_delay
);
829 * When powering on a bridge from D3cold, the
830 * whole hierarchy may be powered on into
831 * D0uninitialized state, resume them to give
832 * them a chance to suspend again
834 pci_wakeup_bus(dev
->subordinate
);
840 * __pci_dev_set_current_state - Set current state of a PCI device
841 * @dev: Device to handle
842 * @data: pointer to state to be set
844 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
846 pci_power_t state
= *(pci_power_t
*)data
;
848 dev
->current_state
= state
;
853 * __pci_bus_set_current_state - Walk given bus and set current state of devices
854 * @bus: Top bus of the subtree to walk.
855 * @state: state to be set
857 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
860 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
864 * __pci_complete_power_transition - Complete power transition of a PCI device
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 * This function should not be called directly by device drivers.
870 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
876 ret
= pci_platform_power_transition(dev
, state
);
877 /* Power off the bridge may power off the whole hierarchy */
878 if (!ret
&& state
== PCI_D3cold
)
879 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
885 * pci_set_power_state - Set the power state of a PCI device
886 * @dev: PCI device to handle.
887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
889 * Transition a device to a new power state, using the platform firmware and/or
890 * the device's PCI PM registers.
893 * -EINVAL if the requested state is invalid.
894 * -EIO if device does not support PCI PM or its PM capabilities register has a
895 * wrong version, or device doesn't support the requested state.
896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
897 * 0 if device already is in the requested state.
898 * 0 if the transition is to D3 but D3 is not supported.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
905 /* bound the state we're entering */
906 if (state
> PCI_D3cold
)
908 else if (state
< PCI_D0
)
910 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev
->current_state
== state
)
922 __pci_start_power_transition(dev
, state
);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
936 if (!__pci_complete_power_transition(dev
, state
))
941 EXPORT_SYMBOL(pci_set_power_state
);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
960 ret
= platform_pci_choose_state(dev
);
961 if (ret
!= PCI_POWER_ERROR
)
964 switch (state
.event
) {
967 case PM_EVENT_FREEZE
:
968 case PM_EVENT_PRETHAW
:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND
:
971 case PM_EVENT_HIBERNATE
:
974 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state
);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
985 u16 cap
, bool extended
)
987 struct pci_cap_saved_state
*tmp
;
989 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
990 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
996 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
998 return _pci_find_saved_cap(dev
, cap
, false);
1001 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1003 return _pci_find_saved_cap(dev
, cap
, true);
1006 static int pci_save_pcie_state(struct pci_dev
*dev
)
1009 struct pci_cap_saved_state
*save_state
;
1012 if (!pci_is_pcie(dev
))
1015 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1017 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1021 cap
= (u16
*)&save_state
->cap
.data
[0];
1022 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1023 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1024 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1025 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1026 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1027 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1028 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1033 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1036 struct pci_cap_saved_state
*save_state
;
1039 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1043 cap
= (u16
*)&save_state
->cap
.data
[0];
1044 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1045 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1046 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1047 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1048 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1049 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1050 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1054 static int pci_save_pcix_state(struct pci_dev
*dev
)
1057 struct pci_cap_saved_state
*save_state
;
1059 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1063 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1065 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1069 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1070 (u16
*)save_state
->cap
.data
);
1075 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1078 struct pci_cap_saved_state
*save_state
;
1081 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1082 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1083 if (!save_state
|| !pos
)
1085 cap
= (u16
*)&save_state
->cap
.data
[0];
1087 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev
*dev
)
1098 /* XXX: 100% dword access ok here? */
1099 for (i
= 0; i
< 16; i
++)
1100 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1101 dev
->state_saved
= true;
1103 i
= pci_save_pcie_state(dev
);
1107 i
= pci_save_pcix_state(dev
);
1111 return pci_save_vc_state(dev
);
1113 EXPORT_SYMBOL(pci_save_state
);
1115 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1116 u32 saved_val
, int retry
, bool force
)
1120 pci_read_config_dword(pdev
, offset
, &val
);
1121 if (!force
&& val
== saved_val
)
1125 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset
, val
, saved_val
);
1127 pci_write_config_dword(pdev
, offset
, saved_val
);
1131 pci_read_config_dword(pdev
, offset
, &val
);
1132 if (val
== saved_val
)
1139 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1140 int start
, int end
, int retry
,
1145 for (index
= end
; index
>= start
; index
--)
1146 pci_restore_config_dword(pdev
, 4 * index
,
1147 pdev
->saved_config_space
[index
],
1151 static void pci_restore_config_space(struct pci_dev
*pdev
)
1153 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1154 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1155 /* Restore BARs before the command register. */
1156 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1157 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1158 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1159 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1162 * Force rewriting of prefetch registers to avoid S3 resume
1163 * issues on Intel PCI bridges that occur when these
1164 * registers are not explicitly written.
1166 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1167 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1169 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1173 static void pci_restore_rebar_state(struct pci_dev
*pdev
)
1175 unsigned int pos
, nbars
, i
;
1178 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
1182 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1183 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
1184 PCI_REBAR_CTRL_NBAR_SHIFT
;
1186 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
1187 struct resource
*res
;
1190 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1191 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
1192 res
= pdev
->resource
+ bar_idx
;
1193 size
= order_base_2((resource_size(res
) >> 20) | 1) - 1;
1194 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
1196 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
1201 * pci_restore_state - Restore the saved state of a PCI device
1202 * @dev: - PCI device that we're dealing with
1204 void pci_restore_state(struct pci_dev
*dev
)
1206 if (!dev
->state_saved
)
1209 /* PCI Express register must be restored first */
1210 pci_restore_pcie_state(dev
);
1211 pci_restore_pasid_state(dev
);
1212 pci_restore_pri_state(dev
);
1213 pci_restore_ats_state(dev
);
1214 pci_restore_vc_state(dev
);
1215 pci_restore_rebar_state(dev
);
1217 pci_cleanup_aer_error_status_regs(dev
);
1219 pci_restore_config_space(dev
);
1221 pci_restore_pcix_state(dev
);
1222 pci_restore_msi_state(dev
);
1224 /* Restore ACS and IOV configuration state */
1225 pci_enable_acs(dev
);
1226 pci_restore_iov_state(dev
);
1228 dev
->state_saved
= false;
1230 EXPORT_SYMBOL(pci_restore_state
);
1232 struct pci_saved_state
{
1233 u32 config_space
[16];
1234 struct pci_cap_saved_data cap
[0];
1238 * pci_store_saved_state - Allocate and return an opaque struct containing
1239 * the device saved state.
1240 * @dev: PCI device that we're dealing with
1242 * Return NULL if no state or error.
1244 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1246 struct pci_saved_state
*state
;
1247 struct pci_cap_saved_state
*tmp
;
1248 struct pci_cap_saved_data
*cap
;
1251 if (!dev
->state_saved
)
1254 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1256 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1257 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1259 state
= kzalloc(size
, GFP_KERNEL
);
1263 memcpy(state
->config_space
, dev
->saved_config_space
,
1264 sizeof(state
->config_space
));
1267 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1268 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1269 memcpy(cap
, &tmp
->cap
, len
);
1270 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1272 /* Empty cap_save terminates list */
1276 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1279 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1280 * @dev: PCI device that we're dealing with
1281 * @state: Saved state returned from pci_store_saved_state()
1283 int pci_load_saved_state(struct pci_dev
*dev
,
1284 struct pci_saved_state
*state
)
1286 struct pci_cap_saved_data
*cap
;
1288 dev
->state_saved
= false;
1293 memcpy(dev
->saved_config_space
, state
->config_space
,
1294 sizeof(state
->config_space
));
1298 struct pci_cap_saved_state
*tmp
;
1300 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1301 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1304 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1305 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1306 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1309 dev
->state_saved
= true;
1312 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1315 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1316 * and free the memory allocated for it.
1317 * @dev: PCI device that we're dealing with
1318 * @state: Pointer to saved state returned from pci_store_saved_state()
1320 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1321 struct pci_saved_state
**state
)
1323 int ret
= pci_load_saved_state(dev
, *state
);
1328 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1330 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1332 return pci_enable_resources(dev
, bars
);
1335 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1338 struct pci_dev
*bridge
;
1342 err
= pci_set_power_state(dev
, PCI_D0
);
1343 if (err
< 0 && err
!= -EIO
)
1346 bridge
= pci_upstream_bridge(dev
);
1348 pcie_aspm_powersave_config_link(bridge
);
1350 err
= pcibios_enable_device(dev
, bars
);
1353 pci_fixup_device(pci_fixup_enable
, dev
);
1355 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1358 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1360 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1361 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1362 pci_write_config_word(dev
, PCI_COMMAND
,
1363 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1370 * pci_reenable_device - Resume abandoned device
1371 * @dev: PCI device to be resumed
1373 * Note this function is a backend of pci_default_resume and is not supposed
1374 * to be called by normal code, write proper resume handler and use it instead.
1376 int pci_reenable_device(struct pci_dev
*dev
)
1378 if (pci_is_enabled(dev
))
1379 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1382 EXPORT_SYMBOL(pci_reenable_device
);
1384 static void pci_enable_bridge(struct pci_dev
*dev
)
1386 struct pci_dev
*bridge
;
1389 bridge
= pci_upstream_bridge(dev
);
1391 pci_enable_bridge(bridge
);
1393 if (pci_is_enabled(dev
)) {
1394 if (!dev
->is_busmaster
)
1395 pci_set_master(dev
);
1399 retval
= pci_enable_device(dev
);
1401 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1403 pci_set_master(dev
);
1406 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1408 struct pci_dev
*bridge
;
1413 * Power state could be unknown at this point, either due to a fresh
1414 * boot or a device removal call. So get the current power state
1415 * so that things like MSI message writing will behave as expected
1416 * (e.g. if the device really is in D0 at enable time).
1420 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1421 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1424 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1425 return 0; /* already enabled */
1427 bridge
= pci_upstream_bridge(dev
);
1429 pci_enable_bridge(bridge
);
1431 /* only skip sriov related */
1432 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1433 if (dev
->resource
[i
].flags
& flags
)
1435 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1436 if (dev
->resource
[i
].flags
& flags
)
1439 err
= do_pci_enable_device(dev
, bars
);
1441 atomic_dec(&dev
->enable_cnt
);
1446 * pci_enable_device_io - Initialize a device for use with IO space
1447 * @dev: PCI device to be initialized
1449 * Initialize device before it's used by a driver. Ask low-level code
1450 * to enable I/O resources. Wake up the device if it was suspended.
1451 * Beware, this function can fail.
1453 int pci_enable_device_io(struct pci_dev
*dev
)
1455 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1457 EXPORT_SYMBOL(pci_enable_device_io
);
1460 * pci_enable_device_mem - Initialize a device for use with Memory space
1461 * @dev: PCI device to be initialized
1463 * Initialize device before it's used by a driver. Ask low-level code
1464 * to enable Memory resources. Wake up the device if it was suspended.
1465 * Beware, this function can fail.
1467 int pci_enable_device_mem(struct pci_dev
*dev
)
1469 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1471 EXPORT_SYMBOL(pci_enable_device_mem
);
1474 * pci_enable_device - Initialize device before it's used by a driver.
1475 * @dev: PCI device to be initialized
1477 * Initialize device before it's used by a driver. Ask low-level code
1478 * to enable I/O and memory. Wake up the device if it was suspended.
1479 * Beware, this function can fail.
1481 * Note we don't actually enable the device many times if we call
1482 * this function repeatedly (we just increment the count).
1484 int pci_enable_device(struct pci_dev
*dev
)
1486 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1488 EXPORT_SYMBOL(pci_enable_device
);
1491 * Managed PCI resources. This manages device on/off, intx/msi/msix
1492 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1493 * there's no need to track it separately. pci_devres is initialized
1494 * when a device is enabled using managed PCI device enable interface.
1497 unsigned int enabled
:1;
1498 unsigned int pinned
:1;
1499 unsigned int orig_intx
:1;
1500 unsigned int restore_intx
:1;
1505 static void pcim_release(struct device
*gendev
, void *res
)
1507 struct pci_dev
*dev
= to_pci_dev(gendev
);
1508 struct pci_devres
*this = res
;
1511 if (dev
->msi_enabled
)
1512 pci_disable_msi(dev
);
1513 if (dev
->msix_enabled
)
1514 pci_disable_msix(dev
);
1516 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1517 if (this->region_mask
& (1 << i
))
1518 pci_release_region(dev
, i
);
1523 if (this->restore_intx
)
1524 pci_intx(dev
, this->orig_intx
);
1526 if (this->enabled
&& !this->pinned
)
1527 pci_disable_device(dev
);
1530 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1532 struct pci_devres
*dr
, *new_dr
;
1534 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1538 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1541 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1544 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1546 if (pci_is_managed(pdev
))
1547 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1552 * pcim_enable_device - Managed pci_enable_device()
1553 * @pdev: PCI device to be initialized
1555 * Managed pci_enable_device().
1557 int pcim_enable_device(struct pci_dev
*pdev
)
1559 struct pci_devres
*dr
;
1562 dr
= get_pci_dr(pdev
);
1568 rc
= pci_enable_device(pdev
);
1570 pdev
->is_managed
= 1;
1575 EXPORT_SYMBOL(pcim_enable_device
);
1578 * pcim_pin_device - Pin managed PCI device
1579 * @pdev: PCI device to pin
1581 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1582 * driver detach. @pdev must have been enabled with
1583 * pcim_enable_device().
1585 void pcim_pin_device(struct pci_dev
*pdev
)
1587 struct pci_devres
*dr
;
1589 dr
= find_pci_dr(pdev
);
1590 WARN_ON(!dr
|| !dr
->enabled
);
1594 EXPORT_SYMBOL(pcim_pin_device
);
1597 * pcibios_add_device - provide arch specific hooks when adding device dev
1598 * @dev: the PCI device being added
1600 * Permits the platform to provide architecture specific functionality when
1601 * devices are added. This is the default implementation. Architecture
1602 * implementations can override this.
1604 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1610 * pcibios_release_device - provide arch specific hooks when releasing device dev
1611 * @dev: the PCI device being released
1613 * Permits the platform to provide architecture specific functionality when
1614 * devices are released. This is the default implementation. Architecture
1615 * implementations can override this.
1617 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1620 * pcibios_disable_device - disable arch specific PCI resources for device dev
1621 * @dev: the PCI device to disable
1623 * Disables architecture specific PCI resources for the device. This
1624 * is the default implementation. Architecture implementations can
1627 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
1630 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1631 * @irq: ISA IRQ to penalize
1632 * @active: IRQ active or not
1634 * Permits the platform to provide architecture-specific functionality when
1635 * penalizing ISA IRQs. This is the default implementation. Architecture
1636 * implementations can override this.
1638 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1640 static void do_pci_disable_device(struct pci_dev
*dev
)
1644 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1645 if (pci_command
& PCI_COMMAND_MASTER
) {
1646 pci_command
&= ~PCI_COMMAND_MASTER
;
1647 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1650 pcibios_disable_device(dev
);
1654 * pci_disable_enabled_device - Disable device without updating enable_cnt
1655 * @dev: PCI device to disable
1657 * NOTE: This function is a backend of PCI power management routines and is
1658 * not supposed to be called drivers.
1660 void pci_disable_enabled_device(struct pci_dev
*dev
)
1662 if (pci_is_enabled(dev
))
1663 do_pci_disable_device(dev
);
1667 * pci_disable_device - Disable PCI device after use
1668 * @dev: PCI device to be disabled
1670 * Signal to the system that the PCI device is not in use by the system
1671 * anymore. This only involves disabling PCI bus-mastering, if active.
1673 * Note we don't actually disable the device until all callers of
1674 * pci_enable_device() have called pci_disable_device().
1676 void pci_disable_device(struct pci_dev
*dev
)
1678 struct pci_devres
*dr
;
1680 dr
= find_pci_dr(dev
);
1684 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1685 "disabling already-disabled device");
1687 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1690 do_pci_disable_device(dev
);
1692 dev
->is_busmaster
= 0;
1694 EXPORT_SYMBOL(pci_disable_device
);
1697 * pcibios_set_pcie_reset_state - set reset state for device dev
1698 * @dev: the PCIe device reset
1699 * @state: Reset state to enter into
1702 * Sets the PCIe reset state for the device. This is the default
1703 * implementation. Architecture implementations can override this.
1705 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1706 enum pcie_reset_state state
)
1712 * pci_set_pcie_reset_state - set reset state for device dev
1713 * @dev: the PCIe device reset
1714 * @state: Reset state to enter into
1717 * Sets the PCI reset state for the device.
1719 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1721 return pcibios_set_pcie_reset_state(dev
, state
);
1723 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1726 * pci_check_pme_status - Check if given device has generated PME.
1727 * @dev: Device to check.
1729 * Check the PME status of the device and if set, clear it and clear PME enable
1730 * (if set). Return 'true' if PME status and PME enable were both set or
1731 * 'false' otherwise.
1733 bool pci_check_pme_status(struct pci_dev
*dev
)
1742 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1743 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1744 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1747 /* Clear PME status. */
1748 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1749 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1750 /* Disable PME to avoid interrupt flood. */
1751 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1755 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1761 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1762 * @dev: Device to handle.
1763 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1765 * Check if @dev has generated PME and queue a resume request for it in that
1768 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1770 if (pme_poll_reset
&& dev
->pme_poll
)
1771 dev
->pme_poll
= false;
1773 if (pci_check_pme_status(dev
)) {
1774 pci_wakeup_event(dev
);
1775 pm_request_resume(&dev
->dev
);
1781 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1782 * @bus: Top bus of the subtree to walk.
1784 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1787 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1792 * pci_pme_capable - check the capability of PCI device to generate PME#
1793 * @dev: PCI device to handle.
1794 * @state: PCI state from which device will issue PME#.
1796 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1801 return !!(dev
->pme_support
& (1 << state
));
1803 EXPORT_SYMBOL(pci_pme_capable
);
1805 static void pci_pme_list_scan(struct work_struct
*work
)
1807 struct pci_pme_device
*pme_dev
, *n
;
1809 mutex_lock(&pci_pme_list_mutex
);
1810 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1811 if (pme_dev
->dev
->pme_poll
) {
1812 struct pci_dev
*bridge
;
1814 bridge
= pme_dev
->dev
->bus
->self
;
1816 * If bridge is in low power state, the
1817 * configuration space of subordinate devices
1818 * may be not accessible
1820 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1822 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1824 list_del(&pme_dev
->list
);
1828 if (!list_empty(&pci_pme_list
))
1829 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
1830 msecs_to_jiffies(PME_TIMEOUT
));
1831 mutex_unlock(&pci_pme_list_mutex
);
1834 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
1838 if (!dev
->pme_support
)
1841 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1842 /* Clear PME_Status by writing 1 to it and enable PME# */
1843 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1845 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1847 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1851 * pci_pme_restore - Restore PME configuration after config space restore.
1852 * @dev: PCI device to update.
1854 void pci_pme_restore(struct pci_dev
*dev
)
1858 if (!dev
->pme_support
)
1861 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1862 if (dev
->wakeup_prepared
) {
1863 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
1864 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
1866 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1867 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1869 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1873 * pci_pme_active - enable or disable PCI device's PME# function
1874 * @dev: PCI device to handle.
1875 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1877 * The caller must verify that the device is capable of generating PME# before
1878 * calling this function with @enable equal to 'true'.
1880 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1882 __pci_pme_active(dev
, enable
);
1885 * PCI (as opposed to PCIe) PME requires that the device have
1886 * its PME# line hooked up correctly. Not all hardware vendors
1887 * do this, so the PME never gets delivered and the device
1888 * remains asleep. The easiest way around this is to
1889 * periodically walk the list of suspended devices and check
1890 * whether any have their PME flag set. The assumption is that
1891 * we'll wake up often enough anyway that this won't be a huge
1892 * hit, and the power savings from the devices will still be a
1895 * Although PCIe uses in-band PME message instead of PME# line
1896 * to report PME, PME does not work for some PCIe devices in
1897 * reality. For example, there are devices that set their PME
1898 * status bits, but don't really bother to send a PME message;
1899 * there are PCI Express Root Ports that don't bother to
1900 * trigger interrupts when they receive PME messages from the
1901 * devices below. So PME poll is used for PCIe devices too.
1904 if (dev
->pme_poll
) {
1905 struct pci_pme_device
*pme_dev
;
1907 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1910 dev_warn(&dev
->dev
, "can't enable PME#\n");
1914 mutex_lock(&pci_pme_list_mutex
);
1915 list_add(&pme_dev
->list
, &pci_pme_list
);
1916 if (list_is_singular(&pci_pme_list
))
1917 queue_delayed_work(system_freezable_wq
,
1919 msecs_to_jiffies(PME_TIMEOUT
));
1920 mutex_unlock(&pci_pme_list_mutex
);
1922 mutex_lock(&pci_pme_list_mutex
);
1923 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1924 if (pme_dev
->dev
== dev
) {
1925 list_del(&pme_dev
->list
);
1930 mutex_unlock(&pci_pme_list_mutex
);
1934 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1936 EXPORT_SYMBOL(pci_pme_active
);
1939 * __pci_enable_wake - enable PCI device as wakeup event source
1940 * @dev: PCI device affected
1941 * @state: PCI state from which device will issue wakeup events
1942 * @enable: True to enable event generation; false to disable
1944 * This enables the device as a wakeup event source, or disables it.
1945 * When such events involves platform-specific hooks, those hooks are
1946 * called automatically by this routine.
1948 * Devices with legacy power management (no standard PCI PM capabilities)
1949 * always require such platform hooks.
1952 * 0 is returned on success
1953 * -EINVAL is returned if device is not supposed to wake up the system
1954 * Error code depending on the platform is returned if both the platform and
1955 * the native mechanism fail to enable the generation of wake-up events
1957 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
1962 * Bridges can only signal wakeup on behalf of subordinate devices,
1963 * but that is set up elsewhere, so skip them.
1965 if (pci_has_subordinate(dev
))
1968 /* Don't do the same thing twice in a row for one device. */
1969 if (!!enable
== !!dev
->wakeup_prepared
)
1973 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1974 * Anderson we should be doing PME# wake enable followed by ACPI wake
1975 * enable. To disable wake-up we call the platform first, for symmetry.
1981 if (pci_pme_capable(dev
, state
))
1982 pci_pme_active(dev
, true);
1985 error
= platform_pci_set_wakeup(dev
, true);
1989 dev
->wakeup_prepared
= true;
1991 platform_pci_set_wakeup(dev
, false);
1992 pci_pme_active(dev
, false);
1993 dev
->wakeup_prepared
= false;
2000 * pci_enable_wake - change wakeup settings for a PCI device
2001 * @pci_dev: Target device
2002 * @state: PCI state from which device will issue wakeup events
2003 * @enable: Whether or not to enable event generation
2005 * If @enable is set, check device_may_wakeup() for the device before calling
2006 * __pci_enable_wake() for it.
2008 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
2010 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
2013 return __pci_enable_wake(pci_dev
, state
, enable
);
2015 EXPORT_SYMBOL(pci_enable_wake
);
2018 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2019 * @dev: PCI device to prepare
2020 * @enable: True to enable wake-up event generation; false to disable
2022 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2023 * and this function allows them to set that up cleanly - pci_enable_wake()
2024 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2025 * ordering constraints.
2027 * This function only returns error code if the device is not allowed to wake
2028 * up the system from sleep or it is not capable of generating PME# from both
2029 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2031 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2033 return pci_pme_capable(dev
, PCI_D3cold
) ?
2034 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2035 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2037 EXPORT_SYMBOL(pci_wake_from_d3
);
2040 * pci_target_state - find an appropriate low power state for a given PCI dev
2042 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2044 * Use underlying platform code to find a supported low power state for @dev.
2045 * If the platform can't manage @dev, return the deepest state from which it
2046 * can generate wake events, based on any available PME info.
2048 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2050 pci_power_t target_state
= PCI_D3hot
;
2052 if (platform_pci_power_manageable(dev
)) {
2054 * Call the platform to choose the target state of the device
2055 * and enable wake-up from this state if supported.
2057 pci_power_t state
= platform_pci_choose_state(dev
);
2060 case PCI_POWER_ERROR
:
2065 if (pci_no_d1d2(dev
))
2068 target_state
= state
;
2071 return target_state
;
2075 target_state
= PCI_D0
;
2078 * If the device is in D3cold even though it's not power-manageable by
2079 * the platform, it may have been powered down by non-standard means.
2080 * Best to let it slumber.
2082 if (dev
->current_state
== PCI_D3cold
)
2083 target_state
= PCI_D3cold
;
2087 * Find the deepest state from which the device can generate
2088 * wake-up events, make it the target state and enable device
2091 if (dev
->pme_support
) {
2093 && !(dev
->pme_support
& (1 << target_state
)))
2098 return target_state
;
2102 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2103 * @dev: Device to handle.
2105 * Choose the power state appropriate for the device depending on whether
2106 * it can wake up the system and/or is power manageable by the platform
2107 * (PCI_D3hot is the default) and put the device into that state.
2109 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2111 bool wakeup
= device_may_wakeup(&dev
->dev
);
2112 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2115 if (target_state
== PCI_POWER_ERROR
)
2118 pci_enable_wake(dev
, target_state
, wakeup
);
2120 error
= pci_set_power_state(dev
, target_state
);
2123 pci_enable_wake(dev
, target_state
, false);
2127 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2130 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2131 * @dev: Device to handle.
2133 * Disable device's system wake-up capability and put it into D0.
2135 int pci_back_from_sleep(struct pci_dev
*dev
)
2137 pci_enable_wake(dev
, PCI_D0
, false);
2138 return pci_set_power_state(dev
, PCI_D0
);
2140 EXPORT_SYMBOL(pci_back_from_sleep
);
2143 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2144 * @dev: PCI device being suspended.
2146 * Prepare @dev to generate wake-up events at run time and put it into a low
2149 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2151 pci_power_t target_state
;
2154 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2155 if (target_state
== PCI_POWER_ERROR
)
2158 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2160 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2162 error
= pci_set_power_state(dev
, target_state
);
2165 pci_enable_wake(dev
, target_state
, false);
2166 dev
->runtime_d3cold
= false;
2173 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2174 * @dev: Device to check.
2176 * Return true if the device itself is capable of generating wake-up events
2177 * (through the platform or using the native PCIe PME) or if the device supports
2178 * PME and one of its upstream bridges can generate wake-up events.
2180 bool pci_dev_run_wake(struct pci_dev
*dev
)
2182 struct pci_bus
*bus
= dev
->bus
;
2184 if (!dev
->pme_support
)
2187 /* PME-capable in principle, but not from the target power state */
2188 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2191 if (device_can_wakeup(&dev
->dev
))
2194 while (bus
->parent
) {
2195 struct pci_dev
*bridge
= bus
->self
;
2197 if (device_can_wakeup(&bridge
->dev
))
2203 /* We have reached the root bus. */
2205 return device_can_wakeup(bus
->bridge
);
2209 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2212 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2213 * @pci_dev: Device to check.
2215 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2216 * reconfigured due to wakeup settings difference between system and runtime
2217 * suspend and the current power state of it is suitable for the upcoming
2218 * (system) transition.
2220 * If the device is not configured for system wakeup, disable PME for it before
2221 * returning 'true' to prevent it from waking up the system unnecessarily.
2223 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2225 struct device
*dev
= &pci_dev
->dev
;
2226 bool wakeup
= device_may_wakeup(dev
);
2228 if (!pm_runtime_suspended(dev
)
2229 || pci_target_state(pci_dev
, wakeup
) != pci_dev
->current_state
2230 || platform_pci_need_resume(pci_dev
))
2234 * At this point the device is good to go unless it's been configured
2235 * to generate PME at the runtime suspend time, but it is not supposed
2236 * to wake up the system. In that case, simply disable PME for it
2237 * (it will have to be re-enabled on exit from system resume).
2239 * If the device's power state is D3cold and the platform check above
2240 * hasn't triggered, the device's configuration is suitable and we don't
2241 * need to manipulate it at all.
2243 spin_lock_irq(&dev
->power
.lock
);
2245 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
&&
2247 __pci_pme_active(pci_dev
, false);
2249 spin_unlock_irq(&dev
->power
.lock
);
2254 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2255 * @pci_dev: Device to handle.
2257 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2258 * it might have been disabled during the prepare phase of system suspend if
2259 * the device was not configured for system wakeup.
2261 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2263 struct device
*dev
= &pci_dev
->dev
;
2265 if (!pci_dev_run_wake(pci_dev
))
2268 spin_lock_irq(&dev
->power
.lock
);
2270 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2271 __pci_pme_active(pci_dev
, true);
2273 spin_unlock_irq(&dev
->power
.lock
);
2276 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2278 struct device
*dev
= &pdev
->dev
;
2279 struct device
*parent
= dev
->parent
;
2282 pm_runtime_get_sync(parent
);
2283 pm_runtime_get_noresume(dev
);
2285 * pdev->current_state is set to PCI_D3cold during suspending,
2286 * so wait until suspending completes
2288 pm_runtime_barrier(dev
);
2290 * Only need to resume devices in D3cold, because config
2291 * registers are still accessible for devices suspended but
2294 if (pdev
->current_state
== PCI_D3cold
)
2295 pm_runtime_resume(dev
);
2298 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2300 struct device
*dev
= &pdev
->dev
;
2301 struct device
*parent
= dev
->parent
;
2303 pm_runtime_put(dev
);
2305 pm_runtime_put_sync(parent
);
2309 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2310 * @bridge: Bridge to check
2312 * This function checks if it is possible to move the bridge to D3.
2313 * Currently we only allow D3 for recent enough PCIe ports.
2315 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2319 if (!pci_is_pcie(bridge
))
2322 switch (pci_pcie_type(bridge
)) {
2323 case PCI_EXP_TYPE_ROOT_PORT
:
2324 case PCI_EXP_TYPE_UPSTREAM
:
2325 case PCI_EXP_TYPE_DOWNSTREAM
:
2326 if (pci_bridge_d3_disable
)
2330 * Hotplug interrupts cannot be delivered if the link is down,
2331 * so parents of a hotplug port must stay awake. In addition,
2332 * hotplug ports handled by firmware in System Management Mode
2333 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2334 * For simplicity, disallow in general for now.
2336 if (bridge
->is_hotplug_bridge
)
2339 if (pci_bridge_d3_force
)
2343 * It should be safe to put PCIe ports from 2015 or newer
2346 if (dmi_get_date(DMI_BIOS_DATE
, &year
, NULL
, NULL
) &&
2356 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2358 bool *d3cold_ok
= data
;
2360 if (/* The device needs to be allowed to go D3cold ... */
2361 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
2363 /* ... and if it is wakeup capable to do so from D3cold. */
2364 (device_may_wakeup(&dev
->dev
) &&
2365 !pci_pme_capable(dev
, PCI_D3cold
)) ||
2367 /* If it is a bridge it must be allowed to go to D3. */
2368 !pci_power_manageable(dev
))
2376 * pci_bridge_d3_update - Update bridge D3 capabilities
2377 * @dev: PCI device which is changed
2379 * Update upstream bridge PM capabilities accordingly depending on if the
2380 * device PM configuration was changed or the device is being removed. The
2381 * change is also propagated upstream.
2383 void pci_bridge_d3_update(struct pci_dev
*dev
)
2385 bool remove
= !device_is_registered(&dev
->dev
);
2386 struct pci_dev
*bridge
;
2387 bool d3cold_ok
= true;
2389 bridge
= pci_upstream_bridge(dev
);
2390 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
2394 * If D3 is currently allowed for the bridge, removing one of its
2395 * children won't change that.
2397 if (remove
&& bridge
->bridge_d3
)
2401 * If D3 is currently allowed for the bridge and a child is added or
2402 * changed, disallowance of D3 can only be caused by that child, so
2403 * we only need to check that single device, not any of its siblings.
2405 * If D3 is currently not allowed for the bridge, checking the device
2406 * first may allow us to skip checking its siblings.
2409 pci_dev_check_d3cold(dev
, &d3cold_ok
);
2412 * If D3 is currently not allowed for the bridge, this may be caused
2413 * either by the device being changed/removed or any of its siblings,
2414 * so we need to go through all children to find out if one of them
2415 * continues to block D3.
2417 if (d3cold_ok
&& !bridge
->bridge_d3
)
2418 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
2421 if (bridge
->bridge_d3
!= d3cold_ok
) {
2422 bridge
->bridge_d3
= d3cold_ok
;
2423 /* Propagate change to upstream bridges */
2424 pci_bridge_d3_update(bridge
);
2429 * pci_d3cold_enable - Enable D3cold for device
2430 * @dev: PCI device to handle
2432 * This function can be used in drivers to enable D3cold from the device
2433 * they handle. It also updates upstream PCI bridge PM capabilities
2436 void pci_d3cold_enable(struct pci_dev
*dev
)
2438 if (dev
->no_d3cold
) {
2439 dev
->no_d3cold
= false;
2440 pci_bridge_d3_update(dev
);
2443 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
2446 * pci_d3cold_disable - Disable D3cold for device
2447 * @dev: PCI device to handle
2449 * This function can be used in drivers to disable D3cold from the device
2450 * they handle. It also updates upstream PCI bridge PM capabilities
2453 void pci_d3cold_disable(struct pci_dev
*dev
)
2455 if (!dev
->no_d3cold
) {
2456 dev
->no_d3cold
= true;
2457 pci_bridge_d3_update(dev
);
2460 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
2463 * pci_pm_init - Initialize PM functions of given PCI device
2464 * @dev: PCI device to handle.
2466 void pci_pm_init(struct pci_dev
*dev
)
2471 pm_runtime_forbid(&dev
->dev
);
2472 pm_runtime_set_active(&dev
->dev
);
2473 pm_runtime_enable(&dev
->dev
);
2474 device_enable_async_suspend(&dev
->dev
);
2475 dev
->wakeup_prepared
= false;
2478 dev
->pme_support
= 0;
2480 /* find PCI PM capability in list */
2481 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2484 /* Check device's ability to generate PME# */
2485 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2487 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2488 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2489 pmc
& PCI_PM_CAP_VER_MASK
);
2494 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2495 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2496 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
2497 dev
->d3cold_allowed
= true;
2499 dev
->d1_support
= false;
2500 dev
->d2_support
= false;
2501 if (!pci_no_d1d2(dev
)) {
2502 if (pmc
& PCI_PM_CAP_D1
)
2503 dev
->d1_support
= true;
2504 if (pmc
& PCI_PM_CAP_D2
)
2505 dev
->d2_support
= true;
2507 if (dev
->d1_support
|| dev
->d2_support
)
2508 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2509 dev
->d1_support
? " D1" : "",
2510 dev
->d2_support
? " D2" : "");
2513 pmc
&= PCI_PM_CAP_PME_MASK
;
2515 dev_printk(KERN_DEBUG
, &dev
->dev
,
2516 "PME# supported from%s%s%s%s%s\n",
2517 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2518 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2519 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2520 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2521 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2522 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2523 dev
->pme_poll
= true;
2525 * Make device's PM flags reflect the wake-up capability, but
2526 * let the user space enable it to wake up the system as needed.
2528 device_set_wakeup_capable(&dev
->dev
, true);
2529 /* Disable the PME# generation functionality */
2530 pci_pme_active(dev
, false);
2534 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
2536 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
2540 case PCI_EA_P_VF_MEM
:
2541 flags
|= IORESOURCE_MEM
;
2543 case PCI_EA_P_MEM_PREFETCH
:
2544 case PCI_EA_P_VF_MEM_PREFETCH
:
2545 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
2548 flags
|= IORESOURCE_IO
;
2557 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
2560 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
2561 return &dev
->resource
[bei
];
2562 #ifdef CONFIG_PCI_IOV
2563 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
2564 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
2565 return &dev
->resource
[PCI_IOV_RESOURCES
+
2566 bei
- PCI_EA_BEI_VF_BAR0
];
2568 else if (bei
== PCI_EA_BEI_ROM
)
2569 return &dev
->resource
[PCI_ROM_RESOURCE
];
2574 /* Read an Enhanced Allocation (EA) entry */
2575 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
2577 struct resource
*res
;
2578 int ent_size
, ent_offset
= offset
;
2579 resource_size_t start
, end
;
2580 unsigned long flags
;
2581 u32 dw0
, bei
, base
, max_offset
;
2583 bool support_64
= (sizeof(resource_size_t
) >= 8);
2585 pci_read_config_dword(dev
, ent_offset
, &dw0
);
2588 /* Entry size field indicates DWORDs after 1st */
2589 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
2591 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
2594 bei
= (dw0
& PCI_EA_BEI
) >> 4;
2595 prop
= (dw0
& PCI_EA_PP
) >> 8;
2598 * If the Property is in the reserved range, try the Secondary
2601 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
2602 prop
= (dw0
& PCI_EA_SP
) >> 16;
2603 if (prop
> PCI_EA_P_BRIDGE_IO
)
2606 res
= pci_ea_get_resource(dev
, bei
, prop
);
2608 dev_err(&dev
->dev
, "Unsupported EA entry BEI: %u\n", bei
);
2612 flags
= pci_ea_flags(dev
, prop
);
2614 dev_err(&dev
->dev
, "Unsupported EA properties: %#x\n", prop
);
2619 pci_read_config_dword(dev
, ent_offset
, &base
);
2620 start
= (base
& PCI_EA_FIELD_MASK
);
2623 /* Read MaxOffset */
2624 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
2627 /* Read Base MSBs (if 64-bit entry) */
2628 if (base
& PCI_EA_IS_64
) {
2631 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
2634 flags
|= IORESOURCE_MEM_64
;
2636 /* entry starts above 32-bit boundary, can't use */
2637 if (!support_64
&& base_upper
)
2641 start
|= ((u64
)base_upper
<< 32);
2644 end
= start
+ (max_offset
| 0x03);
2646 /* Read MaxOffset MSBs (if 64-bit entry) */
2647 if (max_offset
& PCI_EA_IS_64
) {
2648 u32 max_offset_upper
;
2650 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
2653 flags
|= IORESOURCE_MEM_64
;
2655 /* entry too big, can't use */
2656 if (!support_64
&& max_offset_upper
)
2660 end
+= ((u64
)max_offset_upper
<< 32);
2664 dev_err(&dev
->dev
, "EA Entry crosses address boundary\n");
2668 if (ent_size
!= ent_offset
- offset
) {
2670 "EA Entry Size (%d) does not match length read (%d)\n",
2671 ent_size
, ent_offset
- offset
);
2675 res
->name
= pci_name(dev
);
2680 if (bei
<= PCI_EA_BEI_BAR5
)
2681 dev_printk(KERN_DEBUG
, &dev
->dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2683 else if (bei
== PCI_EA_BEI_ROM
)
2684 dev_printk(KERN_DEBUG
, &dev
->dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2686 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
2687 dev_printk(KERN_DEBUG
, &dev
->dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2688 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
2690 dev_printk(KERN_DEBUG
, &dev
->dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2694 return offset
+ ent_size
;
2697 /* Enhanced Allocation Initialization */
2698 void pci_ea_init(struct pci_dev
*dev
)
2705 /* find PCI EA capability in list */
2706 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
2710 /* determine the number of entries */
2711 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
2713 num_ent
&= PCI_EA_NUM_ENT_MASK
;
2715 offset
= ea
+ PCI_EA_FIRST_ENT
;
2717 /* Skip DWORD 2 for type 1 functions */
2718 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2721 /* parse each EA entry */
2722 for (i
= 0; i
< num_ent
; ++i
)
2723 offset
= pci_ea_read(dev
, offset
);
2726 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2727 struct pci_cap_saved_state
*new_cap
)
2729 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2733 * _pci_add_cap_save_buffer - allocate buffer for saving given
2734 * capability registers
2735 * @dev: the PCI device
2736 * @cap: the capability to allocate the buffer for
2737 * @extended: Standard or Extended capability ID
2738 * @size: requested size of the buffer
2740 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2741 bool extended
, unsigned int size
)
2744 struct pci_cap_saved_state
*save_state
;
2747 pos
= pci_find_ext_capability(dev
, cap
);
2749 pos
= pci_find_capability(dev
, cap
);
2754 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2758 save_state
->cap
.cap_nr
= cap
;
2759 save_state
->cap
.cap_extended
= extended
;
2760 save_state
->cap
.size
= size
;
2761 pci_add_saved_cap(dev
, save_state
);
2766 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2768 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2771 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2773 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2777 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2778 * @dev: the PCI device
2780 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2784 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2785 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2788 "unable to preallocate PCI Express save buffer\n");
2790 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2793 "unable to preallocate PCI-X save buffer\n");
2795 pci_allocate_vc_save_buffers(dev
);
2798 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2800 struct pci_cap_saved_state
*tmp
;
2801 struct hlist_node
*n
;
2803 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2808 * pci_configure_ari - enable or disable ARI forwarding
2809 * @dev: the PCI device
2811 * If @dev and its upstream bridge both support ARI, enable ARI in the
2812 * bridge. Otherwise, disable ARI in the bridge.
2814 void pci_configure_ari(struct pci_dev
*dev
)
2817 struct pci_dev
*bridge
;
2819 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2822 bridge
= dev
->bus
->self
;
2826 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2827 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2830 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2831 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2832 PCI_EXP_DEVCTL2_ARI
);
2833 bridge
->ari_enabled
= 1;
2835 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2836 PCI_EXP_DEVCTL2_ARI
);
2837 bridge
->ari_enabled
= 0;
2841 static int pci_acs_enable
;
2844 * pci_request_acs - ask for ACS to be enabled if supported
2846 void pci_request_acs(void)
2852 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2853 * @dev: the PCI device
2855 static void pci_std_enable_acs(struct pci_dev
*dev
)
2861 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2865 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2866 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2868 /* Source Validation */
2869 ctrl
|= (cap
& PCI_ACS_SV
);
2871 /* P2P Request Redirect */
2872 ctrl
|= (cap
& PCI_ACS_RR
);
2874 /* P2P Completion Redirect */
2875 ctrl
|= (cap
& PCI_ACS_CR
);
2877 /* Upstream Forwarding */
2878 ctrl
|= (cap
& PCI_ACS_UF
);
2880 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2884 * pci_enable_acs - enable ACS if hardware support it
2885 * @dev: the PCI device
2887 void pci_enable_acs(struct pci_dev
*dev
)
2889 if (!pci_acs_enable
)
2892 if (!pci_dev_specific_enable_acs(dev
))
2895 pci_std_enable_acs(dev
);
2898 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2903 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2908 * Except for egress control, capabilities are either required
2909 * or only required if controllable. Features missing from the
2910 * capability field can therefore be assumed as hard-wired enabled.
2912 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2913 acs_flags
&= (cap
| PCI_ACS_EC
);
2915 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2916 return (ctrl
& acs_flags
) == acs_flags
;
2920 * pci_acs_enabled - test ACS against required flags for a given device
2921 * @pdev: device to test
2922 * @acs_flags: required PCI ACS flags
2924 * Return true if the device supports the provided flags. Automatically
2925 * filters out flags that are not implemented on multifunction devices.
2927 * Note that this interface checks the effective ACS capabilities of the
2928 * device rather than the actual capabilities. For instance, most single
2929 * function endpoints are not required to support ACS because they have no
2930 * opportunity for peer-to-peer access. We therefore return 'true'
2931 * regardless of whether the device exposes an ACS capability. This makes
2932 * it much easier for callers of this function to ignore the actual type
2933 * or topology of the device when testing ACS support.
2935 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2939 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2944 * Conventional PCI and PCI-X devices never support ACS, either
2945 * effectively or actually. The shared bus topology implies that
2946 * any device on the bus can receive or snoop DMA.
2948 if (!pci_is_pcie(pdev
))
2951 switch (pci_pcie_type(pdev
)) {
2953 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2954 * but since their primary interface is PCI/X, we conservatively
2955 * handle them as we would a non-PCIe device.
2957 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2959 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2960 * applicable... must never implement an ACS Extended Capability...".
2961 * This seems arbitrary, but we take a conservative interpretation
2962 * of this statement.
2964 case PCI_EXP_TYPE_PCI_BRIDGE
:
2965 case PCI_EXP_TYPE_RC_EC
:
2968 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2969 * implement ACS in order to indicate their peer-to-peer capabilities,
2970 * regardless of whether they are single- or multi-function devices.
2972 case PCI_EXP_TYPE_DOWNSTREAM
:
2973 case PCI_EXP_TYPE_ROOT_PORT
:
2974 return pci_acs_flags_enabled(pdev
, acs_flags
);
2976 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2977 * implemented by the remaining PCIe types to indicate peer-to-peer
2978 * capabilities, but only when they are part of a multifunction
2979 * device. The footnote for section 6.12 indicates the specific
2980 * PCIe types included here.
2982 case PCI_EXP_TYPE_ENDPOINT
:
2983 case PCI_EXP_TYPE_UPSTREAM
:
2984 case PCI_EXP_TYPE_LEG_END
:
2985 case PCI_EXP_TYPE_RC_END
:
2986 if (!pdev
->multifunction
)
2989 return pci_acs_flags_enabled(pdev
, acs_flags
);
2993 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2994 * to single function devices with the exception of downstream ports.
3000 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3001 * @start: starting downstream device
3002 * @end: ending upstream device or NULL to search to the root bus
3003 * @acs_flags: required flags
3005 * Walk up a device tree from start to end testing PCI ACS support. If
3006 * any step along the way does not support the required flags, return false.
3008 bool pci_acs_path_enabled(struct pci_dev
*start
,
3009 struct pci_dev
*end
, u16 acs_flags
)
3011 struct pci_dev
*pdev
, *parent
= start
;
3016 if (!pci_acs_enabled(pdev
, acs_flags
))
3019 if (pci_is_root_bus(pdev
->bus
))
3020 return (end
== NULL
);
3022 parent
= pdev
->bus
->self
;
3023 } while (pdev
!= end
);
3029 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3033 * Helper to find the position of the ctrl register for a BAR.
3034 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3035 * Returns -ENOENT if no ctrl register for the BAR could be found.
3037 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3039 unsigned int pos
, nbars
, i
;
3042 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3046 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3047 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3048 PCI_REBAR_CTRL_NBAR_SHIFT
;
3050 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3053 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3054 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3063 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3065 * @bar: BAR to query
3067 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3068 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3070 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3075 pos
= pci_rebar_find_pos(pdev
, bar
);
3079 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3080 return (cap
& PCI_REBAR_CAP_SIZES
) >> 4;
3084 * pci_rebar_get_current_size - get the current size of a BAR
3086 * @bar: BAR to set size to
3088 * Read the size of a BAR from the resizable BAR config.
3089 * Returns size if found or negative error code.
3091 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3096 pos
= pci_rebar_find_pos(pdev
, bar
);
3100 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3101 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> 8;
3105 * pci_rebar_set_size - set a new size for a BAR
3107 * @bar: BAR to set size to
3108 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3110 * Set the new size of a BAR as defined in the spec.
3111 * Returns zero if resizing was successful, error code otherwise.
3113 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3118 pos
= pci_rebar_find_pos(pdev
, bar
);
3122 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3123 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3125 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3130 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3131 * @dev: the PCI device
3132 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3134 * Perform INTx swizzling for a device behind one level of bridge. This is
3135 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3136 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3137 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3138 * the PCI Express Base Specification, Revision 2.1)
3140 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3144 if (pci_ari_enabled(dev
->bus
))
3147 slot
= PCI_SLOT(dev
->devfn
);
3149 return (((pin
- 1) + slot
) % 4) + 1;
3152 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3160 while (!pci_is_root_bus(dev
->bus
)) {
3161 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3162 dev
= dev
->bus
->self
;
3169 * pci_common_swizzle - swizzle INTx all the way to root bridge
3170 * @dev: the PCI device
3171 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3173 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3174 * bridges all the way up to a PCI root bus.
3176 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3180 while (!pci_is_root_bus(dev
->bus
)) {
3181 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3182 dev
= dev
->bus
->self
;
3185 return PCI_SLOT(dev
->devfn
);
3187 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3190 * pci_release_region - Release a PCI bar
3191 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3192 * @bar: BAR to release
3194 * Releases the PCI I/O and memory resources previously reserved by a
3195 * successful call to pci_request_region. Call this function only
3196 * after all use of the PCI regions has ceased.
3198 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3200 struct pci_devres
*dr
;
3202 if (pci_resource_len(pdev
, bar
) == 0)
3204 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3205 release_region(pci_resource_start(pdev
, bar
),
3206 pci_resource_len(pdev
, bar
));
3207 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3208 release_mem_region(pci_resource_start(pdev
, bar
),
3209 pci_resource_len(pdev
, bar
));
3211 dr
= find_pci_dr(pdev
);
3213 dr
->region_mask
&= ~(1 << bar
);
3215 EXPORT_SYMBOL(pci_release_region
);
3218 * __pci_request_region - Reserved PCI I/O and memory resource
3219 * @pdev: PCI device whose resources are to be reserved
3220 * @bar: BAR to be reserved
3221 * @res_name: Name to be associated with resource.
3222 * @exclusive: whether the region access is exclusive or not
3224 * Mark the PCI region associated with PCI device @pdev BR @bar as
3225 * being reserved by owner @res_name. Do not access any
3226 * address inside the PCI regions unless this call returns
3229 * If @exclusive is set, then the region is marked so that userspace
3230 * is explicitly not allowed to map the resource via /dev/mem or
3231 * sysfs MMIO access.
3233 * Returns 0 on success, or %EBUSY on error. A warning
3234 * message is also printed on failure.
3236 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3237 const char *res_name
, int exclusive
)
3239 struct pci_devres
*dr
;
3241 if (pci_resource_len(pdev
, bar
) == 0)
3244 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3245 if (!request_region(pci_resource_start(pdev
, bar
),
3246 pci_resource_len(pdev
, bar
), res_name
))
3248 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3249 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3250 pci_resource_len(pdev
, bar
), res_name
,
3255 dr
= find_pci_dr(pdev
);
3257 dr
->region_mask
|= 1 << bar
;
3262 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
3263 &pdev
->resource
[bar
]);
3268 * pci_request_region - Reserve PCI I/O and memory resource
3269 * @pdev: PCI device whose resources are to be reserved
3270 * @bar: BAR to be reserved
3271 * @res_name: Name to be associated with resource
3273 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3274 * being reserved by owner @res_name. Do not access any
3275 * address inside the PCI regions unless this call returns
3278 * Returns 0 on success, or %EBUSY on error. A warning
3279 * message is also printed on failure.
3281 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3283 return __pci_request_region(pdev
, bar
, res_name
, 0);
3285 EXPORT_SYMBOL(pci_request_region
);
3288 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3289 * @pdev: PCI device whose resources are to be reserved
3290 * @bar: BAR to be reserved
3291 * @res_name: Name to be associated with resource.
3293 * Mark the PCI region associated with PCI device @pdev BR @bar as
3294 * being reserved by owner @res_name. Do not access any
3295 * address inside the PCI regions unless this call returns
3298 * Returns 0 on success, or %EBUSY on error. A warning
3299 * message is also printed on failure.
3301 * The key difference that _exclusive makes it that userspace is
3302 * explicitly not allowed to map the resource via /dev/mem or
3305 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
3306 const char *res_name
)
3308 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
3310 EXPORT_SYMBOL(pci_request_region_exclusive
);
3313 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3314 * @pdev: PCI device whose resources were previously reserved
3315 * @bars: Bitmask of BARs to be released
3317 * Release selected PCI I/O and memory resources previously reserved.
3318 * Call this function only after all use of the PCI regions has ceased.
3320 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
3324 for (i
= 0; i
< 6; i
++)
3325 if (bars
& (1 << i
))
3326 pci_release_region(pdev
, i
);
3328 EXPORT_SYMBOL(pci_release_selected_regions
);
3330 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3331 const char *res_name
, int excl
)
3335 for (i
= 0; i
< 6; i
++)
3336 if (bars
& (1 << i
))
3337 if (__pci_request_region(pdev
, i
, res_name
, excl
))
3343 if (bars
& (1 << i
))
3344 pci_release_region(pdev
, i
);
3351 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3352 * @pdev: PCI device whose resources are to be reserved
3353 * @bars: Bitmask of BARs to be requested
3354 * @res_name: Name to be associated with resource
3356 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3357 const char *res_name
)
3359 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
3361 EXPORT_SYMBOL(pci_request_selected_regions
);
3363 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
3364 const char *res_name
)
3366 return __pci_request_selected_regions(pdev
, bars
, res_name
,
3367 IORESOURCE_EXCLUSIVE
);
3369 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3372 * pci_release_regions - Release reserved PCI I/O and memory resources
3373 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3375 * Releases all PCI I/O and memory resources previously reserved by a
3376 * successful call to pci_request_regions. Call this function only
3377 * after all use of the PCI regions has ceased.
3380 void pci_release_regions(struct pci_dev
*pdev
)
3382 pci_release_selected_regions(pdev
, (1 << 6) - 1);
3384 EXPORT_SYMBOL(pci_release_regions
);
3387 * pci_request_regions - Reserved PCI I/O and memory resources
3388 * @pdev: PCI device whose resources are to be reserved
3389 * @res_name: Name to be associated with resource.
3391 * Mark all PCI regions associated with PCI device @pdev as
3392 * being reserved by owner @res_name. Do not access any
3393 * address inside the PCI regions unless this call returns
3396 * Returns 0 on success, or %EBUSY on error. A warning
3397 * message is also printed on failure.
3399 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
3401 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
3403 EXPORT_SYMBOL(pci_request_regions
);
3406 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3407 * @pdev: PCI device whose resources are to be reserved
3408 * @res_name: Name to be associated with resource.
3410 * Mark all PCI regions associated with PCI device @pdev as
3411 * being reserved by owner @res_name. Do not access any
3412 * address inside the PCI regions unless this call returns
3415 * pci_request_regions_exclusive() will mark the region so that
3416 * /dev/mem and the sysfs MMIO access will not be allowed.
3418 * Returns 0 on success, or %EBUSY on error. A warning
3419 * message is also printed on failure.
3421 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
3423 return pci_request_selected_regions_exclusive(pdev
,
3424 ((1 << 6) - 1), res_name
);
3426 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3429 * Record the PCI IO range (expressed as CPU physical address + size).
3430 * Return a negative value if an error has occured, zero otherwise
3432 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
3433 resource_size_t size
)
3437 struct logic_pio_hwaddr
*range
;
3439 if (!size
|| addr
+ size
< addr
)
3442 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
3446 range
->fwnode
= fwnode
;
3448 range
->hw_start
= addr
;
3449 range
->flags
= LOGIC_PIO_CPU_MMIO
;
3451 ret
= logic_pio_register_range(range
);
3459 phys_addr_t
pci_pio_to_address(unsigned long pio
)
3461 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
3464 if (pio
>= MMIO_UPPER_LIMIT
)
3467 address
= logic_pio_to_hwaddr(pio
);
3473 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
3476 return logic_pio_trans_cpuaddr(address
);
3478 if (address
> IO_SPACE_LIMIT
)
3479 return (unsigned long)-1;
3481 return (unsigned long) address
;
3486 * pci_remap_iospace - Remap the memory mapped I/O space
3487 * @res: Resource describing the I/O space
3488 * @phys_addr: physical address of range to be mapped
3490 * Remap the memory mapped I/O space described by the @res
3491 * and the CPU physical address @phys_addr into virtual address space.
3492 * Only architectures that have memory mapped IO functions defined
3493 * (and the PCI_IOBASE value defined) should call this function.
3495 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
3497 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3498 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3500 if (!(res
->flags
& IORESOURCE_IO
))
3503 if (res
->end
> IO_SPACE_LIMIT
)
3506 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
3507 pgprot_device(PAGE_KERNEL
));
3509 /* this architecture does not have memory mapped I/O space,
3510 so this function should never be called */
3511 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3515 EXPORT_SYMBOL(pci_remap_iospace
);
3518 * pci_unmap_iospace - Unmap the memory mapped I/O space
3519 * @res: resource to be unmapped
3521 * Unmap the CPU virtual address @res from virtual address space.
3522 * Only architectures that have memory mapped IO functions defined
3523 * (and the PCI_IOBASE value defined) should call this function.
3525 void pci_unmap_iospace(struct resource
*res
)
3527 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3528 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3530 unmap_kernel_range(vaddr
, resource_size(res
));
3533 EXPORT_SYMBOL(pci_unmap_iospace
);
3536 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3537 * @dev: Generic device to remap IO address for
3538 * @offset: Resource address to map
3539 * @size: Size of map
3541 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3544 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
3545 resource_size_t offset
,
3546 resource_size_t size
)
3548 void __iomem
**ptr
, *addr
;
3550 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
3554 addr
= pci_remap_cfgspace(offset
, size
);
3557 devres_add(dev
, ptr
);
3563 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
3566 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3567 * @dev: generic device to handle the resource for
3568 * @res: configuration space resource to be handled
3570 * Checks that a resource is a valid memory region, requests the memory
3571 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3572 * proper PCI configuration space memory attributes are guaranteed.
3574 * All operations are managed and will be undone on driver detach.
3576 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3577 * on failure. Usage example::
3579 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3580 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3582 * return PTR_ERR(base);
3584 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
3585 struct resource
*res
)
3587 resource_size_t size
;
3589 void __iomem
*dest_ptr
;
3593 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
3594 dev_err(dev
, "invalid resource\n");
3595 return IOMEM_ERR_PTR(-EINVAL
);
3598 size
= resource_size(res
);
3599 name
= res
->name
?: dev_name(dev
);
3601 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
3602 dev_err(dev
, "can't request region for resource %pR\n", res
);
3603 return IOMEM_ERR_PTR(-EBUSY
);
3606 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
3608 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
3609 devm_release_mem_region(dev
, res
->start
, size
);
3610 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
3615 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
3617 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
3621 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
3623 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
3625 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
3626 if (cmd
!= old_cmd
) {
3627 dev_dbg(&dev
->dev
, "%s bus mastering\n",
3628 enable
? "enabling" : "disabling");
3629 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3631 dev
->is_busmaster
= enable
;
3635 * pcibios_setup - process "pci=" kernel boot arguments
3636 * @str: string used to pass in "pci=" kernel boot arguments
3638 * Process kernel boot arguments. This is the default implementation.
3639 * Architecture specific implementations can override this as necessary.
3641 char * __weak __init
pcibios_setup(char *str
)
3647 * pcibios_set_master - enable PCI bus-mastering for device dev
3648 * @dev: the PCI device to enable
3650 * Enables PCI bus-mastering for the device. This is the default
3651 * implementation. Architecture specific implementations can override
3652 * this if necessary.
3654 void __weak
pcibios_set_master(struct pci_dev
*dev
)
3658 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3659 if (pci_is_pcie(dev
))
3662 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
3664 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
3665 else if (lat
> pcibios_max_latency
)
3666 lat
= pcibios_max_latency
;
3670 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
3674 * pci_set_master - enables bus-mastering for device dev
3675 * @dev: the PCI device to enable
3677 * Enables bus-mastering on the device and calls pcibios_set_master()
3678 * to do the needed arch specific settings.
3680 void pci_set_master(struct pci_dev
*dev
)
3682 __pci_set_master(dev
, true);
3683 pcibios_set_master(dev
);
3685 EXPORT_SYMBOL(pci_set_master
);
3688 * pci_clear_master - disables bus-mastering for device dev
3689 * @dev: the PCI device to disable
3691 void pci_clear_master(struct pci_dev
*dev
)
3693 __pci_set_master(dev
, false);
3695 EXPORT_SYMBOL(pci_clear_master
);
3698 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3699 * @dev: the PCI device for which MWI is to be enabled
3701 * Helper function for pci_set_mwi.
3702 * Originally copied from drivers/net/acenic.c.
3703 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3705 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3707 int pci_set_cacheline_size(struct pci_dev
*dev
)
3711 if (!pci_cache_line_size
)
3714 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3715 equal to or multiple of the right value. */
3716 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3717 if (cacheline_size
>= pci_cache_line_size
&&
3718 (cacheline_size
% pci_cache_line_size
) == 0)
3721 /* Write the correct value. */
3722 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
3724 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3725 if (cacheline_size
== pci_cache_line_size
)
3728 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
3729 pci_cache_line_size
<< 2);
3733 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
3736 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3737 * @dev: the PCI device for which MWI is enabled
3739 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3741 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3743 int pci_set_mwi(struct pci_dev
*dev
)
3745 #ifdef PCI_DISABLE_MWI
3751 rc
= pci_set_cacheline_size(dev
);
3755 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3756 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
3757 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
3758 cmd
|= PCI_COMMAND_INVALIDATE
;
3759 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3764 EXPORT_SYMBOL(pci_set_mwi
);
3767 * pcim_set_mwi - a device-managed pci_set_mwi()
3768 * @dev: the PCI device for which MWI is enabled
3770 * Managed pci_set_mwi().
3772 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3774 int pcim_set_mwi(struct pci_dev
*dev
)
3776 struct pci_devres
*dr
;
3778 dr
= find_pci_dr(dev
);
3783 return pci_set_mwi(dev
);
3785 EXPORT_SYMBOL(pcim_set_mwi
);
3788 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3789 * @dev: the PCI device for which MWI is enabled
3791 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3792 * Callers are not required to check the return value.
3794 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3796 int pci_try_set_mwi(struct pci_dev
*dev
)
3798 #ifdef PCI_DISABLE_MWI
3801 return pci_set_mwi(dev
);
3804 EXPORT_SYMBOL(pci_try_set_mwi
);
3807 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3808 * @dev: the PCI device to disable
3810 * Disables PCI Memory-Write-Invalidate transaction on the device
3812 void pci_clear_mwi(struct pci_dev
*dev
)
3814 #ifndef PCI_DISABLE_MWI
3817 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3818 if (cmd
& PCI_COMMAND_INVALIDATE
) {
3819 cmd
&= ~PCI_COMMAND_INVALIDATE
;
3820 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3824 EXPORT_SYMBOL(pci_clear_mwi
);
3827 * pci_intx - enables/disables PCI INTx for device dev
3828 * @pdev: the PCI device to operate on
3829 * @enable: boolean: whether to enable or disable PCI INTx
3831 * Enables/disables PCI INTx for device dev
3833 void pci_intx(struct pci_dev
*pdev
, int enable
)
3835 u16 pci_command
, new;
3837 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
3840 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
3842 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
3844 if (new != pci_command
) {
3845 struct pci_devres
*dr
;
3847 pci_write_config_word(pdev
, PCI_COMMAND
, new);
3849 dr
= find_pci_dr(pdev
);
3850 if (dr
&& !dr
->restore_intx
) {
3851 dr
->restore_intx
= 1;
3852 dr
->orig_intx
= !enable
;
3856 EXPORT_SYMBOL_GPL(pci_intx
);
3858 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3860 struct pci_bus
*bus
= dev
->bus
;
3861 bool mask_updated
= true;
3862 u32 cmd_status_dword
;
3863 u16 origcmd
, newcmd
;
3864 unsigned long flags
;
3868 * We do a single dword read to retrieve both command and status.
3869 * Document assumptions that make this possible.
3871 BUILD_BUG_ON(PCI_COMMAND
% 4);
3872 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3874 raw_spin_lock_irqsave(&pci_lock
, flags
);
3876 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3878 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3881 * Check interrupt status register to see whether our device
3882 * triggered the interrupt (when masking) or the next IRQ is
3883 * already pending (when unmasking).
3885 if (mask
!= irq_pending
) {
3886 mask_updated
= false;
3890 origcmd
= cmd_status_dword
;
3891 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3893 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3894 if (newcmd
!= origcmd
)
3895 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3898 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3900 return mask_updated
;
3904 * pci_check_and_mask_intx - mask INTx on pending interrupt
3905 * @dev: the PCI device to operate on
3907 * Check if the device dev has its INTx line asserted, mask it and
3908 * return true in that case. False is returned if no interrupt was
3911 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3913 return pci_check_and_set_intx_mask(dev
, true);
3915 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3918 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3919 * @dev: the PCI device to operate on
3921 * Check if the device dev has its INTx line asserted, unmask it if not
3922 * and return true. False is returned and the mask remains active if
3923 * there was still an interrupt pending.
3925 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3927 return pci_check_and_set_intx_mask(dev
, false);
3929 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3932 * pci_wait_for_pending_transaction - waits for pending transaction
3933 * @dev: the PCI device to operate on
3935 * Return 0 if transaction is pending 1 otherwise.
3937 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3939 if (!pci_is_pcie(dev
))
3942 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3943 PCI_EXP_DEVSTA_TRPND
);
3945 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3947 static void pci_flr_wait(struct pci_dev
*dev
)
3949 int delay
= 1, timeout
= 60000;
3953 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3954 * 100ms, but may silently discard requests while the FLR is in
3955 * progress. Wait 100ms before trying to access the device.
3960 * After 100ms, the device should not silently discard config
3961 * requests, but it may still indicate that it needs more time by
3962 * responding to them with CRS completions. The Root Port will
3963 * generally synthesize ~0 data to complete the read (except when
3964 * CRS SV is enabled and the read was for the Vendor ID; in that
3965 * case it synthesizes 0x0001 data).
3967 * Wait for the device to return a non-CRS completion. Read the
3968 * Command register instead of Vendor ID so we don't have to
3969 * contend with the CRS SV value.
3971 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3973 if (delay
> timeout
) {
3974 dev_warn(&dev
->dev
, "not ready %dms after FLR; giving up\n",
3980 dev_info(&dev
->dev
, "not ready %dms after FLR; waiting\n",
3985 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3989 dev_info(&dev
->dev
, "ready %dms after FLR\n", 100 + delay
- 1);
3993 * pcie_has_flr - check if a device supports function level resets
3994 * @dev: device to check
3996 * Returns true if the device advertises support for PCIe function level
3999 static bool pcie_has_flr(struct pci_dev
*dev
)
4003 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4006 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
4007 return cap
& PCI_EXP_DEVCAP_FLR
;
4011 * pcie_flr - initiate a PCIe function level reset
4012 * @dev: device to reset
4014 * Initiate a function level reset on @dev. The caller should ensure the
4015 * device supports FLR before calling this function, e.g. by using the
4016 * pcie_has_flr() helper.
4018 void pcie_flr(struct pci_dev
*dev
)
4020 if (!pci_wait_for_pending_transaction(dev
))
4021 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
4023 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
4026 EXPORT_SYMBOL_GPL(pcie_flr
);
4028 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
4033 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4037 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4040 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4041 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4048 * Wait for Transaction Pending bit to clear. A word-aligned test
4049 * is used, so we use the conrol offset rather than status and shift
4050 * the test bit to match.
4052 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4053 PCI_AF_STATUS_TP
<< 8))
4054 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4056 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4062 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4063 * @dev: Device to reset.
4064 * @probe: If set, only check if the device can be reset this way.
4066 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4067 * unset, it will be reinitialized internally when going from PCI_D3hot to
4068 * PCI_D0. If that's the case and the device is not in a low-power state
4069 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4071 * NOTE: This causes the caller to sleep for twice the device power transition
4072 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4073 * by default (i.e. unless the @dev's d3_delay field has a different value).
4074 * Moreover, only devices in D0 can be reset by this function.
4076 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
4080 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4083 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4084 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4090 if (dev
->current_state
!= PCI_D0
)
4093 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4095 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4096 pci_dev_d3_sleep(dev
);
4098 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4100 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4101 pci_dev_d3_sleep(dev
);
4106 void pci_reset_secondary_bus(struct pci_dev
*dev
)
4110 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
4111 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
4112 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4114 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4115 * this to 2ms to ensure that we meet the minimum requirement.
4119 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
4120 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4123 * Trhfa for conventional PCI is 2^25 clock cycles.
4124 * Assuming a minimum 33MHz clock this results in a 1s
4125 * delay before we can consider subordinate devices to
4126 * be re-initialized. PCIe has some ways to shorten this,
4127 * but we don't make use of them yet.
4132 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
4134 pci_reset_secondary_bus(dev
);
4138 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4139 * @dev: Bridge device
4141 * Use the bridge control register to assert reset on the secondary bus.
4142 * Devices on the secondary bus are left in power-on state.
4144 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
4146 pcibios_reset_secondary_bus(dev
);
4148 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
4150 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
4152 struct pci_dev
*pdev
;
4154 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
4155 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4158 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4165 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
4170 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
4174 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
4177 if (hotplug
->ops
->reset_slot
)
4178 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
4180 module_put(hotplug
->ops
->owner
);
4185 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
4187 struct pci_dev
*pdev
;
4189 if (dev
->subordinate
|| !dev
->slot
||
4190 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4193 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4194 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
4197 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
4200 static void pci_dev_lock(struct pci_dev
*dev
)
4202 pci_cfg_access_lock(dev
);
4203 /* block PM suspend, driver probe, etc. */
4204 device_lock(&dev
->dev
);
4207 /* Return 1 on successful lock, 0 on contention */
4208 static int pci_dev_trylock(struct pci_dev
*dev
)
4210 if (pci_cfg_access_trylock(dev
)) {
4211 if (device_trylock(&dev
->dev
))
4213 pci_cfg_access_unlock(dev
);
4219 static void pci_dev_unlock(struct pci_dev
*dev
)
4221 device_unlock(&dev
->dev
);
4222 pci_cfg_access_unlock(dev
);
4225 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
4227 const struct pci_error_handlers
*err_handler
=
4228 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4231 * dev->driver->err_handler->reset_prepare() is protected against
4232 * races with ->remove() by the device lock, which must be held by
4235 if (err_handler
&& err_handler
->reset_prepare
)
4236 err_handler
->reset_prepare(dev
);
4239 * Wake-up device prior to save. PM registers default to D0 after
4240 * reset and a simple register restore doesn't reliably return
4241 * to a non-D0 state anyway.
4243 pci_set_power_state(dev
, PCI_D0
);
4245 pci_save_state(dev
);
4247 * Disable the device by clearing the Command register, except for
4248 * INTx-disable which is set. This not only disables MMIO and I/O port
4249 * BARs, but also prevents the device from being Bus Master, preventing
4250 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4251 * compliant devices, INTx-disable prevents legacy interrupts.
4253 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
4256 static void pci_dev_restore(struct pci_dev
*dev
)
4258 const struct pci_error_handlers
*err_handler
=
4259 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4261 pci_restore_state(dev
);
4264 * dev->driver->err_handler->reset_done() is protected against
4265 * races with ->remove() by the device lock, which must be held by
4268 if (err_handler
&& err_handler
->reset_done
)
4269 err_handler
->reset_done(dev
);
4273 * __pci_reset_function_locked - reset a PCI device function while holding
4274 * the @dev mutex lock.
4275 * @dev: PCI device to reset
4277 * Some devices allow an individual function to be reset without affecting
4278 * other functions in the same device. The PCI device must be responsive
4279 * to PCI config space in order to use this function.
4281 * The device function is presumed to be unused and the caller is holding
4282 * the device mutex lock when this function is called.
4283 * Resetting the device will make the contents of PCI configuration space
4284 * random, so any caller of this must be prepared to reinitialise the
4285 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4288 * Returns 0 if the device function was successfully reset or negative if the
4289 * device doesn't support resetting a single function.
4291 int __pci_reset_function_locked(struct pci_dev
*dev
)
4298 * A reset method returns -ENOTTY if it doesn't support this device
4299 * and we should try the next method.
4301 * If it returns 0 (success), we're finished. If it returns any
4302 * other error, we're also finished: this indicates that further
4303 * reset mechanisms might be broken on the device.
4305 rc
= pci_dev_specific_reset(dev
, 0);
4308 if (pcie_has_flr(dev
)) {
4312 rc
= pci_af_flr(dev
, 0);
4315 rc
= pci_pm_reset(dev
, 0);
4318 rc
= pci_dev_reset_slot_function(dev
, 0);
4321 return pci_parent_bus_reset(dev
, 0);
4323 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
4326 * pci_probe_reset_function - check whether the device can be safely reset
4327 * @dev: PCI device to reset
4329 * Some devices allow an individual function to be reset without affecting
4330 * other functions in the same device. The PCI device must be responsive
4331 * to PCI config space in order to use this function.
4333 * Returns 0 if the device function can be reset or negative if the
4334 * device doesn't support resetting a single function.
4336 int pci_probe_reset_function(struct pci_dev
*dev
)
4342 rc
= pci_dev_specific_reset(dev
, 1);
4345 if (pcie_has_flr(dev
))
4347 rc
= pci_af_flr(dev
, 1);
4350 rc
= pci_pm_reset(dev
, 1);
4353 rc
= pci_dev_reset_slot_function(dev
, 1);
4357 return pci_parent_bus_reset(dev
, 1);
4361 * pci_reset_function - quiesce and reset a PCI device function
4362 * @dev: PCI device to reset
4364 * Some devices allow an individual function to be reset without affecting
4365 * other functions in the same device. The PCI device must be responsive
4366 * to PCI config space in order to use this function.
4368 * This function does not just reset the PCI portion of a device, but
4369 * clears all the state associated with the device. This function differs
4370 * from __pci_reset_function_locked() in that it saves and restores device state
4371 * over the reset and takes the PCI device lock.
4373 * Returns 0 if the device function was successfully reset or negative if the
4374 * device doesn't support resetting a single function.
4376 int pci_reset_function(struct pci_dev
*dev
)
4380 rc
= pci_probe_reset_function(dev
);
4385 pci_dev_save_and_disable(dev
);
4387 rc
= __pci_reset_function_locked(dev
);
4389 pci_dev_restore(dev
);
4390 pci_dev_unlock(dev
);
4394 EXPORT_SYMBOL_GPL(pci_reset_function
);
4397 * pci_reset_function_locked - quiesce and reset a PCI device function
4398 * @dev: PCI device to reset
4400 * Some devices allow an individual function to be reset without affecting
4401 * other functions in the same device. The PCI device must be responsive
4402 * to PCI config space in order to use this function.
4404 * This function does not just reset the PCI portion of a device, but
4405 * clears all the state associated with the device. This function differs
4406 * from __pci_reset_function_locked() in that it saves and restores device state
4407 * over the reset. It also differs from pci_reset_function() in that it
4408 * requires the PCI device lock to be held.
4410 * Returns 0 if the device function was successfully reset or negative if the
4411 * device doesn't support resetting a single function.
4413 int pci_reset_function_locked(struct pci_dev
*dev
)
4417 rc
= pci_probe_reset_function(dev
);
4421 pci_dev_save_and_disable(dev
);
4423 rc
= __pci_reset_function_locked(dev
);
4425 pci_dev_restore(dev
);
4429 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
4432 * pci_try_reset_function - quiesce and reset a PCI device function
4433 * @dev: PCI device to reset
4435 * Same as above, except return -EAGAIN if unable to lock device.
4437 int pci_try_reset_function(struct pci_dev
*dev
)
4441 rc
= pci_probe_reset_function(dev
);
4445 if (!pci_dev_trylock(dev
))
4448 pci_dev_save_and_disable(dev
);
4449 rc
= __pci_reset_function_locked(dev
);
4450 pci_dev_unlock(dev
);
4452 pci_dev_restore(dev
);
4455 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
4457 /* Do any devices on or below this bus prevent a bus reset? */
4458 static bool pci_bus_resetable(struct pci_bus
*bus
)
4460 struct pci_dev
*dev
;
4463 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4466 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4467 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4468 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4475 /* Lock devices from the top of the tree down */
4476 static void pci_bus_lock(struct pci_bus
*bus
)
4478 struct pci_dev
*dev
;
4480 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4482 if (dev
->subordinate
)
4483 pci_bus_lock(dev
->subordinate
);
4487 /* Unlock devices from the bottom of the tree up */
4488 static void pci_bus_unlock(struct pci_bus
*bus
)
4490 struct pci_dev
*dev
;
4492 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4493 if (dev
->subordinate
)
4494 pci_bus_unlock(dev
->subordinate
);
4495 pci_dev_unlock(dev
);
4499 /* Return 1 on successful lock, 0 on contention */
4500 static int pci_bus_trylock(struct pci_bus
*bus
)
4502 struct pci_dev
*dev
;
4504 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4505 if (!pci_dev_trylock(dev
))
4507 if (dev
->subordinate
) {
4508 if (!pci_bus_trylock(dev
->subordinate
)) {
4509 pci_dev_unlock(dev
);
4517 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
4518 if (dev
->subordinate
)
4519 pci_bus_unlock(dev
->subordinate
);
4520 pci_dev_unlock(dev
);
4525 /* Do any devices on or below this slot prevent a bus reset? */
4526 static bool pci_slot_resetable(struct pci_slot
*slot
)
4528 struct pci_dev
*dev
;
4530 if (slot
->bus
->self
&&
4531 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4534 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4535 if (!dev
->slot
|| dev
->slot
!= slot
)
4537 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4538 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4545 /* Lock devices from the top of the tree down */
4546 static void pci_slot_lock(struct pci_slot
*slot
)
4548 struct pci_dev
*dev
;
4550 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4551 if (!dev
->slot
|| dev
->slot
!= slot
)
4554 if (dev
->subordinate
)
4555 pci_bus_lock(dev
->subordinate
);
4559 /* Unlock devices from the bottom of the tree up */
4560 static void pci_slot_unlock(struct pci_slot
*slot
)
4562 struct pci_dev
*dev
;
4564 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4565 if (!dev
->slot
|| dev
->slot
!= slot
)
4567 if (dev
->subordinate
)
4568 pci_bus_unlock(dev
->subordinate
);
4569 pci_dev_unlock(dev
);
4573 /* Return 1 on successful lock, 0 on contention */
4574 static int pci_slot_trylock(struct pci_slot
*slot
)
4576 struct pci_dev
*dev
;
4578 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4579 if (!dev
->slot
|| dev
->slot
!= slot
)
4581 if (!pci_dev_trylock(dev
))
4583 if (dev
->subordinate
) {
4584 if (!pci_bus_trylock(dev
->subordinate
)) {
4585 pci_dev_unlock(dev
);
4593 list_for_each_entry_continue_reverse(dev
,
4594 &slot
->bus
->devices
, bus_list
) {
4595 if (!dev
->slot
|| dev
->slot
!= slot
)
4597 if (dev
->subordinate
)
4598 pci_bus_unlock(dev
->subordinate
);
4599 pci_dev_unlock(dev
);
4604 /* Save and disable devices from the top of the tree down */
4605 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
4607 struct pci_dev
*dev
;
4609 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4611 pci_dev_save_and_disable(dev
);
4612 pci_dev_unlock(dev
);
4613 if (dev
->subordinate
)
4614 pci_bus_save_and_disable(dev
->subordinate
);
4619 * Restore devices from top of the tree down - parent bridges need to be
4620 * restored before we can get to subordinate devices.
4622 static void pci_bus_restore(struct pci_bus
*bus
)
4624 struct pci_dev
*dev
;
4626 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4628 pci_dev_restore(dev
);
4629 pci_dev_unlock(dev
);
4630 if (dev
->subordinate
)
4631 pci_bus_restore(dev
->subordinate
);
4635 /* Save and disable devices from the top of the tree down */
4636 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
4638 struct pci_dev
*dev
;
4640 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4641 if (!dev
->slot
|| dev
->slot
!= slot
)
4643 pci_dev_save_and_disable(dev
);
4644 if (dev
->subordinate
)
4645 pci_bus_save_and_disable(dev
->subordinate
);
4650 * Restore devices from top of the tree down - parent bridges need to be
4651 * restored before we can get to subordinate devices.
4653 static void pci_slot_restore(struct pci_slot
*slot
)
4655 struct pci_dev
*dev
;
4657 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4658 if (!dev
->slot
|| dev
->slot
!= slot
)
4660 pci_dev_restore(dev
);
4661 if (dev
->subordinate
)
4662 pci_bus_restore(dev
->subordinate
);
4666 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
4670 if (!slot
|| !pci_slot_resetable(slot
))
4674 pci_slot_lock(slot
);
4678 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
4681 pci_slot_unlock(slot
);
4687 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4688 * @slot: PCI slot to probe
4690 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4692 int pci_probe_reset_slot(struct pci_slot
*slot
)
4694 return pci_slot_reset(slot
, 1);
4696 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
4699 * pci_reset_slot - reset a PCI slot
4700 * @slot: PCI slot to reset
4702 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4703 * independent of other slots. For instance, some slots may support slot power
4704 * control. In the case of a 1:1 bus to slot architecture, this function may
4705 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4706 * Generally a slot reset should be attempted before a bus reset. All of the
4707 * function of the slot and any subordinate buses behind the slot are reset
4708 * through this function. PCI config space of all devices in the slot and
4709 * behind the slot is saved before and restored after reset.
4711 * Return 0 on success, non-zero on error.
4713 int pci_reset_slot(struct pci_slot
*slot
)
4717 rc
= pci_slot_reset(slot
, 1);
4721 pci_slot_save_and_disable(slot
);
4723 rc
= pci_slot_reset(slot
, 0);
4725 pci_slot_restore(slot
);
4729 EXPORT_SYMBOL_GPL(pci_reset_slot
);
4732 * pci_try_reset_slot - Try to reset a PCI slot
4733 * @slot: PCI slot to reset
4735 * Same as above except return -EAGAIN if the slot cannot be locked
4737 int pci_try_reset_slot(struct pci_slot
*slot
)
4741 rc
= pci_slot_reset(slot
, 1);
4745 pci_slot_save_and_disable(slot
);
4747 if (pci_slot_trylock(slot
)) {
4749 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
4750 pci_slot_unlock(slot
);
4754 pci_slot_restore(slot
);
4758 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
4760 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
4762 if (!bus
->self
|| !pci_bus_resetable(bus
))
4772 pci_reset_bridge_secondary_bus(bus
->self
);
4774 pci_bus_unlock(bus
);
4780 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4781 * @bus: PCI bus to probe
4783 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4785 int pci_probe_reset_bus(struct pci_bus
*bus
)
4787 return pci_bus_reset(bus
, 1);
4789 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
4792 * pci_reset_bus - reset a PCI bus
4793 * @bus: top level PCI bus to reset
4795 * Do a bus reset on the given bus and any subordinate buses, saving
4796 * and restoring state of all devices.
4798 * Return 0 on success, non-zero on error.
4800 int pci_reset_bus(struct pci_bus
*bus
)
4804 rc
= pci_bus_reset(bus
, 1);
4808 pci_bus_save_and_disable(bus
);
4810 rc
= pci_bus_reset(bus
, 0);
4812 pci_bus_restore(bus
);
4816 EXPORT_SYMBOL_GPL(pci_reset_bus
);
4819 * pci_try_reset_bus - Try to reset a PCI bus
4820 * @bus: top level PCI bus to reset
4822 * Same as above except return -EAGAIN if the bus cannot be locked
4824 int pci_try_reset_bus(struct pci_bus
*bus
)
4828 rc
= pci_bus_reset(bus
, 1);
4832 pci_bus_save_and_disable(bus
);
4834 if (pci_bus_trylock(bus
)) {
4836 pci_reset_bridge_secondary_bus(bus
->self
);
4837 pci_bus_unlock(bus
);
4841 pci_bus_restore(bus
);
4845 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
4848 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4849 * @dev: PCI device to query
4851 * Returns mmrbc: maximum designed memory read count in bytes
4852 * or appropriate error value.
4854 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
4859 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4863 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4866 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
4868 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
4871 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4872 * @dev: PCI device to query
4874 * Returns mmrbc: maximum memory read count in bytes
4875 * or appropriate error value.
4877 int pcix_get_mmrbc(struct pci_dev
*dev
)
4882 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4886 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4889 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
4891 EXPORT_SYMBOL(pcix_get_mmrbc
);
4894 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4895 * @dev: PCI device to query
4896 * @mmrbc: maximum memory read count in bytes
4897 * valid values are 512, 1024, 2048, 4096
4899 * If possible sets maximum memory read byte count, some bridges have erratas
4900 * that prevent this.
4902 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4908 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4911 v
= ffs(mmrbc
) - 10;
4913 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4917 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4920 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4923 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4926 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4928 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4931 cmd
&= ~PCI_X_CMD_MAX_READ
;
4933 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4938 EXPORT_SYMBOL(pcix_set_mmrbc
);
4941 * pcie_get_readrq - get PCI Express read request size
4942 * @dev: PCI device to query
4944 * Returns maximum memory read request in bytes
4945 * or appropriate error value.
4947 int pcie_get_readrq(struct pci_dev
*dev
)
4951 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4953 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4955 EXPORT_SYMBOL(pcie_get_readrq
);
4958 * pcie_set_readrq - set PCI Express maximum memory read request
4959 * @dev: PCI device to query
4960 * @rq: maximum memory read count in bytes
4961 * valid values are 128, 256, 512, 1024, 2048, 4096
4963 * If possible sets maximum memory read request in bytes
4965 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4969 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4973 * If using the "performance" PCIe config, we clamp the
4974 * read rq size to the max packet size to prevent the
4975 * host bridge generating requests larger than we can
4978 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4979 int mps
= pcie_get_mps(dev
);
4985 v
= (ffs(rq
) - 8) << 12;
4987 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4988 PCI_EXP_DEVCTL_READRQ
, v
);
4990 EXPORT_SYMBOL(pcie_set_readrq
);
4993 * pcie_get_mps - get PCI Express maximum payload size
4994 * @dev: PCI device to query
4996 * Returns maximum payload size in bytes
4998 int pcie_get_mps(struct pci_dev
*dev
)
5002 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
5004 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
5006 EXPORT_SYMBOL(pcie_get_mps
);
5009 * pcie_set_mps - set PCI Express maximum payload size
5010 * @dev: PCI device to query
5011 * @mps: maximum payload size in bytes
5012 * valid values are 128, 256, 512, 1024, 2048, 4096
5014 * If possible sets maximum payload size
5016 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
5020 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
5024 if (v
> dev
->pcie_mpss
)
5028 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
5029 PCI_EXP_DEVCTL_PAYLOAD
, v
);
5031 EXPORT_SYMBOL(pcie_set_mps
);
5034 * pcie_get_minimum_link - determine minimum link settings of a PCI device
5035 * @dev: PCI device to query
5036 * @speed: storage for minimum speed
5037 * @width: storage for minimum width
5039 * This function will walk up the PCI device chain and determine the minimum
5040 * link width and speed of the device.
5042 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
5043 enum pcie_link_width
*width
)
5047 *speed
= PCI_SPEED_UNKNOWN
;
5048 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
5052 enum pci_bus_speed next_speed
;
5053 enum pcie_link_width next_width
;
5055 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
5059 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
5060 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
5061 PCI_EXP_LNKSTA_NLW_SHIFT
;
5063 if (next_speed
< *speed
)
5064 *speed
= next_speed
;
5066 if (next_width
< *width
)
5067 *width
= next_width
;
5069 dev
= dev
->bus
->self
;
5074 EXPORT_SYMBOL(pcie_get_minimum_link
);
5077 * pci_select_bars - Make BAR mask from the type of resource
5078 * @dev: the PCI device for which BAR mask is made
5079 * @flags: resource type mask to be selected
5081 * This helper routine makes bar mask from the type of resource.
5083 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
5086 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
5087 if (pci_resource_flags(dev
, i
) & flags
)
5091 EXPORT_SYMBOL(pci_select_bars
);
5093 /* Some architectures require additional programming to enable VGA */
5094 static arch_set_vga_state_t arch_set_vga_state
;
5096 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
5098 arch_set_vga_state
= func
; /* NULL disables */
5101 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
5102 unsigned int command_bits
, u32 flags
)
5104 if (arch_set_vga_state
)
5105 return arch_set_vga_state(dev
, decode
, command_bits
,
5111 * pci_set_vga_state - set VGA decode state on device and parents if requested
5112 * @dev: the PCI device
5113 * @decode: true = enable decoding, false = disable decoding
5114 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5115 * @flags: traverse ancestors and change bridges
5116 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5118 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
5119 unsigned int command_bits
, u32 flags
)
5121 struct pci_bus
*bus
;
5122 struct pci_dev
*bridge
;
5126 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
5128 /* ARCH specific VGA enables */
5129 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
5133 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
5134 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
5136 cmd
|= command_bits
;
5138 cmd
&= ~command_bits
;
5139 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
5142 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
5149 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5152 cmd
|= PCI_BRIDGE_CTL_VGA
;
5154 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
5155 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5164 * pci_add_dma_alias - Add a DMA devfn alias for a device
5165 * @dev: the PCI device for which alias is added
5166 * @devfn: alias slot and function
5168 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5169 * It should be called early, preferably as PCI fixup header quirk.
5171 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
)
5173 if (!dev
->dma_alias_mask
)
5174 dev
->dma_alias_mask
= kcalloc(BITS_TO_LONGS(U8_MAX
),
5175 sizeof(long), GFP_KERNEL
);
5176 if (!dev
->dma_alias_mask
) {
5177 dev_warn(&dev
->dev
, "Unable to allocate DMA alias mask\n");
5181 set_bit(devfn
, dev
->dma_alias_mask
);
5182 dev_info(&dev
->dev
, "Enabling fixed DMA alias to %02x.%d\n",
5183 PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5186 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
5188 return (dev1
->dma_alias_mask
&&
5189 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
5190 (dev2
->dma_alias_mask
&&
5191 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
));
5194 bool pci_device_is_present(struct pci_dev
*pdev
)
5198 if (pci_dev_is_disconnected(pdev
))
5200 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
5202 EXPORT_SYMBOL_GPL(pci_device_is_present
);
5204 void pci_ignore_hotplug(struct pci_dev
*dev
)
5206 struct pci_dev
*bridge
= dev
->bus
->self
;
5208 dev
->ignore_hotplug
= 1;
5209 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5211 bridge
->ignore_hotplug
= 1;
5213 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
5215 resource_size_t __weak
pcibios_default_alignment(void)
5220 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5221 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
5222 static DEFINE_SPINLOCK(resource_alignment_lock
);
5225 * pci_specified_resource_alignment - get resource alignment specified by user.
5226 * @dev: the PCI device to get
5227 * @resize: whether or not to change resources' size when reassigning alignment
5229 * RETURNS: Resource alignment if it is specified.
5230 * Zero if it is not specified.
5232 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
5235 int seg
, bus
, slot
, func
, align_order
, count
;
5236 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
5237 resource_size_t align
= pcibios_default_alignment();
5240 spin_lock(&resource_alignment_lock
);
5241 p
= resource_alignment_param
;
5244 if (pci_has_flag(PCI_PROBE_ONLY
)) {
5246 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5252 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
5258 if (strncmp(p
, "pci:", 4) == 0) {
5259 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5261 if (sscanf(p
, "%hx:%hx:%hx:%hx%n",
5262 &vendor
, &device
, &subsystem_vendor
, &subsystem_device
, &count
) != 4) {
5263 if (sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
) != 2) {
5264 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: pci:%s\n",
5268 subsystem_vendor
= subsystem_device
= 0;
5271 if ((!vendor
|| (vendor
== dev
->vendor
)) &&
5272 (!device
|| (device
== dev
->device
)) &&
5273 (!subsystem_vendor
|| (subsystem_vendor
== dev
->subsystem_vendor
)) &&
5274 (!subsystem_device
|| (subsystem_device
== dev
->subsystem_device
))) {
5276 if (align_order
== -1)
5279 align
= 1 << align_order
;
5285 if (sscanf(p
, "%x:%x:%x.%x%n",
5286 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
5288 if (sscanf(p
, "%x:%x.%x%n",
5289 &bus
, &slot
, &func
, &count
) != 3) {
5290 /* Invalid format */
5291 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
5297 if (seg
== pci_domain_nr(dev
->bus
) &&
5298 bus
== dev
->bus
->number
&&
5299 slot
== PCI_SLOT(dev
->devfn
) &&
5300 func
== PCI_FUNC(dev
->devfn
)) {
5302 if (align_order
== -1)
5305 align
= 1 << align_order
;
5310 if (*p
!= ';' && *p
!= ',') {
5311 /* End of param or invalid format */
5317 spin_unlock(&resource_alignment_lock
);
5321 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
5322 resource_size_t align
, bool resize
)
5324 struct resource
*r
= &dev
->resource
[bar
];
5325 resource_size_t size
;
5327 if (!(r
->flags
& IORESOURCE_MEM
))
5330 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
5331 dev_info(&dev
->dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
5332 bar
, r
, (unsigned long long)align
);
5336 size
= resource_size(r
);
5341 * Increase the alignment of the resource. There are two ways we
5344 * 1) Increase the size of the resource. BARs are aligned on their
5345 * size, so when we reallocate space for this resource, we'll
5346 * allocate it with the larger alignment. This also prevents
5347 * assignment of any other BARs inside the alignment region, so
5348 * if we're requesting page alignment, this means no other BARs
5349 * will share the page.
5351 * The disadvantage is that this makes the resource larger than
5352 * the hardware BAR, which may break drivers that compute things
5353 * based on the resource size, e.g., to find registers at a
5354 * fixed offset before the end of the BAR.
5356 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5357 * set r->start to the desired alignment. By itself this
5358 * doesn't prevent other BARs being put inside the alignment
5359 * region, but if we realign *every* resource of every device in
5360 * the system, none of them will share an alignment region.
5362 * When the user has requested alignment for only some devices via
5363 * the "pci=resource_alignment" argument, "resize" is true and we
5364 * use the first method. Otherwise we assume we're aligning all
5365 * devices and we use the second.
5368 dev_info(&dev
->dev
, "BAR%d %pR: requesting alignment to %#llx\n",
5369 bar
, r
, (unsigned long long)align
);
5375 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
5376 r
->flags
|= IORESOURCE_STARTALIGN
;
5378 r
->end
= r
->start
+ size
- 1;
5380 r
->flags
|= IORESOURCE_UNSET
;
5384 * This function disables memory decoding and releases memory resources
5385 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5386 * It also rounds up size to specified alignment.
5387 * Later on, the kernel will assign page-aligned memory resource back
5390 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
5394 resource_size_t align
;
5396 bool resize
= false;
5399 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5400 * 3.4.1.11. Their resources are allocated from the space
5401 * described by the VF BARx register in the PF's SR-IOV capability.
5402 * We can't influence their alignment here.
5407 /* check if specified PCI is target device to reassign */
5408 align
= pci_specified_resource_alignment(dev
, &resize
);
5412 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
5413 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
5415 "Can't reassign resources to host bridge.\n");
5420 "Disabling memory decoding and releasing memory resources.\n");
5421 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
5422 command
&= ~PCI_COMMAND_MEMORY
;
5423 pci_write_config_word(dev
, PCI_COMMAND
, command
);
5425 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
5426 pci_request_resource_alignment(dev
, i
, align
, resize
);
5429 * Need to disable bridge's resource window,
5430 * to enable the kernel to reassign new resource
5433 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
5434 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
5435 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
5436 r
= &dev
->resource
[i
];
5437 if (!(r
->flags
& IORESOURCE_MEM
))
5439 r
->flags
|= IORESOURCE_UNSET
;
5440 r
->end
= resource_size(r
) - 1;
5443 pci_disable_bridge_window(dev
);
5447 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
5449 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
5450 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
5451 spin_lock(&resource_alignment_lock
);
5452 strncpy(resource_alignment_param
, buf
, count
);
5453 resource_alignment_param
[count
] = '\0';
5454 spin_unlock(&resource_alignment_lock
);
5458 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
5461 spin_lock(&resource_alignment_lock
);
5462 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
5463 spin_unlock(&resource_alignment_lock
);
5467 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
5469 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
5472 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
5473 const char *buf
, size_t count
)
5475 return pci_set_resource_alignment_param(buf
, count
);
5478 static BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
5479 pci_resource_alignment_store
);
5481 static int __init
pci_resource_alignment_sysfs_init(void)
5483 return bus_create_file(&pci_bus_type
,
5484 &bus_attr_resource_alignment
);
5486 late_initcall(pci_resource_alignment_sysfs_init
);
5488 static void pci_no_domains(void)
5490 #ifdef CONFIG_PCI_DOMAINS
5491 pci_domains_supported
= 0;
5495 #ifdef CONFIG_PCI_DOMAINS
5496 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
5498 int pci_get_new_domain_nr(void)
5500 return atomic_inc_return(&__domain_nr
);
5503 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5504 static int of_pci_bus_find_domain_nr(struct device
*parent
)
5506 static int use_dt_domains
= -1;
5510 domain
= of_get_pci_domain_nr(parent
->of_node
);
5512 * Check DT domain and use_dt_domains values.
5514 * If DT domain property is valid (domain >= 0) and
5515 * use_dt_domains != 0, the DT assignment is valid since this means
5516 * we have not previously allocated a domain number by using
5517 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5518 * 1, to indicate that we have just assigned a domain number from
5521 * If DT domain property value is not valid (ie domain < 0), and we
5522 * have not previously assigned a domain number from DT
5523 * (use_dt_domains != 1) we should assign a domain number by
5526 * pci_get_new_domain_nr()
5528 * API and update the use_dt_domains value to keep track of method we
5529 * are using to assign domain numbers (use_dt_domains = 0).
5531 * All other combinations imply we have a platform that is trying
5532 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5533 * which is a recipe for domain mishandling and it is prevented by
5534 * invalidating the domain value (domain = -1) and printing a
5535 * corresponding error.
5537 if (domain
>= 0 && use_dt_domains
) {
5539 } else if (domain
< 0 && use_dt_domains
!= 1) {
5541 domain
= pci_get_new_domain_nr();
5543 dev_err(parent
, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5551 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
5553 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
5554 acpi_pci_bus_find_domain_nr(bus
);
5560 * pci_ext_cfg_avail - can we access extended PCI config space?
5562 * Returns 1 if we can access PCI extended config space (offsets
5563 * greater than 0xff). This is the default implementation. Architecture
5564 * implementations can override this.
5566 int __weak
pci_ext_cfg_avail(void)
5571 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
5574 EXPORT_SYMBOL(pci_fixup_cardbus
);
5576 static int __init
pci_setup(char *str
)
5579 char *k
= strchr(str
, ',');
5582 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
5583 if (!strcmp(str
, "nomsi")) {
5585 } else if (!strcmp(str
, "noaer")) {
5587 } else if (!strncmp(str
, "realloc=", 8)) {
5588 pci_realloc_get_opt(str
+ 8);
5589 } else if (!strncmp(str
, "realloc", 7)) {
5590 pci_realloc_get_opt("on");
5591 } else if (!strcmp(str
, "nodomains")) {
5593 } else if (!strncmp(str
, "noari", 5)) {
5594 pcie_ari_disabled
= true;
5595 } else if (!strncmp(str
, "cbiosize=", 9)) {
5596 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
5597 } else if (!strncmp(str
, "cbmemsize=", 10)) {
5598 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
5599 } else if (!strncmp(str
, "resource_alignment=", 19)) {
5600 pci_set_resource_alignment_param(str
+ 19,
5602 } else if (!strncmp(str
, "ecrc=", 5)) {
5603 pcie_ecrc_get_policy(str
+ 5);
5604 } else if (!strncmp(str
, "hpiosize=", 9)) {
5605 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
5606 } else if (!strncmp(str
, "hpmemsize=", 10)) {
5607 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
5608 } else if (!strncmp(str
, "hpbussize=", 10)) {
5609 pci_hotplug_bus_size
=
5610 simple_strtoul(str
+ 10, &str
, 0);
5611 if (pci_hotplug_bus_size
> 0xff)
5612 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
5613 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
5614 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
5615 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
5616 pcie_bus_config
= PCIE_BUS_SAFE
;
5617 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
5618 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
5619 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
5620 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
5621 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
5622 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
5624 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
5632 early_param("pci", pci_setup
);