2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/logic_pio.h>
25 #include <linux/pci-aspm.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pci-ats.h>
33 #include <asm/setup.h>
35 #include <linux/aer.h>
38 const char *pci_power_names
[] = {
39 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 EXPORT_SYMBOL_GPL(pci_power_names
);
43 int isa_dma_bridge_buggy
;
44 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
47 EXPORT_SYMBOL(pci_pci_problems
);
49 unsigned int pci_pm_d3_delay
;
51 static void pci_pme_list_scan(struct work_struct
*work
);
53 static LIST_HEAD(pci_pme_list
);
54 static DEFINE_MUTEX(pci_pme_list_mutex
);
55 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
57 struct pci_pme_device
{
58 struct list_head list
;
62 #define PME_TIMEOUT 1000 /* How long between PME checks */
64 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
66 unsigned int delay
= dev
->d3_delay
;
68 if (delay
< pci_pm_d3_delay
)
69 delay
= pci_pm_d3_delay
;
75 #ifdef CONFIG_PCI_DOMAINS
76 int pci_domains_supported
= 1;
79 #define DEFAULT_CARDBUS_IO_SIZE (256)
80 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
81 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
82 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
83 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
85 #define DEFAULT_HOTPLUG_IO_SIZE (256)
86 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
87 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
88 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
89 unsigned long pci_hotplug_mem_size
= DEFAULT_HOTPLUG_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_BUS_SIZE 1
92 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
94 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
97 * The default CLS is used if arch didn't set CLS explicitly and not
98 * all pci devices agree on the same value. Arch can override either
99 * the dfl or actual value as it sees fit. Don't forget this is
100 * measured in 32-bit words, not bytes.
102 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
103 u8 pci_cache_line_size
;
106 * If we set up a device for bus mastering, we need to check the latency
107 * timer as certain BIOSes forget to set it properly.
109 unsigned int pcibios_max_latency
= 255;
111 /* If set, the PCIe ARI capability will not be used. */
112 static bool pcie_ari_disabled
;
114 /* Disable bridge_d3 for all PCIe ports */
115 static bool pci_bridge_d3_disable
;
116 /* Force bridge_d3 for all PCIe ports */
117 static bool pci_bridge_d3_force
;
119 static int __init
pcie_port_pm_setup(char *str
)
121 if (!strcmp(str
, "off"))
122 pci_bridge_d3_disable
= true;
123 else if (!strcmp(str
, "force"))
124 pci_bridge_d3_force
= true;
127 __setup("pcie_port_pm=", pcie_port_pm_setup
);
130 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
131 * @bus: pointer to PCI bus structure to search
133 * Given a PCI bus, returns the highest PCI bus number present in the set
134 * including the given PCI bus and its list of child PCI buses.
136 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
139 unsigned char max
, n
;
141 max
= bus
->busn_res
.end
;
142 list_for_each_entry(tmp
, &bus
->children
, node
) {
143 n
= pci_bus_max_busnr(tmp
);
149 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
151 #ifdef CONFIG_HAS_IOMEM
152 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
154 struct resource
*res
= &pdev
->resource
[bar
];
157 * Make sure the BAR is actually a memory resource, not an IO resource
159 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
160 dev_warn(&pdev
->dev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
163 return ioremap_nocache(res
->start
, resource_size(res
));
165 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
167 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
170 * Make sure the BAR is actually a memory resource, not an IO resource
172 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
176 return ioremap_wc(pci_resource_start(pdev
, bar
),
177 pci_resource_len(pdev
, bar
));
179 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
183 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
184 u8 pos
, int cap
, int *ttl
)
189 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
195 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
207 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
210 int ttl
= PCI_FIND_CAP_TTL
;
212 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
215 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
217 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
218 pos
+ PCI_CAP_LIST_NEXT
, cap
);
220 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
222 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
223 unsigned int devfn
, u8 hdr_type
)
227 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
228 if (!(status
& PCI_STATUS_CAP_LIST
))
232 case PCI_HEADER_TYPE_NORMAL
:
233 case PCI_HEADER_TYPE_BRIDGE
:
234 return PCI_CAPABILITY_LIST
;
235 case PCI_HEADER_TYPE_CARDBUS
:
236 return PCI_CB_CAPABILITY_LIST
;
243 * pci_find_capability - query for devices' capabilities
244 * @dev: PCI device to query
245 * @cap: capability code
247 * Tell if a device supports a given PCI capability.
248 * Returns the address of the requested capability structure within the
249 * device's PCI configuration space or 0 in case the device does not
250 * support it. Possible values for @cap:
252 * %PCI_CAP_ID_PM Power Management
253 * %PCI_CAP_ID_AGP Accelerated Graphics Port
254 * %PCI_CAP_ID_VPD Vital Product Data
255 * %PCI_CAP_ID_SLOTID Slot Identification
256 * %PCI_CAP_ID_MSI Message Signalled Interrupts
257 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
258 * %PCI_CAP_ID_PCIX PCI-X
259 * %PCI_CAP_ID_EXP PCI Express
261 int pci_find_capability(struct pci_dev
*dev
, int cap
)
265 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
267 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
271 EXPORT_SYMBOL(pci_find_capability
);
274 * pci_bus_find_capability - query for devices' capabilities
275 * @bus: the PCI bus to query
276 * @devfn: PCI device to query
277 * @cap: capability code
279 * Like pci_find_capability() but works for pci devices that do not have a
280 * pci_dev structure set up yet.
282 * Returns the address of the requested capability structure within the
283 * device's PCI configuration space or 0 in case the device does not
286 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
291 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
293 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
295 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
299 EXPORT_SYMBOL(pci_bus_find_capability
);
302 * pci_find_next_ext_capability - Find an extended capability
303 * @dev: PCI device to query
304 * @start: address at which to start looking (0 to start at beginning of list)
305 * @cap: capability code
307 * Returns the address of the next matching extended capability structure
308 * within the device's PCI configuration space or 0 if the device does
309 * not support it. Some capabilities can occur several times, e.g., the
310 * vendor-specific capability, and this provides a way to find them all.
312 int pci_find_next_ext_capability(struct pci_dev
*dev
, int start
, int cap
)
316 int pos
= PCI_CFG_SPACE_SIZE
;
318 /* minimum 8 bytes per capability */
319 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
321 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
327 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
331 * If we have no capabilities, this is indicated by cap ID,
332 * cap version and next pointer all being 0.
338 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
341 pos
= PCI_EXT_CAP_NEXT(header
);
342 if (pos
< PCI_CFG_SPACE_SIZE
)
345 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
351 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
354 * pci_find_ext_capability - Find an extended capability
355 * @dev: PCI device to query
356 * @cap: capability code
358 * Returns the address of the requested extended capability structure
359 * within the device's PCI configuration space or 0 if the device does
360 * not support it. Possible values for @cap:
362 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
363 * %PCI_EXT_CAP_ID_VC Virtual Channel
364 * %PCI_EXT_CAP_ID_DSN Device Serial Number
365 * %PCI_EXT_CAP_ID_PWR Power Budgeting
367 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
369 return pci_find_next_ext_capability(dev
, 0, cap
);
371 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
373 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
375 int rc
, ttl
= PCI_FIND_CAP_TTL
;
378 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
379 mask
= HT_3BIT_CAP_MASK
;
381 mask
= HT_5BIT_CAP_MASK
;
383 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
384 PCI_CAP_ID_HT
, &ttl
);
386 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
387 if (rc
!= PCIBIOS_SUCCESSFUL
)
390 if ((cap
& mask
) == ht_cap
)
393 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
394 pos
+ PCI_CAP_LIST_NEXT
,
395 PCI_CAP_ID_HT
, &ttl
);
401 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
402 * @dev: PCI device to query
403 * @pos: Position from which to continue searching
404 * @ht_cap: Hypertransport capability code
406 * To be used in conjunction with pci_find_ht_capability() to search for
407 * all capabilities matching @ht_cap. @pos should always be a value returned
408 * from pci_find_ht_capability().
410 * NB. To be 100% safe against broken PCI devices, the caller should take
411 * steps to avoid an infinite loop.
413 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
415 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
417 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
420 * pci_find_ht_capability - query a device's Hypertransport capabilities
421 * @dev: PCI device to query
422 * @ht_cap: Hypertransport capability code
424 * Tell if a device supports a given Hypertransport capability.
425 * Returns an address within the device's PCI configuration space
426 * or 0 in case the device does not support the request capability.
427 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
428 * which has a Hypertransport capability matching @ht_cap.
430 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
434 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
436 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
440 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
443 * pci_find_parent_resource - return resource region of parent bus of given region
444 * @dev: PCI device structure contains resources to be searched
445 * @res: child resource record for which parent is sought
447 * For given resource region of given device, return the resource
448 * region of parent bus the given region is contained in.
450 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
451 struct resource
*res
)
453 const struct pci_bus
*bus
= dev
->bus
;
457 pci_bus_for_each_resource(bus
, r
, i
) {
460 if (resource_contains(r
, res
)) {
463 * If the window is prefetchable but the BAR is
464 * not, the allocator made a mistake.
466 if (r
->flags
& IORESOURCE_PREFETCH
&&
467 !(res
->flags
& IORESOURCE_PREFETCH
))
471 * If we're below a transparent bridge, there may
472 * be both a positively-decoded aperture and a
473 * subtractively-decoded region that contain the BAR.
474 * We want the positively-decoded one, so this depends
475 * on pci_bus_for_each_resource() giving us those
483 EXPORT_SYMBOL(pci_find_parent_resource
);
486 * pci_find_resource - Return matching PCI device resource
487 * @dev: PCI device to query
488 * @res: Resource to look for
490 * Goes over standard PCI resources (BARs) and checks if the given resource
491 * is partially or fully contained in any of them. In that case the
492 * matching resource is returned, %NULL otherwise.
494 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
498 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++) {
499 struct resource
*r
= &dev
->resource
[i
];
501 if (r
->start
&& resource_contains(r
, res
))
507 EXPORT_SYMBOL(pci_find_resource
);
510 * pci_find_pcie_root_port - return PCIe Root Port
511 * @dev: PCI device to query
513 * Traverse up the parent chain and return the PCIe Root Port PCI Device
514 * for a given PCI Device.
516 struct pci_dev
*pci_find_pcie_root_port(struct pci_dev
*dev
)
518 struct pci_dev
*bridge
, *highest_pcie_bridge
= dev
;
520 bridge
= pci_upstream_bridge(dev
);
521 while (bridge
&& pci_is_pcie(bridge
)) {
522 highest_pcie_bridge
= bridge
;
523 bridge
= pci_upstream_bridge(bridge
);
526 if (pci_pcie_type(highest_pcie_bridge
) != PCI_EXP_TYPE_ROOT_PORT
)
529 return highest_pcie_bridge
;
531 EXPORT_SYMBOL(pci_find_pcie_root_port
);
534 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
535 * @dev: the PCI device to operate on
536 * @pos: config space offset of status word
537 * @mask: mask of bit(s) to care about in status word
539 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
541 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
545 /* Wait for Transaction Pending bit clean */
546 for (i
= 0; i
< 4; i
++) {
549 msleep((1 << (i
- 1)) * 100);
551 pci_read_config_word(dev
, pos
, &status
);
552 if (!(status
& mask
))
560 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
561 * @dev: PCI device to have its BARs restored
563 * Restore the BAR values for a given device, so as to make it
564 * accessible by its driver.
566 static void pci_restore_bars(struct pci_dev
*dev
)
570 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
571 pci_update_resource(dev
, i
);
574 static const struct pci_platform_pm_ops
*pci_platform_pm
;
576 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
578 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
579 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
581 pci_platform_pm
= ops
;
585 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
587 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
590 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
593 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
596 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
598 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
601 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
603 return pci_platform_pm
?
604 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
607 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
609 return pci_platform_pm
?
610 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
613 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
615 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
619 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
621 * @dev: PCI device to handle.
622 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
625 * -EINVAL if the requested state is invalid.
626 * -EIO if device does not support PCI PM or its PM capabilities register has a
627 * wrong version, or device doesn't support the requested state.
628 * 0 if device already is in the requested state.
629 * 0 if device's power state has been successfully changed.
631 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
634 bool need_restore
= false;
636 /* Check if we're already there */
637 if (dev
->current_state
== state
)
643 if (state
< PCI_D0
|| state
> PCI_D3hot
)
646 /* Validate current state:
647 * Can enter D0 from any state, but if we can only go deeper
648 * to sleep if we're already in a low power state
650 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
651 && dev
->current_state
> state
) {
652 dev_err(&dev
->dev
, "invalid power transition (from state %d to %d)\n",
653 dev
->current_state
, state
);
657 /* check if this device supports the desired state */
658 if ((state
== PCI_D1
&& !dev
->d1_support
)
659 || (state
== PCI_D2
&& !dev
->d2_support
))
662 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
664 /* If we're (effectively) in D3, force entire word to 0.
665 * This doesn't affect PME_Status, disables PME_En, and
666 * sets PowerState to 0.
668 switch (dev
->current_state
) {
672 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
677 case PCI_UNKNOWN
: /* Boot-up */
678 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
679 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
681 /* Fall-through: force to D0 */
687 /* enter specified state */
688 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
690 /* Mandatory power management transition delays */
691 /* see PCI PM 1.1 5.6.1 table 18 */
692 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
693 pci_dev_d3_sleep(dev
);
694 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
695 udelay(PCI_PM_D2_DELAY
);
697 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
698 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
699 if (dev
->current_state
!= state
&& printk_ratelimit())
700 dev_info(&dev
->dev
, "Refused to change power state, currently in D%d\n",
704 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
705 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
706 * from D3hot to D0 _may_ perform an internal reset, thereby
707 * going to "D0 Uninitialized" rather than "D0 Initialized".
708 * For example, at least some versions of the 3c905B and the
709 * 3c556B exhibit this behaviour.
711 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
712 * devices in a D3hot state at boot. Consequently, we need to
713 * restore at least the BARs so that the device will be
714 * accessible to its driver.
717 pci_restore_bars(dev
);
720 pcie_aspm_pm_state_change(dev
->bus
->self
);
726 * pci_update_current_state - Read power state of given device and cache it
727 * @dev: PCI device to handle.
728 * @state: State to cache in case the device doesn't have the PM capability
730 * The power state is read from the PMCSR register, which however is
731 * inaccessible in D3cold. The platform firmware is therefore queried first
732 * to detect accessibility of the register. In case the platform firmware
733 * reports an incorrect state or the device isn't power manageable by the
734 * platform at all, we try to detect D3cold by testing accessibility of the
735 * vendor ID in config space.
737 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
739 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
740 !pci_device_is_present(dev
)) {
741 dev
->current_state
= PCI_D3cold
;
742 } else if (dev
->pm_cap
) {
745 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
746 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
748 dev
->current_state
= state
;
753 * pci_power_up - Put the given device into D0 forcibly
754 * @dev: PCI device to power up
756 void pci_power_up(struct pci_dev
*dev
)
758 if (platform_pci_power_manageable(dev
))
759 platform_pci_set_power_state(dev
, PCI_D0
);
761 pci_raw_set_power_state(dev
, PCI_D0
);
762 pci_update_current_state(dev
, PCI_D0
);
766 * pci_platform_power_transition - Use platform to change device power state
767 * @dev: PCI device to handle.
768 * @state: State to put the device into.
770 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
774 if (platform_pci_power_manageable(dev
)) {
775 error
= platform_pci_set_power_state(dev
, state
);
777 pci_update_current_state(dev
, state
);
781 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
782 dev
->current_state
= PCI_D0
;
788 * pci_wakeup - Wake up a PCI device
789 * @pci_dev: Device to handle.
790 * @ign: ignored parameter
792 static int pci_wakeup(struct pci_dev
*pci_dev
, void *ign
)
794 pci_wakeup_event(pci_dev
);
795 pm_request_resume(&pci_dev
->dev
);
800 * pci_wakeup_bus - Walk given bus and wake up devices on it
801 * @bus: Top bus of the subtree to walk.
803 static void pci_wakeup_bus(struct pci_bus
*bus
)
806 pci_walk_bus(bus
, pci_wakeup
, NULL
);
810 * __pci_start_power_transition - Start power transition of a PCI device
811 * @dev: PCI device to handle.
812 * @state: State to put the device into.
814 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
816 if (state
== PCI_D0
) {
817 pci_platform_power_transition(dev
, PCI_D0
);
819 * Mandatory power management transition delays, see
820 * PCI Express Base Specification Revision 2.0 Section
821 * 6.6.1: Conventional Reset. Do not delay for
822 * devices powered on/off by corresponding bridge,
823 * because have already delayed for the bridge.
825 if (dev
->runtime_d3cold
) {
826 if (dev
->d3cold_delay
)
827 msleep(dev
->d3cold_delay
);
829 * When powering on a bridge from D3cold, the
830 * whole hierarchy may be powered on into
831 * D0uninitialized state, resume them to give
832 * them a chance to suspend again
834 pci_wakeup_bus(dev
->subordinate
);
840 * __pci_dev_set_current_state - Set current state of a PCI device
841 * @dev: Device to handle
842 * @data: pointer to state to be set
844 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
846 pci_power_t state
= *(pci_power_t
*)data
;
848 dev
->current_state
= state
;
853 * __pci_bus_set_current_state - Walk given bus and set current state of devices
854 * @bus: Top bus of the subtree to walk.
855 * @state: state to be set
857 static void __pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
860 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
864 * __pci_complete_power_transition - Complete power transition of a PCI device
865 * @dev: PCI device to handle.
866 * @state: State to put the device into.
868 * This function should not be called directly by device drivers.
870 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
876 ret
= pci_platform_power_transition(dev
, state
);
877 /* Power off the bridge may power off the whole hierarchy */
878 if (!ret
&& state
== PCI_D3cold
)
879 __pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
882 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
885 * pci_set_power_state - Set the power state of a PCI device
886 * @dev: PCI device to handle.
887 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
889 * Transition a device to a new power state, using the platform firmware and/or
890 * the device's PCI PM registers.
893 * -EINVAL if the requested state is invalid.
894 * -EIO if device does not support PCI PM or its PM capabilities register has a
895 * wrong version, or device doesn't support the requested state.
896 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
897 * 0 if device already is in the requested state.
898 * 0 if the transition is to D3 but D3 is not supported.
899 * 0 if device's power state has been successfully changed.
901 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
905 /* bound the state we're entering */
906 if (state
> PCI_D3cold
)
908 else if (state
< PCI_D0
)
910 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
912 * If the device or the parent bridge do not support PCI PM,
913 * ignore the request if we're doing anything other than putting
914 * it into D0 (which would only happen on boot).
918 /* Check if we're already there */
919 if (dev
->current_state
== state
)
922 __pci_start_power_transition(dev
, state
);
924 /* This device is quirked not to be put into D3, so
925 don't put it in D3 */
926 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
930 * To put device in D3cold, we put device into D3hot in native
931 * way, then put device into D3cold with platform ops
933 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
936 if (!__pci_complete_power_transition(dev
, state
))
941 EXPORT_SYMBOL(pci_set_power_state
);
944 * pci_choose_state - Choose the power state of a PCI device
945 * @dev: PCI device to be suspended
946 * @state: target sleep state for the whole system. This is the value
947 * that is passed to suspend() function.
949 * Returns PCI power state suitable for given device and given system
953 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
960 ret
= platform_pci_choose_state(dev
);
961 if (ret
!= PCI_POWER_ERROR
)
964 switch (state
.event
) {
967 case PM_EVENT_FREEZE
:
968 case PM_EVENT_PRETHAW
:
969 /* REVISIT both freeze and pre-thaw "should" use D0 */
970 case PM_EVENT_SUSPEND
:
971 case PM_EVENT_HIBERNATE
:
974 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
980 EXPORT_SYMBOL(pci_choose_state
);
982 #define PCI_EXP_SAVE_REGS 7
984 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
985 u16 cap
, bool extended
)
987 struct pci_cap_saved_state
*tmp
;
989 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
990 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
996 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
998 return _pci_find_saved_cap(dev
, cap
, false);
1001 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1003 return _pci_find_saved_cap(dev
, cap
, true);
1006 static int pci_save_pcie_state(struct pci_dev
*dev
)
1009 struct pci_cap_saved_state
*save_state
;
1012 if (!pci_is_pcie(dev
))
1015 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1017 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1021 cap
= (u16
*)&save_state
->cap
.data
[0];
1022 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1023 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1024 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1025 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1026 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1027 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1028 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1033 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1036 struct pci_cap_saved_state
*save_state
;
1039 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1043 cap
= (u16
*)&save_state
->cap
.data
[0];
1044 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1045 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1046 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1047 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1048 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1049 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1050 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1054 static int pci_save_pcix_state(struct pci_dev
*dev
)
1057 struct pci_cap_saved_state
*save_state
;
1059 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1063 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1065 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
1069 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1070 (u16
*)save_state
->cap
.data
);
1075 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1078 struct pci_cap_saved_state
*save_state
;
1081 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1082 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1083 if (!save_state
|| !pos
)
1085 cap
= (u16
*)&save_state
->cap
.data
[0];
1087 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1092 * pci_save_state - save the PCI configuration space of a device before suspending
1093 * @dev: - PCI device that we're dealing with
1095 int pci_save_state(struct pci_dev
*dev
)
1098 /* XXX: 100% dword access ok here? */
1099 for (i
= 0; i
< 16; i
++)
1100 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1101 dev
->state_saved
= true;
1103 i
= pci_save_pcie_state(dev
);
1107 i
= pci_save_pcix_state(dev
);
1111 return pci_save_vc_state(dev
);
1113 EXPORT_SYMBOL(pci_save_state
);
1115 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1116 u32 saved_val
, int retry
)
1120 pci_read_config_dword(pdev
, offset
, &val
);
1121 if (val
== saved_val
)
1125 dev_dbg(&pdev
->dev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1126 offset
, val
, saved_val
);
1127 pci_write_config_dword(pdev
, offset
, saved_val
);
1131 pci_read_config_dword(pdev
, offset
, &val
);
1132 if (val
== saved_val
)
1139 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1140 int start
, int end
, int retry
)
1144 for (index
= end
; index
>= start
; index
--)
1145 pci_restore_config_dword(pdev
, 4 * index
,
1146 pdev
->saved_config_space
[index
],
1150 static void pci_restore_config_space(struct pci_dev
*pdev
)
1152 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1153 pci_restore_config_space_range(pdev
, 10, 15, 0);
1154 /* Restore BARs before the command register. */
1155 pci_restore_config_space_range(pdev
, 4, 9, 10);
1156 pci_restore_config_space_range(pdev
, 0, 3, 0);
1158 pci_restore_config_space_range(pdev
, 0, 15, 0);
1163 * pci_restore_state - Restore the saved state of a PCI device
1164 * @dev: - PCI device that we're dealing with
1166 void pci_restore_state(struct pci_dev
*dev
)
1168 if (!dev
->state_saved
)
1171 /* PCI Express register must be restored first */
1172 pci_restore_pcie_state(dev
);
1173 pci_restore_pasid_state(dev
);
1174 pci_restore_pri_state(dev
);
1175 pci_restore_ats_state(dev
);
1176 pci_restore_vc_state(dev
);
1178 pci_cleanup_aer_error_status_regs(dev
);
1180 pci_restore_config_space(dev
);
1182 pci_restore_pcix_state(dev
);
1183 pci_restore_msi_state(dev
);
1185 /* Restore ACS and IOV configuration state */
1186 pci_enable_acs(dev
);
1187 pci_restore_iov_state(dev
);
1189 dev
->state_saved
= false;
1191 EXPORT_SYMBOL(pci_restore_state
);
1193 struct pci_saved_state
{
1194 u32 config_space
[16];
1195 struct pci_cap_saved_data cap
[0];
1199 * pci_store_saved_state - Allocate and return an opaque struct containing
1200 * the device saved state.
1201 * @dev: PCI device that we're dealing with
1203 * Return NULL if no state or error.
1205 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1207 struct pci_saved_state
*state
;
1208 struct pci_cap_saved_state
*tmp
;
1209 struct pci_cap_saved_data
*cap
;
1212 if (!dev
->state_saved
)
1215 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1217 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1218 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1220 state
= kzalloc(size
, GFP_KERNEL
);
1224 memcpy(state
->config_space
, dev
->saved_config_space
,
1225 sizeof(state
->config_space
));
1228 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1229 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1230 memcpy(cap
, &tmp
->cap
, len
);
1231 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1233 /* Empty cap_save terminates list */
1237 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1240 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1241 * @dev: PCI device that we're dealing with
1242 * @state: Saved state returned from pci_store_saved_state()
1244 int pci_load_saved_state(struct pci_dev
*dev
,
1245 struct pci_saved_state
*state
)
1247 struct pci_cap_saved_data
*cap
;
1249 dev
->state_saved
= false;
1254 memcpy(dev
->saved_config_space
, state
->config_space
,
1255 sizeof(state
->config_space
));
1259 struct pci_cap_saved_state
*tmp
;
1261 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1262 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1265 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1266 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1267 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1270 dev
->state_saved
= true;
1273 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1276 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1277 * and free the memory allocated for it.
1278 * @dev: PCI device that we're dealing with
1279 * @state: Pointer to saved state returned from pci_store_saved_state()
1281 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1282 struct pci_saved_state
**state
)
1284 int ret
= pci_load_saved_state(dev
, *state
);
1289 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1291 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1293 return pci_enable_resources(dev
, bars
);
1296 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1299 struct pci_dev
*bridge
;
1303 err
= pci_set_power_state(dev
, PCI_D0
);
1304 if (err
< 0 && err
!= -EIO
)
1307 bridge
= pci_upstream_bridge(dev
);
1309 pcie_aspm_powersave_config_link(bridge
);
1311 err
= pcibios_enable_device(dev
, bars
);
1314 pci_fixup_device(pci_fixup_enable
, dev
);
1316 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1319 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1321 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1322 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1323 pci_write_config_word(dev
, PCI_COMMAND
,
1324 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1331 * pci_reenable_device - Resume abandoned device
1332 * @dev: PCI device to be resumed
1334 * Note this function is a backend of pci_default_resume and is not supposed
1335 * to be called by normal code, write proper resume handler and use it instead.
1337 int pci_reenable_device(struct pci_dev
*dev
)
1339 if (pci_is_enabled(dev
))
1340 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1343 EXPORT_SYMBOL(pci_reenable_device
);
1345 static void pci_enable_bridge(struct pci_dev
*dev
)
1347 struct pci_dev
*bridge
;
1350 bridge
= pci_upstream_bridge(dev
);
1352 pci_enable_bridge(bridge
);
1354 if (pci_is_enabled(dev
)) {
1355 if (!dev
->is_busmaster
)
1356 pci_set_master(dev
);
1360 retval
= pci_enable_device(dev
);
1362 dev_err(&dev
->dev
, "Error enabling bridge (%d), continuing\n",
1364 pci_set_master(dev
);
1367 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1369 struct pci_dev
*bridge
;
1374 * Power state could be unknown at this point, either due to a fresh
1375 * boot or a device removal call. So get the current power state
1376 * so that things like MSI message writing will behave as expected
1377 * (e.g. if the device really is in D0 at enable time).
1381 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1382 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1385 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1386 return 0; /* already enabled */
1388 bridge
= pci_upstream_bridge(dev
);
1390 pci_enable_bridge(bridge
);
1392 /* only skip sriov related */
1393 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1394 if (dev
->resource
[i
].flags
& flags
)
1396 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1397 if (dev
->resource
[i
].flags
& flags
)
1400 err
= do_pci_enable_device(dev
, bars
);
1402 atomic_dec(&dev
->enable_cnt
);
1407 * pci_enable_device_io - Initialize a device for use with IO space
1408 * @dev: PCI device to be initialized
1410 * Initialize device before it's used by a driver. Ask low-level code
1411 * to enable I/O resources. Wake up the device if it was suspended.
1412 * Beware, this function can fail.
1414 int pci_enable_device_io(struct pci_dev
*dev
)
1416 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1418 EXPORT_SYMBOL(pci_enable_device_io
);
1421 * pci_enable_device_mem - Initialize a device for use with Memory space
1422 * @dev: PCI device to be initialized
1424 * Initialize device before it's used by a driver. Ask low-level code
1425 * to enable Memory resources. Wake up the device if it was suspended.
1426 * Beware, this function can fail.
1428 int pci_enable_device_mem(struct pci_dev
*dev
)
1430 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1432 EXPORT_SYMBOL(pci_enable_device_mem
);
1435 * pci_enable_device - Initialize device before it's used by a driver.
1436 * @dev: PCI device to be initialized
1438 * Initialize device before it's used by a driver. Ask low-level code
1439 * to enable I/O and memory. Wake up the device if it was suspended.
1440 * Beware, this function can fail.
1442 * Note we don't actually enable the device many times if we call
1443 * this function repeatedly (we just increment the count).
1445 int pci_enable_device(struct pci_dev
*dev
)
1447 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
1449 EXPORT_SYMBOL(pci_enable_device
);
1452 * Managed PCI resources. This manages device on/off, intx/msi/msix
1453 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1454 * there's no need to track it separately. pci_devres is initialized
1455 * when a device is enabled using managed PCI device enable interface.
1458 unsigned int enabled
:1;
1459 unsigned int pinned
:1;
1460 unsigned int orig_intx
:1;
1461 unsigned int restore_intx
:1;
1466 static void pcim_release(struct device
*gendev
, void *res
)
1468 struct pci_dev
*dev
= to_pci_dev(gendev
);
1469 struct pci_devres
*this = res
;
1472 if (dev
->msi_enabled
)
1473 pci_disable_msi(dev
);
1474 if (dev
->msix_enabled
)
1475 pci_disable_msix(dev
);
1477 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
1478 if (this->region_mask
& (1 << i
))
1479 pci_release_region(dev
, i
);
1484 if (this->restore_intx
)
1485 pci_intx(dev
, this->orig_intx
);
1487 if (this->enabled
&& !this->pinned
)
1488 pci_disable_device(dev
);
1491 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
1493 struct pci_devres
*dr
, *new_dr
;
1495 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1499 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1502 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1505 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
1507 if (pci_is_managed(pdev
))
1508 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1513 * pcim_enable_device - Managed pci_enable_device()
1514 * @pdev: PCI device to be initialized
1516 * Managed pci_enable_device().
1518 int pcim_enable_device(struct pci_dev
*pdev
)
1520 struct pci_devres
*dr
;
1523 dr
= get_pci_dr(pdev
);
1529 rc
= pci_enable_device(pdev
);
1531 pdev
->is_managed
= 1;
1536 EXPORT_SYMBOL(pcim_enable_device
);
1539 * pcim_pin_device - Pin managed PCI device
1540 * @pdev: PCI device to pin
1542 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1543 * driver detach. @pdev must have been enabled with
1544 * pcim_enable_device().
1546 void pcim_pin_device(struct pci_dev
*pdev
)
1548 struct pci_devres
*dr
;
1550 dr
= find_pci_dr(pdev
);
1551 WARN_ON(!dr
|| !dr
->enabled
);
1555 EXPORT_SYMBOL(pcim_pin_device
);
1558 * pcibios_add_device - provide arch specific hooks when adding device dev
1559 * @dev: the PCI device being added
1561 * Permits the platform to provide architecture specific functionality when
1562 * devices are added. This is the default implementation. Architecture
1563 * implementations can override this.
1565 int __weak
pcibios_add_device(struct pci_dev
*dev
)
1571 * pcibios_release_device - provide arch specific hooks when releasing device dev
1572 * @dev: the PCI device being released
1574 * Permits the platform to provide architecture specific functionality when
1575 * devices are released. This is the default implementation. Architecture
1576 * implementations can override this.
1578 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
1581 * pcibios_disable_device - disable arch specific PCI resources for device dev
1582 * @dev: the PCI device to disable
1584 * Disables architecture specific PCI resources for the device. This
1585 * is the default implementation. Architecture implementations can
1588 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
1591 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1592 * @irq: ISA IRQ to penalize
1593 * @active: IRQ active or not
1595 * Permits the platform to provide architecture-specific functionality when
1596 * penalizing ISA IRQs. This is the default implementation. Architecture
1597 * implementations can override this.
1599 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
1601 static void do_pci_disable_device(struct pci_dev
*dev
)
1605 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1606 if (pci_command
& PCI_COMMAND_MASTER
) {
1607 pci_command
&= ~PCI_COMMAND_MASTER
;
1608 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1611 pcibios_disable_device(dev
);
1615 * pci_disable_enabled_device - Disable device without updating enable_cnt
1616 * @dev: PCI device to disable
1618 * NOTE: This function is a backend of PCI power management routines and is
1619 * not supposed to be called drivers.
1621 void pci_disable_enabled_device(struct pci_dev
*dev
)
1623 if (pci_is_enabled(dev
))
1624 do_pci_disable_device(dev
);
1628 * pci_disable_device - Disable PCI device after use
1629 * @dev: PCI device to be disabled
1631 * Signal to the system that the PCI device is not in use by the system
1632 * anymore. This only involves disabling PCI bus-mastering, if active.
1634 * Note we don't actually disable the device until all callers of
1635 * pci_enable_device() have called pci_disable_device().
1637 void pci_disable_device(struct pci_dev
*dev
)
1639 struct pci_devres
*dr
;
1641 dr
= find_pci_dr(dev
);
1645 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
1646 "disabling already-disabled device");
1648 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
1651 do_pci_disable_device(dev
);
1653 dev
->is_busmaster
= 0;
1655 EXPORT_SYMBOL(pci_disable_device
);
1658 * pcibios_set_pcie_reset_state - set reset state for device dev
1659 * @dev: the PCIe device reset
1660 * @state: Reset state to enter into
1663 * Sets the PCIe reset state for the device. This is the default
1664 * implementation. Architecture implementations can override this.
1666 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1667 enum pcie_reset_state state
)
1673 * pci_set_pcie_reset_state - set reset state for device dev
1674 * @dev: the PCIe device reset
1675 * @state: Reset state to enter into
1678 * Sets the PCI reset state for the device.
1680 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1682 return pcibios_set_pcie_reset_state(dev
, state
);
1684 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
1687 * pci_check_pme_status - Check if given device has generated PME.
1688 * @dev: Device to check.
1690 * Check the PME status of the device and if set, clear it and clear PME enable
1691 * (if set). Return 'true' if PME status and PME enable were both set or
1692 * 'false' otherwise.
1694 bool pci_check_pme_status(struct pci_dev
*dev
)
1703 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
1704 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
1705 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
1708 /* Clear PME status. */
1709 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1710 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
1711 /* Disable PME to avoid interrupt flood. */
1712 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1716 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
1722 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1723 * @dev: Device to handle.
1724 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1726 * Check if @dev has generated PME and queue a resume request for it in that
1729 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
1731 if (pme_poll_reset
&& dev
->pme_poll
)
1732 dev
->pme_poll
= false;
1734 if (pci_check_pme_status(dev
)) {
1735 pci_wakeup_event(dev
);
1736 pm_request_resume(&dev
->dev
);
1742 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1743 * @bus: Top bus of the subtree to walk.
1745 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
1748 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
1753 * pci_pme_capable - check the capability of PCI device to generate PME#
1754 * @dev: PCI device to handle.
1755 * @state: PCI state from which device will issue PME#.
1757 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1762 return !!(dev
->pme_support
& (1 << state
));
1764 EXPORT_SYMBOL(pci_pme_capable
);
1766 static void pci_pme_list_scan(struct work_struct
*work
)
1768 struct pci_pme_device
*pme_dev
, *n
;
1770 mutex_lock(&pci_pme_list_mutex
);
1771 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
1772 if (pme_dev
->dev
->pme_poll
) {
1773 struct pci_dev
*bridge
;
1775 bridge
= pme_dev
->dev
->bus
->self
;
1777 * If bridge is in low power state, the
1778 * configuration space of subordinate devices
1779 * may be not accessible
1781 if (bridge
&& bridge
->current_state
!= PCI_D0
)
1783 pci_pme_wakeup(pme_dev
->dev
, NULL
);
1785 list_del(&pme_dev
->list
);
1789 if (!list_empty(&pci_pme_list
))
1790 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
1791 msecs_to_jiffies(PME_TIMEOUT
));
1792 mutex_unlock(&pci_pme_list_mutex
);
1795 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
1799 if (!dev
->pme_support
)
1802 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1803 /* Clear PME_Status by writing 1 to it and enable PME# */
1804 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1806 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1808 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1812 * pci_pme_restore - Restore PME configuration after config space restore.
1813 * @dev: PCI device to update.
1815 void pci_pme_restore(struct pci_dev
*dev
)
1819 if (!dev
->pme_support
)
1822 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1823 if (dev
->wakeup_prepared
) {
1824 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
1825 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
1827 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1828 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
1830 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1834 * pci_pme_active - enable or disable PCI device's PME# function
1835 * @dev: PCI device to handle.
1836 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1838 * The caller must verify that the device is capable of generating PME# before
1839 * calling this function with @enable equal to 'true'.
1841 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1843 __pci_pme_active(dev
, enable
);
1846 * PCI (as opposed to PCIe) PME requires that the device have
1847 * its PME# line hooked up correctly. Not all hardware vendors
1848 * do this, so the PME never gets delivered and the device
1849 * remains asleep. The easiest way around this is to
1850 * periodically walk the list of suspended devices and check
1851 * whether any have their PME flag set. The assumption is that
1852 * we'll wake up often enough anyway that this won't be a huge
1853 * hit, and the power savings from the devices will still be a
1856 * Although PCIe uses in-band PME message instead of PME# line
1857 * to report PME, PME does not work for some PCIe devices in
1858 * reality. For example, there are devices that set their PME
1859 * status bits, but don't really bother to send a PME message;
1860 * there are PCI Express Root Ports that don't bother to
1861 * trigger interrupts when they receive PME messages from the
1862 * devices below. So PME poll is used for PCIe devices too.
1865 if (dev
->pme_poll
) {
1866 struct pci_pme_device
*pme_dev
;
1868 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
1871 dev_warn(&dev
->dev
, "can't enable PME#\n");
1875 mutex_lock(&pci_pme_list_mutex
);
1876 list_add(&pme_dev
->list
, &pci_pme_list
);
1877 if (list_is_singular(&pci_pme_list
))
1878 queue_delayed_work(system_freezable_wq
,
1880 msecs_to_jiffies(PME_TIMEOUT
));
1881 mutex_unlock(&pci_pme_list_mutex
);
1883 mutex_lock(&pci_pme_list_mutex
);
1884 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
1885 if (pme_dev
->dev
== dev
) {
1886 list_del(&pme_dev
->list
);
1891 mutex_unlock(&pci_pme_list_mutex
);
1895 dev_dbg(&dev
->dev
, "PME# %s\n", enable
? "enabled" : "disabled");
1897 EXPORT_SYMBOL(pci_pme_active
);
1900 * __pci_enable_wake - enable PCI device as wakeup event source
1901 * @dev: PCI device affected
1902 * @state: PCI state from which device will issue wakeup events
1903 * @enable: True to enable event generation; false to disable
1905 * This enables the device as a wakeup event source, or disables it.
1906 * When such events involves platform-specific hooks, those hooks are
1907 * called automatically by this routine.
1909 * Devices with legacy power management (no standard PCI PM capabilities)
1910 * always require such platform hooks.
1913 * 0 is returned on success
1914 * -EINVAL is returned if device is not supposed to wake up the system
1915 * Error code depending on the platform is returned if both the platform and
1916 * the native mechanism fail to enable the generation of wake-up events
1918 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
1923 * Bridges can only signal wakeup on behalf of subordinate devices,
1924 * but that is set up elsewhere, so skip them.
1926 if (pci_has_subordinate(dev
))
1929 /* Don't do the same thing twice in a row for one device. */
1930 if (!!enable
== !!dev
->wakeup_prepared
)
1934 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1935 * Anderson we should be doing PME# wake enable followed by ACPI wake
1936 * enable. To disable wake-up we call the platform first, for symmetry.
1942 if (pci_pme_capable(dev
, state
))
1943 pci_pme_active(dev
, true);
1946 error
= platform_pci_set_wakeup(dev
, true);
1950 dev
->wakeup_prepared
= true;
1952 platform_pci_set_wakeup(dev
, false);
1953 pci_pme_active(dev
, false);
1954 dev
->wakeup_prepared
= false;
1961 * pci_enable_wake - change wakeup settings for a PCI device
1962 * @pci_dev: Target device
1963 * @state: PCI state from which device will issue wakeup events
1964 * @enable: Whether or not to enable event generation
1966 * If @enable is set, check device_may_wakeup() for the device before calling
1967 * __pci_enable_wake() for it.
1969 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
1971 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
1974 return __pci_enable_wake(pci_dev
, state
, enable
);
1976 EXPORT_SYMBOL(pci_enable_wake
);
1979 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1980 * @dev: PCI device to prepare
1981 * @enable: True to enable wake-up event generation; false to disable
1983 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1984 * and this function allows them to set that up cleanly - pci_enable_wake()
1985 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1986 * ordering constraints.
1988 * This function only returns error code if the device is not allowed to wake
1989 * up the system from sleep or it is not capable of generating PME# from both
1990 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
1992 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1994 return pci_pme_capable(dev
, PCI_D3cold
) ?
1995 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1996 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1998 EXPORT_SYMBOL(pci_wake_from_d3
);
2001 * pci_target_state - find an appropriate low power state for a given PCI dev
2003 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2005 * Use underlying platform code to find a supported low power state for @dev.
2006 * If the platform can't manage @dev, return the deepest state from which it
2007 * can generate wake events, based on any available PME info.
2009 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2011 pci_power_t target_state
= PCI_D3hot
;
2013 if (platform_pci_power_manageable(dev
)) {
2015 * Call the platform to choose the target state of the device
2016 * and enable wake-up from this state if supported.
2018 pci_power_t state
= platform_pci_choose_state(dev
);
2021 case PCI_POWER_ERROR
:
2026 if (pci_no_d1d2(dev
))
2029 target_state
= state
;
2032 return target_state
;
2036 target_state
= PCI_D0
;
2039 * If the device is in D3cold even though it's not power-manageable by
2040 * the platform, it may have been powered down by non-standard means.
2041 * Best to let it slumber.
2043 if (dev
->current_state
== PCI_D3cold
)
2044 target_state
= PCI_D3cold
;
2048 * Find the deepest state from which the device can generate
2049 * wake-up events, make it the target state and enable device
2052 if (dev
->pme_support
) {
2054 && !(dev
->pme_support
& (1 << target_state
)))
2059 return target_state
;
2063 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2064 * @dev: Device to handle.
2066 * Choose the power state appropriate for the device depending on whether
2067 * it can wake up the system and/or is power manageable by the platform
2068 * (PCI_D3hot is the default) and put the device into that state.
2070 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2072 bool wakeup
= device_may_wakeup(&dev
->dev
);
2073 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2076 if (target_state
== PCI_POWER_ERROR
)
2079 pci_enable_wake(dev
, target_state
, wakeup
);
2081 error
= pci_set_power_state(dev
, target_state
);
2084 pci_enable_wake(dev
, target_state
, false);
2088 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2091 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2092 * @dev: Device to handle.
2094 * Disable device's system wake-up capability and put it into D0.
2096 int pci_back_from_sleep(struct pci_dev
*dev
)
2098 pci_enable_wake(dev
, PCI_D0
, false);
2099 return pci_set_power_state(dev
, PCI_D0
);
2101 EXPORT_SYMBOL(pci_back_from_sleep
);
2104 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2105 * @dev: PCI device being suspended.
2107 * Prepare @dev to generate wake-up events at run time and put it into a low
2110 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2112 pci_power_t target_state
;
2115 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2116 if (target_state
== PCI_POWER_ERROR
)
2119 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2121 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2123 error
= pci_set_power_state(dev
, target_state
);
2126 pci_enable_wake(dev
, target_state
, false);
2127 dev
->runtime_d3cold
= false;
2134 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2135 * @dev: Device to check.
2137 * Return true if the device itself is capable of generating wake-up events
2138 * (through the platform or using the native PCIe PME) or if the device supports
2139 * PME and one of its upstream bridges can generate wake-up events.
2141 bool pci_dev_run_wake(struct pci_dev
*dev
)
2143 struct pci_bus
*bus
= dev
->bus
;
2145 if (!dev
->pme_support
)
2148 /* PME-capable in principle, but not from the target power state */
2149 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2152 if (device_can_wakeup(&dev
->dev
))
2155 while (bus
->parent
) {
2156 struct pci_dev
*bridge
= bus
->self
;
2158 if (device_can_wakeup(&bridge
->dev
))
2164 /* We have reached the root bus. */
2166 return device_can_wakeup(bus
->bridge
);
2170 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2173 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2174 * @pci_dev: Device to check.
2176 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2177 * reconfigured due to wakeup settings difference between system and runtime
2178 * suspend and the current power state of it is suitable for the upcoming
2179 * (system) transition.
2181 * If the device is not configured for system wakeup, disable PME for it before
2182 * returning 'true' to prevent it from waking up the system unnecessarily.
2184 bool pci_dev_keep_suspended(struct pci_dev
*pci_dev
)
2186 struct device
*dev
= &pci_dev
->dev
;
2187 bool wakeup
= device_may_wakeup(dev
);
2189 if (!pm_runtime_suspended(dev
)
2190 || pci_target_state(pci_dev
, wakeup
) != pci_dev
->current_state
2191 || platform_pci_need_resume(pci_dev
))
2195 * At this point the device is good to go unless it's been configured
2196 * to generate PME at the runtime suspend time, but it is not supposed
2197 * to wake up the system. In that case, simply disable PME for it
2198 * (it will have to be re-enabled on exit from system resume).
2200 * If the device's power state is D3cold and the platform check above
2201 * hasn't triggered, the device's configuration is suitable and we don't
2202 * need to manipulate it at all.
2204 spin_lock_irq(&dev
->power
.lock
);
2206 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
&&
2208 __pci_pme_active(pci_dev
, false);
2210 spin_unlock_irq(&dev
->power
.lock
);
2215 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2216 * @pci_dev: Device to handle.
2218 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2219 * it might have been disabled during the prepare phase of system suspend if
2220 * the device was not configured for system wakeup.
2222 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2224 struct device
*dev
= &pci_dev
->dev
;
2226 if (!pci_dev_run_wake(pci_dev
))
2229 spin_lock_irq(&dev
->power
.lock
);
2231 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2232 __pci_pme_active(pci_dev
, true);
2234 spin_unlock_irq(&dev
->power
.lock
);
2237 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2239 struct device
*dev
= &pdev
->dev
;
2240 struct device
*parent
= dev
->parent
;
2243 pm_runtime_get_sync(parent
);
2244 pm_runtime_get_noresume(dev
);
2246 * pdev->current_state is set to PCI_D3cold during suspending,
2247 * so wait until suspending completes
2249 pm_runtime_barrier(dev
);
2251 * Only need to resume devices in D3cold, because config
2252 * registers are still accessible for devices suspended but
2255 if (pdev
->current_state
== PCI_D3cold
)
2256 pm_runtime_resume(dev
);
2259 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2261 struct device
*dev
= &pdev
->dev
;
2262 struct device
*parent
= dev
->parent
;
2264 pm_runtime_put(dev
);
2266 pm_runtime_put_sync(parent
);
2270 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2271 * @bridge: Bridge to check
2273 * This function checks if it is possible to move the bridge to D3.
2274 * Currently we only allow D3 for recent enough PCIe ports.
2276 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2280 if (!pci_is_pcie(bridge
))
2283 switch (pci_pcie_type(bridge
)) {
2284 case PCI_EXP_TYPE_ROOT_PORT
:
2285 case PCI_EXP_TYPE_UPSTREAM
:
2286 case PCI_EXP_TYPE_DOWNSTREAM
:
2287 if (pci_bridge_d3_disable
)
2291 * Hotplug interrupts cannot be delivered if the link is down,
2292 * so parents of a hotplug port must stay awake. In addition,
2293 * hotplug ports handled by firmware in System Management Mode
2294 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2295 * For simplicity, disallow in general for now.
2297 if (bridge
->is_hotplug_bridge
)
2300 if (pci_bridge_d3_force
)
2304 * It should be safe to put PCIe ports from 2015 or newer
2307 if (dmi_get_date(DMI_BIOS_DATE
, &year
, NULL
, NULL
) &&
2317 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2319 bool *d3cold_ok
= data
;
2321 if (/* The device needs to be allowed to go D3cold ... */
2322 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
2324 /* ... and if it is wakeup capable to do so from D3cold. */
2325 (device_may_wakeup(&dev
->dev
) &&
2326 !pci_pme_capable(dev
, PCI_D3cold
)) ||
2328 /* If it is a bridge it must be allowed to go to D3. */
2329 !pci_power_manageable(dev
))
2337 * pci_bridge_d3_update - Update bridge D3 capabilities
2338 * @dev: PCI device which is changed
2340 * Update upstream bridge PM capabilities accordingly depending on if the
2341 * device PM configuration was changed or the device is being removed. The
2342 * change is also propagated upstream.
2344 void pci_bridge_d3_update(struct pci_dev
*dev
)
2346 bool remove
= !device_is_registered(&dev
->dev
);
2347 struct pci_dev
*bridge
;
2348 bool d3cold_ok
= true;
2350 bridge
= pci_upstream_bridge(dev
);
2351 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
2355 * If D3 is currently allowed for the bridge, removing one of its
2356 * children won't change that.
2358 if (remove
&& bridge
->bridge_d3
)
2362 * If D3 is currently allowed for the bridge and a child is added or
2363 * changed, disallowance of D3 can only be caused by that child, so
2364 * we only need to check that single device, not any of its siblings.
2366 * If D3 is currently not allowed for the bridge, checking the device
2367 * first may allow us to skip checking its siblings.
2370 pci_dev_check_d3cold(dev
, &d3cold_ok
);
2373 * If D3 is currently not allowed for the bridge, this may be caused
2374 * either by the device being changed/removed or any of its siblings,
2375 * so we need to go through all children to find out if one of them
2376 * continues to block D3.
2378 if (d3cold_ok
&& !bridge
->bridge_d3
)
2379 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
2382 if (bridge
->bridge_d3
!= d3cold_ok
) {
2383 bridge
->bridge_d3
= d3cold_ok
;
2384 /* Propagate change to upstream bridges */
2385 pci_bridge_d3_update(bridge
);
2390 * pci_d3cold_enable - Enable D3cold for device
2391 * @dev: PCI device to handle
2393 * This function can be used in drivers to enable D3cold from the device
2394 * they handle. It also updates upstream PCI bridge PM capabilities
2397 void pci_d3cold_enable(struct pci_dev
*dev
)
2399 if (dev
->no_d3cold
) {
2400 dev
->no_d3cold
= false;
2401 pci_bridge_d3_update(dev
);
2404 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
2407 * pci_d3cold_disable - Disable D3cold for device
2408 * @dev: PCI device to handle
2410 * This function can be used in drivers to disable D3cold from the device
2411 * they handle. It also updates upstream PCI bridge PM capabilities
2414 void pci_d3cold_disable(struct pci_dev
*dev
)
2416 if (!dev
->no_d3cold
) {
2417 dev
->no_d3cold
= true;
2418 pci_bridge_d3_update(dev
);
2421 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
2424 * pci_pm_init - Initialize PM functions of given PCI device
2425 * @dev: PCI device to handle.
2427 void pci_pm_init(struct pci_dev
*dev
)
2432 pm_runtime_forbid(&dev
->dev
);
2433 pm_runtime_set_active(&dev
->dev
);
2434 pm_runtime_enable(&dev
->dev
);
2435 device_enable_async_suspend(&dev
->dev
);
2436 dev
->wakeup_prepared
= false;
2439 dev
->pme_support
= 0;
2441 /* find PCI PM capability in list */
2442 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
2445 /* Check device's ability to generate PME# */
2446 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
2448 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
2449 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
2450 pmc
& PCI_PM_CAP_VER_MASK
);
2455 dev
->d3_delay
= PCI_PM_D3_WAIT
;
2456 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
2457 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
2458 dev
->d3cold_allowed
= true;
2460 dev
->d1_support
= false;
2461 dev
->d2_support
= false;
2462 if (!pci_no_d1d2(dev
)) {
2463 if (pmc
& PCI_PM_CAP_D1
)
2464 dev
->d1_support
= true;
2465 if (pmc
& PCI_PM_CAP_D2
)
2466 dev
->d2_support
= true;
2468 if (dev
->d1_support
|| dev
->d2_support
)
2469 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
2470 dev
->d1_support
? " D1" : "",
2471 dev
->d2_support
? " D2" : "");
2474 pmc
&= PCI_PM_CAP_PME_MASK
;
2476 dev_printk(KERN_DEBUG
, &dev
->dev
,
2477 "PME# supported from%s%s%s%s%s\n",
2478 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
2479 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
2480 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
2481 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
2482 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
2483 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
2484 dev
->pme_poll
= true;
2486 * Make device's PM flags reflect the wake-up capability, but
2487 * let the user space enable it to wake up the system as needed.
2489 device_set_wakeup_capable(&dev
->dev
, true);
2490 /* Disable the PME# generation functionality */
2491 pci_pme_active(dev
, false);
2495 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
2497 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
2501 case PCI_EA_P_VF_MEM
:
2502 flags
|= IORESOURCE_MEM
;
2504 case PCI_EA_P_MEM_PREFETCH
:
2505 case PCI_EA_P_VF_MEM_PREFETCH
:
2506 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
2509 flags
|= IORESOURCE_IO
;
2518 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
2521 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
2522 return &dev
->resource
[bei
];
2523 #ifdef CONFIG_PCI_IOV
2524 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
2525 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
2526 return &dev
->resource
[PCI_IOV_RESOURCES
+
2527 bei
- PCI_EA_BEI_VF_BAR0
];
2529 else if (bei
== PCI_EA_BEI_ROM
)
2530 return &dev
->resource
[PCI_ROM_RESOURCE
];
2535 /* Read an Enhanced Allocation (EA) entry */
2536 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
2538 struct resource
*res
;
2539 int ent_size
, ent_offset
= offset
;
2540 resource_size_t start
, end
;
2541 unsigned long flags
;
2542 u32 dw0
, bei
, base
, max_offset
;
2544 bool support_64
= (sizeof(resource_size_t
) >= 8);
2546 pci_read_config_dword(dev
, ent_offset
, &dw0
);
2549 /* Entry size field indicates DWORDs after 1st */
2550 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
2552 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
2555 bei
= (dw0
& PCI_EA_BEI
) >> 4;
2556 prop
= (dw0
& PCI_EA_PP
) >> 8;
2559 * If the Property is in the reserved range, try the Secondary
2562 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
2563 prop
= (dw0
& PCI_EA_SP
) >> 16;
2564 if (prop
> PCI_EA_P_BRIDGE_IO
)
2567 res
= pci_ea_get_resource(dev
, bei
, prop
);
2569 dev_err(&dev
->dev
, "Unsupported EA entry BEI: %u\n", bei
);
2573 flags
= pci_ea_flags(dev
, prop
);
2575 dev_err(&dev
->dev
, "Unsupported EA properties: %#x\n", prop
);
2580 pci_read_config_dword(dev
, ent_offset
, &base
);
2581 start
= (base
& PCI_EA_FIELD_MASK
);
2584 /* Read MaxOffset */
2585 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
2588 /* Read Base MSBs (if 64-bit entry) */
2589 if (base
& PCI_EA_IS_64
) {
2592 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
2595 flags
|= IORESOURCE_MEM_64
;
2597 /* entry starts above 32-bit boundary, can't use */
2598 if (!support_64
&& base_upper
)
2602 start
|= ((u64
)base_upper
<< 32);
2605 end
= start
+ (max_offset
| 0x03);
2607 /* Read MaxOffset MSBs (if 64-bit entry) */
2608 if (max_offset
& PCI_EA_IS_64
) {
2609 u32 max_offset_upper
;
2611 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
2614 flags
|= IORESOURCE_MEM_64
;
2616 /* entry too big, can't use */
2617 if (!support_64
&& max_offset_upper
)
2621 end
+= ((u64
)max_offset_upper
<< 32);
2625 dev_err(&dev
->dev
, "EA Entry crosses address boundary\n");
2629 if (ent_size
!= ent_offset
- offset
) {
2631 "EA Entry Size (%d) does not match length read (%d)\n",
2632 ent_size
, ent_offset
- offset
);
2636 res
->name
= pci_name(dev
);
2641 if (bei
<= PCI_EA_BEI_BAR5
)
2642 dev_printk(KERN_DEBUG
, &dev
->dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2644 else if (bei
== PCI_EA_BEI_ROM
)
2645 dev_printk(KERN_DEBUG
, &dev
->dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2647 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
2648 dev_printk(KERN_DEBUG
, &dev
->dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2649 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
2651 dev_printk(KERN_DEBUG
, &dev
->dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2655 return offset
+ ent_size
;
2658 /* Enhanced Allocation Initialization */
2659 void pci_ea_init(struct pci_dev
*dev
)
2666 /* find PCI EA capability in list */
2667 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
2671 /* determine the number of entries */
2672 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
2674 num_ent
&= PCI_EA_NUM_ENT_MASK
;
2676 offset
= ea
+ PCI_EA_FIRST_ENT
;
2678 /* Skip DWORD 2 for type 1 functions */
2679 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
2682 /* parse each EA entry */
2683 for (i
= 0; i
< num_ent
; ++i
)
2684 offset
= pci_ea_read(dev
, offset
);
2687 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
2688 struct pci_cap_saved_state
*new_cap
)
2690 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
2694 * _pci_add_cap_save_buffer - allocate buffer for saving given
2695 * capability registers
2696 * @dev: the PCI device
2697 * @cap: the capability to allocate the buffer for
2698 * @extended: Standard or Extended capability ID
2699 * @size: requested size of the buffer
2701 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
2702 bool extended
, unsigned int size
)
2705 struct pci_cap_saved_state
*save_state
;
2708 pos
= pci_find_ext_capability(dev
, cap
);
2710 pos
= pci_find_capability(dev
, cap
);
2715 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
2719 save_state
->cap
.cap_nr
= cap
;
2720 save_state
->cap
.cap_extended
= extended
;
2721 save_state
->cap
.size
= size
;
2722 pci_add_saved_cap(dev
, save_state
);
2727 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
2729 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
2732 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
2734 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
2738 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2739 * @dev: the PCI device
2741 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
2745 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
2746 PCI_EXP_SAVE_REGS
* sizeof(u16
));
2749 "unable to preallocate PCI Express save buffer\n");
2751 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
2754 "unable to preallocate PCI-X save buffer\n");
2756 pci_allocate_vc_save_buffers(dev
);
2759 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
2761 struct pci_cap_saved_state
*tmp
;
2762 struct hlist_node
*n
;
2764 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
2769 * pci_configure_ari - enable or disable ARI forwarding
2770 * @dev: the PCI device
2772 * If @dev and its upstream bridge both support ARI, enable ARI in the
2773 * bridge. Otherwise, disable ARI in the bridge.
2775 void pci_configure_ari(struct pci_dev
*dev
)
2778 struct pci_dev
*bridge
;
2780 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
2783 bridge
= dev
->bus
->self
;
2787 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
2788 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
2791 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
2792 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
2793 PCI_EXP_DEVCTL2_ARI
);
2794 bridge
->ari_enabled
= 1;
2796 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
2797 PCI_EXP_DEVCTL2_ARI
);
2798 bridge
->ari_enabled
= 0;
2802 static int pci_acs_enable
;
2805 * pci_request_acs - ask for ACS to be enabled if supported
2807 void pci_request_acs(void)
2813 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2814 * @dev: the PCI device
2816 static void pci_std_enable_acs(struct pci_dev
*dev
)
2822 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
2826 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
2827 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2829 /* Source Validation */
2830 ctrl
|= (cap
& PCI_ACS_SV
);
2832 /* P2P Request Redirect */
2833 ctrl
|= (cap
& PCI_ACS_RR
);
2835 /* P2P Completion Redirect */
2836 ctrl
|= (cap
& PCI_ACS_CR
);
2838 /* Upstream Forwarding */
2839 ctrl
|= (cap
& PCI_ACS_UF
);
2841 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
2845 * pci_enable_acs - enable ACS if hardware support it
2846 * @dev: the PCI device
2848 void pci_enable_acs(struct pci_dev
*dev
)
2850 if (!pci_acs_enable
)
2853 if (!pci_dev_specific_enable_acs(dev
))
2856 pci_std_enable_acs(dev
);
2859 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2864 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ACS
);
2869 * Except for egress control, capabilities are either required
2870 * or only required if controllable. Features missing from the
2871 * capability field can therefore be assumed as hard-wired enabled.
2873 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
2874 acs_flags
&= (cap
| PCI_ACS_EC
);
2876 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
2877 return (ctrl
& acs_flags
) == acs_flags
;
2881 * pci_acs_enabled - test ACS against required flags for a given device
2882 * @pdev: device to test
2883 * @acs_flags: required PCI ACS flags
2885 * Return true if the device supports the provided flags. Automatically
2886 * filters out flags that are not implemented on multifunction devices.
2888 * Note that this interface checks the effective ACS capabilities of the
2889 * device rather than the actual capabilities. For instance, most single
2890 * function endpoints are not required to support ACS because they have no
2891 * opportunity for peer-to-peer access. We therefore return 'true'
2892 * regardless of whether the device exposes an ACS capability. This makes
2893 * it much easier for callers of this function to ignore the actual type
2894 * or topology of the device when testing ACS support.
2896 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
2900 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
2905 * Conventional PCI and PCI-X devices never support ACS, either
2906 * effectively or actually. The shared bus topology implies that
2907 * any device on the bus can receive or snoop DMA.
2909 if (!pci_is_pcie(pdev
))
2912 switch (pci_pcie_type(pdev
)) {
2914 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2915 * but since their primary interface is PCI/X, we conservatively
2916 * handle them as we would a non-PCIe device.
2918 case PCI_EXP_TYPE_PCIE_BRIDGE
:
2920 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2921 * applicable... must never implement an ACS Extended Capability...".
2922 * This seems arbitrary, but we take a conservative interpretation
2923 * of this statement.
2925 case PCI_EXP_TYPE_PCI_BRIDGE
:
2926 case PCI_EXP_TYPE_RC_EC
:
2929 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2930 * implement ACS in order to indicate their peer-to-peer capabilities,
2931 * regardless of whether they are single- or multi-function devices.
2933 case PCI_EXP_TYPE_DOWNSTREAM
:
2934 case PCI_EXP_TYPE_ROOT_PORT
:
2935 return pci_acs_flags_enabled(pdev
, acs_flags
);
2937 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2938 * implemented by the remaining PCIe types to indicate peer-to-peer
2939 * capabilities, but only when they are part of a multifunction
2940 * device. The footnote for section 6.12 indicates the specific
2941 * PCIe types included here.
2943 case PCI_EXP_TYPE_ENDPOINT
:
2944 case PCI_EXP_TYPE_UPSTREAM
:
2945 case PCI_EXP_TYPE_LEG_END
:
2946 case PCI_EXP_TYPE_RC_END
:
2947 if (!pdev
->multifunction
)
2950 return pci_acs_flags_enabled(pdev
, acs_flags
);
2954 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2955 * to single function devices with the exception of downstream ports.
2961 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2962 * @start: starting downstream device
2963 * @end: ending upstream device or NULL to search to the root bus
2964 * @acs_flags: required flags
2966 * Walk up a device tree from start to end testing PCI ACS support. If
2967 * any step along the way does not support the required flags, return false.
2969 bool pci_acs_path_enabled(struct pci_dev
*start
,
2970 struct pci_dev
*end
, u16 acs_flags
)
2972 struct pci_dev
*pdev
, *parent
= start
;
2977 if (!pci_acs_enabled(pdev
, acs_flags
))
2980 if (pci_is_root_bus(pdev
->bus
))
2981 return (end
== NULL
);
2983 parent
= pdev
->bus
->self
;
2984 } while (pdev
!= end
);
2990 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
2994 * Helper to find the position of the ctrl register for a BAR.
2995 * Returns -ENOTSUPP if resizable BARs are not supported at all.
2996 * Returns -ENOENT if no ctrl register for the BAR could be found.
2998 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3000 unsigned int pos
, nbars
, i
;
3003 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3007 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3008 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3009 PCI_REBAR_CTRL_NBAR_SHIFT
;
3011 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3014 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3015 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3024 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3026 * @bar: BAR to query
3028 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3029 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3031 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3036 pos
= pci_rebar_find_pos(pdev
, bar
);
3040 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3041 return (cap
& PCI_REBAR_CAP_SIZES
) >> 4;
3045 * pci_rebar_get_current_size - get the current size of a BAR
3047 * @bar: BAR to set size to
3049 * Read the size of a BAR from the resizable BAR config.
3050 * Returns size if found or negative error code.
3052 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3057 pos
= pci_rebar_find_pos(pdev
, bar
);
3061 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3062 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> 8;
3066 * pci_rebar_set_size - set a new size for a BAR
3068 * @bar: BAR to set size to
3069 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3071 * Set the new size of a BAR as defined in the spec.
3072 * Returns zero if resizing was successful, error code otherwise.
3074 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3079 pos
= pci_rebar_find_pos(pdev
, bar
);
3083 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3084 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3086 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3091 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3092 * @dev: the PCI device
3093 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3095 * Perform INTx swizzling for a device behind one level of bridge. This is
3096 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3097 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3098 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3099 * the PCI Express Base Specification, Revision 2.1)
3101 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3105 if (pci_ari_enabled(dev
->bus
))
3108 slot
= PCI_SLOT(dev
->devfn
);
3110 return (((pin
- 1) + slot
) % 4) + 1;
3113 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3121 while (!pci_is_root_bus(dev
->bus
)) {
3122 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3123 dev
= dev
->bus
->self
;
3130 * pci_common_swizzle - swizzle INTx all the way to root bridge
3131 * @dev: the PCI device
3132 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3134 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3135 * bridges all the way up to a PCI root bus.
3137 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3141 while (!pci_is_root_bus(dev
->bus
)) {
3142 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3143 dev
= dev
->bus
->self
;
3146 return PCI_SLOT(dev
->devfn
);
3148 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3151 * pci_release_region - Release a PCI bar
3152 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3153 * @bar: BAR to release
3155 * Releases the PCI I/O and memory resources previously reserved by a
3156 * successful call to pci_request_region. Call this function only
3157 * after all use of the PCI regions has ceased.
3159 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3161 struct pci_devres
*dr
;
3163 if (pci_resource_len(pdev
, bar
) == 0)
3165 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3166 release_region(pci_resource_start(pdev
, bar
),
3167 pci_resource_len(pdev
, bar
));
3168 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3169 release_mem_region(pci_resource_start(pdev
, bar
),
3170 pci_resource_len(pdev
, bar
));
3172 dr
= find_pci_dr(pdev
);
3174 dr
->region_mask
&= ~(1 << bar
);
3176 EXPORT_SYMBOL(pci_release_region
);
3179 * __pci_request_region - Reserved PCI I/O and memory resource
3180 * @pdev: PCI device whose resources are to be reserved
3181 * @bar: BAR to be reserved
3182 * @res_name: Name to be associated with resource.
3183 * @exclusive: whether the region access is exclusive or not
3185 * Mark the PCI region associated with PCI device @pdev BR @bar as
3186 * being reserved by owner @res_name. Do not access any
3187 * address inside the PCI regions unless this call returns
3190 * If @exclusive is set, then the region is marked so that userspace
3191 * is explicitly not allowed to map the resource via /dev/mem or
3192 * sysfs MMIO access.
3194 * Returns 0 on success, or %EBUSY on error. A warning
3195 * message is also printed on failure.
3197 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3198 const char *res_name
, int exclusive
)
3200 struct pci_devres
*dr
;
3202 if (pci_resource_len(pdev
, bar
) == 0)
3205 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3206 if (!request_region(pci_resource_start(pdev
, bar
),
3207 pci_resource_len(pdev
, bar
), res_name
))
3209 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3210 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3211 pci_resource_len(pdev
, bar
), res_name
,
3216 dr
= find_pci_dr(pdev
);
3218 dr
->region_mask
|= 1 << bar
;
3223 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %pR\n", bar
,
3224 &pdev
->resource
[bar
]);
3229 * pci_request_region - Reserve PCI I/O and memory resource
3230 * @pdev: PCI device whose resources are to be reserved
3231 * @bar: BAR to be reserved
3232 * @res_name: Name to be associated with resource
3234 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3235 * being reserved by owner @res_name. Do not access any
3236 * address inside the PCI regions unless this call returns
3239 * Returns 0 on success, or %EBUSY on error. A warning
3240 * message is also printed on failure.
3242 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3244 return __pci_request_region(pdev
, bar
, res_name
, 0);
3246 EXPORT_SYMBOL(pci_request_region
);
3249 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3250 * @pdev: PCI device whose resources are to be reserved
3251 * @bar: BAR to be reserved
3252 * @res_name: Name to be associated with resource.
3254 * Mark the PCI region associated with PCI device @pdev BR @bar as
3255 * being reserved by owner @res_name. Do not access any
3256 * address inside the PCI regions unless this call returns
3259 * Returns 0 on success, or %EBUSY on error. A warning
3260 * message is also printed on failure.
3262 * The key difference that _exclusive makes it that userspace is
3263 * explicitly not allowed to map the resource via /dev/mem or
3266 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
,
3267 const char *res_name
)
3269 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
3271 EXPORT_SYMBOL(pci_request_region_exclusive
);
3274 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3275 * @pdev: PCI device whose resources were previously reserved
3276 * @bars: Bitmask of BARs to be released
3278 * Release selected PCI I/O and memory resources previously reserved.
3279 * Call this function only after all use of the PCI regions has ceased.
3281 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
3285 for (i
= 0; i
< 6; i
++)
3286 if (bars
& (1 << i
))
3287 pci_release_region(pdev
, i
);
3289 EXPORT_SYMBOL(pci_release_selected_regions
);
3291 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3292 const char *res_name
, int excl
)
3296 for (i
= 0; i
< 6; i
++)
3297 if (bars
& (1 << i
))
3298 if (__pci_request_region(pdev
, i
, res_name
, excl
))
3304 if (bars
& (1 << i
))
3305 pci_release_region(pdev
, i
);
3312 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3313 * @pdev: PCI device whose resources are to be reserved
3314 * @bars: Bitmask of BARs to be requested
3315 * @res_name: Name to be associated with resource
3317 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3318 const char *res_name
)
3320 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
3322 EXPORT_SYMBOL(pci_request_selected_regions
);
3324 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
3325 const char *res_name
)
3327 return __pci_request_selected_regions(pdev
, bars
, res_name
,
3328 IORESOURCE_EXCLUSIVE
);
3330 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
3333 * pci_release_regions - Release reserved PCI I/O and memory resources
3334 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3336 * Releases all PCI I/O and memory resources previously reserved by a
3337 * successful call to pci_request_regions. Call this function only
3338 * after all use of the PCI regions has ceased.
3341 void pci_release_regions(struct pci_dev
*pdev
)
3343 pci_release_selected_regions(pdev
, (1 << 6) - 1);
3345 EXPORT_SYMBOL(pci_release_regions
);
3348 * pci_request_regions - Reserved PCI I/O and memory resources
3349 * @pdev: PCI device whose resources are to be reserved
3350 * @res_name: Name to be associated with resource.
3352 * Mark all PCI regions associated with PCI device @pdev as
3353 * being reserved by owner @res_name. Do not access any
3354 * address inside the PCI regions unless this call returns
3357 * Returns 0 on success, or %EBUSY on error. A warning
3358 * message is also printed on failure.
3360 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
3362 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
3364 EXPORT_SYMBOL(pci_request_regions
);
3367 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3368 * @pdev: PCI device whose resources are to be reserved
3369 * @res_name: Name to be associated with resource.
3371 * Mark all PCI regions associated with PCI device @pdev as
3372 * being reserved by owner @res_name. Do not access any
3373 * address inside the PCI regions unless this call returns
3376 * pci_request_regions_exclusive() will mark the region so that
3377 * /dev/mem and the sysfs MMIO access will not be allowed.
3379 * Returns 0 on success, or %EBUSY on error. A warning
3380 * message is also printed on failure.
3382 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
3384 return pci_request_selected_regions_exclusive(pdev
,
3385 ((1 << 6) - 1), res_name
);
3387 EXPORT_SYMBOL(pci_request_regions_exclusive
);
3390 * Record the PCI IO range (expressed as CPU physical address + size).
3391 * Return a negative value if an error has occured, zero otherwise
3393 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
3394 resource_size_t size
)
3398 struct logic_pio_hwaddr
*range
;
3400 if (!size
|| addr
+ size
< addr
)
3403 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
3407 range
->fwnode
= fwnode
;
3409 range
->hw_start
= addr
;
3410 range
->flags
= LOGIC_PIO_CPU_MMIO
;
3412 ret
= logic_pio_register_range(range
);
3420 phys_addr_t
pci_pio_to_address(unsigned long pio
)
3422 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
3425 if (pio
>= MMIO_UPPER_LIMIT
)
3428 address
= logic_pio_to_hwaddr(pio
);
3434 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
3437 return logic_pio_trans_cpuaddr(address
);
3439 if (address
> IO_SPACE_LIMIT
)
3440 return (unsigned long)-1;
3442 return (unsigned long) address
;
3447 * pci_remap_iospace - Remap the memory mapped I/O space
3448 * @res: Resource describing the I/O space
3449 * @phys_addr: physical address of range to be mapped
3451 * Remap the memory mapped I/O space described by the @res
3452 * and the CPU physical address @phys_addr into virtual address space.
3453 * Only architectures that have memory mapped IO functions defined
3454 * (and the PCI_IOBASE value defined) should call this function.
3456 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
3458 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3459 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3461 if (!(res
->flags
& IORESOURCE_IO
))
3464 if (res
->end
> IO_SPACE_LIMIT
)
3467 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
3468 pgprot_device(PAGE_KERNEL
));
3470 /* this architecture does not have memory mapped I/O space,
3471 so this function should never be called */
3472 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3476 EXPORT_SYMBOL(pci_remap_iospace
);
3479 * pci_unmap_iospace - Unmap the memory mapped I/O space
3480 * @res: resource to be unmapped
3482 * Unmap the CPU virtual address @res from virtual address space.
3483 * Only architectures that have memory mapped IO functions defined
3484 * (and the PCI_IOBASE value defined) should call this function.
3486 void pci_unmap_iospace(struct resource
*res
)
3488 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3489 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
3491 unmap_kernel_range(vaddr
, resource_size(res
));
3494 EXPORT_SYMBOL(pci_unmap_iospace
);
3497 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3498 * @dev: Generic device to remap IO address for
3499 * @offset: Resource address to map
3500 * @size: Size of map
3502 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3505 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
3506 resource_size_t offset
,
3507 resource_size_t size
)
3509 void __iomem
**ptr
, *addr
;
3511 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
3515 addr
= pci_remap_cfgspace(offset
, size
);
3518 devres_add(dev
, ptr
);
3524 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
3527 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3528 * @dev: generic device to handle the resource for
3529 * @res: configuration space resource to be handled
3531 * Checks that a resource is a valid memory region, requests the memory
3532 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3533 * proper PCI configuration space memory attributes are guaranteed.
3535 * All operations are managed and will be undone on driver detach.
3537 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3538 * on failure. Usage example::
3540 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3541 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3543 * return PTR_ERR(base);
3545 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
3546 struct resource
*res
)
3548 resource_size_t size
;
3550 void __iomem
*dest_ptr
;
3554 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
3555 dev_err(dev
, "invalid resource\n");
3556 return IOMEM_ERR_PTR(-EINVAL
);
3559 size
= resource_size(res
);
3560 name
= res
->name
?: dev_name(dev
);
3562 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
3563 dev_err(dev
, "can't request region for resource %pR\n", res
);
3564 return IOMEM_ERR_PTR(-EBUSY
);
3567 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
3569 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
3570 devm_release_mem_region(dev
, res
->start
, size
);
3571 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
3576 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
3578 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
3582 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
3584 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
3586 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
3587 if (cmd
!= old_cmd
) {
3588 dev_dbg(&dev
->dev
, "%s bus mastering\n",
3589 enable
? "enabling" : "disabling");
3590 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3592 dev
->is_busmaster
= enable
;
3596 * pcibios_setup - process "pci=" kernel boot arguments
3597 * @str: string used to pass in "pci=" kernel boot arguments
3599 * Process kernel boot arguments. This is the default implementation.
3600 * Architecture specific implementations can override this as necessary.
3602 char * __weak __init
pcibios_setup(char *str
)
3608 * pcibios_set_master - enable PCI bus-mastering for device dev
3609 * @dev: the PCI device to enable
3611 * Enables PCI bus-mastering for the device. This is the default
3612 * implementation. Architecture specific implementations can override
3613 * this if necessary.
3615 void __weak
pcibios_set_master(struct pci_dev
*dev
)
3619 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3620 if (pci_is_pcie(dev
))
3623 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
3625 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
3626 else if (lat
> pcibios_max_latency
)
3627 lat
= pcibios_max_latency
;
3631 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
3635 * pci_set_master - enables bus-mastering for device dev
3636 * @dev: the PCI device to enable
3638 * Enables bus-mastering on the device and calls pcibios_set_master()
3639 * to do the needed arch specific settings.
3641 void pci_set_master(struct pci_dev
*dev
)
3643 __pci_set_master(dev
, true);
3644 pcibios_set_master(dev
);
3646 EXPORT_SYMBOL(pci_set_master
);
3649 * pci_clear_master - disables bus-mastering for device dev
3650 * @dev: the PCI device to disable
3652 void pci_clear_master(struct pci_dev
*dev
)
3654 __pci_set_master(dev
, false);
3656 EXPORT_SYMBOL(pci_clear_master
);
3659 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3660 * @dev: the PCI device for which MWI is to be enabled
3662 * Helper function for pci_set_mwi.
3663 * Originally copied from drivers/net/acenic.c.
3664 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3666 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3668 int pci_set_cacheline_size(struct pci_dev
*dev
)
3672 if (!pci_cache_line_size
)
3675 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3676 equal to or multiple of the right value. */
3677 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3678 if (cacheline_size
>= pci_cache_line_size
&&
3679 (cacheline_size
% pci_cache_line_size
) == 0)
3682 /* Write the correct value. */
3683 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
3685 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
3686 if (cacheline_size
== pci_cache_line_size
)
3689 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not supported\n",
3690 pci_cache_line_size
<< 2);
3694 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
3697 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3698 * @dev: the PCI device for which MWI is enabled
3700 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3702 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3704 int pci_set_mwi(struct pci_dev
*dev
)
3706 #ifdef PCI_DISABLE_MWI
3712 rc
= pci_set_cacheline_size(dev
);
3716 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3717 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
3718 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
3719 cmd
|= PCI_COMMAND_INVALIDATE
;
3720 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3725 EXPORT_SYMBOL(pci_set_mwi
);
3728 * pcim_set_mwi - a device-managed pci_set_mwi()
3729 * @dev: the PCI device for which MWI is enabled
3731 * Managed pci_set_mwi().
3733 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3735 int pcim_set_mwi(struct pci_dev
*dev
)
3737 struct pci_devres
*dr
;
3739 dr
= find_pci_dr(dev
);
3744 return pci_set_mwi(dev
);
3746 EXPORT_SYMBOL(pcim_set_mwi
);
3749 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3750 * @dev: the PCI device for which MWI is enabled
3752 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3753 * Callers are not required to check the return value.
3755 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3757 int pci_try_set_mwi(struct pci_dev
*dev
)
3759 #ifdef PCI_DISABLE_MWI
3762 return pci_set_mwi(dev
);
3765 EXPORT_SYMBOL(pci_try_set_mwi
);
3768 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3769 * @dev: the PCI device to disable
3771 * Disables PCI Memory-Write-Invalidate transaction on the device
3773 void pci_clear_mwi(struct pci_dev
*dev
)
3775 #ifndef PCI_DISABLE_MWI
3778 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
3779 if (cmd
& PCI_COMMAND_INVALIDATE
) {
3780 cmd
&= ~PCI_COMMAND_INVALIDATE
;
3781 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
3785 EXPORT_SYMBOL(pci_clear_mwi
);
3788 * pci_intx - enables/disables PCI INTx for device dev
3789 * @pdev: the PCI device to operate on
3790 * @enable: boolean: whether to enable or disable PCI INTx
3792 * Enables/disables PCI INTx for device dev
3794 void pci_intx(struct pci_dev
*pdev
, int enable
)
3796 u16 pci_command
, new;
3798 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
3801 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
3803 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
3805 if (new != pci_command
) {
3806 struct pci_devres
*dr
;
3808 pci_write_config_word(pdev
, PCI_COMMAND
, new);
3810 dr
= find_pci_dr(pdev
);
3811 if (dr
&& !dr
->restore_intx
) {
3812 dr
->restore_intx
= 1;
3813 dr
->orig_intx
= !enable
;
3817 EXPORT_SYMBOL_GPL(pci_intx
);
3819 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
3821 struct pci_bus
*bus
= dev
->bus
;
3822 bool mask_updated
= true;
3823 u32 cmd_status_dword
;
3824 u16 origcmd
, newcmd
;
3825 unsigned long flags
;
3829 * We do a single dword read to retrieve both command and status.
3830 * Document assumptions that make this possible.
3832 BUILD_BUG_ON(PCI_COMMAND
% 4);
3833 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
3835 raw_spin_lock_irqsave(&pci_lock
, flags
);
3837 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
3839 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
3842 * Check interrupt status register to see whether our device
3843 * triggered the interrupt (when masking) or the next IRQ is
3844 * already pending (when unmasking).
3846 if (mask
!= irq_pending
) {
3847 mask_updated
= false;
3851 origcmd
= cmd_status_dword
;
3852 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
3854 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
3855 if (newcmd
!= origcmd
)
3856 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
3859 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
3861 return mask_updated
;
3865 * pci_check_and_mask_intx - mask INTx on pending interrupt
3866 * @dev: the PCI device to operate on
3868 * Check if the device dev has its INTx line asserted, mask it and
3869 * return true in that case. False is returned if no interrupt was
3872 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
3874 return pci_check_and_set_intx_mask(dev
, true);
3876 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
3879 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3880 * @dev: the PCI device to operate on
3882 * Check if the device dev has its INTx line asserted, unmask it if not
3883 * and return true. False is returned and the mask remains active if
3884 * there was still an interrupt pending.
3886 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
3888 return pci_check_and_set_intx_mask(dev
, false);
3890 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
3893 * pci_wait_for_pending_transaction - waits for pending transaction
3894 * @dev: the PCI device to operate on
3896 * Return 0 if transaction is pending 1 otherwise.
3898 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
3900 if (!pci_is_pcie(dev
))
3903 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
3904 PCI_EXP_DEVSTA_TRPND
);
3906 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
3908 static void pci_flr_wait(struct pci_dev
*dev
)
3910 int delay
= 1, timeout
= 60000;
3914 * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
3915 * 100ms, but may silently discard requests while the FLR is in
3916 * progress. Wait 100ms before trying to access the device.
3921 * After 100ms, the device should not silently discard config
3922 * requests, but it may still indicate that it needs more time by
3923 * responding to them with CRS completions. The Root Port will
3924 * generally synthesize ~0 data to complete the read (except when
3925 * CRS SV is enabled and the read was for the Vendor ID; in that
3926 * case it synthesizes 0x0001 data).
3928 * Wait for the device to return a non-CRS completion. Read the
3929 * Command register instead of Vendor ID so we don't have to
3930 * contend with the CRS SV value.
3932 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3934 if (delay
> timeout
) {
3935 dev_warn(&dev
->dev
, "not ready %dms after FLR; giving up\n",
3941 dev_info(&dev
->dev
, "not ready %dms after FLR; waiting\n",
3946 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
3950 dev_info(&dev
->dev
, "ready %dms after FLR\n", 100 + delay
- 1);
3954 * pcie_has_flr - check if a device supports function level resets
3955 * @dev: device to check
3957 * Returns true if the device advertises support for PCIe function level
3960 static bool pcie_has_flr(struct pci_dev
*dev
)
3964 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
3967 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
3968 return cap
& PCI_EXP_DEVCAP_FLR
;
3972 * pcie_flr - initiate a PCIe function level reset
3973 * @dev: device to reset
3975 * Initiate a function level reset on @dev. The caller should ensure the
3976 * device supports FLR before calling this function, e.g. by using the
3977 * pcie_has_flr() helper.
3979 void pcie_flr(struct pci_dev
*dev
)
3981 if (!pci_wait_for_pending_transaction(dev
))
3982 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
3984 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
3987 EXPORT_SYMBOL_GPL(pcie_flr
);
3989 static int pci_af_flr(struct pci_dev
*dev
, int probe
)
3994 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
3998 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4001 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4002 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4009 * Wait for Transaction Pending bit to clear. A word-aligned test
4010 * is used, so we use the conrol offset rather than status and shift
4011 * the test bit to match.
4013 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4014 PCI_AF_STATUS_TP
<< 8))
4015 dev_err(&dev
->dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4017 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4023 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4024 * @dev: Device to reset.
4025 * @probe: If set, only check if the device can be reset this way.
4027 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4028 * unset, it will be reinitialized internally when going from PCI_D3hot to
4029 * PCI_D0. If that's the case and the device is not in a low-power state
4030 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4032 * NOTE: This causes the caller to sleep for twice the device power transition
4033 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4034 * by default (i.e. unless the @dev's d3_delay field has a different value).
4035 * Moreover, only devices in D0 can be reset by this function.
4037 static int pci_pm_reset(struct pci_dev
*dev
, int probe
)
4041 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4044 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4045 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4051 if (dev
->current_state
!= PCI_D0
)
4054 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4056 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4057 pci_dev_d3_sleep(dev
);
4059 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4061 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4062 pci_dev_d3_sleep(dev
);
4067 void pci_reset_secondary_bus(struct pci_dev
*dev
)
4071 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
4072 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
4073 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4075 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4076 * this to 2ms to ensure that we meet the minimum requirement.
4080 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
4081 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
4084 * Trhfa for conventional PCI is 2^25 clock cycles.
4085 * Assuming a minimum 33MHz clock this results in a 1s
4086 * delay before we can consider subordinate devices to
4087 * be re-initialized. PCIe has some ways to shorten this,
4088 * but we don't make use of them yet.
4093 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
4095 pci_reset_secondary_bus(dev
);
4099 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4100 * @dev: Bridge device
4102 * Use the bridge control register to assert reset on the secondary bus.
4103 * Devices on the secondary bus are left in power-on state.
4105 void pci_reset_bridge_secondary_bus(struct pci_dev
*dev
)
4107 pcibios_reset_secondary_bus(dev
);
4109 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus
);
4111 static int pci_parent_bus_reset(struct pci_dev
*dev
, int probe
)
4113 struct pci_dev
*pdev
;
4115 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
4116 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4119 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4126 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
4131 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, int probe
)
4135 if (!hotplug
|| !try_module_get(hotplug
->ops
->owner
))
4138 if (hotplug
->ops
->reset_slot
)
4139 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
4141 module_put(hotplug
->ops
->owner
);
4146 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, int probe
)
4148 struct pci_dev
*pdev
;
4150 if (dev
->subordinate
|| !dev
->slot
||
4151 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
4154 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
4155 if (pdev
!= dev
&& pdev
->slot
== dev
->slot
)
4158 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
4161 static void pci_dev_lock(struct pci_dev
*dev
)
4163 pci_cfg_access_lock(dev
);
4164 /* block PM suspend, driver probe, etc. */
4165 device_lock(&dev
->dev
);
4168 /* Return 1 on successful lock, 0 on contention */
4169 static int pci_dev_trylock(struct pci_dev
*dev
)
4171 if (pci_cfg_access_trylock(dev
)) {
4172 if (device_trylock(&dev
->dev
))
4174 pci_cfg_access_unlock(dev
);
4180 static void pci_dev_unlock(struct pci_dev
*dev
)
4182 device_unlock(&dev
->dev
);
4183 pci_cfg_access_unlock(dev
);
4186 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
4188 const struct pci_error_handlers
*err_handler
=
4189 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4192 * dev->driver->err_handler->reset_prepare() is protected against
4193 * races with ->remove() by the device lock, which must be held by
4196 if (err_handler
&& err_handler
->reset_prepare
)
4197 err_handler
->reset_prepare(dev
);
4200 * Wake-up device prior to save. PM registers default to D0 after
4201 * reset and a simple register restore doesn't reliably return
4202 * to a non-D0 state anyway.
4204 pci_set_power_state(dev
, PCI_D0
);
4206 pci_save_state(dev
);
4208 * Disable the device by clearing the Command register, except for
4209 * INTx-disable which is set. This not only disables MMIO and I/O port
4210 * BARs, but also prevents the device from being Bus Master, preventing
4211 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4212 * compliant devices, INTx-disable prevents legacy interrupts.
4214 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
4217 static void pci_dev_restore(struct pci_dev
*dev
)
4219 const struct pci_error_handlers
*err_handler
=
4220 dev
->driver
? dev
->driver
->err_handler
: NULL
;
4222 pci_restore_state(dev
);
4225 * dev->driver->err_handler->reset_done() is protected against
4226 * races with ->remove() by the device lock, which must be held by
4229 if (err_handler
&& err_handler
->reset_done
)
4230 err_handler
->reset_done(dev
);
4234 * __pci_reset_function_locked - reset a PCI device function while holding
4235 * the @dev mutex lock.
4236 * @dev: PCI device to reset
4238 * Some devices allow an individual function to be reset without affecting
4239 * other functions in the same device. The PCI device must be responsive
4240 * to PCI config space in order to use this function.
4242 * The device function is presumed to be unused and the caller is holding
4243 * the device mutex lock when this function is called.
4244 * Resetting the device will make the contents of PCI configuration space
4245 * random, so any caller of this must be prepared to reinitialise the
4246 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4249 * Returns 0 if the device function was successfully reset or negative if the
4250 * device doesn't support resetting a single function.
4252 int __pci_reset_function_locked(struct pci_dev
*dev
)
4259 * A reset method returns -ENOTTY if it doesn't support this device
4260 * and we should try the next method.
4262 * If it returns 0 (success), we're finished. If it returns any
4263 * other error, we're also finished: this indicates that further
4264 * reset mechanisms might be broken on the device.
4266 rc
= pci_dev_specific_reset(dev
, 0);
4269 if (pcie_has_flr(dev
)) {
4273 rc
= pci_af_flr(dev
, 0);
4276 rc
= pci_pm_reset(dev
, 0);
4279 rc
= pci_dev_reset_slot_function(dev
, 0);
4282 return pci_parent_bus_reset(dev
, 0);
4284 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
4287 * pci_probe_reset_function - check whether the device can be safely reset
4288 * @dev: PCI device to reset
4290 * Some devices allow an individual function to be reset without affecting
4291 * other functions in the same device. The PCI device must be responsive
4292 * to PCI config space in order to use this function.
4294 * Returns 0 if the device function can be reset or negative if the
4295 * device doesn't support resetting a single function.
4297 int pci_probe_reset_function(struct pci_dev
*dev
)
4303 rc
= pci_dev_specific_reset(dev
, 1);
4306 if (pcie_has_flr(dev
))
4308 rc
= pci_af_flr(dev
, 1);
4311 rc
= pci_pm_reset(dev
, 1);
4314 rc
= pci_dev_reset_slot_function(dev
, 1);
4318 return pci_parent_bus_reset(dev
, 1);
4322 * pci_reset_function - quiesce and reset a PCI device function
4323 * @dev: PCI device to reset
4325 * Some devices allow an individual function to be reset without affecting
4326 * other functions in the same device. The PCI device must be responsive
4327 * to PCI config space in order to use this function.
4329 * This function does not just reset the PCI portion of a device, but
4330 * clears all the state associated with the device. This function differs
4331 * from __pci_reset_function_locked() in that it saves and restores device state
4332 * over the reset and takes the PCI device lock.
4334 * Returns 0 if the device function was successfully reset or negative if the
4335 * device doesn't support resetting a single function.
4337 int pci_reset_function(struct pci_dev
*dev
)
4341 rc
= pci_probe_reset_function(dev
);
4346 pci_dev_save_and_disable(dev
);
4348 rc
= __pci_reset_function_locked(dev
);
4350 pci_dev_restore(dev
);
4351 pci_dev_unlock(dev
);
4355 EXPORT_SYMBOL_GPL(pci_reset_function
);
4358 * pci_reset_function_locked - quiesce and reset a PCI device function
4359 * @dev: PCI device to reset
4361 * Some devices allow an individual function to be reset without affecting
4362 * other functions in the same device. The PCI device must be responsive
4363 * to PCI config space in order to use this function.
4365 * This function does not just reset the PCI portion of a device, but
4366 * clears all the state associated with the device. This function differs
4367 * from __pci_reset_function_locked() in that it saves and restores device state
4368 * over the reset. It also differs from pci_reset_function() in that it
4369 * requires the PCI device lock to be held.
4371 * Returns 0 if the device function was successfully reset or negative if the
4372 * device doesn't support resetting a single function.
4374 int pci_reset_function_locked(struct pci_dev
*dev
)
4378 rc
= pci_probe_reset_function(dev
);
4382 pci_dev_save_and_disable(dev
);
4384 rc
= __pci_reset_function_locked(dev
);
4386 pci_dev_restore(dev
);
4390 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
4393 * pci_try_reset_function - quiesce and reset a PCI device function
4394 * @dev: PCI device to reset
4396 * Same as above, except return -EAGAIN if unable to lock device.
4398 int pci_try_reset_function(struct pci_dev
*dev
)
4402 rc
= pci_probe_reset_function(dev
);
4406 if (!pci_dev_trylock(dev
))
4409 pci_dev_save_and_disable(dev
);
4410 rc
= __pci_reset_function_locked(dev
);
4411 pci_dev_unlock(dev
);
4413 pci_dev_restore(dev
);
4416 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
4418 /* Do any devices on or below this bus prevent a bus reset? */
4419 static bool pci_bus_resetable(struct pci_bus
*bus
)
4421 struct pci_dev
*dev
;
4424 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4427 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4428 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4429 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4436 /* Lock devices from the top of the tree down */
4437 static void pci_bus_lock(struct pci_bus
*bus
)
4439 struct pci_dev
*dev
;
4441 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4443 if (dev
->subordinate
)
4444 pci_bus_lock(dev
->subordinate
);
4448 /* Unlock devices from the bottom of the tree up */
4449 static void pci_bus_unlock(struct pci_bus
*bus
)
4451 struct pci_dev
*dev
;
4453 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4454 if (dev
->subordinate
)
4455 pci_bus_unlock(dev
->subordinate
);
4456 pci_dev_unlock(dev
);
4460 /* Return 1 on successful lock, 0 on contention */
4461 static int pci_bus_trylock(struct pci_bus
*bus
)
4463 struct pci_dev
*dev
;
4465 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4466 if (!pci_dev_trylock(dev
))
4468 if (dev
->subordinate
) {
4469 if (!pci_bus_trylock(dev
->subordinate
)) {
4470 pci_dev_unlock(dev
);
4478 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
4479 if (dev
->subordinate
)
4480 pci_bus_unlock(dev
->subordinate
);
4481 pci_dev_unlock(dev
);
4486 /* Do any devices on or below this slot prevent a bus reset? */
4487 static bool pci_slot_resetable(struct pci_slot
*slot
)
4489 struct pci_dev
*dev
;
4491 if (slot
->bus
->self
&&
4492 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
4495 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4496 if (!dev
->slot
|| dev
->slot
!= slot
)
4498 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
4499 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
4506 /* Lock devices from the top of the tree down */
4507 static void pci_slot_lock(struct pci_slot
*slot
)
4509 struct pci_dev
*dev
;
4511 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4512 if (!dev
->slot
|| dev
->slot
!= slot
)
4515 if (dev
->subordinate
)
4516 pci_bus_lock(dev
->subordinate
);
4520 /* Unlock devices from the bottom of the tree up */
4521 static void pci_slot_unlock(struct pci_slot
*slot
)
4523 struct pci_dev
*dev
;
4525 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4526 if (!dev
->slot
|| dev
->slot
!= slot
)
4528 if (dev
->subordinate
)
4529 pci_bus_unlock(dev
->subordinate
);
4530 pci_dev_unlock(dev
);
4534 /* Return 1 on successful lock, 0 on contention */
4535 static int pci_slot_trylock(struct pci_slot
*slot
)
4537 struct pci_dev
*dev
;
4539 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4540 if (!dev
->slot
|| dev
->slot
!= slot
)
4542 if (!pci_dev_trylock(dev
))
4544 if (dev
->subordinate
) {
4545 if (!pci_bus_trylock(dev
->subordinate
)) {
4546 pci_dev_unlock(dev
);
4554 list_for_each_entry_continue_reverse(dev
,
4555 &slot
->bus
->devices
, bus_list
) {
4556 if (!dev
->slot
|| dev
->slot
!= slot
)
4558 if (dev
->subordinate
)
4559 pci_bus_unlock(dev
->subordinate
);
4560 pci_dev_unlock(dev
);
4565 /* Save and disable devices from the top of the tree down */
4566 static void pci_bus_save_and_disable(struct pci_bus
*bus
)
4568 struct pci_dev
*dev
;
4570 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4572 pci_dev_save_and_disable(dev
);
4573 pci_dev_unlock(dev
);
4574 if (dev
->subordinate
)
4575 pci_bus_save_and_disable(dev
->subordinate
);
4580 * Restore devices from top of the tree down - parent bridges need to be
4581 * restored before we can get to subordinate devices.
4583 static void pci_bus_restore(struct pci_bus
*bus
)
4585 struct pci_dev
*dev
;
4587 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
4589 pci_dev_restore(dev
);
4590 pci_dev_unlock(dev
);
4591 if (dev
->subordinate
)
4592 pci_bus_restore(dev
->subordinate
);
4596 /* Save and disable devices from the top of the tree down */
4597 static void pci_slot_save_and_disable(struct pci_slot
*slot
)
4599 struct pci_dev
*dev
;
4601 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4602 if (!dev
->slot
|| dev
->slot
!= slot
)
4604 pci_dev_save_and_disable(dev
);
4605 if (dev
->subordinate
)
4606 pci_bus_save_and_disable(dev
->subordinate
);
4611 * Restore devices from top of the tree down - parent bridges need to be
4612 * restored before we can get to subordinate devices.
4614 static void pci_slot_restore(struct pci_slot
*slot
)
4616 struct pci_dev
*dev
;
4618 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
4619 if (!dev
->slot
|| dev
->slot
!= slot
)
4621 pci_dev_restore(dev
);
4622 if (dev
->subordinate
)
4623 pci_bus_restore(dev
->subordinate
);
4627 static int pci_slot_reset(struct pci_slot
*slot
, int probe
)
4631 if (!slot
|| !pci_slot_resetable(slot
))
4635 pci_slot_lock(slot
);
4639 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
4642 pci_slot_unlock(slot
);
4648 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4649 * @slot: PCI slot to probe
4651 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4653 int pci_probe_reset_slot(struct pci_slot
*slot
)
4655 return pci_slot_reset(slot
, 1);
4657 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
4660 * pci_reset_slot - reset a PCI slot
4661 * @slot: PCI slot to reset
4663 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4664 * independent of other slots. For instance, some slots may support slot power
4665 * control. In the case of a 1:1 bus to slot architecture, this function may
4666 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4667 * Generally a slot reset should be attempted before a bus reset. All of the
4668 * function of the slot and any subordinate buses behind the slot are reset
4669 * through this function. PCI config space of all devices in the slot and
4670 * behind the slot is saved before and restored after reset.
4672 * Return 0 on success, non-zero on error.
4674 int pci_reset_slot(struct pci_slot
*slot
)
4678 rc
= pci_slot_reset(slot
, 1);
4682 pci_slot_save_and_disable(slot
);
4684 rc
= pci_slot_reset(slot
, 0);
4686 pci_slot_restore(slot
);
4690 EXPORT_SYMBOL_GPL(pci_reset_slot
);
4693 * pci_try_reset_slot - Try to reset a PCI slot
4694 * @slot: PCI slot to reset
4696 * Same as above except return -EAGAIN if the slot cannot be locked
4698 int pci_try_reset_slot(struct pci_slot
*slot
)
4702 rc
= pci_slot_reset(slot
, 1);
4706 pci_slot_save_and_disable(slot
);
4708 if (pci_slot_trylock(slot
)) {
4710 rc
= pci_reset_hotplug_slot(slot
->hotplug
, 0);
4711 pci_slot_unlock(slot
);
4715 pci_slot_restore(slot
);
4719 EXPORT_SYMBOL_GPL(pci_try_reset_slot
);
4721 static int pci_bus_reset(struct pci_bus
*bus
, int probe
)
4723 if (!bus
->self
|| !pci_bus_resetable(bus
))
4733 pci_reset_bridge_secondary_bus(bus
->self
);
4735 pci_bus_unlock(bus
);
4741 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4742 * @bus: PCI bus to probe
4744 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4746 int pci_probe_reset_bus(struct pci_bus
*bus
)
4748 return pci_bus_reset(bus
, 1);
4750 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
4753 * pci_reset_bus - reset a PCI bus
4754 * @bus: top level PCI bus to reset
4756 * Do a bus reset on the given bus and any subordinate buses, saving
4757 * and restoring state of all devices.
4759 * Return 0 on success, non-zero on error.
4761 int pci_reset_bus(struct pci_bus
*bus
)
4765 rc
= pci_bus_reset(bus
, 1);
4769 pci_bus_save_and_disable(bus
);
4771 rc
= pci_bus_reset(bus
, 0);
4773 pci_bus_restore(bus
);
4777 EXPORT_SYMBOL_GPL(pci_reset_bus
);
4780 * pci_try_reset_bus - Try to reset a PCI bus
4781 * @bus: top level PCI bus to reset
4783 * Same as above except return -EAGAIN if the bus cannot be locked
4785 int pci_try_reset_bus(struct pci_bus
*bus
)
4789 rc
= pci_bus_reset(bus
, 1);
4793 pci_bus_save_and_disable(bus
);
4795 if (pci_bus_trylock(bus
)) {
4797 pci_reset_bridge_secondary_bus(bus
->self
);
4798 pci_bus_unlock(bus
);
4802 pci_bus_restore(bus
);
4806 EXPORT_SYMBOL_GPL(pci_try_reset_bus
);
4809 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4810 * @dev: PCI device to query
4812 * Returns mmrbc: maximum designed memory read count in bytes
4813 * or appropriate error value.
4815 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
4820 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4824 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4827 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
4829 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
4832 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4833 * @dev: PCI device to query
4835 * Returns mmrbc: maximum memory read count in bytes
4836 * or appropriate error value.
4838 int pcix_get_mmrbc(struct pci_dev
*dev
)
4843 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4847 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4850 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
4852 EXPORT_SYMBOL(pcix_get_mmrbc
);
4855 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4856 * @dev: PCI device to query
4857 * @mmrbc: maximum memory read count in bytes
4858 * valid values are 512, 1024, 2048, 4096
4860 * If possible sets maximum memory read byte count, some bridges have erratas
4861 * that prevent this.
4863 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
4869 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
4872 v
= ffs(mmrbc
) - 10;
4874 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
4878 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
4881 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
4884 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
4887 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
4889 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
4892 cmd
&= ~PCI_X_CMD_MAX_READ
;
4894 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
4899 EXPORT_SYMBOL(pcix_set_mmrbc
);
4902 * pcie_get_readrq - get PCI Express read request size
4903 * @dev: PCI device to query
4905 * Returns maximum memory read request in bytes
4906 * or appropriate error value.
4908 int pcie_get_readrq(struct pci_dev
*dev
)
4912 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4914 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
4916 EXPORT_SYMBOL(pcie_get_readrq
);
4919 * pcie_set_readrq - set PCI Express maximum memory read request
4920 * @dev: PCI device to query
4921 * @rq: maximum memory read count in bytes
4922 * valid values are 128, 256, 512, 1024, 2048, 4096
4924 * If possible sets maximum memory read request in bytes
4926 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
4930 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
4934 * If using the "performance" PCIe config, we clamp the
4935 * read rq size to the max packet size to prevent the
4936 * host bridge generating requests larger than we can
4939 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
4940 int mps
= pcie_get_mps(dev
);
4946 v
= (ffs(rq
) - 8) << 12;
4948 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4949 PCI_EXP_DEVCTL_READRQ
, v
);
4951 EXPORT_SYMBOL(pcie_set_readrq
);
4954 * pcie_get_mps - get PCI Express maximum payload size
4955 * @dev: PCI device to query
4957 * Returns maximum payload size in bytes
4959 int pcie_get_mps(struct pci_dev
*dev
)
4963 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
4965 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
4967 EXPORT_SYMBOL(pcie_get_mps
);
4970 * pcie_set_mps - set PCI Express maximum payload size
4971 * @dev: PCI device to query
4972 * @mps: maximum payload size in bytes
4973 * valid values are 128, 256, 512, 1024, 2048, 4096
4975 * If possible sets maximum payload size
4977 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
4981 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
4985 if (v
> dev
->pcie_mpss
)
4989 return pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
4990 PCI_EXP_DEVCTL_PAYLOAD
, v
);
4992 EXPORT_SYMBOL(pcie_set_mps
);
4995 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4996 * @dev: PCI device to query
4997 * @speed: storage for minimum speed
4998 * @width: storage for minimum width
5000 * This function will walk up the PCI device chain and determine the minimum
5001 * link width and speed of the device.
5003 int pcie_get_minimum_link(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
5004 enum pcie_link_width
*width
)
5008 *speed
= PCI_SPEED_UNKNOWN
;
5009 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
5013 enum pci_bus_speed next_speed
;
5014 enum pcie_link_width next_width
;
5016 ret
= pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
5020 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
5021 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
5022 PCI_EXP_LNKSTA_NLW_SHIFT
;
5024 if (next_speed
< *speed
)
5025 *speed
= next_speed
;
5027 if (next_width
< *width
)
5028 *width
= next_width
;
5030 dev
= dev
->bus
->self
;
5035 EXPORT_SYMBOL(pcie_get_minimum_link
);
5038 * pci_select_bars - Make BAR mask from the type of resource
5039 * @dev: the PCI device for which BAR mask is made
5040 * @flags: resource type mask to be selected
5042 * This helper routine makes bar mask from the type of resource.
5044 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
5047 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
5048 if (pci_resource_flags(dev
, i
) & flags
)
5052 EXPORT_SYMBOL(pci_select_bars
);
5054 /* Some architectures require additional programming to enable VGA */
5055 static arch_set_vga_state_t arch_set_vga_state
;
5057 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
5059 arch_set_vga_state
= func
; /* NULL disables */
5062 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
5063 unsigned int command_bits
, u32 flags
)
5065 if (arch_set_vga_state
)
5066 return arch_set_vga_state(dev
, decode
, command_bits
,
5072 * pci_set_vga_state - set VGA decode state on device and parents if requested
5073 * @dev: the PCI device
5074 * @decode: true = enable decoding, false = disable decoding
5075 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5076 * @flags: traverse ancestors and change bridges
5077 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5079 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
5080 unsigned int command_bits
, u32 flags
)
5082 struct pci_bus
*bus
;
5083 struct pci_dev
*bridge
;
5087 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
5089 /* ARCH specific VGA enables */
5090 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
5094 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
5095 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
5097 cmd
|= command_bits
;
5099 cmd
&= ~command_bits
;
5100 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
5103 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
5110 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5113 cmd
|= PCI_BRIDGE_CTL_VGA
;
5115 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
5116 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
5125 * pci_add_dma_alias - Add a DMA devfn alias for a device
5126 * @dev: the PCI device for which alias is added
5127 * @devfn: alias slot and function
5129 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5130 * It should be called early, preferably as PCI fixup header quirk.
5132 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn
)
5134 if (!dev
->dma_alias_mask
)
5135 dev
->dma_alias_mask
= kcalloc(BITS_TO_LONGS(U8_MAX
),
5136 sizeof(long), GFP_KERNEL
);
5137 if (!dev
->dma_alias_mask
) {
5138 dev_warn(&dev
->dev
, "Unable to allocate DMA alias mask\n");
5142 set_bit(devfn
, dev
->dma_alias_mask
);
5143 dev_info(&dev
->dev
, "Enabling fixed DMA alias to %02x.%d\n",
5144 PCI_SLOT(devfn
), PCI_FUNC(devfn
));
5147 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
5149 return (dev1
->dma_alias_mask
&&
5150 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
5151 (dev2
->dma_alias_mask
&&
5152 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
));
5155 bool pci_device_is_present(struct pci_dev
*pdev
)
5159 if (pci_dev_is_disconnected(pdev
))
5161 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
5163 EXPORT_SYMBOL_GPL(pci_device_is_present
);
5165 void pci_ignore_hotplug(struct pci_dev
*dev
)
5167 struct pci_dev
*bridge
= dev
->bus
->self
;
5169 dev
->ignore_hotplug
= 1;
5170 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5172 bridge
->ignore_hotplug
= 1;
5174 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
5176 resource_size_t __weak
pcibios_default_alignment(void)
5181 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5182 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
5183 static DEFINE_SPINLOCK(resource_alignment_lock
);
5186 * pci_specified_resource_alignment - get resource alignment specified by user.
5187 * @dev: the PCI device to get
5188 * @resize: whether or not to change resources' size when reassigning alignment
5190 * RETURNS: Resource alignment if it is specified.
5191 * Zero if it is not specified.
5193 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
5196 int seg
, bus
, slot
, func
, align_order
, count
;
5197 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
5198 resource_size_t align
= pcibios_default_alignment();
5201 spin_lock(&resource_alignment_lock
);
5202 p
= resource_alignment_param
;
5205 if (pci_has_flag(PCI_PROBE_ONLY
)) {
5207 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5213 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
5219 if (strncmp(p
, "pci:", 4) == 0) {
5220 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5222 if (sscanf(p
, "%hx:%hx:%hx:%hx%n",
5223 &vendor
, &device
, &subsystem_vendor
, &subsystem_device
, &count
) != 4) {
5224 if (sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
) != 2) {
5225 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: pci:%s\n",
5229 subsystem_vendor
= subsystem_device
= 0;
5232 if ((!vendor
|| (vendor
== dev
->vendor
)) &&
5233 (!device
|| (device
== dev
->device
)) &&
5234 (!subsystem_vendor
|| (subsystem_vendor
== dev
->subsystem_vendor
)) &&
5235 (!subsystem_device
|| (subsystem_device
== dev
->subsystem_device
))) {
5237 if (align_order
== -1)
5240 align
= 1 << align_order
;
5246 if (sscanf(p
, "%x:%x:%x.%x%n",
5247 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
5249 if (sscanf(p
, "%x:%x.%x%n",
5250 &bus
, &slot
, &func
, &count
) != 3) {
5251 /* Invalid format */
5252 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
5258 if (seg
== pci_domain_nr(dev
->bus
) &&
5259 bus
== dev
->bus
->number
&&
5260 slot
== PCI_SLOT(dev
->devfn
) &&
5261 func
== PCI_FUNC(dev
->devfn
)) {
5263 if (align_order
== -1)
5266 align
= 1 << align_order
;
5271 if (*p
!= ';' && *p
!= ',') {
5272 /* End of param or invalid format */
5278 spin_unlock(&resource_alignment_lock
);
5282 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
5283 resource_size_t align
, bool resize
)
5285 struct resource
*r
= &dev
->resource
[bar
];
5286 resource_size_t size
;
5288 if (!(r
->flags
& IORESOURCE_MEM
))
5291 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
5292 dev_info(&dev
->dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
5293 bar
, r
, (unsigned long long)align
);
5297 size
= resource_size(r
);
5302 * Increase the alignment of the resource. There are two ways we
5305 * 1) Increase the size of the resource. BARs are aligned on their
5306 * size, so when we reallocate space for this resource, we'll
5307 * allocate it with the larger alignment. This also prevents
5308 * assignment of any other BARs inside the alignment region, so
5309 * if we're requesting page alignment, this means no other BARs
5310 * will share the page.
5312 * The disadvantage is that this makes the resource larger than
5313 * the hardware BAR, which may break drivers that compute things
5314 * based on the resource size, e.g., to find registers at a
5315 * fixed offset before the end of the BAR.
5317 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5318 * set r->start to the desired alignment. By itself this
5319 * doesn't prevent other BARs being put inside the alignment
5320 * region, but if we realign *every* resource of every device in
5321 * the system, none of them will share an alignment region.
5323 * When the user has requested alignment for only some devices via
5324 * the "pci=resource_alignment" argument, "resize" is true and we
5325 * use the first method. Otherwise we assume we're aligning all
5326 * devices and we use the second.
5329 dev_info(&dev
->dev
, "BAR%d %pR: requesting alignment to %#llx\n",
5330 bar
, r
, (unsigned long long)align
);
5336 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
5337 r
->flags
|= IORESOURCE_STARTALIGN
;
5339 r
->end
= r
->start
+ size
- 1;
5341 r
->flags
|= IORESOURCE_UNSET
;
5345 * This function disables memory decoding and releases memory resources
5346 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5347 * It also rounds up size to specified alignment.
5348 * Later on, the kernel will assign page-aligned memory resource back
5351 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
5355 resource_size_t align
;
5357 bool resize
= false;
5360 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5361 * 3.4.1.11. Their resources are allocated from the space
5362 * described by the VF BARx register in the PF's SR-IOV capability.
5363 * We can't influence their alignment here.
5368 /* check if specified PCI is target device to reassign */
5369 align
= pci_specified_resource_alignment(dev
, &resize
);
5373 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
5374 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
5376 "Can't reassign resources to host bridge.\n");
5381 "Disabling memory decoding and releasing memory resources.\n");
5382 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
5383 command
&= ~PCI_COMMAND_MEMORY
;
5384 pci_write_config_word(dev
, PCI_COMMAND
, command
);
5386 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
5387 pci_request_resource_alignment(dev
, i
, align
, resize
);
5390 * Need to disable bridge's resource window,
5391 * to enable the kernel to reassign new resource
5394 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
&&
5395 (dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
5396 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
5397 r
= &dev
->resource
[i
];
5398 if (!(r
->flags
& IORESOURCE_MEM
))
5400 r
->flags
|= IORESOURCE_UNSET
;
5401 r
->end
= resource_size(r
) - 1;
5404 pci_disable_bridge_window(dev
);
5408 static ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
5410 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
5411 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
5412 spin_lock(&resource_alignment_lock
);
5413 strncpy(resource_alignment_param
, buf
, count
);
5414 resource_alignment_param
[count
] = '\0';
5415 spin_unlock(&resource_alignment_lock
);
5419 static ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
5422 spin_lock(&resource_alignment_lock
);
5423 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
5424 spin_unlock(&resource_alignment_lock
);
5428 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
5430 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
5433 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
5434 const char *buf
, size_t count
)
5436 return pci_set_resource_alignment_param(buf
, count
);
5439 static BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
5440 pci_resource_alignment_store
);
5442 static int __init
pci_resource_alignment_sysfs_init(void)
5444 return bus_create_file(&pci_bus_type
,
5445 &bus_attr_resource_alignment
);
5447 late_initcall(pci_resource_alignment_sysfs_init
);
5449 static void pci_no_domains(void)
5451 #ifdef CONFIG_PCI_DOMAINS
5452 pci_domains_supported
= 0;
5456 #ifdef CONFIG_PCI_DOMAINS
5457 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
5459 int pci_get_new_domain_nr(void)
5461 return atomic_inc_return(&__domain_nr
);
5464 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5465 static int of_pci_bus_find_domain_nr(struct device
*parent
)
5467 static int use_dt_domains
= -1;
5471 domain
= of_get_pci_domain_nr(parent
->of_node
);
5473 * Check DT domain and use_dt_domains values.
5475 * If DT domain property is valid (domain >= 0) and
5476 * use_dt_domains != 0, the DT assignment is valid since this means
5477 * we have not previously allocated a domain number by using
5478 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5479 * 1, to indicate that we have just assigned a domain number from
5482 * If DT domain property value is not valid (ie domain < 0), and we
5483 * have not previously assigned a domain number from DT
5484 * (use_dt_domains != 1) we should assign a domain number by
5487 * pci_get_new_domain_nr()
5489 * API and update the use_dt_domains value to keep track of method we
5490 * are using to assign domain numbers (use_dt_domains = 0).
5492 * All other combinations imply we have a platform that is trying
5493 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5494 * which is a recipe for domain mishandling and it is prevented by
5495 * invalidating the domain value (domain = -1) and printing a
5496 * corresponding error.
5498 if (domain
>= 0 && use_dt_domains
) {
5500 } else if (domain
< 0 && use_dt_domains
!= 1) {
5502 domain
= pci_get_new_domain_nr();
5504 dev_err(parent
, "Node %pOF has inconsistent \"linux,pci-domain\" property in DT\n",
5512 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
5514 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
5515 acpi_pci_bus_find_domain_nr(bus
);
5521 * pci_ext_cfg_avail - can we access extended PCI config space?
5523 * Returns 1 if we can access PCI extended config space (offsets
5524 * greater than 0xff). This is the default implementation. Architecture
5525 * implementations can override this.
5527 int __weak
pci_ext_cfg_avail(void)
5532 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
5535 EXPORT_SYMBOL(pci_fixup_cardbus
);
5537 static int __init
pci_setup(char *str
)
5540 char *k
= strchr(str
, ',');
5543 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
5544 if (!strcmp(str
, "nomsi")) {
5546 } else if (!strcmp(str
, "noaer")) {
5548 } else if (!strncmp(str
, "realloc=", 8)) {
5549 pci_realloc_get_opt(str
+ 8);
5550 } else if (!strncmp(str
, "realloc", 7)) {
5551 pci_realloc_get_opt("on");
5552 } else if (!strcmp(str
, "nodomains")) {
5554 } else if (!strncmp(str
, "noari", 5)) {
5555 pcie_ari_disabled
= true;
5556 } else if (!strncmp(str
, "cbiosize=", 9)) {
5557 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
5558 } else if (!strncmp(str
, "cbmemsize=", 10)) {
5559 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
5560 } else if (!strncmp(str
, "resource_alignment=", 19)) {
5561 pci_set_resource_alignment_param(str
+ 19,
5563 } else if (!strncmp(str
, "ecrc=", 5)) {
5564 pcie_ecrc_get_policy(str
+ 5);
5565 } else if (!strncmp(str
, "hpiosize=", 9)) {
5566 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
5567 } else if (!strncmp(str
, "hpmemsize=", 10)) {
5568 pci_hotplug_mem_size
= memparse(str
+ 10, &str
);
5569 } else if (!strncmp(str
, "hpbussize=", 10)) {
5570 pci_hotplug_bus_size
=
5571 simple_strtoul(str
+ 10, &str
, 0);
5572 if (pci_hotplug_bus_size
> 0xff)
5573 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
5574 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
5575 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
5576 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
5577 pcie_bus_config
= PCIE_BUS_SAFE
;
5578 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
5579 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
5580 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
5581 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
5582 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
5583 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
5585 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
5593 early_param("pci", pci_setup
);