1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex
);
39 const char *pci_power_names
[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names
);
44 int isa_dma_bridge_buggy
;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
48 EXPORT_SYMBOL(pci_pci_problems
);
50 unsigned int pci_pm_d3hot_delay
;
52 static void pci_pme_list_scan(struct work_struct
*work
);
54 static LIST_HEAD(pci_pme_list
);
55 static DEFINE_MUTEX(pci_pme_list_mutex
);
56 static DECLARE_DELAYED_WORK(pci_pme_work
, pci_pme_list_scan
);
58 struct pci_pme_device
{
59 struct list_head list
;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev
*dev
)
67 unsigned int delay
= dev
->d3hot_delay
;
69 if (delay
< pci_pm_d3hot_delay
)
70 delay
= pci_pm_d3hot_delay
;
76 bool pci_reset_supported(struct pci_dev
*dev
)
78 return dev
->reset_methods
[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported
= 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
89 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size
= DEFAULT_HOTPLUG_IO_SIZE
;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size
= DEFAULT_HOTPLUG_MMIO_SIZE
;
102 unsigned long pci_hotplug_mmio_pref_size
= DEFAULT_HOTPLUG_MMIO_PREF_SIZE
;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_SAFE
;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_PEER2PEER
;
118 enum pcie_bus_config_types pcie_bus_config
= PCIE_BUS_DEFAULT
;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size
= L1_CACHE_BYTES
>> 2;
128 u8 pci_cache_line_size
;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency
= 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled
;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled
;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled
;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled
);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable
;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force
;
156 static int __init
pcie_port_pm_setup(char *str
)
158 if (!strcmp(str
, "off"))
159 pci_bridge_d3_disable
= true;
160 else if (!strcmp(str
, "force"))
161 pci_bridge_d3_force
= true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup
);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
176 unsigned char pci_bus_max_busnr(struct pci_bus
*bus
)
179 unsigned char max
, n
;
181 max
= bus
->busn_res
.end
;
182 list_for_each_entry(tmp
, &bus
->children
, node
) {
183 n
= pci_bus_max_busnr(tmp
);
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
195 * Returns error bits set in PCI_STATUS and clears them.
197 int pci_status_get_and_clear_errors(struct pci_dev
*pdev
)
202 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
203 if (ret
!= PCIBIOS_SUCCESSFUL
)
206 status
&= PCI_STATUS_ERROR_BITS
;
208 pci_write_config_word(pdev
, PCI_STATUS
, status
);
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors
);
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem
*__pci_ioremap_resource(struct pci_dev
*pdev
, int bar
,
218 struct resource
*res
= &pdev
->resource
[bar
];
219 resource_size_t start
= res
->start
;
220 resource_size_t size
= resource_size(res
);
223 * Make sure the BAR is actually a memory resource, not an IO resource
225 if (res
->flags
& IORESOURCE_UNSET
|| !(res
->flags
& IORESOURCE_MEM
)) {
226 pci_err(pdev
, "can't ioremap BAR %d: %pR\n", bar
, res
);
231 return ioremap_wc(start
, size
);
233 return ioremap(start
, size
);
236 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
238 return __pci_ioremap_resource(pdev
, bar
, false);
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
242 void __iomem
*pci_ioremap_wc_bar(struct pci_dev
*pdev
, int bar
)
244 return __pci_ioremap_resource(pdev
, bar
, true);
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar
);
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
268 static int pci_dev_str_match_path(struct pci_dev
*dev
, const char *path
,
272 int seg
, bus
, slot
, func
;
276 *endptr
= strchrnul(path
, ';');
278 wpath
= kmemdup_nul(path
, *endptr
- path
, GFP_ATOMIC
);
283 p
= strrchr(wpath
, '/');
286 ret
= sscanf(p
, "/%x.%x%c", &slot
, &func
, &end
);
292 if (dev
->devfn
!= PCI_DEVFN(slot
, func
)) {
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
303 dev
= pci_upstream_bridge(dev
);
312 ret
= sscanf(wpath
, "%x:%x:%x.%x%c", &seg
, &bus
, &slot
,
316 ret
= sscanf(wpath
, "%x:%x.%x%c", &bus
, &slot
, &func
, &end
);
323 ret
= (seg
== pci_domain_nr(dev
->bus
) &&
324 bus
== dev
->bus
->number
&&
325 dev
->devfn
== PCI_DEVFN(slot
, func
));
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
362 static int pci_dev_str_match(struct pci_dev
*dev
, const char *p
,
367 unsigned short vendor
, device
, subsystem_vendor
, subsystem_device
;
369 if (strncmp(p
, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 ret
= sscanf(p
, "%hx:%hx:%hx:%hx%n", &vendor
, &device
,
373 &subsystem_vendor
, &subsystem_device
, &count
);
375 ret
= sscanf(p
, "%hx:%hx%n", &vendor
, &device
, &count
);
379 subsystem_vendor
= 0;
380 subsystem_device
= 0;
385 if ((!vendor
|| vendor
== dev
->vendor
) &&
386 (!device
|| device
== dev
->device
) &&
387 (!subsystem_vendor
||
388 subsystem_vendor
== dev
->subsystem_vendor
) &&
389 (!subsystem_device
||
390 subsystem_device
== dev
->subsystem_device
))
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
397 ret
= pci_dev_str_match_path(dev
, p
, &p
);
412 static u8
__pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
413 u8 pos
, int cap
, int *ttl
)
418 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
424 pci_bus_read_config_word(bus
, devfn
, pos
, &ent
);
436 static u8
__pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
439 int ttl
= PCI_FIND_CAP_TTL
;
441 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
444 u8
pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
446 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
447 pos
+ PCI_CAP_LIST_NEXT
, cap
);
449 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
451 static u8
__pci_bus_find_cap_start(struct pci_bus
*bus
,
452 unsigned int devfn
, u8 hdr_type
)
456 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
457 if (!(status
& PCI_STATUS_CAP_LIST
))
461 case PCI_HEADER_TYPE_NORMAL
:
462 case PCI_HEADER_TYPE_BRIDGE
:
463 return PCI_CAPABILITY_LIST
;
464 case PCI_HEADER_TYPE_CARDBUS
:
465 return PCI_CB_CAPABILITY_LIST
;
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
490 u8
pci_find_capability(struct pci_dev
*dev
, int cap
)
494 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
496 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
500 EXPORT_SYMBOL(pci_find_capability
);
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
515 u8
pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
519 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
521 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
523 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
527 EXPORT_SYMBOL(pci_bus_find_capability
);
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
540 u16
pci_find_next_ext_capability(struct pci_dev
*dev
, u16 start
, int cap
)
544 u16 pos
= PCI_CFG_SPACE_SIZE
;
546 /* minimum 8 bytes per capability */
547 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
549 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
555 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
566 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
569 pos
= PCI_EXT_CAP_NEXT(header
);
570 if (pos
< PCI_CFG_SPACE_SIZE
)
573 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability
);
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 u16
pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
597 return pci_find_next_ext_capability(dev
, 0, cap
);
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
608 * Returns the DSN, or zero if the capability does not exist.
610 u64
pci_get_dsn(struct pci_dev
*dev
)
616 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_DSN
);
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
626 pci_read_config_dword(dev
, pos
, &dword
);
628 pci_read_config_dword(dev
, pos
+ 4, &dword
);
629 dsn
|= ((u64
)dword
) << 32;
633 EXPORT_SYMBOL_GPL(pci_get_dsn
);
635 static u8
__pci_find_next_ht_cap(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
637 int rc
, ttl
= PCI_FIND_CAP_TTL
;
640 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
641 mask
= HT_3BIT_CAP_MASK
;
643 mask
= HT_5BIT_CAP_MASK
;
645 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
646 PCI_CAP_ID_HT
, &ttl
);
648 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
649 if (rc
!= PCIBIOS_SUCCESSFUL
)
652 if ((cap
& mask
) == ht_cap
)
655 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
656 pos
+ PCI_CAP_LIST_NEXT
,
657 PCI_CAP_ID_HT
, &ttl
);
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
676 u8
pci_find_next_ht_capability(struct pci_dev
*dev
, u8 pos
, int ht_cap
)
678 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
693 u8
pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
697 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
699 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
715 u16
pci_find_vsec_capability(struct pci_dev
*dev
, u16 vendor
, int cap
)
720 if (vendor
!= dev
->vendor
)
723 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
724 PCI_EXT_CAP_ID_VNDR
))) {
725 if (pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
,
726 &header
) == PCIBIOS_SUCCESSFUL
&&
727 PCI_VNDR_HEADER_ID(header
) == cap
)
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability
);
736 * pci_find_parent_resource - return resource region of parent bus of given
738 * @dev: PCI device structure contains resources to be searched
739 * @res: child resource record for which parent is sought
741 * For given resource region of given device, return the resource region of
742 * parent bus the given region is contained in.
744 struct resource
*pci_find_parent_resource(const struct pci_dev
*dev
,
745 struct resource
*res
)
747 const struct pci_bus
*bus
= dev
->bus
;
751 pci_bus_for_each_resource(bus
, r
, i
) {
754 if (resource_contains(r
, res
)) {
757 * If the window is prefetchable but the BAR is
758 * not, the allocator made a mistake.
760 if (r
->flags
& IORESOURCE_PREFETCH
&&
761 !(res
->flags
& IORESOURCE_PREFETCH
))
765 * If we're below a transparent bridge, there may
766 * be both a positively-decoded aperture and a
767 * subtractively-decoded region that contain the BAR.
768 * We want the positively-decoded one, so this depends
769 * on pci_bus_for_each_resource() giving us those
777 EXPORT_SYMBOL(pci_find_parent_resource
);
780 * pci_find_resource - Return matching PCI device resource
781 * @dev: PCI device to query
782 * @res: Resource to look for
784 * Goes over standard PCI resources (BARs) and checks if the given resource
785 * is partially or fully contained in any of them. In that case the
786 * matching resource is returned, %NULL otherwise.
788 struct resource
*pci_find_resource(struct pci_dev
*dev
, struct resource
*res
)
792 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++) {
793 struct resource
*r
= &dev
->resource
[i
];
795 if (r
->start
&& resource_contains(r
, res
))
801 EXPORT_SYMBOL(pci_find_resource
);
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
805 * @dev: the PCI device to operate on
806 * @pos: config space offset of status word
807 * @mask: mask of bit(s) to care about in status word
809 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
811 int pci_wait_for_pending(struct pci_dev
*dev
, int pos
, u16 mask
)
815 /* Wait for Transaction Pending bit clean */
816 for (i
= 0; i
< 4; i
++) {
819 msleep((1 << (i
- 1)) * 100);
821 pci_read_config_word(dev
, pos
, &status
);
822 if (!(status
& mask
))
829 static int pci_acs_enable
;
832 * pci_request_acs - ask for ACS to be enabled if supported
834 void pci_request_acs(void)
839 static const char *disable_acs_redir_param
;
842 * pci_disable_acs_redir - disable ACS redirect capabilities
843 * @dev: the PCI device
845 * For only devices specified in the disable_acs_redir parameter.
847 static void pci_disable_acs_redir(struct pci_dev
*dev
)
854 if (!disable_acs_redir_param
)
857 p
= disable_acs_redir_param
;
859 ret
= pci_dev_str_match(dev
, p
, &p
);
861 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
862 disable_acs_redir_param
);
865 } else if (ret
== 1) {
870 if (*p
!= ';' && *p
!= ',') {
871 /* End of param or invalid format */
880 if (!pci_dev_specific_disable_acs_redir(dev
))
885 pci_warn(dev
, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
889 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
891 /* P2P Request & Completion Redirect */
892 ctrl
&= ~(PCI_ACS_RR
| PCI_ACS_CR
| PCI_ACS_EC
);
894 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
896 pci_info(dev
, "disabled ACS redirect\n");
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
901 * @dev: the PCI device
903 static void pci_std_enable_acs(struct pci_dev
*dev
)
913 pci_read_config_word(dev
, pos
+ PCI_ACS_CAP
, &cap
);
914 pci_read_config_word(dev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
916 /* Source Validation */
917 ctrl
|= (cap
& PCI_ACS_SV
);
919 /* P2P Request Redirect */
920 ctrl
|= (cap
& PCI_ACS_RR
);
922 /* P2P Completion Redirect */
923 ctrl
|= (cap
& PCI_ACS_CR
);
925 /* Upstream Forwarding */
926 ctrl
|= (cap
& PCI_ACS_UF
);
928 /* Enable Translation Blocking for external devices and noats */
929 if (pci_ats_disabled() || dev
->external_facing
|| dev
->untrusted
)
930 ctrl
|= (cap
& PCI_ACS_TB
);
932 pci_write_config_word(dev
, pos
+ PCI_ACS_CTRL
, ctrl
);
936 * pci_enable_acs - enable ACS if hardware support it
937 * @dev: the PCI device
939 static void pci_enable_acs(struct pci_dev
*dev
)
942 goto disable_acs_redir
;
944 if (!pci_dev_specific_enable_acs(dev
))
945 goto disable_acs_redir
;
947 pci_std_enable_acs(dev
);
951 * Note: pci_disable_acs_redir() must be called even if ACS was not
952 * enabled by the kernel because it may have been enabled by
953 * platform firmware. So if we are told to disable it, we should
954 * always disable it after setting the kernel's default
957 pci_disable_acs_redir(dev
);
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
962 * @dev: PCI device to have its BARs restored
964 * Restore the BAR values for a given device, so as to make it
965 * accessible by its driver.
967 static void pci_restore_bars(struct pci_dev
*dev
)
971 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
972 pci_update_resource(dev
, i
);
975 static const struct pci_platform_pm_ops
*pci_platform_pm
;
977 int pci_set_platform_pm(const struct pci_platform_pm_ops
*ops
)
979 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->get_state
||
980 !ops
->choose_state
|| !ops
->set_wakeup
|| !ops
->need_resume
)
982 pci_platform_pm
= ops
;
986 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
988 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
991 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
994 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
997 static inline pci_power_t
platform_pci_get_power_state(struct pci_dev
*dev
)
999 return pci_platform_pm
? pci_platform_pm
->get_state(dev
) : PCI_UNKNOWN
;
1002 static inline void platform_pci_refresh_power_state(struct pci_dev
*dev
)
1004 if (pci_platform_pm
&& pci_platform_pm
->refresh_state
)
1005 pci_platform_pm
->refresh_state(dev
);
1008 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
1010 return pci_platform_pm
?
1011 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
1014 static inline int platform_pci_set_wakeup(struct pci_dev
*dev
, bool enable
)
1016 return pci_platform_pm
?
1017 pci_platform_pm
->set_wakeup(dev
, enable
) : -ENODEV
;
1020 static inline bool platform_pci_need_resume(struct pci_dev
*dev
)
1022 return pci_platform_pm
? pci_platform_pm
->need_resume(dev
) : false;
1025 static inline bool platform_pci_bridge_d3(struct pci_dev
*dev
)
1027 if (pci_platform_pm
&& pci_platform_pm
->bridge_d3
)
1028 return pci_platform_pm
->bridge_d3(dev
);
1033 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1035 * @dev: PCI device to handle.
1036 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1039 * -EINVAL if the requested state is invalid.
1040 * -EIO if device does not support PCI PM or its PM capabilities register has a
1041 * wrong version, or device doesn't support the requested state.
1042 * 0 if device already is in the requested state.
1043 * 0 if device's power state has been successfully changed.
1045 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1048 bool need_restore
= false;
1050 /* Check if we're already there */
1051 if (dev
->current_state
== state
)
1057 if (state
< PCI_D0
|| state
> PCI_D3hot
)
1061 * Validate transition: We can enter D0 from any state, but if
1062 * we're already in a low-power state, we can only go deeper. E.g.,
1063 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1064 * we'd have to go from D3 to D0, then to D1.
1066 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
1067 && dev
->current_state
> state
) {
1068 pci_err(dev
, "invalid power transition (from %s to %s)\n",
1069 pci_power_name(dev
->current_state
),
1070 pci_power_name(state
));
1074 /* Check if this device supports the desired state */
1075 if ((state
== PCI_D1
&& !dev
->d1_support
)
1076 || (state
== PCI_D2
&& !dev
->d2_support
))
1079 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1080 if (pmcsr
== (u16
) ~0) {
1081 pci_err(dev
, "can't change power state from %s to %s (config space inaccessible)\n",
1082 pci_power_name(dev
->current_state
),
1083 pci_power_name(state
));
1088 * If we're (effectively) in D3, force entire word to 0.
1089 * This doesn't affect PME_Status, disables PME_En, and
1090 * sets PowerState to 0.
1092 switch (dev
->current_state
) {
1096 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
1101 case PCI_UNKNOWN
: /* Boot-up */
1102 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
1103 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
1104 need_restore
= true;
1105 fallthrough
; /* force to D0 */
1111 /* Enter specified state */
1112 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1115 * Mandatory power management transition delays; see PCI PM 1.1
1118 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
1119 pci_dev_d3_sleep(dev
);
1120 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
1121 udelay(PCI_PM_D2_DELAY
);
1123 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1124 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1125 if (dev
->current_state
!= state
)
1126 pci_info_ratelimited(dev
, "refused to change power state from %s to %s\n",
1127 pci_power_name(dev
->current_state
),
1128 pci_power_name(state
));
1131 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1132 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1133 * from D3hot to D0 _may_ perform an internal reset, thereby
1134 * going to "D0 Uninitialized" rather than "D0 Initialized".
1135 * For example, at least some versions of the 3c905B and the
1136 * 3c556B exhibit this behaviour.
1138 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1139 * devices in a D3hot state at boot. Consequently, we need to
1140 * restore at least the BARs so that the device will be
1141 * accessible to its driver.
1144 pci_restore_bars(dev
);
1147 pcie_aspm_pm_state_change(dev
->bus
->self
);
1153 * pci_update_current_state - Read power state of given device and cache it
1154 * @dev: PCI device to handle.
1155 * @state: State to cache in case the device doesn't have the PM capability
1157 * The power state is read from the PMCSR register, which however is
1158 * inaccessible in D3cold. The platform firmware is therefore queried first
1159 * to detect accessibility of the register. In case the platform firmware
1160 * reports an incorrect state or the device isn't power manageable by the
1161 * platform at all, we try to detect D3cold by testing accessibility of the
1162 * vendor ID in config space.
1164 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
1166 if (platform_pci_get_power_state(dev
) == PCI_D3cold
||
1167 !pci_device_is_present(dev
)) {
1168 dev
->current_state
= PCI_D3cold
;
1169 } else if (dev
->pm_cap
) {
1172 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1173 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
1175 dev
->current_state
= state
;
1180 * pci_refresh_power_state - Refresh the given device's power state data
1181 * @dev: Target PCI device.
1183 * Ask the platform to refresh the devices power state information and invoke
1184 * pci_update_current_state() to update its current PCI power state.
1186 void pci_refresh_power_state(struct pci_dev
*dev
)
1188 if (platform_pci_power_manageable(dev
))
1189 platform_pci_refresh_power_state(dev
);
1191 pci_update_current_state(dev
, dev
->current_state
);
1195 * pci_platform_power_transition - Use platform to change device power state
1196 * @dev: PCI device to handle.
1197 * @state: State to put the device into.
1199 int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
1203 if (platform_pci_power_manageable(dev
)) {
1204 error
= platform_pci_set_power_state(dev
, state
);
1206 pci_update_current_state(dev
, state
);
1210 if (error
&& !dev
->pm_cap
) /* Fall back to PCI_D0 */
1211 dev
->current_state
= PCI_D0
;
1215 EXPORT_SYMBOL_GPL(pci_platform_power_transition
);
1217 static int pci_resume_one(struct pci_dev
*pci_dev
, void *ign
)
1219 pm_request_resume(&pci_dev
->dev
);
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1225 * @bus: Top bus of the subtree to walk.
1227 void pci_resume_bus(struct pci_bus
*bus
)
1230 pci_walk_bus(bus
, pci_resume_one
, NULL
);
1233 static int pci_dev_wait(struct pci_dev
*dev
, char *reset_type
, int timeout
)
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 data to complete the read (except when
1243 * CRS SV is enabled and the read was for the Vendor ID; in that
1244 * case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1250 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1252 if (delay
> timeout
) {
1253 pci_warn(dev
, "not ready %dms after %s; giving up\n",
1254 delay
- 1, reset_type
);
1259 pci_info(dev
, "not ready %dms after %s; waiting\n",
1260 delay
- 1, reset_type
);
1264 pci_read_config_dword(dev
, PCI_COMMAND
, &id
);
1268 pci_info(dev
, "ready %dms after %s\n", delay
- 1,
1275 * pci_power_up - Put the given device into D0
1276 * @dev: PCI device to power up
1278 int pci_power_up(struct pci_dev
*dev
)
1280 pci_platform_power_transition(dev
, PCI_D0
);
1283 * Mandatory power management transition delays are handled in
1284 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1285 * corresponding bridge.
1287 if (dev
->runtime_d3cold
) {
1289 * When powering on a bridge from D3cold, the whole hierarchy
1290 * may be powered on into D0uninitialized state, resume them to
1291 * give them a chance to suspend again
1293 pci_resume_bus(dev
->subordinate
);
1296 return pci_raw_set_power_state(dev
, PCI_D0
);
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1301 * @dev: Device to handle
1302 * @data: pointer to state to be set
1304 static int __pci_dev_set_current_state(struct pci_dev
*dev
, void *data
)
1306 pci_power_t state
= *(pci_power_t
*)data
;
1308 dev
->current_state
= state
;
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1314 * @bus: Top bus of the subtree to walk.
1315 * @state: state to be set
1317 void pci_bus_set_current_state(struct pci_bus
*bus
, pci_power_t state
)
1320 pci_walk_bus(bus
, __pci_dev_set_current_state
, &state
);
1324 * pci_set_power_state - Set the power state of a PCI device
1325 * @dev: PCI device to handle.
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1328 * Transition a device to a new power state, using the platform firmware and/or
1329 * the device's PCI PM registers.
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1335 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1336 * 0 if device already is in the requested state.
1337 * 0 if the transition is to D3 but D3 is not supported.
1338 * 0 if device's power state has been successfully changed.
1340 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
1344 /* Bound the state we're entering */
1345 if (state
> PCI_D3cold
)
1347 else if (state
< PCI_D0
)
1349 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
1352 * If the device or the parent bridge do not support PCI
1353 * PM, ignore the request if we're doing anything other
1354 * than putting it into D0 (which would only happen on
1359 /* Check if we're already there */
1360 if (dev
->current_state
== state
)
1363 if (state
== PCI_D0
)
1364 return pci_power_up(dev
);
1367 * This device is quirked not to be put into D3, so don't put it in
1370 if (state
>= PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
1374 * To put device in D3cold, we put device into D3hot in native
1375 * way, then put device into D3cold with platform ops
1377 error
= pci_raw_set_power_state(dev
, state
> PCI_D3hot
?
1380 if (pci_platform_power_transition(dev
, state
))
1383 /* Powering off a bridge may power off the whole hierarchy */
1384 if (state
== PCI_D3cold
)
1385 pci_bus_set_current_state(dev
->subordinate
, PCI_D3cold
);
1389 EXPORT_SYMBOL(pci_set_power_state
);
1392 * pci_choose_state - Choose the power state of a PCI device
1393 * @dev: PCI device to be suspended
1394 * @state: target sleep state for the whole system. This is the value
1395 * that is passed to suspend() function.
1397 * Returns PCI power state suitable for given device and given system
1400 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
1407 ret
= platform_pci_choose_state(dev
);
1408 if (ret
!= PCI_POWER_ERROR
)
1411 switch (state
.event
) {
1414 case PM_EVENT_FREEZE
:
1415 case PM_EVENT_PRETHAW
:
1416 /* REVISIT both freeze and pre-thaw "should" use D0 */
1417 case PM_EVENT_SUSPEND
:
1418 case PM_EVENT_HIBERNATE
:
1421 pci_info(dev
, "unrecognized suspend event %d\n",
1427 EXPORT_SYMBOL(pci_choose_state
);
1429 #define PCI_EXP_SAVE_REGS 7
1431 static struct pci_cap_saved_state
*_pci_find_saved_cap(struct pci_dev
*pci_dev
,
1432 u16 cap
, bool extended
)
1434 struct pci_cap_saved_state
*tmp
;
1436 hlist_for_each_entry(tmp
, &pci_dev
->saved_cap_space
, next
) {
1437 if (tmp
->cap
.cap_extended
== extended
&& tmp
->cap
.cap_nr
== cap
)
1443 struct pci_cap_saved_state
*pci_find_saved_cap(struct pci_dev
*dev
, char cap
)
1445 return _pci_find_saved_cap(dev
, cap
, false);
1448 struct pci_cap_saved_state
*pci_find_saved_ext_cap(struct pci_dev
*dev
, u16 cap
)
1450 return _pci_find_saved_cap(dev
, cap
, true);
1453 static int pci_save_pcie_state(struct pci_dev
*dev
)
1456 struct pci_cap_saved_state
*save_state
;
1459 if (!pci_is_pcie(dev
))
1462 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1464 pci_err(dev
, "buffer not found in %s\n", __func__
);
1468 cap
= (u16
*)&save_state
->cap
.data
[0];
1469 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &cap
[i
++]);
1470 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL
, &cap
[i
++]);
1471 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL
, &cap
[i
++]);
1472 pcie_capability_read_word(dev
, PCI_EXP_RTCTL
, &cap
[i
++]);
1473 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL2
, &cap
[i
++]);
1474 pcie_capability_read_word(dev
, PCI_EXP_LNKCTL2
, &cap
[i
++]);
1475 pcie_capability_read_word(dev
, PCI_EXP_SLTCTL2
, &cap
[i
++]);
1480 void pci_bridge_reconfigure_ltr(struct pci_dev
*dev
)
1482 #ifdef CONFIG_PCIEASPM
1483 struct pci_dev
*bridge
;
1486 bridge
= pci_upstream_bridge(dev
);
1487 if (bridge
&& bridge
->ltr_path
) {
1488 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
, &ctl
);
1489 if (!(ctl
& PCI_EXP_DEVCTL2_LTR_EN
)) {
1490 pci_dbg(bridge
, "re-enabling LTR\n");
1491 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
1492 PCI_EXP_DEVCTL2_LTR_EN
);
1498 static void pci_restore_pcie_state(struct pci_dev
*dev
)
1501 struct pci_cap_saved_state
*save_state
;
1504 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
1509 * Downstream ports reset the LTR enable bit when link goes down.
1510 * Check and re-configure the bit here before restoring device.
1511 * PCIe r5.0, sec 7.5.3.16.
1513 pci_bridge_reconfigure_ltr(dev
);
1515 cap
= (u16
*)&save_state
->cap
.data
[0];
1516 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL
, cap
[i
++]);
1517 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL
, cap
[i
++]);
1518 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL
, cap
[i
++]);
1519 pcie_capability_write_word(dev
, PCI_EXP_RTCTL
, cap
[i
++]);
1520 pcie_capability_write_word(dev
, PCI_EXP_DEVCTL2
, cap
[i
++]);
1521 pcie_capability_write_word(dev
, PCI_EXP_LNKCTL2
, cap
[i
++]);
1522 pcie_capability_write_word(dev
, PCI_EXP_SLTCTL2
, cap
[i
++]);
1525 static int pci_save_pcix_state(struct pci_dev
*dev
)
1528 struct pci_cap_saved_state
*save_state
;
1530 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1534 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1536 pci_err(dev
, "buffer not found in %s\n", __func__
);
1540 pci_read_config_word(dev
, pos
+ PCI_X_CMD
,
1541 (u16
*)save_state
->cap
.data
);
1546 static void pci_restore_pcix_state(struct pci_dev
*dev
)
1549 struct pci_cap_saved_state
*save_state
;
1552 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
1553 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1554 if (!save_state
|| !pos
)
1556 cap
= (u16
*)&save_state
->cap
.data
[0];
1558 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
1561 static void pci_save_ltr_state(struct pci_dev
*dev
)
1564 struct pci_cap_saved_state
*save_state
;
1567 if (!pci_is_pcie(dev
))
1570 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1574 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1576 pci_err(dev
, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1580 cap
= (u16
*)&save_state
->cap
.data
[0];
1581 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, cap
++);
1582 pci_read_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, cap
++);
1585 static void pci_restore_ltr_state(struct pci_dev
*dev
)
1587 struct pci_cap_saved_state
*save_state
;
1591 save_state
= pci_find_saved_ext_cap(dev
, PCI_EXT_CAP_ID_LTR
);
1592 ltr
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_LTR
);
1593 if (!save_state
|| !ltr
)
1596 cap
= (u16
*)&save_state
->cap
.data
[0];
1597 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_SNOOP_LAT
, *cap
++);
1598 pci_write_config_word(dev
, ltr
+ PCI_LTR_MAX_NOSNOOP_LAT
, *cap
++);
1602 * pci_save_state - save the PCI configuration space of a device before
1604 * @dev: PCI device that we're dealing with
1606 int pci_save_state(struct pci_dev
*dev
)
1609 /* XXX: 100% dword access ok here? */
1610 for (i
= 0; i
< 16; i
++) {
1611 pci_read_config_dword(dev
, i
* 4, &dev
->saved_config_space
[i
]);
1612 pci_dbg(dev
, "saving config space at offset %#x (reading %#x)\n",
1613 i
* 4, dev
->saved_config_space
[i
]);
1615 dev
->state_saved
= true;
1617 i
= pci_save_pcie_state(dev
);
1621 i
= pci_save_pcix_state(dev
);
1625 pci_save_ltr_state(dev
);
1626 pci_save_dpc_state(dev
);
1627 pci_save_aer_state(dev
);
1628 pci_save_ptm_state(dev
);
1629 return pci_save_vc_state(dev
);
1631 EXPORT_SYMBOL(pci_save_state
);
1633 static void pci_restore_config_dword(struct pci_dev
*pdev
, int offset
,
1634 u32 saved_val
, int retry
, bool force
)
1638 pci_read_config_dword(pdev
, offset
, &val
);
1639 if (!force
&& val
== saved_val
)
1643 pci_dbg(pdev
, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1644 offset
, val
, saved_val
);
1645 pci_write_config_dword(pdev
, offset
, saved_val
);
1649 pci_read_config_dword(pdev
, offset
, &val
);
1650 if (val
== saved_val
)
1657 static void pci_restore_config_space_range(struct pci_dev
*pdev
,
1658 int start
, int end
, int retry
,
1663 for (index
= end
; index
>= start
; index
--)
1664 pci_restore_config_dword(pdev
, 4 * index
,
1665 pdev
->saved_config_space
[index
],
1669 static void pci_restore_config_space(struct pci_dev
*pdev
)
1671 if (pdev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
) {
1672 pci_restore_config_space_range(pdev
, 10, 15, 0, false);
1673 /* Restore BARs before the command register. */
1674 pci_restore_config_space_range(pdev
, 4, 9, 10, false);
1675 pci_restore_config_space_range(pdev
, 0, 3, 0, false);
1676 } else if (pdev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
1677 pci_restore_config_space_range(pdev
, 12, 15, 0, false);
1680 * Force rewriting of prefetch registers to avoid S3 resume
1681 * issues on Intel PCI bridges that occur when these
1682 * registers are not explicitly written.
1684 pci_restore_config_space_range(pdev
, 9, 11, 0, true);
1685 pci_restore_config_space_range(pdev
, 0, 8, 0, false);
1687 pci_restore_config_space_range(pdev
, 0, 15, 0, false);
1691 static void pci_restore_rebar_state(struct pci_dev
*pdev
)
1693 unsigned int pos
, nbars
, i
;
1696 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
1700 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1701 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
1702 PCI_REBAR_CTRL_NBAR_SHIFT
;
1704 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
1705 struct resource
*res
;
1708 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
1709 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
1710 res
= pdev
->resource
+ bar_idx
;
1711 size
= pci_rebar_bytes_to_size(resource_size(res
));
1712 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
1713 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
1714 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
1719 * pci_restore_state - Restore the saved state of a PCI device
1720 * @dev: PCI device that we're dealing with
1722 void pci_restore_state(struct pci_dev
*dev
)
1724 if (!dev
->state_saved
)
1728 * Restore max latencies (in the LTR capability) before enabling
1729 * LTR itself (in the PCIe capability).
1731 pci_restore_ltr_state(dev
);
1733 pci_restore_pcie_state(dev
);
1734 pci_restore_pasid_state(dev
);
1735 pci_restore_pri_state(dev
);
1736 pci_restore_ats_state(dev
);
1737 pci_restore_vc_state(dev
);
1738 pci_restore_rebar_state(dev
);
1739 pci_restore_dpc_state(dev
);
1740 pci_restore_ptm_state(dev
);
1742 pci_aer_clear_status(dev
);
1743 pci_restore_aer_state(dev
);
1745 pci_restore_config_space(dev
);
1747 pci_restore_pcix_state(dev
);
1748 pci_restore_msi_state(dev
);
1750 /* Restore ACS and IOV configuration state */
1751 pci_enable_acs(dev
);
1752 pci_restore_iov_state(dev
);
1754 dev
->state_saved
= false;
1756 EXPORT_SYMBOL(pci_restore_state
);
1758 struct pci_saved_state
{
1759 u32 config_space
[16];
1760 struct pci_cap_saved_data cap
[];
1764 * pci_store_saved_state - Allocate and return an opaque struct containing
1765 * the device saved state.
1766 * @dev: PCI device that we're dealing with
1768 * Return NULL if no state or error.
1770 struct pci_saved_state
*pci_store_saved_state(struct pci_dev
*dev
)
1772 struct pci_saved_state
*state
;
1773 struct pci_cap_saved_state
*tmp
;
1774 struct pci_cap_saved_data
*cap
;
1777 if (!dev
->state_saved
)
1780 size
= sizeof(*state
) + sizeof(struct pci_cap_saved_data
);
1782 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
)
1783 size
+= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1785 state
= kzalloc(size
, GFP_KERNEL
);
1789 memcpy(state
->config_space
, dev
->saved_config_space
,
1790 sizeof(state
->config_space
));
1793 hlist_for_each_entry(tmp
, &dev
->saved_cap_space
, next
) {
1794 size_t len
= sizeof(struct pci_cap_saved_data
) + tmp
->cap
.size
;
1795 memcpy(cap
, &tmp
->cap
, len
);
1796 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+ len
);
1798 /* Empty cap_save terminates list */
1802 EXPORT_SYMBOL_GPL(pci_store_saved_state
);
1805 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1806 * @dev: PCI device that we're dealing with
1807 * @state: Saved state returned from pci_store_saved_state()
1809 int pci_load_saved_state(struct pci_dev
*dev
,
1810 struct pci_saved_state
*state
)
1812 struct pci_cap_saved_data
*cap
;
1814 dev
->state_saved
= false;
1819 memcpy(dev
->saved_config_space
, state
->config_space
,
1820 sizeof(state
->config_space
));
1824 struct pci_cap_saved_state
*tmp
;
1826 tmp
= _pci_find_saved_cap(dev
, cap
->cap_nr
, cap
->cap_extended
);
1827 if (!tmp
|| tmp
->cap
.size
!= cap
->size
)
1830 memcpy(tmp
->cap
.data
, cap
->data
, tmp
->cap
.size
);
1831 cap
= (struct pci_cap_saved_data
*)((u8
*)cap
+
1832 sizeof(struct pci_cap_saved_data
) + cap
->size
);
1835 dev
->state_saved
= true;
1838 EXPORT_SYMBOL_GPL(pci_load_saved_state
);
1841 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1842 * and free the memory allocated for it.
1843 * @dev: PCI device that we're dealing with
1844 * @state: Pointer to saved state returned from pci_store_saved_state()
1846 int pci_load_and_free_saved_state(struct pci_dev
*dev
,
1847 struct pci_saved_state
**state
)
1849 int ret
= pci_load_saved_state(dev
, *state
);
1854 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state
);
1856 int __weak
pcibios_enable_device(struct pci_dev
*dev
, int bars
)
1858 return pci_enable_resources(dev
, bars
);
1861 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
1864 struct pci_dev
*bridge
;
1868 err
= pci_set_power_state(dev
, PCI_D0
);
1869 if (err
< 0 && err
!= -EIO
)
1872 bridge
= pci_upstream_bridge(dev
);
1874 pcie_aspm_powersave_config_link(bridge
);
1876 err
= pcibios_enable_device(dev
, bars
);
1879 pci_fixup_device(pci_fixup_enable
, dev
);
1881 if (dev
->msi_enabled
|| dev
->msix_enabled
)
1884 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
1886 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1887 if (cmd
& PCI_COMMAND_INTX_DISABLE
)
1888 pci_write_config_word(dev
, PCI_COMMAND
,
1889 cmd
& ~PCI_COMMAND_INTX_DISABLE
);
1896 * pci_reenable_device - Resume abandoned device
1897 * @dev: PCI device to be resumed
1899 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1900 * to be called by normal code, write proper resume handler and use it instead.
1902 int pci_reenable_device(struct pci_dev
*dev
)
1904 if (pci_is_enabled(dev
))
1905 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
1908 EXPORT_SYMBOL(pci_reenable_device
);
1910 static void pci_enable_bridge(struct pci_dev
*dev
)
1912 struct pci_dev
*bridge
;
1915 bridge
= pci_upstream_bridge(dev
);
1917 pci_enable_bridge(bridge
);
1919 if (pci_is_enabled(dev
)) {
1920 if (!dev
->is_busmaster
)
1921 pci_set_master(dev
);
1925 retval
= pci_enable_device(dev
);
1927 pci_err(dev
, "Error enabling bridge (%d), continuing\n",
1929 pci_set_master(dev
);
1932 static int pci_enable_device_flags(struct pci_dev
*dev
, unsigned long flags
)
1934 struct pci_dev
*bridge
;
1939 * Power state could be unknown at this point, either due to a fresh
1940 * boot or a device removal call. So get the current power state
1941 * so that things like MSI message writing will behave as expected
1942 * (e.g. if the device really is in D0 at enable time).
1944 pci_update_current_state(dev
, dev
->current_state
);
1946 if (atomic_inc_return(&dev
->enable_cnt
) > 1)
1947 return 0; /* already enabled */
1949 bridge
= pci_upstream_bridge(dev
);
1951 pci_enable_bridge(bridge
);
1953 /* only skip sriov related */
1954 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
1955 if (dev
->resource
[i
].flags
& flags
)
1957 for (i
= PCI_BRIDGE_RESOURCES
; i
< DEVICE_COUNT_RESOURCE
; i
++)
1958 if (dev
->resource
[i
].flags
& flags
)
1961 err
= do_pci_enable_device(dev
, bars
);
1963 atomic_dec(&dev
->enable_cnt
);
1968 * pci_enable_device_io - Initialize a device for use with IO space
1969 * @dev: PCI device to be initialized
1971 * Initialize device before it's used by a driver. Ask low-level code
1972 * to enable I/O resources. Wake up the device if it was suspended.
1973 * Beware, this function can fail.
1975 int pci_enable_device_io(struct pci_dev
*dev
)
1977 return pci_enable_device_flags(dev
, IORESOURCE_IO
);
1979 EXPORT_SYMBOL(pci_enable_device_io
);
1982 * pci_enable_device_mem - Initialize a device for use with Memory space
1983 * @dev: PCI device to be initialized
1985 * Initialize device before it's used by a driver. Ask low-level code
1986 * to enable Memory resources. Wake up the device if it was suspended.
1987 * Beware, this function can fail.
1989 int pci_enable_device_mem(struct pci_dev
*dev
)
1991 return pci_enable_device_flags(dev
, IORESOURCE_MEM
);
1993 EXPORT_SYMBOL(pci_enable_device_mem
);
1996 * pci_enable_device - Initialize device before it's used by a driver.
1997 * @dev: PCI device to be initialized
1999 * Initialize device before it's used by a driver. Ask low-level code
2000 * to enable I/O and memory. Wake up the device if it was suspended.
2001 * Beware, this function can fail.
2003 * Note we don't actually enable the device many times if we call
2004 * this function repeatedly (we just increment the count).
2006 int pci_enable_device(struct pci_dev
*dev
)
2008 return pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
2010 EXPORT_SYMBOL(pci_enable_device
);
2013 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2014 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2015 * there's no need to track it separately. pci_devres is initialized
2016 * when a device is enabled using managed PCI device enable interface.
2019 unsigned int enabled
:1;
2020 unsigned int pinned
:1;
2021 unsigned int orig_intx
:1;
2022 unsigned int restore_intx
:1;
2027 static void pcim_release(struct device
*gendev
, void *res
)
2029 struct pci_dev
*dev
= to_pci_dev(gendev
);
2030 struct pci_devres
*this = res
;
2033 if (dev
->msi_enabled
)
2034 pci_disable_msi(dev
);
2035 if (dev
->msix_enabled
)
2036 pci_disable_msix(dev
);
2038 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
2039 if (this->region_mask
& (1 << i
))
2040 pci_release_region(dev
, i
);
2045 if (this->restore_intx
)
2046 pci_intx(dev
, this->orig_intx
);
2048 if (this->enabled
&& !this->pinned
)
2049 pci_disable_device(dev
);
2052 static struct pci_devres
*get_pci_dr(struct pci_dev
*pdev
)
2054 struct pci_devres
*dr
, *new_dr
;
2056 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2060 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
2063 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
2066 static struct pci_devres
*find_pci_dr(struct pci_dev
*pdev
)
2068 if (pci_is_managed(pdev
))
2069 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
2074 * pcim_enable_device - Managed pci_enable_device()
2075 * @pdev: PCI device to be initialized
2077 * Managed pci_enable_device().
2079 int pcim_enable_device(struct pci_dev
*pdev
)
2081 struct pci_devres
*dr
;
2084 dr
= get_pci_dr(pdev
);
2090 rc
= pci_enable_device(pdev
);
2092 pdev
->is_managed
= 1;
2097 EXPORT_SYMBOL(pcim_enable_device
);
2100 * pcim_pin_device - Pin managed PCI device
2101 * @pdev: PCI device to pin
2103 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2104 * driver detach. @pdev must have been enabled with
2105 * pcim_enable_device().
2107 void pcim_pin_device(struct pci_dev
*pdev
)
2109 struct pci_devres
*dr
;
2111 dr
= find_pci_dr(pdev
);
2112 WARN_ON(!dr
|| !dr
->enabled
);
2116 EXPORT_SYMBOL(pcim_pin_device
);
2119 * pcibios_device_add - provide arch specific hooks when adding device dev
2120 * @dev: the PCI device being added
2122 * Permits the platform to provide architecture specific functionality when
2123 * devices are added. This is the default implementation. Architecture
2124 * implementations can override this.
2126 int __weak
pcibios_device_add(struct pci_dev
*dev
)
2132 * pcibios_release_device - provide arch specific hooks when releasing
2134 * @dev: the PCI device being released
2136 * Permits the platform to provide architecture specific functionality when
2137 * devices are released. This is the default implementation. Architecture
2138 * implementations can override this.
2140 void __weak
pcibios_release_device(struct pci_dev
*dev
) {}
2143 * pcibios_disable_device - disable arch specific PCI resources for device dev
2144 * @dev: the PCI device to disable
2146 * Disables architecture specific PCI resources for the device. This
2147 * is the default implementation. Architecture implementations can
2150 void __weak
pcibios_disable_device(struct pci_dev
*dev
) {}
2153 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2154 * @irq: ISA IRQ to penalize
2155 * @active: IRQ active or not
2157 * Permits the platform to provide architecture-specific functionality when
2158 * penalizing ISA IRQs. This is the default implementation. Architecture
2159 * implementations can override this.
2161 void __weak
pcibios_penalize_isa_irq(int irq
, int active
) {}
2163 static void do_pci_disable_device(struct pci_dev
*dev
)
2167 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
2168 if (pci_command
& PCI_COMMAND_MASTER
) {
2169 pci_command
&= ~PCI_COMMAND_MASTER
;
2170 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
2173 pcibios_disable_device(dev
);
2177 * pci_disable_enabled_device - Disable device without updating enable_cnt
2178 * @dev: PCI device to disable
2180 * NOTE: This function is a backend of PCI power management routines and is
2181 * not supposed to be called drivers.
2183 void pci_disable_enabled_device(struct pci_dev
*dev
)
2185 if (pci_is_enabled(dev
))
2186 do_pci_disable_device(dev
);
2190 * pci_disable_device - Disable PCI device after use
2191 * @dev: PCI device to be disabled
2193 * Signal to the system that the PCI device is not in use by the system
2194 * anymore. This only involves disabling PCI bus-mastering, if active.
2196 * Note we don't actually disable the device until all callers of
2197 * pci_enable_device() have called pci_disable_device().
2199 void pci_disable_device(struct pci_dev
*dev
)
2201 struct pci_devres
*dr
;
2203 dr
= find_pci_dr(dev
);
2207 dev_WARN_ONCE(&dev
->dev
, atomic_read(&dev
->enable_cnt
) <= 0,
2208 "disabling already-disabled device");
2210 if (atomic_dec_return(&dev
->enable_cnt
) != 0)
2213 do_pci_disable_device(dev
);
2215 dev
->is_busmaster
= 0;
2217 EXPORT_SYMBOL(pci_disable_device
);
2220 * pcibios_set_pcie_reset_state - set reset state for device dev
2221 * @dev: the PCIe device reset
2222 * @state: Reset state to enter into
2224 * Set the PCIe reset state for the device. This is the default
2225 * implementation. Architecture implementations can override this.
2227 int __weak
pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
2228 enum pcie_reset_state state
)
2234 * pci_set_pcie_reset_state - set reset state for device dev
2235 * @dev: the PCIe device reset
2236 * @state: Reset state to enter into
2238 * Sets the PCI reset state for the device.
2240 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
2242 return pcibios_set_pcie_reset_state(dev
, state
);
2244 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);
2246 void pcie_clear_device_status(struct pci_dev
*dev
)
2250 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
2251 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
2255 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2256 * @dev: PCIe root port or event collector.
2258 void pcie_clear_root_pme_status(struct pci_dev
*dev
)
2260 pcie_capability_set_dword(dev
, PCI_EXP_RTSTA
, PCI_EXP_RTSTA_PME
);
2264 * pci_check_pme_status - Check if given device has generated PME.
2265 * @dev: Device to check.
2267 * Check the PME status of the device and if set, clear it and clear PME enable
2268 * (if set). Return 'true' if PME status and PME enable were both set or
2269 * 'false' otherwise.
2271 bool pci_check_pme_status(struct pci_dev
*dev
)
2280 pmcsr_pos
= dev
->pm_cap
+ PCI_PM_CTRL
;
2281 pci_read_config_word(dev
, pmcsr_pos
, &pmcsr
);
2282 if (!(pmcsr
& PCI_PM_CTRL_PME_STATUS
))
2285 /* Clear PME status. */
2286 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2287 if (pmcsr
& PCI_PM_CTRL_PME_ENABLE
) {
2288 /* Disable PME to avoid interrupt flood. */
2289 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2293 pci_write_config_word(dev
, pmcsr_pos
, pmcsr
);
2299 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2300 * @dev: Device to handle.
2301 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2303 * Check if @dev has generated PME and queue a resume request for it in that
2306 static int pci_pme_wakeup(struct pci_dev
*dev
, void *pme_poll_reset
)
2308 if (pme_poll_reset
&& dev
->pme_poll
)
2309 dev
->pme_poll
= false;
2311 if (pci_check_pme_status(dev
)) {
2312 pci_wakeup_event(dev
);
2313 pm_request_resume(&dev
->dev
);
2319 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2320 * @bus: Top bus of the subtree to walk.
2322 void pci_pme_wakeup_bus(struct pci_bus
*bus
)
2325 pci_walk_bus(bus
, pci_pme_wakeup
, (void *)true);
2330 * pci_pme_capable - check the capability of PCI device to generate PME#
2331 * @dev: PCI device to handle.
2332 * @state: PCI state from which device will issue PME#.
2334 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
2339 return !!(dev
->pme_support
& (1 << state
));
2341 EXPORT_SYMBOL(pci_pme_capable
);
2343 static void pci_pme_list_scan(struct work_struct
*work
)
2345 struct pci_pme_device
*pme_dev
, *n
;
2347 mutex_lock(&pci_pme_list_mutex
);
2348 list_for_each_entry_safe(pme_dev
, n
, &pci_pme_list
, list
) {
2349 if (pme_dev
->dev
->pme_poll
) {
2350 struct pci_dev
*bridge
;
2352 bridge
= pme_dev
->dev
->bus
->self
;
2354 * If bridge is in low power state, the
2355 * configuration space of subordinate devices
2356 * may be not accessible
2358 if (bridge
&& bridge
->current_state
!= PCI_D0
)
2361 * If the device is in D3cold it should not be
2364 if (pme_dev
->dev
->current_state
== PCI_D3cold
)
2367 pci_pme_wakeup(pme_dev
->dev
, NULL
);
2369 list_del(&pme_dev
->list
);
2373 if (!list_empty(&pci_pme_list
))
2374 queue_delayed_work(system_freezable_wq
, &pci_pme_work
,
2375 msecs_to_jiffies(PME_TIMEOUT
));
2376 mutex_unlock(&pci_pme_list_mutex
);
2379 static void __pci_pme_active(struct pci_dev
*dev
, bool enable
)
2383 if (!dev
->pme_support
)
2386 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2387 /* Clear PME_Status by writing 1 to it and enable PME# */
2388 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
2390 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2392 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2396 * pci_pme_restore - Restore PME configuration after config space restore.
2397 * @dev: PCI device to update.
2399 void pci_pme_restore(struct pci_dev
*dev
)
2403 if (!dev
->pme_support
)
2406 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
2407 if (dev
->wakeup_prepared
) {
2408 pmcsr
|= PCI_PM_CTRL_PME_ENABLE
;
2409 pmcsr
&= ~PCI_PM_CTRL_PME_STATUS
;
2411 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
2412 pmcsr
|= PCI_PM_CTRL_PME_STATUS
;
2414 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
2418 * pci_pme_active - enable or disable PCI device's PME# function
2419 * @dev: PCI device to handle.
2420 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2422 * The caller must verify that the device is capable of generating PME# before
2423 * calling this function with @enable equal to 'true'.
2425 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
2427 __pci_pme_active(dev
, enable
);
2430 * PCI (as opposed to PCIe) PME requires that the device have
2431 * its PME# line hooked up correctly. Not all hardware vendors
2432 * do this, so the PME never gets delivered and the device
2433 * remains asleep. The easiest way around this is to
2434 * periodically walk the list of suspended devices and check
2435 * whether any have their PME flag set. The assumption is that
2436 * we'll wake up often enough anyway that this won't be a huge
2437 * hit, and the power savings from the devices will still be a
2440 * Although PCIe uses in-band PME message instead of PME# line
2441 * to report PME, PME does not work for some PCIe devices in
2442 * reality. For example, there are devices that set their PME
2443 * status bits, but don't really bother to send a PME message;
2444 * there are PCI Express Root Ports that don't bother to
2445 * trigger interrupts when they receive PME messages from the
2446 * devices below. So PME poll is used for PCIe devices too.
2449 if (dev
->pme_poll
) {
2450 struct pci_pme_device
*pme_dev
;
2452 pme_dev
= kmalloc(sizeof(struct pci_pme_device
),
2455 pci_warn(dev
, "can't enable PME#\n");
2459 mutex_lock(&pci_pme_list_mutex
);
2460 list_add(&pme_dev
->list
, &pci_pme_list
);
2461 if (list_is_singular(&pci_pme_list
))
2462 queue_delayed_work(system_freezable_wq
,
2464 msecs_to_jiffies(PME_TIMEOUT
));
2465 mutex_unlock(&pci_pme_list_mutex
);
2467 mutex_lock(&pci_pme_list_mutex
);
2468 list_for_each_entry(pme_dev
, &pci_pme_list
, list
) {
2469 if (pme_dev
->dev
== dev
) {
2470 list_del(&pme_dev
->list
);
2475 mutex_unlock(&pci_pme_list_mutex
);
2479 pci_dbg(dev
, "PME# %s\n", enable
? "enabled" : "disabled");
2481 EXPORT_SYMBOL(pci_pme_active
);
2484 * __pci_enable_wake - enable PCI device as wakeup event source
2485 * @dev: PCI device affected
2486 * @state: PCI state from which device will issue wakeup events
2487 * @enable: True to enable event generation; false to disable
2489 * This enables the device as a wakeup event source, or disables it.
2490 * When such events involves platform-specific hooks, those hooks are
2491 * called automatically by this routine.
2493 * Devices with legacy power management (no standard PCI PM capabilities)
2494 * always require such platform hooks.
2497 * 0 is returned on success
2498 * -EINVAL is returned if device is not supposed to wake up the system
2499 * Error code depending on the platform is returned if both the platform and
2500 * the native mechanism fail to enable the generation of wake-up events
2502 static int __pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, bool enable
)
2507 * Bridges that are not power-manageable directly only signal
2508 * wakeup on behalf of subordinate devices which is set up
2509 * elsewhere, so skip them. However, bridges that are
2510 * power-manageable may signal wakeup for themselves (for example,
2511 * on a hotplug event) and they need to be covered here.
2513 if (!pci_power_manageable(dev
))
2516 /* Don't do the same thing twice in a row for one device. */
2517 if (!!enable
== !!dev
->wakeup_prepared
)
2521 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2522 * Anderson we should be doing PME# wake enable followed by ACPI wake
2523 * enable. To disable wake-up we call the platform first, for symmetry.
2530 * Enable PME signaling if the device can signal PME from
2531 * D3cold regardless of whether or not it can signal PME from
2532 * the current target state, because that will allow it to
2533 * signal PME when the hierarchy above it goes into D3cold and
2534 * the device itself ends up in D3cold as a result of that.
2536 if (pci_pme_capable(dev
, state
) || pci_pme_capable(dev
, PCI_D3cold
))
2537 pci_pme_active(dev
, true);
2540 error
= platform_pci_set_wakeup(dev
, true);
2544 dev
->wakeup_prepared
= true;
2546 platform_pci_set_wakeup(dev
, false);
2547 pci_pme_active(dev
, false);
2548 dev
->wakeup_prepared
= false;
2555 * pci_enable_wake - change wakeup settings for a PCI device
2556 * @pci_dev: Target device
2557 * @state: PCI state from which device will issue wakeup events
2558 * @enable: Whether or not to enable event generation
2560 * If @enable is set, check device_may_wakeup() for the device before calling
2561 * __pci_enable_wake() for it.
2563 int pci_enable_wake(struct pci_dev
*pci_dev
, pci_power_t state
, bool enable
)
2565 if (enable
&& !device_may_wakeup(&pci_dev
->dev
))
2568 return __pci_enable_wake(pci_dev
, state
, enable
);
2570 EXPORT_SYMBOL(pci_enable_wake
);
2573 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2574 * @dev: PCI device to prepare
2575 * @enable: True to enable wake-up event generation; false to disable
2577 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2578 * and this function allows them to set that up cleanly - pci_enable_wake()
2579 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2580 * ordering constraints.
2582 * This function only returns error code if the device is not allowed to wake
2583 * up the system from sleep or it is not capable of generating PME# from both
2584 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2586 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
2588 return pci_pme_capable(dev
, PCI_D3cold
) ?
2589 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
2590 pci_enable_wake(dev
, PCI_D3hot
, enable
);
2592 EXPORT_SYMBOL(pci_wake_from_d3
);
2595 * pci_target_state - find an appropriate low power state for a given PCI dev
2597 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2599 * Use underlying platform code to find a supported low power state for @dev.
2600 * If the platform can't manage @dev, return the deepest state from which it
2601 * can generate wake events, based on any available PME info.
2603 static pci_power_t
pci_target_state(struct pci_dev
*dev
, bool wakeup
)
2605 pci_power_t target_state
= PCI_D3hot
;
2607 if (platform_pci_power_manageable(dev
)) {
2609 * Call the platform to find the target state for the device.
2611 pci_power_t state
= platform_pci_choose_state(dev
);
2614 case PCI_POWER_ERROR
:
2619 if (pci_no_d1d2(dev
))
2623 target_state
= state
;
2626 return target_state
;
2630 target_state
= PCI_D0
;
2633 * If the device is in D3cold even though it's not power-manageable by
2634 * the platform, it may have been powered down by non-standard means.
2635 * Best to let it slumber.
2637 if (dev
->current_state
== PCI_D3cold
)
2638 target_state
= PCI_D3cold
;
2640 if (wakeup
&& dev
->pme_support
) {
2641 pci_power_t state
= target_state
;
2644 * Find the deepest state from which the device can generate
2647 while (state
&& !(dev
->pme_support
& (1 << state
)))
2652 else if (dev
->pme_support
& 1)
2656 return target_state
;
2660 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2661 * into a sleep state
2662 * @dev: Device to handle.
2664 * Choose the power state appropriate for the device depending on whether
2665 * it can wake up the system and/or is power manageable by the platform
2666 * (PCI_D3hot is the default) and put the device into that state.
2668 int pci_prepare_to_sleep(struct pci_dev
*dev
)
2670 bool wakeup
= device_may_wakeup(&dev
->dev
);
2671 pci_power_t target_state
= pci_target_state(dev
, wakeup
);
2674 if (target_state
== PCI_POWER_ERROR
)
2678 * There are systems (for example, Intel mobile chips since Coffee
2679 * Lake) where the power drawn while suspended can be significantly
2680 * reduced by disabling PTM on PCIe root ports as this allows the
2681 * port to enter a lower-power PM state and the SoC to reach a
2682 * lower-power idle state as a whole.
2684 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2685 pci_disable_ptm(dev
);
2687 pci_enable_wake(dev
, target_state
, wakeup
);
2689 error
= pci_set_power_state(dev
, target_state
);
2692 pci_enable_wake(dev
, target_state
, false);
2693 pci_restore_ptm_state(dev
);
2698 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2701 * pci_back_from_sleep - turn PCI device on during system-wide transition
2702 * into working state
2703 * @dev: Device to handle.
2705 * Disable device's system wake-up capability and put it into D0.
2707 int pci_back_from_sleep(struct pci_dev
*dev
)
2709 pci_enable_wake(dev
, PCI_D0
, false);
2710 return pci_set_power_state(dev
, PCI_D0
);
2712 EXPORT_SYMBOL(pci_back_from_sleep
);
2715 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2716 * @dev: PCI device being suspended.
2718 * Prepare @dev to generate wake-up events at run time and put it into a low
2721 int pci_finish_runtime_suspend(struct pci_dev
*dev
)
2723 pci_power_t target_state
;
2726 target_state
= pci_target_state(dev
, device_can_wakeup(&dev
->dev
));
2727 if (target_state
== PCI_POWER_ERROR
)
2730 dev
->runtime_d3cold
= target_state
== PCI_D3cold
;
2733 * There are systems (for example, Intel mobile chips since Coffee
2734 * Lake) where the power drawn while suspended can be significantly
2735 * reduced by disabling PTM on PCIe root ports as this allows the
2736 * port to enter a lower-power PM state and the SoC to reach a
2737 * lower-power idle state as a whole.
2739 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
)
2740 pci_disable_ptm(dev
);
2742 __pci_enable_wake(dev
, target_state
, pci_dev_run_wake(dev
));
2744 error
= pci_set_power_state(dev
, target_state
);
2747 pci_enable_wake(dev
, target_state
, false);
2748 pci_restore_ptm_state(dev
);
2749 dev
->runtime_d3cold
= false;
2756 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2757 * @dev: Device to check.
2759 * Return true if the device itself is capable of generating wake-up events
2760 * (through the platform or using the native PCIe PME) or if the device supports
2761 * PME and one of its upstream bridges can generate wake-up events.
2763 bool pci_dev_run_wake(struct pci_dev
*dev
)
2765 struct pci_bus
*bus
= dev
->bus
;
2767 if (!dev
->pme_support
)
2770 /* PME-capable in principle, but not from the target power state */
2771 if (!pci_pme_capable(dev
, pci_target_state(dev
, true)))
2774 if (device_can_wakeup(&dev
->dev
))
2777 while (bus
->parent
) {
2778 struct pci_dev
*bridge
= bus
->self
;
2780 if (device_can_wakeup(&bridge
->dev
))
2786 /* We have reached the root bus. */
2788 return device_can_wakeup(bus
->bridge
);
2792 EXPORT_SYMBOL_GPL(pci_dev_run_wake
);
2795 * pci_dev_need_resume - Check if it is necessary to resume the device.
2796 * @pci_dev: Device to check.
2798 * Return 'true' if the device is not runtime-suspended or it has to be
2799 * reconfigured due to wakeup settings difference between system and runtime
2800 * suspend, or the current power state of it is not suitable for the upcoming
2801 * (system-wide) transition.
2803 bool pci_dev_need_resume(struct pci_dev
*pci_dev
)
2805 struct device
*dev
= &pci_dev
->dev
;
2806 pci_power_t target_state
;
2808 if (!pm_runtime_suspended(dev
) || platform_pci_need_resume(pci_dev
))
2811 target_state
= pci_target_state(pci_dev
, device_may_wakeup(dev
));
2814 * If the earlier platform check has not triggered, D3cold is just power
2815 * removal on top of D3hot, so no need to resume the device in that
2818 return target_state
!= pci_dev
->current_state
&&
2819 target_state
!= PCI_D3cold
&&
2820 pci_dev
->current_state
!= PCI_D3hot
;
2824 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2825 * @pci_dev: Device to check.
2827 * If the device is suspended and it is not configured for system wakeup,
2828 * disable PME for it to prevent it from waking up the system unnecessarily.
2830 * Note that if the device's power state is D3cold and the platform check in
2831 * pci_dev_need_resume() has not triggered, the device's configuration need not
2834 void pci_dev_adjust_pme(struct pci_dev
*pci_dev
)
2836 struct device
*dev
= &pci_dev
->dev
;
2838 spin_lock_irq(&dev
->power
.lock
);
2840 if (pm_runtime_suspended(dev
) && !device_may_wakeup(dev
) &&
2841 pci_dev
->current_state
< PCI_D3cold
)
2842 __pci_pme_active(pci_dev
, false);
2844 spin_unlock_irq(&dev
->power
.lock
);
2848 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2849 * @pci_dev: Device to handle.
2851 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2852 * it might have been disabled during the prepare phase of system suspend if
2853 * the device was not configured for system wakeup.
2855 void pci_dev_complete_resume(struct pci_dev
*pci_dev
)
2857 struct device
*dev
= &pci_dev
->dev
;
2859 if (!pci_dev_run_wake(pci_dev
))
2862 spin_lock_irq(&dev
->power
.lock
);
2864 if (pm_runtime_suspended(dev
) && pci_dev
->current_state
< PCI_D3cold
)
2865 __pci_pme_active(pci_dev
, true);
2867 spin_unlock_irq(&dev
->power
.lock
);
2870 void pci_config_pm_runtime_get(struct pci_dev
*pdev
)
2872 struct device
*dev
= &pdev
->dev
;
2873 struct device
*parent
= dev
->parent
;
2876 pm_runtime_get_sync(parent
);
2877 pm_runtime_get_noresume(dev
);
2879 * pdev->current_state is set to PCI_D3cold during suspending,
2880 * so wait until suspending completes
2882 pm_runtime_barrier(dev
);
2884 * Only need to resume devices in D3cold, because config
2885 * registers are still accessible for devices suspended but
2888 if (pdev
->current_state
== PCI_D3cold
)
2889 pm_runtime_resume(dev
);
2892 void pci_config_pm_runtime_put(struct pci_dev
*pdev
)
2894 struct device
*dev
= &pdev
->dev
;
2895 struct device
*parent
= dev
->parent
;
2897 pm_runtime_put(dev
);
2899 pm_runtime_put_sync(parent
);
2902 static const struct dmi_system_id bridge_d3_blacklist
[] = {
2906 * Gigabyte X299 root port is not marked as hotplug capable
2907 * which allows Linux to power manage it. However, this
2908 * confuses the BIOS SMI handler so don't power manage root
2909 * ports on that system.
2911 .ident
= "X299 DESIGNARE EX-CF",
2913 DMI_MATCH(DMI_BOARD_VENDOR
, "Gigabyte Technology Co., Ltd."),
2914 DMI_MATCH(DMI_BOARD_NAME
, "X299 DESIGNARE EX-CF"),
2922 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2923 * @bridge: Bridge to check
2925 * This function checks if it is possible to move the bridge to D3.
2926 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2928 bool pci_bridge_d3_possible(struct pci_dev
*bridge
)
2930 if (!pci_is_pcie(bridge
))
2933 switch (pci_pcie_type(bridge
)) {
2934 case PCI_EXP_TYPE_ROOT_PORT
:
2935 case PCI_EXP_TYPE_UPSTREAM
:
2936 case PCI_EXP_TYPE_DOWNSTREAM
:
2937 if (pci_bridge_d3_disable
)
2941 * Hotplug ports handled by firmware in System Management Mode
2942 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2944 if (bridge
->is_hotplug_bridge
&& !pciehp_is_native(bridge
))
2947 if (pci_bridge_d3_force
)
2950 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2951 if (bridge
->is_thunderbolt
)
2954 /* Platform might know better if the bridge supports D3 */
2955 if (platform_pci_bridge_d3(bridge
))
2959 * Hotplug ports handled natively by the OS were not validated
2960 * by vendors for runtime D3 at least until 2018 because there
2961 * was no OS support.
2963 if (bridge
->is_hotplug_bridge
)
2966 if (dmi_check_system(bridge_d3_blacklist
))
2970 * It should be safe to put PCIe ports from 2015 or newer
2973 if (dmi_get_bios_year() >= 2015)
2981 static int pci_dev_check_d3cold(struct pci_dev
*dev
, void *data
)
2983 bool *d3cold_ok
= data
;
2985 if (/* The device needs to be allowed to go D3cold ... */
2986 dev
->no_d3cold
|| !dev
->d3cold_allowed
||
2988 /* ... and if it is wakeup capable to do so from D3cold. */
2989 (device_may_wakeup(&dev
->dev
) &&
2990 !pci_pme_capable(dev
, PCI_D3cold
)) ||
2992 /* If it is a bridge it must be allowed to go to D3. */
2993 !pci_power_manageable(dev
))
3001 * pci_bridge_d3_update - Update bridge D3 capabilities
3002 * @dev: PCI device which is changed
3004 * Update upstream bridge PM capabilities accordingly depending on if the
3005 * device PM configuration was changed or the device is being removed. The
3006 * change is also propagated upstream.
3008 void pci_bridge_d3_update(struct pci_dev
*dev
)
3010 bool remove
= !device_is_registered(&dev
->dev
);
3011 struct pci_dev
*bridge
;
3012 bool d3cold_ok
= true;
3014 bridge
= pci_upstream_bridge(dev
);
3015 if (!bridge
|| !pci_bridge_d3_possible(bridge
))
3019 * If D3 is currently allowed for the bridge, removing one of its
3020 * children won't change that.
3022 if (remove
&& bridge
->bridge_d3
)
3026 * If D3 is currently allowed for the bridge and a child is added or
3027 * changed, disallowance of D3 can only be caused by that child, so
3028 * we only need to check that single device, not any of its siblings.
3030 * If D3 is currently not allowed for the bridge, checking the device
3031 * first may allow us to skip checking its siblings.
3034 pci_dev_check_d3cold(dev
, &d3cold_ok
);
3037 * If D3 is currently not allowed for the bridge, this may be caused
3038 * either by the device being changed/removed or any of its siblings,
3039 * so we need to go through all children to find out if one of them
3040 * continues to block D3.
3042 if (d3cold_ok
&& !bridge
->bridge_d3
)
3043 pci_walk_bus(bridge
->subordinate
, pci_dev_check_d3cold
,
3046 if (bridge
->bridge_d3
!= d3cold_ok
) {
3047 bridge
->bridge_d3
= d3cold_ok
;
3048 /* Propagate change to upstream bridges */
3049 pci_bridge_d3_update(bridge
);
3054 * pci_d3cold_enable - Enable D3cold for device
3055 * @dev: PCI device to handle
3057 * This function can be used in drivers to enable D3cold from the device
3058 * they handle. It also updates upstream PCI bridge PM capabilities
3061 void pci_d3cold_enable(struct pci_dev
*dev
)
3063 if (dev
->no_d3cold
) {
3064 dev
->no_d3cold
= false;
3065 pci_bridge_d3_update(dev
);
3068 EXPORT_SYMBOL_GPL(pci_d3cold_enable
);
3071 * pci_d3cold_disable - Disable D3cold for device
3072 * @dev: PCI device to handle
3074 * This function can be used in drivers to disable D3cold from the device
3075 * they handle. It also updates upstream PCI bridge PM capabilities
3078 void pci_d3cold_disable(struct pci_dev
*dev
)
3080 if (!dev
->no_d3cold
) {
3081 dev
->no_d3cold
= true;
3082 pci_bridge_d3_update(dev
);
3085 EXPORT_SYMBOL_GPL(pci_d3cold_disable
);
3088 * pci_pm_init - Initialize PM functions of given PCI device
3089 * @dev: PCI device to handle.
3091 void pci_pm_init(struct pci_dev
*dev
)
3097 pm_runtime_forbid(&dev
->dev
);
3098 pm_runtime_set_active(&dev
->dev
);
3099 pm_runtime_enable(&dev
->dev
);
3100 device_enable_async_suspend(&dev
->dev
);
3101 dev
->wakeup_prepared
= false;
3104 dev
->pme_support
= 0;
3106 /* find PCI PM capability in list */
3107 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
3110 /* Check device's ability to generate PME# */
3111 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
3113 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
3114 pci_err(dev
, "unsupported PM cap regs version (%u)\n",
3115 pmc
& PCI_PM_CAP_VER_MASK
);
3120 dev
->d3hot_delay
= PCI_PM_D3HOT_WAIT
;
3121 dev
->d3cold_delay
= PCI_PM_D3COLD_WAIT
;
3122 dev
->bridge_d3
= pci_bridge_d3_possible(dev
);
3123 dev
->d3cold_allowed
= true;
3125 dev
->d1_support
= false;
3126 dev
->d2_support
= false;
3127 if (!pci_no_d1d2(dev
)) {
3128 if (pmc
& PCI_PM_CAP_D1
)
3129 dev
->d1_support
= true;
3130 if (pmc
& PCI_PM_CAP_D2
)
3131 dev
->d2_support
= true;
3133 if (dev
->d1_support
|| dev
->d2_support
)
3134 pci_info(dev
, "supports%s%s\n",
3135 dev
->d1_support
? " D1" : "",
3136 dev
->d2_support
? " D2" : "");
3139 pmc
&= PCI_PM_CAP_PME_MASK
;
3141 pci_info(dev
, "PME# supported from%s%s%s%s%s\n",
3142 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
3143 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
3144 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
3145 (pmc
& PCI_PM_CAP_PME_D3hot
) ? " D3hot" : "",
3146 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
3147 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
3148 dev
->pme_poll
= true;
3150 * Make device's PM flags reflect the wake-up capability, but
3151 * let the user space enable it to wake up the system as needed.
3153 device_set_wakeup_capable(&dev
->dev
, true);
3154 /* Disable the PME# generation functionality */
3155 pci_pme_active(dev
, false);
3158 pci_read_config_word(dev
, PCI_STATUS
, &status
);
3159 if (status
& PCI_STATUS_IMM_READY
)
3163 static unsigned long pci_ea_flags(struct pci_dev
*dev
, u8 prop
)
3165 unsigned long flags
= IORESOURCE_PCI_FIXED
| IORESOURCE_PCI_EA_BEI
;
3169 case PCI_EA_P_VF_MEM
:
3170 flags
|= IORESOURCE_MEM
;
3172 case PCI_EA_P_MEM_PREFETCH
:
3173 case PCI_EA_P_VF_MEM_PREFETCH
:
3174 flags
|= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
3177 flags
|= IORESOURCE_IO
;
3186 static struct resource
*pci_ea_get_resource(struct pci_dev
*dev
, u8 bei
,
3189 if (bei
<= PCI_EA_BEI_BAR5
&& prop
<= PCI_EA_P_IO
)
3190 return &dev
->resource
[bei
];
3191 #ifdef CONFIG_PCI_IOV
3192 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
&&
3193 (prop
== PCI_EA_P_VF_MEM
|| prop
== PCI_EA_P_VF_MEM_PREFETCH
))
3194 return &dev
->resource
[PCI_IOV_RESOURCES
+
3195 bei
- PCI_EA_BEI_VF_BAR0
];
3197 else if (bei
== PCI_EA_BEI_ROM
)
3198 return &dev
->resource
[PCI_ROM_RESOURCE
];
3203 /* Read an Enhanced Allocation (EA) entry */
3204 static int pci_ea_read(struct pci_dev
*dev
, int offset
)
3206 struct resource
*res
;
3207 int ent_size
, ent_offset
= offset
;
3208 resource_size_t start
, end
;
3209 unsigned long flags
;
3210 u32 dw0
, bei
, base
, max_offset
;
3212 bool support_64
= (sizeof(resource_size_t
) >= 8);
3214 pci_read_config_dword(dev
, ent_offset
, &dw0
);
3217 /* Entry size field indicates DWORDs after 1st */
3218 ent_size
= ((dw0
& PCI_EA_ES
) + 1) << 2;
3220 if (!(dw0
& PCI_EA_ENABLE
)) /* Entry not enabled */
3223 bei
= (dw0
& PCI_EA_BEI
) >> 4;
3224 prop
= (dw0
& PCI_EA_PP
) >> 8;
3227 * If the Property is in the reserved range, try the Secondary
3230 if (prop
> PCI_EA_P_BRIDGE_IO
&& prop
< PCI_EA_P_MEM_RESERVED
)
3231 prop
= (dw0
& PCI_EA_SP
) >> 16;
3232 if (prop
> PCI_EA_P_BRIDGE_IO
)
3235 res
= pci_ea_get_resource(dev
, bei
, prop
);
3237 pci_err(dev
, "Unsupported EA entry BEI: %u\n", bei
);
3241 flags
= pci_ea_flags(dev
, prop
);
3243 pci_err(dev
, "Unsupported EA properties: %#x\n", prop
);
3248 pci_read_config_dword(dev
, ent_offset
, &base
);
3249 start
= (base
& PCI_EA_FIELD_MASK
);
3252 /* Read MaxOffset */
3253 pci_read_config_dword(dev
, ent_offset
, &max_offset
);
3256 /* Read Base MSBs (if 64-bit entry) */
3257 if (base
& PCI_EA_IS_64
) {
3260 pci_read_config_dword(dev
, ent_offset
, &base_upper
);
3263 flags
|= IORESOURCE_MEM_64
;
3265 /* entry starts above 32-bit boundary, can't use */
3266 if (!support_64
&& base_upper
)
3270 start
|= ((u64
)base_upper
<< 32);
3273 end
= start
+ (max_offset
| 0x03);
3275 /* Read MaxOffset MSBs (if 64-bit entry) */
3276 if (max_offset
& PCI_EA_IS_64
) {
3277 u32 max_offset_upper
;
3279 pci_read_config_dword(dev
, ent_offset
, &max_offset_upper
);
3282 flags
|= IORESOURCE_MEM_64
;
3284 /* entry too big, can't use */
3285 if (!support_64
&& max_offset_upper
)
3289 end
+= ((u64
)max_offset_upper
<< 32);
3293 pci_err(dev
, "EA Entry crosses address boundary\n");
3297 if (ent_size
!= ent_offset
- offset
) {
3298 pci_err(dev
, "EA Entry Size (%d) does not match length read (%d)\n",
3299 ent_size
, ent_offset
- offset
);
3303 res
->name
= pci_name(dev
);
3308 if (bei
<= PCI_EA_BEI_BAR5
)
3309 pci_info(dev
, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3311 else if (bei
== PCI_EA_BEI_ROM
)
3312 pci_info(dev
, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3314 else if (bei
>= PCI_EA_BEI_VF_BAR0
&& bei
<= PCI_EA_BEI_VF_BAR5
)
3315 pci_info(dev
, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3316 bei
- PCI_EA_BEI_VF_BAR0
, res
, prop
);
3318 pci_info(dev
, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3322 return offset
+ ent_size
;
3325 /* Enhanced Allocation Initialization */
3326 void pci_ea_init(struct pci_dev
*dev
)
3333 /* find PCI EA capability in list */
3334 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
3338 /* determine the number of entries */
3339 pci_bus_read_config_byte(dev
->bus
, dev
->devfn
, ea
+ PCI_EA_NUM_ENT
,
3341 num_ent
&= PCI_EA_NUM_ENT_MASK
;
3343 offset
= ea
+ PCI_EA_FIRST_ENT
;
3345 /* Skip DWORD 2 for type 1 functions */
3346 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
)
3349 /* parse each EA entry */
3350 for (i
= 0; i
< num_ent
; ++i
)
3351 offset
= pci_ea_read(dev
, offset
);
3354 static void pci_add_saved_cap(struct pci_dev
*pci_dev
,
3355 struct pci_cap_saved_state
*new_cap
)
3357 hlist_add_head(&new_cap
->next
, &pci_dev
->saved_cap_space
);
3361 * _pci_add_cap_save_buffer - allocate buffer for saving given
3362 * capability registers
3363 * @dev: the PCI device
3364 * @cap: the capability to allocate the buffer for
3365 * @extended: Standard or Extended capability ID
3366 * @size: requested size of the buffer
3368 static int _pci_add_cap_save_buffer(struct pci_dev
*dev
, u16 cap
,
3369 bool extended
, unsigned int size
)
3372 struct pci_cap_saved_state
*save_state
;
3375 pos
= pci_find_ext_capability(dev
, cap
);
3377 pos
= pci_find_capability(dev
, cap
);
3382 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
3386 save_state
->cap
.cap_nr
= cap
;
3387 save_state
->cap
.cap_extended
= extended
;
3388 save_state
->cap
.size
= size
;
3389 pci_add_saved_cap(dev
, save_state
);
3394 int pci_add_cap_save_buffer(struct pci_dev
*dev
, char cap
, unsigned int size
)
3396 return _pci_add_cap_save_buffer(dev
, cap
, false, size
);
3399 int pci_add_ext_cap_save_buffer(struct pci_dev
*dev
, u16 cap
, unsigned int size
)
3401 return _pci_add_cap_save_buffer(dev
, cap
, true, size
);
3405 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3406 * @dev: the PCI device
3408 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
3412 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
3413 PCI_EXP_SAVE_REGS
* sizeof(u16
));
3415 pci_err(dev
, "unable to preallocate PCI Express save buffer\n");
3417 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
3419 pci_err(dev
, "unable to preallocate PCI-X save buffer\n");
3421 error
= pci_add_ext_cap_save_buffer(dev
, PCI_EXT_CAP_ID_LTR
,
3424 pci_err(dev
, "unable to allocate suspend buffer for LTR\n");
3426 pci_allocate_vc_save_buffers(dev
);
3429 void pci_free_cap_save_buffers(struct pci_dev
*dev
)
3431 struct pci_cap_saved_state
*tmp
;
3432 struct hlist_node
*n
;
3434 hlist_for_each_entry_safe(tmp
, n
, &dev
->saved_cap_space
, next
)
3439 * pci_configure_ari - enable or disable ARI forwarding
3440 * @dev: the PCI device
3442 * If @dev and its upstream bridge both support ARI, enable ARI in the
3443 * bridge. Otherwise, disable ARI in the bridge.
3445 void pci_configure_ari(struct pci_dev
*dev
)
3448 struct pci_dev
*bridge
;
3450 if (pcie_ari_disabled
|| !pci_is_pcie(dev
) || dev
->devfn
)
3453 bridge
= dev
->bus
->self
;
3457 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3458 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
3461 if (pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
)) {
3462 pcie_capability_set_word(bridge
, PCI_EXP_DEVCTL2
,
3463 PCI_EXP_DEVCTL2_ARI
);
3464 bridge
->ari_enabled
= 1;
3466 pcie_capability_clear_word(bridge
, PCI_EXP_DEVCTL2
,
3467 PCI_EXP_DEVCTL2_ARI
);
3468 bridge
->ari_enabled
= 0;
3472 static bool pci_acs_flags_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3477 pos
= pdev
->acs_cap
;
3482 * Except for egress control, capabilities are either required
3483 * or only required if controllable. Features missing from the
3484 * capability field can therefore be assumed as hard-wired enabled.
3486 pci_read_config_word(pdev
, pos
+ PCI_ACS_CAP
, &cap
);
3487 acs_flags
&= (cap
| PCI_ACS_EC
);
3489 pci_read_config_word(pdev
, pos
+ PCI_ACS_CTRL
, &ctrl
);
3490 return (ctrl
& acs_flags
) == acs_flags
;
3494 * pci_acs_enabled - test ACS against required flags for a given device
3495 * @pdev: device to test
3496 * @acs_flags: required PCI ACS flags
3498 * Return true if the device supports the provided flags. Automatically
3499 * filters out flags that are not implemented on multifunction devices.
3501 * Note that this interface checks the effective ACS capabilities of the
3502 * device rather than the actual capabilities. For instance, most single
3503 * function endpoints are not required to support ACS because they have no
3504 * opportunity for peer-to-peer access. We therefore return 'true'
3505 * regardless of whether the device exposes an ACS capability. This makes
3506 * it much easier for callers of this function to ignore the actual type
3507 * or topology of the device when testing ACS support.
3509 bool pci_acs_enabled(struct pci_dev
*pdev
, u16 acs_flags
)
3513 ret
= pci_dev_specific_acs_enabled(pdev
, acs_flags
);
3518 * Conventional PCI and PCI-X devices never support ACS, either
3519 * effectively or actually. The shared bus topology implies that
3520 * any device on the bus can receive or snoop DMA.
3522 if (!pci_is_pcie(pdev
))
3525 switch (pci_pcie_type(pdev
)) {
3527 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3528 * but since their primary interface is PCI/X, we conservatively
3529 * handle them as we would a non-PCIe device.
3531 case PCI_EXP_TYPE_PCIE_BRIDGE
:
3533 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3534 * applicable... must never implement an ACS Extended Capability...".
3535 * This seems arbitrary, but we take a conservative interpretation
3536 * of this statement.
3538 case PCI_EXP_TYPE_PCI_BRIDGE
:
3539 case PCI_EXP_TYPE_RC_EC
:
3542 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3543 * implement ACS in order to indicate their peer-to-peer capabilities,
3544 * regardless of whether they are single- or multi-function devices.
3546 case PCI_EXP_TYPE_DOWNSTREAM
:
3547 case PCI_EXP_TYPE_ROOT_PORT
:
3548 return pci_acs_flags_enabled(pdev
, acs_flags
);
3550 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3551 * implemented by the remaining PCIe types to indicate peer-to-peer
3552 * capabilities, but only when they are part of a multifunction
3553 * device. The footnote for section 6.12 indicates the specific
3554 * PCIe types included here.
3556 case PCI_EXP_TYPE_ENDPOINT
:
3557 case PCI_EXP_TYPE_UPSTREAM
:
3558 case PCI_EXP_TYPE_LEG_END
:
3559 case PCI_EXP_TYPE_RC_END
:
3560 if (!pdev
->multifunction
)
3563 return pci_acs_flags_enabled(pdev
, acs_flags
);
3567 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3568 * to single function devices with the exception of downstream ports.
3574 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3575 * @start: starting downstream device
3576 * @end: ending upstream device or NULL to search to the root bus
3577 * @acs_flags: required flags
3579 * Walk up a device tree from start to end testing PCI ACS support. If
3580 * any step along the way does not support the required flags, return false.
3582 bool pci_acs_path_enabled(struct pci_dev
*start
,
3583 struct pci_dev
*end
, u16 acs_flags
)
3585 struct pci_dev
*pdev
, *parent
= start
;
3590 if (!pci_acs_enabled(pdev
, acs_flags
))
3593 if (pci_is_root_bus(pdev
->bus
))
3594 return (end
== NULL
);
3596 parent
= pdev
->bus
->self
;
3597 } while (pdev
!= end
);
3603 * pci_acs_init - Initialize ACS if hardware supports it
3604 * @dev: the PCI device
3606 void pci_acs_init(struct pci_dev
*dev
)
3608 dev
->acs_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ACS
);
3611 * Attempt to enable ACS regardless of capability because some Root
3612 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3613 * the standard ACS capability but still support ACS via those
3616 pci_enable_acs(dev
);
3620 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3624 * Helper to find the position of the ctrl register for a BAR.
3625 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3626 * Returns -ENOENT if no ctrl register for the BAR could be found.
3628 static int pci_rebar_find_pos(struct pci_dev
*pdev
, int bar
)
3630 unsigned int pos
, nbars
, i
;
3633 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_REBAR
);
3637 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3638 nbars
= (ctrl
& PCI_REBAR_CTRL_NBAR_MASK
) >>
3639 PCI_REBAR_CTRL_NBAR_SHIFT
;
3641 for (i
= 0; i
< nbars
; i
++, pos
+= 8) {
3644 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3645 bar_idx
= ctrl
& PCI_REBAR_CTRL_BAR_IDX
;
3654 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3656 * @bar: BAR to query
3658 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3659 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3661 u32
pci_rebar_get_possible_sizes(struct pci_dev
*pdev
, int bar
)
3666 pos
= pci_rebar_find_pos(pdev
, bar
);
3670 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CAP
, &cap
);
3671 cap
&= PCI_REBAR_CAP_SIZES
;
3673 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3674 if (pdev
->vendor
== PCI_VENDOR_ID_ATI
&& pdev
->device
== 0x731f &&
3675 bar
== 0 && cap
== 0x7000)
3680 EXPORT_SYMBOL(pci_rebar_get_possible_sizes
);
3683 * pci_rebar_get_current_size - get the current size of a BAR
3685 * @bar: BAR to set size to
3687 * Read the size of a BAR from the resizable BAR config.
3688 * Returns size if found or negative error code.
3690 int pci_rebar_get_current_size(struct pci_dev
*pdev
, int bar
)
3695 pos
= pci_rebar_find_pos(pdev
, bar
);
3699 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3700 return (ctrl
& PCI_REBAR_CTRL_BAR_SIZE
) >> PCI_REBAR_CTRL_BAR_SHIFT
;
3704 * pci_rebar_set_size - set a new size for a BAR
3706 * @bar: BAR to set size to
3707 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3709 * Set the new size of a BAR as defined in the spec.
3710 * Returns zero if resizing was successful, error code otherwise.
3712 int pci_rebar_set_size(struct pci_dev
*pdev
, int bar
, int size
)
3717 pos
= pci_rebar_find_pos(pdev
, bar
);
3721 pci_read_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, &ctrl
);
3722 ctrl
&= ~PCI_REBAR_CTRL_BAR_SIZE
;
3723 ctrl
|= size
<< PCI_REBAR_CTRL_BAR_SHIFT
;
3724 pci_write_config_dword(pdev
, pos
+ PCI_REBAR_CTRL
, ctrl
);
3729 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3730 * @dev: the PCI device
3731 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3732 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3733 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3734 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3736 * Return 0 if all upstream bridges support AtomicOp routing, egress
3737 * blocking is disabled on all upstream ports, and the root port supports
3738 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3739 * AtomicOp completion), or negative otherwise.
3741 int pci_enable_atomic_ops_to_root(struct pci_dev
*dev
, u32 cap_mask
)
3743 struct pci_bus
*bus
= dev
->bus
;
3744 struct pci_dev
*bridge
;
3748 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3749 * in Device Control 2 is reserved in VFs and the PF value applies
3750 * to all associated VFs.
3755 if (!pci_is_pcie(dev
))
3759 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3760 * AtomicOp requesters. For now, we only support endpoints as
3761 * requesters and root ports as completers. No endpoints as
3762 * completers, and no peer-to-peer.
3765 switch (pci_pcie_type(dev
)) {
3766 case PCI_EXP_TYPE_ENDPOINT
:
3767 case PCI_EXP_TYPE_LEG_END
:
3768 case PCI_EXP_TYPE_RC_END
:
3774 while (bus
->parent
) {
3777 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCAP2
, &cap
);
3779 switch (pci_pcie_type(bridge
)) {
3780 /* Ensure switch ports support AtomicOp routing */
3781 case PCI_EXP_TYPE_UPSTREAM
:
3782 case PCI_EXP_TYPE_DOWNSTREAM
:
3783 if (!(cap
& PCI_EXP_DEVCAP2_ATOMIC_ROUTE
))
3787 /* Ensure root port supports all the sizes we care about */
3788 case PCI_EXP_TYPE_ROOT_PORT
:
3789 if ((cap
& cap_mask
) != cap_mask
)
3794 /* Ensure upstream ports don't block AtomicOps on egress */
3795 if (pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
) {
3796 pcie_capability_read_dword(bridge
, PCI_EXP_DEVCTL2
,
3798 if (ctl2
& PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK
)
3805 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
3806 PCI_EXP_DEVCTL2_ATOMIC_REQ
);
3809 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root
);
3812 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3813 * @dev: the PCI device
3814 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3816 * Perform INTx swizzling for a device behind one level of bridge. This is
3817 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3818 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3819 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3820 * the PCI Express Base Specification, Revision 2.1)
3822 u8
pci_swizzle_interrupt_pin(const struct pci_dev
*dev
, u8 pin
)
3826 if (pci_ari_enabled(dev
->bus
))
3829 slot
= PCI_SLOT(dev
->devfn
);
3831 return (((pin
- 1) + slot
) % 4) + 1;
3834 int pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
3842 while (!pci_is_root_bus(dev
->bus
)) {
3843 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3844 dev
= dev
->bus
->self
;
3851 * pci_common_swizzle - swizzle INTx all the way to root bridge
3852 * @dev: the PCI device
3853 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3855 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3856 * bridges all the way up to a PCI root bus.
3858 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
3862 while (!pci_is_root_bus(dev
->bus
)) {
3863 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
3864 dev
= dev
->bus
->self
;
3867 return PCI_SLOT(dev
->devfn
);
3869 EXPORT_SYMBOL_GPL(pci_common_swizzle
);
3872 * pci_release_region - Release a PCI bar
3873 * @pdev: PCI device whose resources were previously reserved by
3874 * pci_request_region()
3875 * @bar: BAR to release
3877 * Releases the PCI I/O and memory resources previously reserved by a
3878 * successful call to pci_request_region(). Call this function only
3879 * after all use of the PCI regions has ceased.
3881 void pci_release_region(struct pci_dev
*pdev
, int bar
)
3883 struct pci_devres
*dr
;
3885 if (pci_resource_len(pdev
, bar
) == 0)
3887 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
3888 release_region(pci_resource_start(pdev
, bar
),
3889 pci_resource_len(pdev
, bar
));
3890 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
3891 release_mem_region(pci_resource_start(pdev
, bar
),
3892 pci_resource_len(pdev
, bar
));
3894 dr
= find_pci_dr(pdev
);
3896 dr
->region_mask
&= ~(1 << bar
);
3898 EXPORT_SYMBOL(pci_release_region
);
3901 * __pci_request_region - Reserved PCI I/O and memory resource
3902 * @pdev: PCI device whose resources are to be reserved
3903 * @bar: BAR to be reserved
3904 * @res_name: Name to be associated with resource.
3905 * @exclusive: whether the region access is exclusive or not
3907 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3908 * being reserved by owner @res_name. Do not access any
3909 * address inside the PCI regions unless this call returns
3912 * If @exclusive is set, then the region is marked so that userspace
3913 * is explicitly not allowed to map the resource via /dev/mem or
3914 * sysfs MMIO access.
3916 * Returns 0 on success, or %EBUSY on error. A warning
3917 * message is also printed on failure.
3919 static int __pci_request_region(struct pci_dev
*pdev
, int bar
,
3920 const char *res_name
, int exclusive
)
3922 struct pci_devres
*dr
;
3924 if (pci_resource_len(pdev
, bar
) == 0)
3927 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
3928 if (!request_region(pci_resource_start(pdev
, bar
),
3929 pci_resource_len(pdev
, bar
), res_name
))
3931 } else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
3932 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
3933 pci_resource_len(pdev
, bar
), res_name
,
3938 dr
= find_pci_dr(pdev
);
3940 dr
->region_mask
|= 1 << bar
;
3945 pci_warn(pdev
, "BAR %d: can't reserve %pR\n", bar
,
3946 &pdev
->resource
[bar
]);
3951 * pci_request_region - Reserve PCI I/O and memory resource
3952 * @pdev: PCI device whose resources are to be reserved
3953 * @bar: BAR to be reserved
3954 * @res_name: Name to be associated with resource
3956 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3957 * being reserved by owner @res_name. Do not access any
3958 * address inside the PCI regions unless this call returns
3961 * Returns 0 on success, or %EBUSY on error. A warning
3962 * message is also printed on failure.
3964 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
3966 return __pci_request_region(pdev
, bar
, res_name
, 0);
3968 EXPORT_SYMBOL(pci_request_region
);
3971 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3972 * @pdev: PCI device whose resources were previously reserved
3973 * @bars: Bitmask of BARs to be released
3975 * Release selected PCI I/O and memory resources previously reserved.
3976 * Call this function only after all use of the PCI regions has ceased.
3978 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
3982 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
3983 if (bars
& (1 << i
))
3984 pci_release_region(pdev
, i
);
3986 EXPORT_SYMBOL(pci_release_selected_regions
);
3988 static int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
3989 const char *res_name
, int excl
)
3993 for (i
= 0; i
< PCI_STD_NUM_BARS
; i
++)
3994 if (bars
& (1 << i
))
3995 if (__pci_request_region(pdev
, i
, res_name
, excl
))
4001 if (bars
& (1 << i
))
4002 pci_release_region(pdev
, i
);
4009 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4010 * @pdev: PCI device whose resources are to be reserved
4011 * @bars: Bitmask of BARs to be requested
4012 * @res_name: Name to be associated with resource
4014 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
4015 const char *res_name
)
4017 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
4019 EXPORT_SYMBOL(pci_request_selected_regions
);
4021 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
, int bars
,
4022 const char *res_name
)
4024 return __pci_request_selected_regions(pdev
, bars
, res_name
,
4025 IORESOURCE_EXCLUSIVE
);
4027 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
4030 * pci_release_regions - Release reserved PCI I/O and memory resources
4031 * @pdev: PCI device whose resources were previously reserved by
4032 * pci_request_regions()
4034 * Releases all PCI I/O and memory resources previously reserved by a
4035 * successful call to pci_request_regions(). Call this function only
4036 * after all use of the PCI regions has ceased.
4039 void pci_release_regions(struct pci_dev
*pdev
)
4041 pci_release_selected_regions(pdev
, (1 << PCI_STD_NUM_BARS
) - 1);
4043 EXPORT_SYMBOL(pci_release_regions
);
4046 * pci_request_regions - Reserve PCI I/O and memory resources
4047 * @pdev: PCI device whose resources are to be reserved
4048 * @res_name: Name to be associated with resource.
4050 * Mark all PCI regions associated with PCI device @pdev as
4051 * being reserved by owner @res_name. Do not access any
4052 * address inside the PCI regions unless this call returns
4055 * Returns 0 on success, or %EBUSY on error. A warning
4056 * message is also printed on failure.
4058 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
4060 return pci_request_selected_regions(pdev
,
4061 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4063 EXPORT_SYMBOL(pci_request_regions
);
4066 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4067 * @pdev: PCI device whose resources are to be reserved
4068 * @res_name: Name to be associated with resource.
4070 * Mark all PCI regions associated with PCI device @pdev as being reserved
4071 * by owner @res_name. Do not access any address inside the PCI regions
4072 * unless this call returns successfully.
4074 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4075 * and the sysfs MMIO access will not be allowed.
4077 * Returns 0 on success, or %EBUSY on error. A warning message is also
4078 * printed on failure.
4080 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
4082 return pci_request_selected_regions_exclusive(pdev
,
4083 ((1 << PCI_STD_NUM_BARS
) - 1), res_name
);
4085 EXPORT_SYMBOL(pci_request_regions_exclusive
);
4088 * Record the PCI IO range (expressed as CPU physical address + size).
4089 * Return a negative value if an error has occurred, zero otherwise
4091 int pci_register_io_range(struct fwnode_handle
*fwnode
, phys_addr_t addr
,
4092 resource_size_t size
)
4096 struct logic_pio_hwaddr
*range
;
4098 if (!size
|| addr
+ size
< addr
)
4101 range
= kzalloc(sizeof(*range
), GFP_ATOMIC
);
4105 range
->fwnode
= fwnode
;
4107 range
->hw_start
= addr
;
4108 range
->flags
= LOGIC_PIO_CPU_MMIO
;
4110 ret
= logic_pio_register_range(range
);
4114 /* Ignore duplicates due to deferred probing */
4122 phys_addr_t
pci_pio_to_address(unsigned long pio
)
4124 phys_addr_t address
= (phys_addr_t
)OF_BAD_ADDR
;
4127 if (pio
>= MMIO_UPPER_LIMIT
)
4130 address
= logic_pio_to_hwaddr(pio
);
4135 EXPORT_SYMBOL_GPL(pci_pio_to_address
);
4137 unsigned long __weak
pci_address_to_pio(phys_addr_t address
)
4140 return logic_pio_trans_cpuaddr(address
);
4142 if (address
> IO_SPACE_LIMIT
)
4143 return (unsigned long)-1;
4145 return (unsigned long) address
;
4150 * pci_remap_iospace - Remap the memory mapped I/O space
4151 * @res: Resource describing the I/O space
4152 * @phys_addr: physical address of range to be mapped
4154 * Remap the memory mapped I/O space described by the @res and the CPU
4155 * physical address @phys_addr into virtual address space. Only
4156 * architectures that have memory mapped IO functions defined (and the
4157 * PCI_IOBASE value defined) should call this function.
4159 int pci_remap_iospace(const struct resource
*res
, phys_addr_t phys_addr
)
4161 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4162 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4164 if (!(res
->flags
& IORESOURCE_IO
))
4167 if (res
->end
> IO_SPACE_LIMIT
)
4170 return ioremap_page_range(vaddr
, vaddr
+ resource_size(res
), phys_addr
,
4171 pgprot_device(PAGE_KERNEL
));
4174 * This architecture does not have memory mapped I/O space,
4175 * so this function should never be called
4177 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4181 EXPORT_SYMBOL(pci_remap_iospace
);
4184 * pci_unmap_iospace - Unmap the memory mapped I/O space
4185 * @res: resource to be unmapped
4187 * Unmap the CPU virtual address @res from virtual address space. Only
4188 * architectures that have memory mapped IO functions defined (and the
4189 * PCI_IOBASE value defined) should call this function.
4191 void pci_unmap_iospace(struct resource
*res
)
4193 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4194 unsigned long vaddr
= (unsigned long)PCI_IOBASE
+ res
->start
;
4196 vunmap_range(vaddr
, vaddr
+ resource_size(res
));
4199 EXPORT_SYMBOL(pci_unmap_iospace
);
4201 static void devm_pci_unmap_iospace(struct device
*dev
, void *ptr
)
4203 struct resource
**res
= ptr
;
4205 pci_unmap_iospace(*res
);
4209 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4210 * @dev: Generic device to remap IO address for
4211 * @res: Resource describing the I/O space
4212 * @phys_addr: physical address of range to be mapped
4214 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4217 int devm_pci_remap_iospace(struct device
*dev
, const struct resource
*res
,
4218 phys_addr_t phys_addr
)
4220 const struct resource
**ptr
;
4223 ptr
= devres_alloc(devm_pci_unmap_iospace
, sizeof(*ptr
), GFP_KERNEL
);
4227 error
= pci_remap_iospace(res
, phys_addr
);
4232 devres_add(dev
, ptr
);
4237 EXPORT_SYMBOL(devm_pci_remap_iospace
);
4240 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4241 * @dev: Generic device to remap IO address for
4242 * @offset: Resource address to map
4243 * @size: Size of map
4245 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4248 void __iomem
*devm_pci_remap_cfgspace(struct device
*dev
,
4249 resource_size_t offset
,
4250 resource_size_t size
)
4252 void __iomem
**ptr
, *addr
;
4254 ptr
= devres_alloc(devm_ioremap_release
, sizeof(*ptr
), GFP_KERNEL
);
4258 addr
= pci_remap_cfgspace(offset
, size
);
4261 devres_add(dev
, ptr
);
4267 EXPORT_SYMBOL(devm_pci_remap_cfgspace
);
4270 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4271 * @dev: generic device to handle the resource for
4272 * @res: configuration space resource to be handled
4274 * Checks that a resource is a valid memory region, requests the memory
4275 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4276 * proper PCI configuration space memory attributes are guaranteed.
4278 * All operations are managed and will be undone on driver detach.
4280 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4281 * on failure. Usage example::
4283 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4284 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4286 * return PTR_ERR(base);
4288 void __iomem
*devm_pci_remap_cfg_resource(struct device
*dev
,
4289 struct resource
*res
)
4291 resource_size_t size
;
4293 void __iomem
*dest_ptr
;
4297 if (!res
|| resource_type(res
) != IORESOURCE_MEM
) {
4298 dev_err(dev
, "invalid resource\n");
4299 return IOMEM_ERR_PTR(-EINVAL
);
4302 size
= resource_size(res
);
4305 name
= devm_kasprintf(dev
, GFP_KERNEL
, "%s %s", dev_name(dev
),
4308 name
= devm_kstrdup(dev
, dev_name(dev
), GFP_KERNEL
);
4310 return IOMEM_ERR_PTR(-ENOMEM
);
4312 if (!devm_request_mem_region(dev
, res
->start
, size
, name
)) {
4313 dev_err(dev
, "can't request region for resource %pR\n", res
);
4314 return IOMEM_ERR_PTR(-EBUSY
);
4317 dest_ptr
= devm_pci_remap_cfgspace(dev
, res
->start
, size
);
4319 dev_err(dev
, "ioremap failed for resource %pR\n", res
);
4320 devm_release_mem_region(dev
, res
->start
, size
);
4321 dest_ptr
= IOMEM_ERR_PTR(-ENOMEM
);
4326 EXPORT_SYMBOL(devm_pci_remap_cfg_resource
);
4328 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
4332 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
4334 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
4336 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
4337 if (cmd
!= old_cmd
) {
4338 pci_dbg(dev
, "%s bus mastering\n",
4339 enable
? "enabling" : "disabling");
4340 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4342 dev
->is_busmaster
= enable
;
4346 * pcibios_setup - process "pci=" kernel boot arguments
4347 * @str: string used to pass in "pci=" kernel boot arguments
4349 * Process kernel boot arguments. This is the default implementation.
4350 * Architecture specific implementations can override this as necessary.
4352 char * __weak __init
pcibios_setup(char *str
)
4358 * pcibios_set_master - enable PCI bus-mastering for device dev
4359 * @dev: the PCI device to enable
4361 * Enables PCI bus-mastering for the device. This is the default
4362 * implementation. Architecture specific implementations can override
4363 * this if necessary.
4365 void __weak
pcibios_set_master(struct pci_dev
*dev
)
4369 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4370 if (pci_is_pcie(dev
))
4373 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
4375 lat
= (64 <= pcibios_max_latency
) ? 64 : pcibios_max_latency
;
4376 else if (lat
> pcibios_max_latency
)
4377 lat
= pcibios_max_latency
;
4381 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, lat
);
4385 * pci_set_master - enables bus-mastering for device dev
4386 * @dev: the PCI device to enable
4388 * Enables bus-mastering on the device and calls pcibios_set_master()
4389 * to do the needed arch specific settings.
4391 void pci_set_master(struct pci_dev
*dev
)
4393 __pci_set_master(dev
, true);
4394 pcibios_set_master(dev
);
4396 EXPORT_SYMBOL(pci_set_master
);
4399 * pci_clear_master - disables bus-mastering for device dev
4400 * @dev: the PCI device to disable
4402 void pci_clear_master(struct pci_dev
*dev
)
4404 __pci_set_master(dev
, false);
4406 EXPORT_SYMBOL(pci_clear_master
);
4409 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4410 * @dev: the PCI device for which MWI is to be enabled
4412 * Helper function for pci_set_mwi.
4413 * Originally copied from drivers/net/acenic.c.
4414 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4416 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4418 int pci_set_cacheline_size(struct pci_dev
*dev
)
4422 if (!pci_cache_line_size
)
4425 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4426 equal to or multiple of the right value. */
4427 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4428 if (cacheline_size
>= pci_cache_line_size
&&
4429 (cacheline_size
% pci_cache_line_size
) == 0)
4432 /* Write the correct value. */
4433 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
4435 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
4436 if (cacheline_size
== pci_cache_line_size
)
4439 pci_dbg(dev
, "cache line size of %d is not supported\n",
4440 pci_cache_line_size
<< 2);
4444 EXPORT_SYMBOL_GPL(pci_set_cacheline_size
);
4447 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4448 * @dev: the PCI device for which MWI is enabled
4450 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4452 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4454 int pci_set_mwi(struct pci_dev
*dev
)
4456 #ifdef PCI_DISABLE_MWI
4462 rc
= pci_set_cacheline_size(dev
);
4466 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4467 if (!(cmd
& PCI_COMMAND_INVALIDATE
)) {
4468 pci_dbg(dev
, "enabling Mem-Wr-Inval\n");
4469 cmd
|= PCI_COMMAND_INVALIDATE
;
4470 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4475 EXPORT_SYMBOL(pci_set_mwi
);
4478 * pcim_set_mwi - a device-managed pci_set_mwi()
4479 * @dev: the PCI device for which MWI is enabled
4481 * Managed pci_set_mwi().
4483 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4485 int pcim_set_mwi(struct pci_dev
*dev
)
4487 struct pci_devres
*dr
;
4489 dr
= find_pci_dr(dev
);
4494 return pci_set_mwi(dev
);
4496 EXPORT_SYMBOL(pcim_set_mwi
);
4499 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4500 * @dev: the PCI device for which MWI is enabled
4502 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4503 * Callers are not required to check the return value.
4505 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4507 int pci_try_set_mwi(struct pci_dev
*dev
)
4509 #ifdef PCI_DISABLE_MWI
4512 return pci_set_mwi(dev
);
4515 EXPORT_SYMBOL(pci_try_set_mwi
);
4518 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4519 * @dev: the PCI device to disable
4521 * Disables PCI Memory-Write-Invalidate transaction on the device
4523 void pci_clear_mwi(struct pci_dev
*dev
)
4525 #ifndef PCI_DISABLE_MWI
4528 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4529 if (cmd
& PCI_COMMAND_INVALIDATE
) {
4530 cmd
&= ~PCI_COMMAND_INVALIDATE
;
4531 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4535 EXPORT_SYMBOL(pci_clear_mwi
);
4538 * pci_disable_parity - disable parity checking for device
4539 * @dev: the PCI device to operate on
4541 * Disable parity checking for device @dev
4543 void pci_disable_parity(struct pci_dev
*dev
)
4547 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
4548 if (cmd
& PCI_COMMAND_PARITY
) {
4549 cmd
&= ~PCI_COMMAND_PARITY
;
4550 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
4555 * pci_intx - enables/disables PCI INTx for device dev
4556 * @pdev: the PCI device to operate on
4557 * @enable: boolean: whether to enable or disable PCI INTx
4559 * Enables/disables PCI INTx for device @pdev
4561 void pci_intx(struct pci_dev
*pdev
, int enable
)
4563 u16 pci_command
, new;
4565 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
4568 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
4570 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
4572 if (new != pci_command
) {
4573 struct pci_devres
*dr
;
4575 pci_write_config_word(pdev
, PCI_COMMAND
, new);
4577 dr
= find_pci_dr(pdev
);
4578 if (dr
&& !dr
->restore_intx
) {
4579 dr
->restore_intx
= 1;
4580 dr
->orig_intx
= !enable
;
4584 EXPORT_SYMBOL_GPL(pci_intx
);
4586 static bool pci_check_and_set_intx_mask(struct pci_dev
*dev
, bool mask
)
4588 struct pci_bus
*bus
= dev
->bus
;
4589 bool mask_updated
= true;
4590 u32 cmd_status_dword
;
4591 u16 origcmd
, newcmd
;
4592 unsigned long flags
;
4596 * We do a single dword read to retrieve both command and status.
4597 * Document assumptions that make this possible.
4599 BUILD_BUG_ON(PCI_COMMAND
% 4);
4600 BUILD_BUG_ON(PCI_COMMAND
+ 2 != PCI_STATUS
);
4602 raw_spin_lock_irqsave(&pci_lock
, flags
);
4604 bus
->ops
->read(bus
, dev
->devfn
, PCI_COMMAND
, 4, &cmd_status_dword
);
4606 irq_pending
= (cmd_status_dword
>> 16) & PCI_STATUS_INTERRUPT
;
4609 * Check interrupt status register to see whether our device
4610 * triggered the interrupt (when masking) or the next IRQ is
4611 * already pending (when unmasking).
4613 if (mask
!= irq_pending
) {
4614 mask_updated
= false;
4618 origcmd
= cmd_status_dword
;
4619 newcmd
= origcmd
& ~PCI_COMMAND_INTX_DISABLE
;
4621 newcmd
|= PCI_COMMAND_INTX_DISABLE
;
4622 if (newcmd
!= origcmd
)
4623 bus
->ops
->write(bus
, dev
->devfn
, PCI_COMMAND
, 2, newcmd
);
4626 raw_spin_unlock_irqrestore(&pci_lock
, flags
);
4628 return mask_updated
;
4632 * pci_check_and_mask_intx - mask INTx on pending interrupt
4633 * @dev: the PCI device to operate on
4635 * Check if the device dev has its INTx line asserted, mask it and return
4636 * true in that case. False is returned if no interrupt was pending.
4638 bool pci_check_and_mask_intx(struct pci_dev
*dev
)
4640 return pci_check_and_set_intx_mask(dev
, true);
4642 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx
);
4645 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4646 * @dev: the PCI device to operate on
4648 * Check if the device dev has its INTx line asserted, unmask it if not and
4649 * return true. False is returned and the mask remains active if there was
4650 * still an interrupt pending.
4652 bool pci_check_and_unmask_intx(struct pci_dev
*dev
)
4654 return pci_check_and_set_intx_mask(dev
, false);
4656 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx
);
4659 * pci_wait_for_pending_transaction - wait for pending transaction
4660 * @dev: the PCI device to operate on
4662 * Return 0 if transaction is pending 1 otherwise.
4664 int pci_wait_for_pending_transaction(struct pci_dev
*dev
)
4666 if (!pci_is_pcie(dev
))
4669 return pci_wait_for_pending(dev
, pci_pcie_cap(dev
) + PCI_EXP_DEVSTA
,
4670 PCI_EXP_DEVSTA_TRPND
);
4672 EXPORT_SYMBOL(pci_wait_for_pending_transaction
);
4675 * pcie_flr - initiate a PCIe function level reset
4676 * @dev: device to reset
4678 * Initiate a function level reset unconditionally on @dev without
4679 * checking any flags and DEVCAP
4681 int pcie_flr(struct pci_dev
*dev
)
4683 if (!pci_wait_for_pending_transaction(dev
))
4684 pci_err(dev
, "timed out waiting for pending transaction; performing function level reset anyway\n");
4686 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_BCR_FLR
);
4692 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4693 * 100ms, but may silently discard requests while the FLR is in
4694 * progress. Wait 100ms before trying to access the device.
4698 return pci_dev_wait(dev
, "FLR", PCIE_RESET_READY_POLL_MS
);
4700 EXPORT_SYMBOL_GPL(pcie_flr
);
4703 * pcie_reset_flr - initiate a PCIe function level reset
4704 * @dev: device to reset
4705 * @probe: if true, return 0 if device can be reset this way
4707 * Initiate a function level reset on @dev.
4709 int pcie_reset_flr(struct pci_dev
*dev
, bool probe
)
4711 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4714 if (!(dev
->devcap
& PCI_EXP_DEVCAP_FLR
))
4720 return pcie_flr(dev
);
4722 EXPORT_SYMBOL_GPL(pcie_reset_flr
);
4724 static int pci_af_flr(struct pci_dev
*dev
, bool probe
)
4729 pos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
4733 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_FLR_RESET
)
4736 pci_read_config_byte(dev
, pos
+ PCI_AF_CAP
, &cap
);
4737 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
4744 * Wait for Transaction Pending bit to clear. A word-aligned test
4745 * is used, so we use the control offset rather than status and shift
4746 * the test bit to match.
4748 if (!pci_wait_for_pending(dev
, pos
+ PCI_AF_CTRL
,
4749 PCI_AF_STATUS_TP
<< 8))
4750 pci_err(dev
, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4752 pci_write_config_byte(dev
, pos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
4758 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4759 * updated 27 July 2006; a device must complete an FLR within
4760 * 100ms, but may silently discard requests while the FLR is in
4761 * progress. Wait 100ms before trying to access the device.
4765 return pci_dev_wait(dev
, "AF_FLR", PCIE_RESET_READY_POLL_MS
);
4769 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4770 * @dev: Device to reset.
4771 * @probe: if true, return 0 if the device can be reset this way.
4773 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4774 * unset, it will be reinitialized internally when going from PCI_D3hot to
4775 * PCI_D0. If that's the case and the device is not in a low-power state
4776 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4778 * NOTE: This causes the caller to sleep for twice the device power transition
4779 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4780 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4781 * Moreover, only devices in D0 can be reset by this function.
4783 static int pci_pm_reset(struct pci_dev
*dev
, bool probe
)
4787 if (!dev
->pm_cap
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_PM_RESET
)
4790 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &csr
);
4791 if (csr
& PCI_PM_CTRL_NO_SOFT_RESET
)
4797 if (dev
->current_state
!= PCI_D0
)
4800 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4802 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4803 pci_dev_d3_sleep(dev
);
4805 csr
&= ~PCI_PM_CTRL_STATE_MASK
;
4807 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, csr
);
4808 pci_dev_d3_sleep(dev
);
4810 return pci_dev_wait(dev
, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS
);
4814 * pcie_wait_for_link_delay - Wait until link is active or inactive
4815 * @pdev: Bridge device
4816 * @active: waiting for active or inactive?
4817 * @delay: Delay to wait after link has become active (in ms)
4819 * Use this to wait till link becomes active or inactive.
4821 static bool pcie_wait_for_link_delay(struct pci_dev
*pdev
, bool active
,
4829 * Some controllers might not implement link active reporting. In this
4830 * case, we wait for 1000 ms + any delay requested by the caller.
4832 if (!pdev
->link_active_reporting
) {
4833 msleep(timeout
+ delay
);
4838 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4839 * after which we should expect an link active if the reset was
4840 * successful. If so, software must wait a minimum 100ms before sending
4841 * configuration requests to devices downstream this port.
4843 * If the link fails to activate, either the device was physically
4844 * removed or the link is permanently failed.
4849 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
4850 ret
= !!(lnk_status
& PCI_EXP_LNKSTA_DLLLA
);
4861 return ret
== active
;
4865 * pcie_wait_for_link - Wait until link is active or inactive
4866 * @pdev: Bridge device
4867 * @active: waiting for active or inactive?
4869 * Use this to wait till link becomes active or inactive.
4871 bool pcie_wait_for_link(struct pci_dev
*pdev
, bool active
)
4873 return pcie_wait_for_link_delay(pdev
, active
, 100);
4877 * Find maximum D3cold delay required by all the devices on the bus. The
4878 * spec says 100 ms, but firmware can lower it and we allow drivers to
4879 * increase it as well.
4881 * Called with @pci_bus_sem locked for reading.
4883 static int pci_bus_max_d3cold_delay(const struct pci_bus
*bus
)
4885 const struct pci_dev
*pdev
;
4886 int min_delay
= 100;
4889 list_for_each_entry(pdev
, &bus
->devices
, bus_list
) {
4890 if (pdev
->d3cold_delay
< min_delay
)
4891 min_delay
= pdev
->d3cold_delay
;
4892 if (pdev
->d3cold_delay
> max_delay
)
4893 max_delay
= pdev
->d3cold_delay
;
4896 return max(min_delay
, max_delay
);
4900 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4903 * Handle necessary delays before access to the devices on the secondary
4904 * side of the bridge are permitted after D3cold to D0 transition.
4906 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4907 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4910 void pci_bridge_wait_for_secondary_bus(struct pci_dev
*dev
)
4912 struct pci_dev
*child
;
4915 if (pci_dev_is_disconnected(dev
))
4918 if (!pci_is_bridge(dev
) || !dev
->bridge_d3
)
4921 down_read(&pci_bus_sem
);
4924 * We only deal with devices that are present currently on the bus.
4925 * For any hot-added devices the access delay is handled in pciehp
4926 * board_added(). In case of ACPI hotplug the firmware is expected
4927 * to configure the devices before OS is notified.
4929 if (!dev
->subordinate
|| list_empty(&dev
->subordinate
->devices
)) {
4930 up_read(&pci_bus_sem
);
4934 /* Take d3cold_delay requirements into account */
4935 delay
= pci_bus_max_d3cold_delay(dev
->subordinate
);
4937 up_read(&pci_bus_sem
);
4941 child
= list_first_entry(&dev
->subordinate
->devices
, struct pci_dev
,
4943 up_read(&pci_bus_sem
);
4946 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4947 * accessing the device after reset (that is 1000 ms + 100 ms). In
4948 * practice this should not be needed because we don't do power
4949 * management for them (see pci_bridge_d3_possible()).
4951 if (!pci_is_pcie(dev
)) {
4952 pci_dbg(dev
, "waiting %d ms for secondary bus\n", 1000 + delay
);
4953 msleep(1000 + delay
);
4958 * For PCIe downstream and root ports that do not support speeds
4959 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4960 * speeds (gen3) we need to wait first for the data link layer to
4963 * However, 100 ms is the minimum and the PCIe spec says the
4964 * software must allow at least 1s before it can determine that the
4965 * device that did not respond is a broken device. There is
4966 * evidence that 100 ms is not always enough, for example certain
4967 * Titan Ridge xHCI controller does not always respond to
4968 * configuration requests if we only wait for 100 ms (see
4969 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4971 * Therefore we wait for 100 ms and check for the device presence.
4972 * If it is still not present give it an additional 100 ms.
4974 if (!pcie_downstream_port(dev
))
4977 if (pcie_get_speed_cap(dev
) <= PCIE_SPEED_5_0GT
) {
4978 pci_dbg(dev
, "waiting %d ms for downstream link\n", delay
);
4981 pci_dbg(dev
, "waiting %d ms for downstream link, after activation\n",
4983 if (!pcie_wait_for_link_delay(dev
, true, delay
)) {
4984 /* Did not train, no need to wait any further */
4985 pci_info(dev
, "Data Link Layer Link Active not set in 1000 msec\n");
4990 if (!pci_device_is_present(child
)) {
4991 pci_dbg(child
, "waiting additional %d ms to become accessible\n", delay
);
4996 void pci_reset_secondary_bus(struct pci_dev
*dev
)
5000 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &ctrl
);
5001 ctrl
|= PCI_BRIDGE_CTL_BUS_RESET
;
5002 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5005 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5006 * this to 2ms to ensure that we meet the minimum requirement.
5010 ctrl
&= ~PCI_BRIDGE_CTL_BUS_RESET
;
5011 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, ctrl
);
5014 * Trhfa for conventional PCI is 2^25 clock cycles.
5015 * Assuming a minimum 33MHz clock this results in a 1s
5016 * delay before we can consider subordinate devices to
5017 * be re-initialized. PCIe has some ways to shorten this,
5018 * but we don't make use of them yet.
5023 void __weak
pcibios_reset_secondary_bus(struct pci_dev
*dev
)
5025 pci_reset_secondary_bus(dev
);
5029 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5030 * @dev: Bridge device
5032 * Use the bridge control register to assert reset on the secondary bus.
5033 * Devices on the secondary bus are left in power-on state.
5035 int pci_bridge_secondary_bus_reset(struct pci_dev
*dev
)
5037 pcibios_reset_secondary_bus(dev
);
5039 return pci_dev_wait(dev
, "bus reset", PCIE_RESET_READY_POLL_MS
);
5041 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset
);
5043 static int pci_parent_bus_reset(struct pci_dev
*dev
, bool probe
)
5045 struct pci_dev
*pdev
;
5047 if (pci_is_root_bus(dev
->bus
) || dev
->subordinate
||
5048 !dev
->bus
->self
|| dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5051 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
5058 return pci_bridge_secondary_bus_reset(dev
->bus
->self
);
5061 static int pci_reset_hotplug_slot(struct hotplug_slot
*hotplug
, bool probe
)
5065 if (!hotplug
|| !try_module_get(hotplug
->owner
))
5068 if (hotplug
->ops
->reset_slot
)
5069 rc
= hotplug
->ops
->reset_slot(hotplug
, probe
);
5071 module_put(hotplug
->owner
);
5076 static int pci_dev_reset_slot_function(struct pci_dev
*dev
, bool probe
)
5078 if (dev
->multifunction
|| dev
->subordinate
|| !dev
->slot
||
5079 dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
)
5082 return pci_reset_hotplug_slot(dev
->slot
->hotplug
, probe
);
5085 static int pci_reset_bus_function(struct pci_dev
*dev
, bool probe
)
5089 rc
= pci_dev_reset_slot_function(dev
, probe
);
5092 return pci_parent_bus_reset(dev
, probe
);
5095 static void pci_dev_lock(struct pci_dev
*dev
)
5097 pci_cfg_access_lock(dev
);
5098 /* block PM suspend, driver probe, etc. */
5099 device_lock(&dev
->dev
);
5102 /* Return 1 on successful lock, 0 on contention */
5103 int pci_dev_trylock(struct pci_dev
*dev
)
5105 if (pci_cfg_access_trylock(dev
)) {
5106 if (device_trylock(&dev
->dev
))
5108 pci_cfg_access_unlock(dev
);
5113 EXPORT_SYMBOL_GPL(pci_dev_trylock
);
5115 void pci_dev_unlock(struct pci_dev
*dev
)
5117 device_unlock(&dev
->dev
);
5118 pci_cfg_access_unlock(dev
);
5120 EXPORT_SYMBOL_GPL(pci_dev_unlock
);
5122 static void pci_dev_save_and_disable(struct pci_dev
*dev
)
5124 struct pci_driver
*drv
= to_pci_driver(dev
->dev
.driver
);
5125 const struct pci_error_handlers
*err_handler
=
5126 drv
? drv
->err_handler
: NULL
;
5129 * drv->err_handler->reset_prepare() is protected against races
5130 * with ->remove() by the device lock, which must be held by the
5133 if (err_handler
&& err_handler
->reset_prepare
)
5134 err_handler
->reset_prepare(dev
);
5137 * Wake-up device prior to save. PM registers default to D0 after
5138 * reset and a simple register restore doesn't reliably return
5139 * to a non-D0 state anyway.
5141 pci_set_power_state(dev
, PCI_D0
);
5143 pci_save_state(dev
);
5145 * Disable the device by clearing the Command register, except for
5146 * INTx-disable which is set. This not only disables MMIO and I/O port
5147 * BARs, but also prevents the device from being Bus Master, preventing
5148 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5149 * compliant devices, INTx-disable prevents legacy interrupts.
5151 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
5154 static void pci_dev_restore(struct pci_dev
*dev
)
5156 struct pci_driver
*drv
= to_pci_driver(dev
->dev
.driver
);
5157 const struct pci_error_handlers
*err_handler
=
5158 drv
? drv
->err_handler
: NULL
;
5160 pci_restore_state(dev
);
5163 * drv->err_handler->reset_done() is protected against races with
5164 * ->remove() by the device lock, which must be held by the caller.
5166 if (err_handler
&& err_handler
->reset_done
)
5167 err_handler
->reset_done(dev
);
5170 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5171 static const struct pci_reset_fn_method pci_reset_fn_methods
[] = {
5173 { pci_dev_specific_reset
, .name
= "device_specific" },
5174 { pci_dev_acpi_reset
, .name
= "acpi" },
5175 { pcie_reset_flr
, .name
= "flr" },
5176 { pci_af_flr
, .name
= "af_flr" },
5177 { pci_pm_reset
, .name
= "pm" },
5178 { pci_reset_bus_function
, .name
= "bus" },
5181 static ssize_t
reset_method_show(struct device
*dev
,
5182 struct device_attribute
*attr
, char *buf
)
5184 struct pci_dev
*pdev
= to_pci_dev(dev
);
5188 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5189 m
= pdev
->reset_methods
[i
];
5193 len
+= sysfs_emit_at(buf
, len
, "%s%s", len
? " " : "",
5194 pci_reset_fn_methods
[m
].name
);
5198 len
+= sysfs_emit_at(buf
, len
, "\n");
5203 static int reset_method_lookup(const char *name
)
5207 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5208 if (sysfs_streq(name
, pci_reset_fn_methods
[m
].name
))
5212 return 0; /* not found */
5215 static ssize_t
reset_method_store(struct device
*dev
,
5216 struct device_attribute
*attr
,
5217 const char *buf
, size_t count
)
5219 struct pci_dev
*pdev
= to_pci_dev(dev
);
5220 char *options
, *name
;
5222 u8 reset_methods
[PCI_NUM_RESET_METHODS
] = { 0 };
5224 if (sysfs_streq(buf
, "")) {
5225 pdev
->reset_methods
[0] = 0;
5226 pci_warn(pdev
, "All device reset methods disabled by user");
5230 if (sysfs_streq(buf
, "default")) {
5231 pci_init_reset_methods(pdev
);
5235 options
= kstrndup(buf
, count
, GFP_KERNEL
);
5240 while ((name
= strsep(&options
, " ")) != NULL
) {
5241 if (sysfs_streq(name
, ""))
5246 m
= reset_method_lookup(name
);
5248 pci_err(pdev
, "Invalid reset method '%s'", name
);
5252 if (pci_reset_fn_methods
[m
].reset_fn(pdev
, PCI_RESET_PROBE
)) {
5253 pci_err(pdev
, "Unsupported reset method '%s'", name
);
5257 if (n
== PCI_NUM_RESET_METHODS
- 1) {
5258 pci_err(pdev
, "Too many reset methods\n");
5262 reset_methods
[n
++] = m
;
5265 reset_methods
[n
] = 0;
5267 /* Warn if dev-specific supported but not highest priority */
5268 if (pci_reset_fn_methods
[1].reset_fn(pdev
, PCI_RESET_PROBE
) == 0 &&
5269 reset_methods
[0] != 1)
5270 pci_warn(pdev
, "Device-specific reset disabled/de-prioritized by user");
5271 memcpy(pdev
->reset_methods
, reset_methods
, sizeof(pdev
->reset_methods
));
5276 /* Leave previous methods unchanged */
5280 static DEVICE_ATTR_RW(reset_method
);
5282 static struct attribute
*pci_dev_reset_method_attrs
[] = {
5283 &dev_attr_reset_method
.attr
,
5287 static umode_t
pci_dev_reset_method_attr_is_visible(struct kobject
*kobj
,
5288 struct attribute
*a
, int n
)
5290 struct pci_dev
*pdev
= to_pci_dev(kobj_to_dev(kobj
));
5292 if (!pci_reset_supported(pdev
))
5298 const struct attribute_group pci_dev_reset_method_attr_group
= {
5299 .attrs
= pci_dev_reset_method_attrs
,
5300 .is_visible
= pci_dev_reset_method_attr_is_visible
,
5304 * __pci_reset_function_locked - reset a PCI device function while holding
5305 * the @dev mutex lock.
5306 * @dev: PCI device to reset
5308 * Some devices allow an individual function to be reset without affecting
5309 * other functions in the same device. The PCI device must be responsive
5310 * to PCI config space in order to use this function.
5312 * The device function is presumed to be unused and the caller is holding
5313 * the device mutex lock when this function is called.
5315 * Resetting the device will make the contents of PCI configuration space
5316 * random, so any caller of this must be prepared to reinitialise the
5317 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5320 * Returns 0 if the device function was successfully reset or negative if the
5321 * device doesn't support resetting a single function.
5323 int __pci_reset_function_locked(struct pci_dev
*dev
)
5325 int i
, m
, rc
= -ENOTTY
;
5330 * A reset method returns -ENOTTY if it doesn't support this device and
5331 * we should try the next method.
5333 * If it returns 0 (success), we're finished. If it returns any other
5334 * error, we're also finished: this indicates that further reset
5335 * mechanisms might be broken on the device.
5337 for (i
= 0; i
< PCI_NUM_RESET_METHODS
; i
++) {
5338 m
= dev
->reset_methods
[i
];
5342 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_DO_RESET
);
5351 EXPORT_SYMBOL_GPL(__pci_reset_function_locked
);
5354 * pci_init_reset_methods - check whether device can be safely reset
5355 * and store supported reset mechanisms.
5356 * @dev: PCI device to check for reset mechanisms
5358 * Some devices allow an individual function to be reset without affecting
5359 * other functions in the same device. The PCI device must be in D0-D3hot
5362 * Stores reset mechanisms supported by device in reset_methods byte array
5363 * which is a member of struct pci_dev.
5365 void pci_init_reset_methods(struct pci_dev
*dev
)
5369 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods
) != PCI_NUM_RESET_METHODS
);
5374 for (m
= 1; m
< PCI_NUM_RESET_METHODS
; m
++) {
5375 rc
= pci_reset_fn_methods
[m
].reset_fn(dev
, PCI_RESET_PROBE
);
5377 dev
->reset_methods
[i
++] = m
;
5378 else if (rc
!= -ENOTTY
)
5382 dev
->reset_methods
[i
] = 0;
5386 * pci_reset_function - quiesce and reset a PCI device function
5387 * @dev: PCI device to reset
5389 * Some devices allow an individual function to be reset without affecting
5390 * other functions in the same device. The PCI device must be responsive
5391 * to PCI config space in order to use this function.
5393 * This function does not just reset the PCI portion of a device, but
5394 * clears all the state associated with the device. This function differs
5395 * from __pci_reset_function_locked() in that it saves and restores device state
5396 * over the reset and takes the PCI device lock.
5398 * Returns 0 if the device function was successfully reset or negative if the
5399 * device doesn't support resetting a single function.
5401 int pci_reset_function(struct pci_dev
*dev
)
5405 if (!pci_reset_supported(dev
))
5409 pci_dev_save_and_disable(dev
);
5411 rc
= __pci_reset_function_locked(dev
);
5413 pci_dev_restore(dev
);
5414 pci_dev_unlock(dev
);
5418 EXPORT_SYMBOL_GPL(pci_reset_function
);
5421 * pci_reset_function_locked - quiesce and reset a PCI device function
5422 * @dev: PCI device to reset
5424 * Some devices allow an individual function to be reset without affecting
5425 * other functions in the same device. The PCI device must be responsive
5426 * to PCI config space in order to use this function.
5428 * This function does not just reset the PCI portion of a device, but
5429 * clears all the state associated with the device. This function differs
5430 * from __pci_reset_function_locked() in that it saves and restores device state
5431 * over the reset. It also differs from pci_reset_function() in that it
5432 * requires the PCI device lock to be held.
5434 * Returns 0 if the device function was successfully reset or negative if the
5435 * device doesn't support resetting a single function.
5437 int pci_reset_function_locked(struct pci_dev
*dev
)
5441 if (!pci_reset_supported(dev
))
5444 pci_dev_save_and_disable(dev
);
5446 rc
= __pci_reset_function_locked(dev
);
5448 pci_dev_restore(dev
);
5452 EXPORT_SYMBOL_GPL(pci_reset_function_locked
);
5455 * pci_try_reset_function - quiesce and reset a PCI device function
5456 * @dev: PCI device to reset
5458 * Same as above, except return -EAGAIN if unable to lock device.
5460 int pci_try_reset_function(struct pci_dev
*dev
)
5464 if (!pci_reset_supported(dev
))
5467 if (!pci_dev_trylock(dev
))
5470 pci_dev_save_and_disable(dev
);
5471 rc
= __pci_reset_function_locked(dev
);
5472 pci_dev_restore(dev
);
5473 pci_dev_unlock(dev
);
5477 EXPORT_SYMBOL_GPL(pci_try_reset_function
);
5479 /* Do any devices on or below this bus prevent a bus reset? */
5480 static bool pci_bus_resetable(struct pci_bus
*bus
)
5482 struct pci_dev
*dev
;
5485 if (bus
->self
&& (bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5488 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5489 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5490 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5497 /* Lock devices from the top of the tree down */
5498 static void pci_bus_lock(struct pci_bus
*bus
)
5500 struct pci_dev
*dev
;
5502 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5504 if (dev
->subordinate
)
5505 pci_bus_lock(dev
->subordinate
);
5509 /* Unlock devices from the bottom of the tree up */
5510 static void pci_bus_unlock(struct pci_bus
*bus
)
5512 struct pci_dev
*dev
;
5514 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5515 if (dev
->subordinate
)
5516 pci_bus_unlock(dev
->subordinate
);
5517 pci_dev_unlock(dev
);
5521 /* Return 1 on successful lock, 0 on contention */
5522 static int pci_bus_trylock(struct pci_bus
*bus
)
5524 struct pci_dev
*dev
;
5526 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5527 if (!pci_dev_trylock(dev
))
5529 if (dev
->subordinate
) {
5530 if (!pci_bus_trylock(dev
->subordinate
)) {
5531 pci_dev_unlock(dev
);
5539 list_for_each_entry_continue_reverse(dev
, &bus
->devices
, bus_list
) {
5540 if (dev
->subordinate
)
5541 pci_bus_unlock(dev
->subordinate
);
5542 pci_dev_unlock(dev
);
5547 /* Do any devices on or below this slot prevent a bus reset? */
5548 static bool pci_slot_resetable(struct pci_slot
*slot
)
5550 struct pci_dev
*dev
;
5552 if (slot
->bus
->self
&&
5553 (slot
->bus
->self
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
))
5556 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5557 if (!dev
->slot
|| dev
->slot
!= slot
)
5559 if (dev
->dev_flags
& PCI_DEV_FLAGS_NO_BUS_RESET
||
5560 (dev
->subordinate
&& !pci_bus_resetable(dev
->subordinate
)))
5567 /* Lock devices from the top of the tree down */
5568 static void pci_slot_lock(struct pci_slot
*slot
)
5570 struct pci_dev
*dev
;
5572 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5573 if (!dev
->slot
|| dev
->slot
!= slot
)
5576 if (dev
->subordinate
)
5577 pci_bus_lock(dev
->subordinate
);
5581 /* Unlock devices from the bottom of the tree up */
5582 static void pci_slot_unlock(struct pci_slot
*slot
)
5584 struct pci_dev
*dev
;
5586 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5587 if (!dev
->slot
|| dev
->slot
!= slot
)
5589 if (dev
->subordinate
)
5590 pci_bus_unlock(dev
->subordinate
);
5591 pci_dev_unlock(dev
);
5595 /* Return 1 on successful lock, 0 on contention */
5596 static int pci_slot_trylock(struct pci_slot
*slot
)
5598 struct pci_dev
*dev
;
5600 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5601 if (!dev
->slot
|| dev
->slot
!= slot
)
5603 if (!pci_dev_trylock(dev
))
5605 if (dev
->subordinate
) {
5606 if (!pci_bus_trylock(dev
->subordinate
)) {
5607 pci_dev_unlock(dev
);
5615 list_for_each_entry_continue_reverse(dev
,
5616 &slot
->bus
->devices
, bus_list
) {
5617 if (!dev
->slot
|| dev
->slot
!= slot
)
5619 if (dev
->subordinate
)
5620 pci_bus_unlock(dev
->subordinate
);
5621 pci_dev_unlock(dev
);
5627 * Save and disable devices from the top of the tree down while holding
5628 * the @dev mutex lock for the entire tree.
5630 static void pci_bus_save_and_disable_locked(struct pci_bus
*bus
)
5632 struct pci_dev
*dev
;
5634 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5635 pci_dev_save_and_disable(dev
);
5636 if (dev
->subordinate
)
5637 pci_bus_save_and_disable_locked(dev
->subordinate
);
5642 * Restore devices from top of the tree down while holding @dev mutex lock
5643 * for the entire tree. Parent bridges need to be restored before we can
5644 * get to subordinate devices.
5646 static void pci_bus_restore_locked(struct pci_bus
*bus
)
5648 struct pci_dev
*dev
;
5650 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
5651 pci_dev_restore(dev
);
5652 if (dev
->subordinate
)
5653 pci_bus_restore_locked(dev
->subordinate
);
5658 * Save and disable devices from the top of the tree down while holding
5659 * the @dev mutex lock for the entire tree.
5661 static void pci_slot_save_and_disable_locked(struct pci_slot
*slot
)
5663 struct pci_dev
*dev
;
5665 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5666 if (!dev
->slot
|| dev
->slot
!= slot
)
5668 pci_dev_save_and_disable(dev
);
5669 if (dev
->subordinate
)
5670 pci_bus_save_and_disable_locked(dev
->subordinate
);
5675 * Restore devices from top of the tree down while holding @dev mutex lock
5676 * for the entire tree. Parent bridges need to be restored before we can
5677 * get to subordinate devices.
5679 static void pci_slot_restore_locked(struct pci_slot
*slot
)
5681 struct pci_dev
*dev
;
5683 list_for_each_entry(dev
, &slot
->bus
->devices
, bus_list
) {
5684 if (!dev
->slot
|| dev
->slot
!= slot
)
5686 pci_dev_restore(dev
);
5687 if (dev
->subordinate
)
5688 pci_bus_restore_locked(dev
->subordinate
);
5692 static int pci_slot_reset(struct pci_slot
*slot
, bool probe
)
5696 if (!slot
|| !pci_slot_resetable(slot
))
5700 pci_slot_lock(slot
);
5704 rc
= pci_reset_hotplug_slot(slot
->hotplug
, probe
);
5707 pci_slot_unlock(slot
);
5713 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5714 * @slot: PCI slot to probe
5716 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5718 int pci_probe_reset_slot(struct pci_slot
*slot
)
5720 return pci_slot_reset(slot
, PCI_RESET_PROBE
);
5722 EXPORT_SYMBOL_GPL(pci_probe_reset_slot
);
5725 * __pci_reset_slot - Try to reset a PCI slot
5726 * @slot: PCI slot to reset
5728 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5729 * independent of other slots. For instance, some slots may support slot power
5730 * control. In the case of a 1:1 bus to slot architecture, this function may
5731 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5732 * Generally a slot reset should be attempted before a bus reset. All of the
5733 * function of the slot and any subordinate buses behind the slot are reset
5734 * through this function. PCI config space of all devices in the slot and
5735 * behind the slot is saved before and restored after reset.
5737 * Same as above except return -EAGAIN if the slot cannot be locked
5739 static int __pci_reset_slot(struct pci_slot
*slot
)
5743 rc
= pci_slot_reset(slot
, PCI_RESET_PROBE
);
5747 if (pci_slot_trylock(slot
)) {
5748 pci_slot_save_and_disable_locked(slot
);
5750 rc
= pci_reset_hotplug_slot(slot
->hotplug
, PCI_RESET_DO_RESET
);
5751 pci_slot_restore_locked(slot
);
5752 pci_slot_unlock(slot
);
5759 static int pci_bus_reset(struct pci_bus
*bus
, bool probe
)
5763 if (!bus
->self
|| !pci_bus_resetable(bus
))
5773 ret
= pci_bridge_secondary_bus_reset(bus
->self
);
5775 pci_bus_unlock(bus
);
5781 * pci_bus_error_reset - reset the bridge's subordinate bus
5782 * @bridge: The parent device that connects to the bus to reset
5784 * This function will first try to reset the slots on this bus if the method is
5785 * available. If slot reset fails or is not available, this will fall back to a
5786 * secondary bus reset.
5788 int pci_bus_error_reset(struct pci_dev
*bridge
)
5790 struct pci_bus
*bus
= bridge
->subordinate
;
5791 struct pci_slot
*slot
;
5796 mutex_lock(&pci_slot_mutex
);
5797 if (list_empty(&bus
->slots
))
5800 list_for_each_entry(slot
, &bus
->slots
, list
)
5801 if (pci_probe_reset_slot(slot
))
5804 list_for_each_entry(slot
, &bus
->slots
, list
)
5805 if (pci_slot_reset(slot
, PCI_RESET_DO_RESET
))
5808 mutex_unlock(&pci_slot_mutex
);
5811 mutex_unlock(&pci_slot_mutex
);
5812 return pci_bus_reset(bridge
->subordinate
, PCI_RESET_DO_RESET
);
5816 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5817 * @bus: PCI bus to probe
5819 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5821 int pci_probe_reset_bus(struct pci_bus
*bus
)
5823 return pci_bus_reset(bus
, PCI_RESET_PROBE
);
5825 EXPORT_SYMBOL_GPL(pci_probe_reset_bus
);
5828 * __pci_reset_bus - Try to reset a PCI bus
5829 * @bus: top level PCI bus to reset
5831 * Same as above except return -EAGAIN if the bus cannot be locked
5833 static int __pci_reset_bus(struct pci_bus
*bus
)
5837 rc
= pci_bus_reset(bus
, PCI_RESET_PROBE
);
5841 if (pci_bus_trylock(bus
)) {
5842 pci_bus_save_and_disable_locked(bus
);
5844 rc
= pci_bridge_secondary_bus_reset(bus
->self
);
5845 pci_bus_restore_locked(bus
);
5846 pci_bus_unlock(bus
);
5854 * pci_reset_bus - Try to reset a PCI bus
5855 * @pdev: top level PCI device to reset via slot/bus
5857 * Same as above except return -EAGAIN if the bus cannot be locked
5859 int pci_reset_bus(struct pci_dev
*pdev
)
5861 return (!pci_probe_reset_slot(pdev
->slot
)) ?
5862 __pci_reset_slot(pdev
->slot
) : __pci_reset_bus(pdev
->bus
);
5864 EXPORT_SYMBOL_GPL(pci_reset_bus
);
5867 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5868 * @dev: PCI device to query
5870 * Returns mmrbc: maximum designed memory read count in bytes or
5871 * appropriate error value.
5873 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
5878 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5882 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5885 return 512 << ((stat
& PCI_X_STATUS_MAX_READ
) >> 21);
5887 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
5890 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5891 * @dev: PCI device to query
5893 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5896 int pcix_get_mmrbc(struct pci_dev
*dev
)
5901 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5905 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5908 return 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
5910 EXPORT_SYMBOL(pcix_get_mmrbc
);
5913 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5914 * @dev: PCI device to query
5915 * @mmrbc: maximum memory read count in bytes
5916 * valid values are 512, 1024, 2048, 4096
5918 * If possible sets maximum memory read byte count, some bridges have errata
5919 * that prevent this.
5921 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
5927 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
5930 v
= ffs(mmrbc
) - 10;
5932 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
5936 if (pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
))
5939 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
5942 if (pci_read_config_word(dev
, cap
+ PCI_X_CMD
, &cmd
))
5945 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
5947 if (v
> o
&& (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
5950 cmd
&= ~PCI_X_CMD_MAX_READ
;
5952 if (pci_write_config_word(dev
, cap
+ PCI_X_CMD
, cmd
))
5957 EXPORT_SYMBOL(pcix_set_mmrbc
);
5960 * pcie_get_readrq - get PCI Express read request size
5961 * @dev: PCI device to query
5963 * Returns maximum memory read request in bytes or appropriate error value.
5965 int pcie_get_readrq(struct pci_dev
*dev
)
5969 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
5971 return 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5973 EXPORT_SYMBOL(pcie_get_readrq
);
5976 * pcie_set_readrq - set PCI Express maximum memory read request
5977 * @dev: PCI device to query
5978 * @rq: maximum memory read count in bytes
5979 * valid values are 128, 256, 512, 1024, 2048, 4096
5981 * If possible sets maximum memory read request in bytes
5983 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
5988 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
5992 * If using the "performance" PCIe config, we clamp the read rq
5993 * size to the max packet size to keep the host bridge from
5994 * generating requests larger than we can cope with.
5996 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
5997 int mps
= pcie_get_mps(dev
);
6003 v
= (ffs(rq
) - 8) << 12;
6005 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6006 PCI_EXP_DEVCTL_READRQ
, v
);
6008 return pcibios_err_to_errno(ret
);
6010 EXPORT_SYMBOL(pcie_set_readrq
);
6013 * pcie_get_mps - get PCI Express maximum payload size
6014 * @dev: PCI device to query
6016 * Returns maximum payload size in bytes
6018 int pcie_get_mps(struct pci_dev
*dev
)
6022 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
6024 return 128 << ((ctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6026 EXPORT_SYMBOL(pcie_get_mps
);
6029 * pcie_set_mps - set PCI Express maximum payload size
6030 * @dev: PCI device to query
6031 * @mps: maximum payload size in bytes
6032 * valid values are 128, 256, 512, 1024, 2048, 4096
6034 * If possible sets maximum payload size
6036 int pcie_set_mps(struct pci_dev
*dev
, int mps
)
6041 if (mps
< 128 || mps
> 4096 || !is_power_of_2(mps
))
6045 if (v
> dev
->pcie_mpss
)
6049 ret
= pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
6050 PCI_EXP_DEVCTL_PAYLOAD
, v
);
6052 return pcibios_err_to_errno(ret
);
6054 EXPORT_SYMBOL(pcie_set_mps
);
6057 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6058 * device and its bandwidth limitation
6059 * @dev: PCI device to query
6060 * @limiting_dev: storage for device causing the bandwidth limitation
6061 * @speed: storage for speed of limiting device
6062 * @width: storage for width of limiting device
6064 * Walk up the PCI device chain and find the point where the minimum
6065 * bandwidth is available. Return the bandwidth available there and (if
6066 * limiting_dev, speed, and width pointers are supplied) information about
6067 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6070 u32
pcie_bandwidth_available(struct pci_dev
*dev
, struct pci_dev
**limiting_dev
,
6071 enum pci_bus_speed
*speed
,
6072 enum pcie_link_width
*width
)
6075 enum pci_bus_speed next_speed
;
6076 enum pcie_link_width next_width
;
6080 *speed
= PCI_SPEED_UNKNOWN
;
6082 *width
= PCIE_LNK_WIDTH_UNKNOWN
;
6087 pcie_capability_read_word(dev
, PCI_EXP_LNKSTA
, &lnksta
);
6089 next_speed
= pcie_link_speed
[lnksta
& PCI_EXP_LNKSTA_CLS
];
6090 next_width
= (lnksta
& PCI_EXP_LNKSTA_NLW
) >>
6091 PCI_EXP_LNKSTA_NLW_SHIFT
;
6093 next_bw
= next_width
* PCIE_SPEED2MBS_ENC(next_speed
);
6095 /* Check if current device limits the total bandwidth */
6096 if (!bw
|| next_bw
<= bw
) {
6100 *limiting_dev
= dev
;
6102 *speed
= next_speed
;
6104 *width
= next_width
;
6107 dev
= pci_upstream_bridge(dev
);
6112 EXPORT_SYMBOL(pcie_bandwidth_available
);
6115 * pcie_get_speed_cap - query for the PCI device's link speed capability
6116 * @dev: PCI device to query
6118 * Query the PCI device speed capability. Return the maximum link speed
6119 * supported by the device.
6121 enum pci_bus_speed
pcie_get_speed_cap(struct pci_dev
*dev
)
6123 u32 lnkcap2
, lnkcap
;
6126 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6127 * implementation note there recommends using the Supported Link
6128 * Speeds Vector in Link Capabilities 2 when supported.
6130 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6131 * should use the Supported Link Speeds field in Link Capabilities,
6132 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6134 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP2
, &lnkcap2
);
6136 /* PCIe r3.0-compliant */
6138 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2
);
6140 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6141 if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_5_0GB
)
6142 return PCIE_SPEED_5_0GT
;
6143 else if ((lnkcap
& PCI_EXP_LNKCAP_SLS
) == PCI_EXP_LNKCAP_SLS_2_5GB
)
6144 return PCIE_SPEED_2_5GT
;
6146 return PCI_SPEED_UNKNOWN
;
6148 EXPORT_SYMBOL(pcie_get_speed_cap
);
6151 * pcie_get_width_cap - query for the PCI device's link width capability
6152 * @dev: PCI device to query
6154 * Query the PCI device width capability. Return the maximum link width
6155 * supported by the device.
6157 enum pcie_link_width
pcie_get_width_cap(struct pci_dev
*dev
)
6161 pcie_capability_read_dword(dev
, PCI_EXP_LNKCAP
, &lnkcap
);
6163 return (lnkcap
& PCI_EXP_LNKCAP_MLW
) >> 4;
6165 return PCIE_LNK_WIDTH_UNKNOWN
;
6167 EXPORT_SYMBOL(pcie_get_width_cap
);
6170 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6172 * @speed: storage for link speed
6173 * @width: storage for link width
6175 * Calculate a PCI device's link bandwidth by querying for its link speed
6176 * and width, multiplying them, and applying encoding overhead. The result
6177 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6179 u32
pcie_bandwidth_capable(struct pci_dev
*dev
, enum pci_bus_speed
*speed
,
6180 enum pcie_link_width
*width
)
6182 *speed
= pcie_get_speed_cap(dev
);
6183 *width
= pcie_get_width_cap(dev
);
6185 if (*speed
== PCI_SPEED_UNKNOWN
|| *width
== PCIE_LNK_WIDTH_UNKNOWN
)
6188 return *width
* PCIE_SPEED2MBS_ENC(*speed
);
6192 * __pcie_print_link_status - Report the PCI device's link speed and width
6193 * @dev: PCI device to query
6194 * @verbose: Print info even when enough bandwidth is available
6196 * If the available bandwidth at the device is less than the device is
6197 * capable of, report the device's maximum possible bandwidth and the
6198 * upstream link that limits its performance. If @verbose, always print
6199 * the available bandwidth, even if the device isn't constrained.
6201 void __pcie_print_link_status(struct pci_dev
*dev
, bool verbose
)
6203 enum pcie_link_width width
, width_cap
;
6204 enum pci_bus_speed speed
, speed_cap
;
6205 struct pci_dev
*limiting_dev
= NULL
;
6206 u32 bw_avail
, bw_cap
;
6208 bw_cap
= pcie_bandwidth_capable(dev
, &speed_cap
, &width_cap
);
6209 bw_avail
= pcie_bandwidth_available(dev
, &limiting_dev
, &speed
, &width
);
6211 if (bw_avail
>= bw_cap
&& verbose
)
6212 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6213 bw_cap
/ 1000, bw_cap
% 1000,
6214 pci_speed_string(speed_cap
), width_cap
);
6215 else if (bw_avail
< bw_cap
)
6216 pci_info(dev
, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6217 bw_avail
/ 1000, bw_avail
% 1000,
6218 pci_speed_string(speed
), width
,
6219 limiting_dev
? pci_name(limiting_dev
) : "<unknown>",
6220 bw_cap
/ 1000, bw_cap
% 1000,
6221 pci_speed_string(speed_cap
), width_cap
);
6225 * pcie_print_link_status - Report the PCI device's link speed and width
6226 * @dev: PCI device to query
6228 * Report the available bandwidth at the device.
6230 void pcie_print_link_status(struct pci_dev
*dev
)
6232 __pcie_print_link_status(dev
, true);
6234 EXPORT_SYMBOL(pcie_print_link_status
);
6237 * pci_select_bars - Make BAR mask from the type of resource
6238 * @dev: the PCI device for which BAR mask is made
6239 * @flags: resource type mask to be selected
6241 * This helper routine makes bar mask from the type of resource.
6243 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
6246 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
6247 if (pci_resource_flags(dev
, i
) & flags
)
6251 EXPORT_SYMBOL(pci_select_bars
);
6253 /* Some architectures require additional programming to enable VGA */
6254 static arch_set_vga_state_t arch_set_vga_state
;
6256 void __init
pci_register_set_vga_state(arch_set_vga_state_t func
)
6258 arch_set_vga_state
= func
; /* NULL disables */
6261 static int pci_set_vga_state_arch(struct pci_dev
*dev
, bool decode
,
6262 unsigned int command_bits
, u32 flags
)
6264 if (arch_set_vga_state
)
6265 return arch_set_vga_state(dev
, decode
, command_bits
,
6271 * pci_set_vga_state - set VGA decode state on device and parents if requested
6272 * @dev: the PCI device
6273 * @decode: true = enable decoding, false = disable decoding
6274 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6275 * @flags: traverse ancestors and change bridges
6276 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6278 int pci_set_vga_state(struct pci_dev
*dev
, bool decode
,
6279 unsigned int command_bits
, u32 flags
)
6281 struct pci_bus
*bus
;
6282 struct pci_dev
*bridge
;
6286 WARN_ON((flags
& PCI_VGA_STATE_CHANGE_DECODES
) && (command_bits
& ~(PCI_COMMAND_IO
|PCI_COMMAND_MEMORY
)));
6288 /* ARCH specific VGA enables */
6289 rc
= pci_set_vga_state_arch(dev
, decode
, command_bits
, flags
);
6293 if (flags
& PCI_VGA_STATE_CHANGE_DECODES
) {
6294 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
6296 cmd
|= command_bits
;
6298 cmd
&= ~command_bits
;
6299 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
6302 if (!(flags
& PCI_VGA_STATE_CHANGE_BRIDGE
))
6309 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6312 cmd
|= PCI_BRIDGE_CTL_VGA
;
6314 cmd
&= ~PCI_BRIDGE_CTL_VGA
;
6315 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
,
6324 bool pci_pr3_present(struct pci_dev
*pdev
)
6326 struct acpi_device
*adev
;
6331 adev
= ACPI_COMPANION(&pdev
->dev
);
6335 return adev
->power
.flags
.power_resources
&&
6336 acpi_has_method(adev
->handle
, "_PR3");
6338 EXPORT_SYMBOL_GPL(pci_pr3_present
);
6342 * pci_add_dma_alias - Add a DMA devfn alias for a device
6343 * @dev: the PCI device for which alias is added
6344 * @devfn_from: alias slot and function
6345 * @nr_devfns: number of subsequent devfns to alias
6347 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6348 * which is used to program permissible bus-devfn source addresses for DMA
6349 * requests in an IOMMU. These aliases factor into IOMMU group creation
6350 * and are useful for devices generating DMA requests beyond or different
6351 * from their logical bus-devfn. Examples include device quirks where the
6352 * device simply uses the wrong devfn, as well as non-transparent bridges
6353 * where the alias may be a proxy for devices in another domain.
6355 * IOMMU group creation is performed during device discovery or addition,
6356 * prior to any potential DMA mapping and therefore prior to driver probing
6357 * (especially for userspace assigned devices where IOMMU group definition
6358 * cannot be left as a userspace activity). DMA aliases should therefore
6359 * be configured via quirks, such as the PCI fixup header quirk.
6361 void pci_add_dma_alias(struct pci_dev
*dev
, u8 devfn_from
, unsigned nr_devfns
)
6365 nr_devfns
= min(nr_devfns
, (unsigned) MAX_NR_DEVFNS
- devfn_from
);
6366 devfn_to
= devfn_from
+ nr_devfns
- 1;
6368 if (!dev
->dma_alias_mask
)
6369 dev
->dma_alias_mask
= bitmap_zalloc(MAX_NR_DEVFNS
, GFP_KERNEL
);
6370 if (!dev
->dma_alias_mask
) {
6371 pci_warn(dev
, "Unable to allocate DMA alias mask\n");
6375 bitmap_set(dev
->dma_alias_mask
, devfn_from
, nr_devfns
);
6378 pci_info(dev
, "Enabling fixed DMA alias to %02x.%d\n",
6379 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
));
6380 else if (nr_devfns
> 1)
6381 pci_info(dev
, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6382 PCI_SLOT(devfn_from
), PCI_FUNC(devfn_from
),
6383 PCI_SLOT(devfn_to
), PCI_FUNC(devfn_to
));
6386 bool pci_devs_are_dma_aliases(struct pci_dev
*dev1
, struct pci_dev
*dev2
)
6388 return (dev1
->dma_alias_mask
&&
6389 test_bit(dev2
->devfn
, dev1
->dma_alias_mask
)) ||
6390 (dev2
->dma_alias_mask
&&
6391 test_bit(dev1
->devfn
, dev2
->dma_alias_mask
)) ||
6392 pci_real_dma_dev(dev1
) == dev2
||
6393 pci_real_dma_dev(dev2
) == dev1
;
6396 bool pci_device_is_present(struct pci_dev
*pdev
)
6400 if (pci_dev_is_disconnected(pdev
))
6402 return pci_bus_read_dev_vendor_id(pdev
->bus
, pdev
->devfn
, &v
, 0);
6404 EXPORT_SYMBOL_GPL(pci_device_is_present
);
6406 void pci_ignore_hotplug(struct pci_dev
*dev
)
6408 struct pci_dev
*bridge
= dev
->bus
->self
;
6410 dev
->ignore_hotplug
= 1;
6411 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6413 bridge
->ignore_hotplug
= 1;
6415 EXPORT_SYMBOL_GPL(pci_ignore_hotplug
);
6418 * pci_real_dma_dev - Get PCI DMA device for PCI device
6419 * @dev: the PCI device that may have a PCI DMA alias
6421 * Permits the platform to provide architecture-specific functionality to
6422 * devices needing to alias DMA to another PCI device on another PCI bus. If
6423 * the PCI device is on the same bus, it is recommended to use
6424 * pci_add_dma_alias(). This is the default implementation. Architecture
6425 * implementations can override this.
6427 struct pci_dev __weak
*pci_real_dma_dev(struct pci_dev
*dev
)
6432 resource_size_t __weak
pcibios_default_alignment(void)
6438 * Arches that don't want to expose struct resource to userland as-is in
6439 * sysfs and /proc can implement their own pci_resource_to_user().
6441 void __weak
pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
6442 const struct resource
*rsrc
,
6443 resource_size_t
*start
, resource_size_t
*end
)
6445 *start
= rsrc
->start
;
6449 static char *resource_alignment_param
;
6450 static DEFINE_SPINLOCK(resource_alignment_lock
);
6453 * pci_specified_resource_alignment - get resource alignment specified by user.
6454 * @dev: the PCI device to get
6455 * @resize: whether or not to change resources' size when reassigning alignment
6457 * RETURNS: Resource alignment if it is specified.
6458 * Zero if it is not specified.
6460 static resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
,
6463 int align_order
, count
;
6464 resource_size_t align
= pcibios_default_alignment();
6468 spin_lock(&resource_alignment_lock
);
6469 p
= resource_alignment_param
;
6472 if (pci_has_flag(PCI_PROBE_ONLY
)) {
6474 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6480 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
6483 if (align_order
> 63) {
6484 pr_err("PCI: Invalid requested alignment (order %d)\n",
6486 align_order
= PAGE_SHIFT
;
6489 align_order
= PAGE_SHIFT
;
6492 ret
= pci_dev_str_match(dev
, p
, &p
);
6495 align
= 1ULL << align_order
;
6497 } else if (ret
< 0) {
6498 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6503 if (*p
!= ';' && *p
!= ',') {
6504 /* End of param or invalid format */
6510 spin_unlock(&resource_alignment_lock
);
6514 static void pci_request_resource_alignment(struct pci_dev
*dev
, int bar
,
6515 resource_size_t align
, bool resize
)
6517 struct resource
*r
= &dev
->resource
[bar
];
6518 resource_size_t size
;
6520 if (!(r
->flags
& IORESOURCE_MEM
))
6523 if (r
->flags
& IORESOURCE_PCI_FIXED
) {
6524 pci_info(dev
, "BAR%d %pR: ignoring requested alignment %#llx\n",
6525 bar
, r
, (unsigned long long)align
);
6529 size
= resource_size(r
);
6534 * Increase the alignment of the resource. There are two ways we
6537 * 1) Increase the size of the resource. BARs are aligned on their
6538 * size, so when we reallocate space for this resource, we'll
6539 * allocate it with the larger alignment. This also prevents
6540 * assignment of any other BARs inside the alignment region, so
6541 * if we're requesting page alignment, this means no other BARs
6542 * will share the page.
6544 * The disadvantage is that this makes the resource larger than
6545 * the hardware BAR, which may break drivers that compute things
6546 * based on the resource size, e.g., to find registers at a
6547 * fixed offset before the end of the BAR.
6549 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6550 * set r->start to the desired alignment. By itself this
6551 * doesn't prevent other BARs being put inside the alignment
6552 * region, but if we realign *every* resource of every device in
6553 * the system, none of them will share an alignment region.
6555 * When the user has requested alignment for only some devices via
6556 * the "pci=resource_alignment" argument, "resize" is true and we
6557 * use the first method. Otherwise we assume we're aligning all
6558 * devices and we use the second.
6561 pci_info(dev
, "BAR%d %pR: requesting alignment to %#llx\n",
6562 bar
, r
, (unsigned long long)align
);
6568 r
->flags
&= ~IORESOURCE_SIZEALIGN
;
6569 r
->flags
|= IORESOURCE_STARTALIGN
;
6571 r
->end
= r
->start
+ size
- 1;
6573 r
->flags
|= IORESOURCE_UNSET
;
6577 * This function disables memory decoding and releases memory resources
6578 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6579 * It also rounds up size to specified alignment.
6580 * Later on, the kernel will assign page-aligned memory resource back
6583 void pci_reassigndev_resource_alignment(struct pci_dev
*dev
)
6587 resource_size_t align
;
6589 bool resize
= false;
6592 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6593 * 3.4.1.11. Their resources are allocated from the space
6594 * described by the VF BARx register in the PF's SR-IOV capability.
6595 * We can't influence their alignment here.
6600 /* check if specified PCI is target device to reassign */
6601 align
= pci_specified_resource_alignment(dev
, &resize
);
6605 if (dev
->hdr_type
== PCI_HEADER_TYPE_NORMAL
&&
6606 (dev
->class >> 8) == PCI_CLASS_BRIDGE_HOST
) {
6607 pci_warn(dev
, "Can't reassign resources to host bridge\n");
6611 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
6612 command
&= ~PCI_COMMAND_MEMORY
;
6613 pci_write_config_word(dev
, PCI_COMMAND
, command
);
6615 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++)
6616 pci_request_resource_alignment(dev
, i
, align
, resize
);
6619 * Need to disable bridge's resource window,
6620 * to enable the kernel to reassign new resource
6623 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
6624 for (i
= PCI_BRIDGE_RESOURCES
; i
< PCI_NUM_RESOURCES
; i
++) {
6625 r
= &dev
->resource
[i
];
6626 if (!(r
->flags
& IORESOURCE_MEM
))
6628 r
->flags
|= IORESOURCE_UNSET
;
6629 r
->end
= resource_size(r
) - 1;
6632 pci_disable_bridge_window(dev
);
6636 static ssize_t
resource_alignment_show(struct bus_type
*bus
, char *buf
)
6640 spin_lock(&resource_alignment_lock
);
6641 if (resource_alignment_param
)
6642 count
= sysfs_emit(buf
, "%s\n", resource_alignment_param
);
6643 spin_unlock(&resource_alignment_lock
);
6648 static ssize_t
resource_alignment_store(struct bus_type
*bus
,
6649 const char *buf
, size_t count
)
6651 char *param
, *old
, *end
;
6653 if (count
>= (PAGE_SIZE
- 1))
6656 param
= kstrndup(buf
, count
, GFP_KERNEL
);
6660 end
= strchr(param
, '\n');
6664 spin_lock(&resource_alignment_lock
);
6665 old
= resource_alignment_param
;
6666 if (strlen(param
)) {
6667 resource_alignment_param
= param
;
6670 resource_alignment_param
= NULL
;
6672 spin_unlock(&resource_alignment_lock
);
6679 static BUS_ATTR_RW(resource_alignment
);
6681 static int __init
pci_resource_alignment_sysfs_init(void)
6683 return bus_create_file(&pci_bus_type
,
6684 &bus_attr_resource_alignment
);
6686 late_initcall(pci_resource_alignment_sysfs_init
);
6688 static void pci_no_domains(void)
6690 #ifdef CONFIG_PCI_DOMAINS
6691 pci_domains_supported
= 0;
6695 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6696 static atomic_t __domain_nr
= ATOMIC_INIT(-1);
6698 static int pci_get_new_domain_nr(void)
6700 return atomic_inc_return(&__domain_nr
);
6703 static int of_pci_bus_find_domain_nr(struct device
*parent
)
6705 static int use_dt_domains
= -1;
6709 domain
= of_get_pci_domain_nr(parent
->of_node
);
6712 * Check DT domain and use_dt_domains values.
6714 * If DT domain property is valid (domain >= 0) and
6715 * use_dt_domains != 0, the DT assignment is valid since this means
6716 * we have not previously allocated a domain number by using
6717 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6718 * 1, to indicate that we have just assigned a domain number from
6721 * If DT domain property value is not valid (ie domain < 0), and we
6722 * have not previously assigned a domain number from DT
6723 * (use_dt_domains != 1) we should assign a domain number by
6726 * pci_get_new_domain_nr()
6728 * API and update the use_dt_domains value to keep track of method we
6729 * are using to assign domain numbers (use_dt_domains = 0).
6731 * All other combinations imply we have a platform that is trying
6732 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6733 * which is a recipe for domain mishandling and it is prevented by
6734 * invalidating the domain value (domain = -1) and printing a
6735 * corresponding error.
6737 if (domain
>= 0 && use_dt_domains
) {
6739 } else if (domain
< 0 && use_dt_domains
!= 1) {
6741 domain
= pci_get_new_domain_nr();
6744 pr_err("Node %pOF has ", parent
->of_node
);
6745 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6752 int pci_bus_find_domain_nr(struct pci_bus
*bus
, struct device
*parent
)
6754 return acpi_disabled
? of_pci_bus_find_domain_nr(parent
) :
6755 acpi_pci_bus_find_domain_nr(bus
);
6760 * pci_ext_cfg_avail - can we access extended PCI config space?
6762 * Returns 1 if we can access PCI extended config space (offsets
6763 * greater than 0xff). This is the default implementation. Architecture
6764 * implementations can override this.
6766 int __weak
pci_ext_cfg_avail(void)
6771 void __weak
pci_fixup_cardbus(struct pci_bus
*bus
)
6774 EXPORT_SYMBOL(pci_fixup_cardbus
);
6776 static int __init
pci_setup(char *str
)
6779 char *k
= strchr(str
, ',');
6782 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
6783 if (!strcmp(str
, "nomsi")) {
6785 } else if (!strncmp(str
, "noats", 5)) {
6786 pr_info("PCIe: ATS is disabled\n");
6787 pcie_ats_disabled
= true;
6788 } else if (!strcmp(str
, "noaer")) {
6790 } else if (!strcmp(str
, "earlydump")) {
6791 pci_early_dump
= true;
6792 } else if (!strncmp(str
, "realloc=", 8)) {
6793 pci_realloc_get_opt(str
+ 8);
6794 } else if (!strncmp(str
, "realloc", 7)) {
6795 pci_realloc_get_opt("on");
6796 } else if (!strcmp(str
, "nodomains")) {
6798 } else if (!strncmp(str
, "noari", 5)) {
6799 pcie_ari_disabled
= true;
6800 } else if (!strncmp(str
, "cbiosize=", 9)) {
6801 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
6802 } else if (!strncmp(str
, "cbmemsize=", 10)) {
6803 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
6804 } else if (!strncmp(str
, "resource_alignment=", 19)) {
6805 resource_alignment_param
= str
+ 19;
6806 } else if (!strncmp(str
, "ecrc=", 5)) {
6807 pcie_ecrc_get_policy(str
+ 5);
6808 } else if (!strncmp(str
, "hpiosize=", 9)) {
6809 pci_hotplug_io_size
= memparse(str
+ 9, &str
);
6810 } else if (!strncmp(str
, "hpmmiosize=", 11)) {
6811 pci_hotplug_mmio_size
= memparse(str
+ 11, &str
);
6812 } else if (!strncmp(str
, "hpmmioprefsize=", 15)) {
6813 pci_hotplug_mmio_pref_size
= memparse(str
+ 15, &str
);
6814 } else if (!strncmp(str
, "hpmemsize=", 10)) {
6815 pci_hotplug_mmio_size
= memparse(str
+ 10, &str
);
6816 pci_hotplug_mmio_pref_size
= pci_hotplug_mmio_size
;
6817 } else if (!strncmp(str
, "hpbussize=", 10)) {
6818 pci_hotplug_bus_size
=
6819 simple_strtoul(str
+ 10, &str
, 0);
6820 if (pci_hotplug_bus_size
> 0xff)
6821 pci_hotplug_bus_size
= DEFAULT_HOTPLUG_BUS_SIZE
;
6822 } else if (!strncmp(str
, "pcie_bus_tune_off", 17)) {
6823 pcie_bus_config
= PCIE_BUS_TUNE_OFF
;
6824 } else if (!strncmp(str
, "pcie_bus_safe", 13)) {
6825 pcie_bus_config
= PCIE_BUS_SAFE
;
6826 } else if (!strncmp(str
, "pcie_bus_perf", 13)) {
6827 pcie_bus_config
= PCIE_BUS_PERFORMANCE
;
6828 } else if (!strncmp(str
, "pcie_bus_peer2peer", 18)) {
6829 pcie_bus_config
= PCIE_BUS_PEER2PEER
;
6830 } else if (!strncmp(str
, "pcie_scan_all", 13)) {
6831 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS
);
6832 } else if (!strncmp(str
, "disable_acs_redir=", 18)) {
6833 disable_acs_redir_param
= str
+ 18;
6835 pr_err("PCI: Unknown option `%s'\n", str
);
6842 early_param("pci", pci_setup
);
6845 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6846 * in pci_setup(), above, to point to data in the __initdata section which
6847 * will be freed after the init sequence is complete. We can't allocate memory
6848 * in pci_setup() because some architectures do not have any memory allocation
6849 * service available during an early_param() call. So we allocate memory and
6850 * copy the variable here before the init section is freed.
6853 static int __init
pci_realloc_setup_params(void)
6855 resource_alignment_param
= kstrdup(resource_alignment_param
,
6857 disable_acs_redir_param
= kstrdup(disable_acs_redir_param
, GFP_KERNEL
);
6861 pure_initcall(pci_realloc_setup_params
);