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1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 *
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
7 *
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
17 #include <linux/of.h>
18 #include <linux/pci.h>
19 #include <linux/pm.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
32 #include <asm/dma.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
35 #include "pci.h"
36
37 DEFINE_MUTEX(pci_slot_mutex);
38
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
41 };
42 EXPORT_SYMBOL_GPL(pci_power_names);
43
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
46
47 int pci_pci_problems;
48 EXPORT_SYMBOL(pci_pci_problems);
49
50 unsigned int pci_pm_d3hot_delay;
51
52 static void pci_pme_list_scan(struct work_struct *work);
53
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
57
58 struct pci_pme_device {
59 struct list_head list;
60 struct pci_dev *dev;
61 };
62
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
64
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 {
67 unsigned int delay = dev->d3hot_delay;
68
69 if (delay < pci_pm_d3hot_delay)
70 delay = pci_pm_d3hot_delay;
71
72 if (delay)
73 msleep(delay);
74 }
75
76 bool pci_reset_supported(struct pci_dev *dev)
77 {
78 return dev->reset_methods[0] != 0;
79 }
80
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported = 1;
83 #endif
84
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
89 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
90
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
96 /*
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
100 */
101 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
102 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
103
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
106
107
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
117 #else
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
119 #endif
120
121 /*
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
126 */
127 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
128 u8 pci_cache_line_size;
129
130 /*
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
133 */
134 unsigned int pcibios_max_latency = 255;
135
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled;
138
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled;
141
142 /* If set, the PCI config space of each device is printed during boot. */
143 bool pci_early_dump;
144
145 bool pci_ats_disabled(void)
146 {
147 return pcie_ats_disabled;
148 }
149 EXPORT_SYMBOL_GPL(pci_ats_disabled);
150
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force;
155
156 static int __init pcie_port_pm_setup(char *str)
157 {
158 if (!strcmp(str, "off"))
159 pci_bridge_d3_disable = true;
160 else if (!strcmp(str, "force"))
161 pci_bridge_d3_force = true;
162 return 1;
163 }
164 __setup("pcie_port_pm=", pcie_port_pm_setup);
165
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
168
169 /**
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
172 *
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
175 */
176 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
177 {
178 struct pci_bus *tmp;
179 unsigned char max, n;
180
181 max = bus->busn_res.end;
182 list_for_each_entry(tmp, &bus->children, node) {
183 n = pci_bus_max_busnr(tmp);
184 if (n > max)
185 max = n;
186 }
187 return max;
188 }
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
190
191 /**
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
194 *
195 * Returns error bits set in PCI_STATUS and clears them.
196 */
197 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
198 {
199 u16 status;
200 int ret;
201
202 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
203 if (ret != PCIBIOS_SUCCESSFUL)
204 return -EIO;
205
206 status &= PCI_STATUS_ERROR_BITS;
207 if (status)
208 pci_write_config_word(pdev, PCI_STATUS, status);
209
210 return status;
211 }
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
213
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
216 bool write_combine)
217 {
218 struct resource *res = &pdev->resource[bar];
219 resource_size_t start = res->start;
220 resource_size_t size = resource_size(res);
221
222 /*
223 * Make sure the BAR is actually a memory resource, not an IO resource
224 */
225 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
226 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
227 return NULL;
228 }
229
230 if (write_combine)
231 return ioremap_wc(start, size);
232
233 return ioremap(start, size);
234 }
235
236 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
237 {
238 return __pci_ioremap_resource(pdev, bar, false);
239 }
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
241
242 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
243 {
244 return __pci_ioremap_resource(pdev, bar, true);
245 }
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
247 #endif
248
249 /**
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
254 *
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
257 * be of the form:
258 *
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
260 *
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
264 *
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
267 */
268 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
269 const char **endptr)
270 {
271 int ret;
272 int seg, bus, slot, func;
273 char *wpath, *p;
274 char end;
275
276 *endptr = strchrnul(path, ';');
277
278 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
279 if (!wpath)
280 return -ENOMEM;
281
282 while (1) {
283 p = strrchr(wpath, '/');
284 if (!p)
285 break;
286 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
287 if (ret != 2) {
288 ret = -EINVAL;
289 goto free_and_exit;
290 }
291
292 if (dev->devfn != PCI_DEVFN(slot, func)) {
293 ret = 0;
294 goto free_and_exit;
295 }
296
297 /*
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
301 * and so on.
302 */
303 dev = pci_upstream_bridge(dev);
304 if (!dev) {
305 ret = 0;
306 goto free_and_exit;
307 }
308
309 *p = 0;
310 }
311
312 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
313 &func, &end);
314 if (ret != 4) {
315 seg = 0;
316 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
317 if (ret != 3) {
318 ret = -EINVAL;
319 goto free_and_exit;
320 }
321 }
322
323 ret = (seg == pci_domain_nr(dev->bus) &&
324 bus == dev->bus->number &&
325 dev->devfn == PCI_DEVFN(slot, func));
326
327 free_and_exit:
328 kfree(wpath);
329 return ret;
330 }
331
332 /**
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
337 *
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
340 *
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
343 *
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
351 *
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
358 *
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
361 */
362 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
363 const char **endptr)
364 {
365 int ret;
366 int count;
367 unsigned short vendor, device, subsystem_vendor, subsystem_device;
368
369 if (strncmp(p, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
371 p += 4;
372 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
373 &subsystem_vendor, &subsystem_device, &count);
374 if (ret != 4) {
375 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
376 if (ret != 2)
377 return -EINVAL;
378
379 subsystem_vendor = 0;
380 subsystem_device = 0;
381 }
382
383 p += count;
384
385 if ((!vendor || vendor == dev->vendor) &&
386 (!device || device == dev->device) &&
387 (!subsystem_vendor ||
388 subsystem_vendor == dev->subsystem_vendor) &&
389 (!subsystem_device ||
390 subsystem_device == dev->subsystem_device))
391 goto found;
392 } else {
393 /*
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
396 */
397 ret = pci_dev_str_match_path(dev, p, &p);
398 if (ret < 0)
399 return ret;
400 else if (ret)
401 goto found;
402 }
403
404 *endptr = p;
405 return 0;
406
407 found:
408 *endptr = p;
409 return 1;
410 }
411
412 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
413 u8 pos, int cap, int *ttl)
414 {
415 u8 id;
416 u16 ent;
417
418 pci_bus_read_config_byte(bus, devfn, pos, &pos);
419
420 while ((*ttl)--) {
421 if (pos < 0x40)
422 break;
423 pos &= ~3;
424 pci_bus_read_config_word(bus, devfn, pos, &ent);
425
426 id = ent & 0xff;
427 if (id == 0xff)
428 break;
429 if (id == cap)
430 return pos;
431 pos = (ent >> 8);
432 }
433 return 0;
434 }
435
436 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
437 u8 pos, int cap)
438 {
439 int ttl = PCI_FIND_CAP_TTL;
440
441 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
442 }
443
444 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
445 {
446 return __pci_find_next_cap(dev->bus, dev->devfn,
447 pos + PCI_CAP_LIST_NEXT, cap);
448 }
449 EXPORT_SYMBOL_GPL(pci_find_next_capability);
450
451 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
452 unsigned int devfn, u8 hdr_type)
453 {
454 u16 status;
455
456 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
457 if (!(status & PCI_STATUS_CAP_LIST))
458 return 0;
459
460 switch (hdr_type) {
461 case PCI_HEADER_TYPE_NORMAL:
462 case PCI_HEADER_TYPE_BRIDGE:
463 return PCI_CAPABILITY_LIST;
464 case PCI_HEADER_TYPE_CARDBUS:
465 return PCI_CB_CAPABILITY_LIST;
466 }
467
468 return 0;
469 }
470
471 /**
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
475 *
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
480 *
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
489 */
490 u8 pci_find_capability(struct pci_dev *dev, int cap)
491 {
492 u8 pos;
493
494 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
495 if (pos)
496 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
497
498 return pos;
499 }
500 EXPORT_SYMBOL(pci_find_capability);
501
502 /**
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
507 *
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
510 *
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
513 * support it.
514 */
515 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
516 {
517 u8 hdr_type, pos;
518
519 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
520
521 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
522 if (pos)
523 pos = __pci_find_next_cap(bus, devfn, pos, cap);
524
525 return pos;
526 }
527 EXPORT_SYMBOL(pci_bus_find_capability);
528
529 /**
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
534 *
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
539 */
540 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
541 {
542 u32 header;
543 int ttl;
544 u16 pos = PCI_CFG_SPACE_SIZE;
545
546 /* minimum 8 bytes per capability */
547 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
548
549 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
550 return 0;
551
552 if (start)
553 pos = start;
554
555 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
556 return 0;
557
558 /*
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
561 */
562 if (header == 0)
563 return 0;
564
565 while (ttl-- > 0) {
566 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
567 return pos;
568
569 pos = PCI_EXT_CAP_NEXT(header);
570 if (pos < PCI_CFG_SPACE_SIZE)
571 break;
572
573 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
574 break;
575 }
576
577 return 0;
578 }
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
580
581 /**
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
585 *
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
589 *
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
594 */
595 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
596 {
597 return pci_find_next_ext_capability(dev, 0, cap);
598 }
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
600
601 /**
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
604 *
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
606 * Number.
607 *
608 * Returns the DSN, or zero if the capability does not exist.
609 */
610 u64 pci_get_dsn(struct pci_dev *dev)
611 {
612 u32 dword;
613 u64 dsn;
614 int pos;
615
616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
617 if (!pos)
618 return 0;
619
620 /*
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
624 */
625 pos += 4;
626 pci_read_config_dword(dev, pos, &dword);
627 dsn = (u64)dword;
628 pci_read_config_dword(dev, pos + 4, &dword);
629 dsn |= ((u64)dword) << 32;
630
631 return dsn;
632 }
633 EXPORT_SYMBOL_GPL(pci_get_dsn);
634
635 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
636 {
637 int rc, ttl = PCI_FIND_CAP_TTL;
638 u8 cap, mask;
639
640 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
641 mask = HT_3BIT_CAP_MASK;
642 else
643 mask = HT_5BIT_CAP_MASK;
644
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
646 PCI_CAP_ID_HT, &ttl);
647 while (pos) {
648 rc = pci_read_config_byte(dev, pos + 3, &cap);
649 if (rc != PCIBIOS_SUCCESSFUL)
650 return 0;
651
652 if ((cap & mask) == ht_cap)
653 return pos;
654
655 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
656 pos + PCI_CAP_LIST_NEXT,
657 PCI_CAP_ID_HT, &ttl);
658 }
659
660 return 0;
661 }
662
663 /**
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
668 *
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
672 *
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
675 */
676 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
677 {
678 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
679 }
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
681
682 /**
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
686 *
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
692 */
693 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
694 {
695 u8 pos;
696
697 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
698 if (pos)
699 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
700
701 return pos;
702 }
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
704
705 /**
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
710 *
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
714 */
715 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
716 {
717 u16 vsec = 0;
718 u32 header;
719
720 if (vendor != dev->vendor)
721 return 0;
722
723 while ((vsec = pci_find_next_ext_capability(dev, vsec,
724 PCI_EXT_CAP_ID_VNDR))) {
725 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
726 &header) == PCIBIOS_SUCCESSFUL &&
727 PCI_VNDR_HEADER_ID(header) == cap)
728 return vsec;
729 }
730
731 return 0;
732 }
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
734
735 /**
736 * pci_find_parent_resource - return resource region of parent bus of given
737 * region
738 * @dev: PCI device structure contains resources to be searched
739 * @res: child resource record for which parent is sought
740 *
741 * For given resource region of given device, return the resource region of
742 * parent bus the given region is contained in.
743 */
744 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
745 struct resource *res)
746 {
747 const struct pci_bus *bus = dev->bus;
748 struct resource *r;
749 int i;
750
751 pci_bus_for_each_resource(bus, r, i) {
752 if (!r)
753 continue;
754 if (resource_contains(r, res)) {
755
756 /*
757 * If the window is prefetchable but the BAR is
758 * not, the allocator made a mistake.
759 */
760 if (r->flags & IORESOURCE_PREFETCH &&
761 !(res->flags & IORESOURCE_PREFETCH))
762 return NULL;
763
764 /*
765 * If we're below a transparent bridge, there may
766 * be both a positively-decoded aperture and a
767 * subtractively-decoded region that contain the BAR.
768 * We want the positively-decoded one, so this depends
769 * on pci_bus_for_each_resource() giving us those
770 * first.
771 */
772 return r;
773 }
774 }
775 return NULL;
776 }
777 EXPORT_SYMBOL(pci_find_parent_resource);
778
779 /**
780 * pci_find_resource - Return matching PCI device resource
781 * @dev: PCI device to query
782 * @res: Resource to look for
783 *
784 * Goes over standard PCI resources (BARs) and checks if the given resource
785 * is partially or fully contained in any of them. In that case the
786 * matching resource is returned, %NULL otherwise.
787 */
788 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
789 {
790 int i;
791
792 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
793 struct resource *r = &dev->resource[i];
794
795 if (r->start && resource_contains(r, res))
796 return r;
797 }
798
799 return NULL;
800 }
801 EXPORT_SYMBOL(pci_find_resource);
802
803 /**
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
805 * @dev: the PCI device to operate on
806 * @pos: config space offset of status word
807 * @mask: mask of bit(s) to care about in status word
808 *
809 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
810 */
811 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
812 {
813 int i;
814
815 /* Wait for Transaction Pending bit clean */
816 for (i = 0; i < 4; i++) {
817 u16 status;
818 if (i)
819 msleep((1 << (i - 1)) * 100);
820
821 pci_read_config_word(dev, pos, &status);
822 if (!(status & mask))
823 return 1;
824 }
825
826 return 0;
827 }
828
829 static int pci_acs_enable;
830
831 /**
832 * pci_request_acs - ask for ACS to be enabled if supported
833 */
834 void pci_request_acs(void)
835 {
836 pci_acs_enable = 1;
837 }
838
839 static const char *disable_acs_redir_param;
840
841 /**
842 * pci_disable_acs_redir - disable ACS redirect capabilities
843 * @dev: the PCI device
844 *
845 * For only devices specified in the disable_acs_redir parameter.
846 */
847 static void pci_disable_acs_redir(struct pci_dev *dev)
848 {
849 int ret = 0;
850 const char *p;
851 int pos;
852 u16 ctrl;
853
854 if (!disable_acs_redir_param)
855 return;
856
857 p = disable_acs_redir_param;
858 while (*p) {
859 ret = pci_dev_str_match(dev, p, &p);
860 if (ret < 0) {
861 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
862 disable_acs_redir_param);
863
864 break;
865 } else if (ret == 1) {
866 /* Found a match */
867 break;
868 }
869
870 if (*p != ';' && *p != ',') {
871 /* End of param or invalid format */
872 break;
873 }
874 p++;
875 }
876
877 if (ret != 1)
878 return;
879
880 if (!pci_dev_specific_disable_acs_redir(dev))
881 return;
882
883 pos = dev->acs_cap;
884 if (!pos) {
885 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
886 return;
887 }
888
889 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
890
891 /* P2P Request & Completion Redirect */
892 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
893
894 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
895
896 pci_info(dev, "disabled ACS redirect\n");
897 }
898
899 /**
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
901 * @dev: the PCI device
902 */
903 static void pci_std_enable_acs(struct pci_dev *dev)
904 {
905 int pos;
906 u16 cap;
907 u16 ctrl;
908
909 pos = dev->acs_cap;
910 if (!pos)
911 return;
912
913 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
914 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
915
916 /* Source Validation */
917 ctrl |= (cap & PCI_ACS_SV);
918
919 /* P2P Request Redirect */
920 ctrl |= (cap & PCI_ACS_RR);
921
922 /* P2P Completion Redirect */
923 ctrl |= (cap & PCI_ACS_CR);
924
925 /* Upstream Forwarding */
926 ctrl |= (cap & PCI_ACS_UF);
927
928 /* Enable Translation Blocking for external devices and noats */
929 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
930 ctrl |= (cap & PCI_ACS_TB);
931
932 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
933 }
934
935 /**
936 * pci_enable_acs - enable ACS if hardware support it
937 * @dev: the PCI device
938 */
939 static void pci_enable_acs(struct pci_dev *dev)
940 {
941 if (!pci_acs_enable)
942 goto disable_acs_redir;
943
944 if (!pci_dev_specific_enable_acs(dev))
945 goto disable_acs_redir;
946
947 pci_std_enable_acs(dev);
948
949 disable_acs_redir:
950 /*
951 * Note: pci_disable_acs_redir() must be called even if ACS was not
952 * enabled by the kernel because it may have been enabled by
953 * platform firmware. So if we are told to disable it, we should
954 * always disable it after setting the kernel's default
955 * preferences.
956 */
957 pci_disable_acs_redir(dev);
958 }
959
960 /**
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
962 * @dev: PCI device to have its BARs restored
963 *
964 * Restore the BAR values for a given device, so as to make it
965 * accessible by its driver.
966 */
967 static void pci_restore_bars(struct pci_dev *dev)
968 {
969 int i;
970
971 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
972 pci_update_resource(dev, i);
973 }
974
975 static const struct pci_platform_pm_ops *pci_platform_pm;
976
977 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
978 {
979 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
980 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
981 return -EINVAL;
982 pci_platform_pm = ops;
983 return 0;
984 }
985
986 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
987 {
988 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
989 }
990
991 static inline int platform_pci_set_power_state(struct pci_dev *dev,
992 pci_power_t t)
993 {
994 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
995 }
996
997 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
998 {
999 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
1000 }
1001
1002 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1003 {
1004 if (pci_platform_pm && pci_platform_pm->refresh_state)
1005 pci_platform_pm->refresh_state(dev);
1006 }
1007
1008 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1009 {
1010 return pci_platform_pm ?
1011 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
1012 }
1013
1014 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1015 {
1016 return pci_platform_pm ?
1017 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
1018 }
1019
1020 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1021 {
1022 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
1023 }
1024
1025 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1026 {
1027 if (pci_platform_pm && pci_platform_pm->bridge_d3)
1028 return pci_platform_pm->bridge_d3(dev);
1029 return false;
1030 }
1031
1032 /**
1033 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1034 * given PCI device
1035 * @dev: PCI device to handle.
1036 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1037 *
1038 * RETURN VALUE:
1039 * -EINVAL if the requested state is invalid.
1040 * -EIO if device does not support PCI PM or its PM capabilities register has a
1041 * wrong version, or device doesn't support the requested state.
1042 * 0 if device already is in the requested state.
1043 * 0 if device's power state has been successfully changed.
1044 */
1045 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1046 {
1047 u16 pmcsr;
1048 bool need_restore = false;
1049
1050 /* Check if we're already there */
1051 if (dev->current_state == state)
1052 return 0;
1053
1054 if (!dev->pm_cap)
1055 return -EIO;
1056
1057 if (state < PCI_D0 || state > PCI_D3hot)
1058 return -EINVAL;
1059
1060 /*
1061 * Validate transition: We can enter D0 from any state, but if
1062 * we're already in a low-power state, we can only go deeper. E.g.,
1063 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1064 * we'd have to go from D3 to D0, then to D1.
1065 */
1066 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1067 && dev->current_state > state) {
1068 pci_err(dev, "invalid power transition (from %s to %s)\n",
1069 pci_power_name(dev->current_state),
1070 pci_power_name(state));
1071 return -EINVAL;
1072 }
1073
1074 /* Check if this device supports the desired state */
1075 if ((state == PCI_D1 && !dev->d1_support)
1076 || (state == PCI_D2 && !dev->d2_support))
1077 return -EIO;
1078
1079 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1080 if (pmcsr == (u16) ~0) {
1081 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1082 pci_power_name(dev->current_state),
1083 pci_power_name(state));
1084 return -EIO;
1085 }
1086
1087 /*
1088 * If we're (effectively) in D3, force entire word to 0.
1089 * This doesn't affect PME_Status, disables PME_En, and
1090 * sets PowerState to 0.
1091 */
1092 switch (dev->current_state) {
1093 case PCI_D0:
1094 case PCI_D1:
1095 case PCI_D2:
1096 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1097 pmcsr |= state;
1098 break;
1099 case PCI_D3hot:
1100 case PCI_D3cold:
1101 case PCI_UNKNOWN: /* Boot-up */
1102 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1103 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1104 need_restore = true;
1105 fallthrough; /* force to D0 */
1106 default:
1107 pmcsr = 0;
1108 break;
1109 }
1110
1111 /* Enter specified state */
1112 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1113
1114 /*
1115 * Mandatory power management transition delays; see PCI PM 1.1
1116 * 5.6.1 table 18
1117 */
1118 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1119 pci_dev_d3_sleep(dev);
1120 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1121 udelay(PCI_PM_D2_DELAY);
1122
1123 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1124 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1125 if (dev->current_state != state)
1126 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1127 pci_power_name(dev->current_state),
1128 pci_power_name(state));
1129
1130 /*
1131 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1132 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1133 * from D3hot to D0 _may_ perform an internal reset, thereby
1134 * going to "D0 Uninitialized" rather than "D0 Initialized".
1135 * For example, at least some versions of the 3c905B and the
1136 * 3c556B exhibit this behaviour.
1137 *
1138 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1139 * devices in a D3hot state at boot. Consequently, we need to
1140 * restore at least the BARs so that the device will be
1141 * accessible to its driver.
1142 */
1143 if (need_restore)
1144 pci_restore_bars(dev);
1145
1146 if (dev->bus->self)
1147 pcie_aspm_pm_state_change(dev->bus->self);
1148
1149 return 0;
1150 }
1151
1152 /**
1153 * pci_update_current_state - Read power state of given device and cache it
1154 * @dev: PCI device to handle.
1155 * @state: State to cache in case the device doesn't have the PM capability
1156 *
1157 * The power state is read from the PMCSR register, which however is
1158 * inaccessible in D3cold. The platform firmware is therefore queried first
1159 * to detect accessibility of the register. In case the platform firmware
1160 * reports an incorrect state or the device isn't power manageable by the
1161 * platform at all, we try to detect D3cold by testing accessibility of the
1162 * vendor ID in config space.
1163 */
1164 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1165 {
1166 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1167 !pci_device_is_present(dev)) {
1168 dev->current_state = PCI_D3cold;
1169 } else if (dev->pm_cap) {
1170 u16 pmcsr;
1171
1172 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1173 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1174 } else {
1175 dev->current_state = state;
1176 }
1177 }
1178
1179 /**
1180 * pci_refresh_power_state - Refresh the given device's power state data
1181 * @dev: Target PCI device.
1182 *
1183 * Ask the platform to refresh the devices power state information and invoke
1184 * pci_update_current_state() to update its current PCI power state.
1185 */
1186 void pci_refresh_power_state(struct pci_dev *dev)
1187 {
1188 if (platform_pci_power_manageable(dev))
1189 platform_pci_refresh_power_state(dev);
1190
1191 pci_update_current_state(dev, dev->current_state);
1192 }
1193
1194 /**
1195 * pci_platform_power_transition - Use platform to change device power state
1196 * @dev: PCI device to handle.
1197 * @state: State to put the device into.
1198 */
1199 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1200 {
1201 int error;
1202
1203 if (platform_pci_power_manageable(dev)) {
1204 error = platform_pci_set_power_state(dev, state);
1205 if (!error)
1206 pci_update_current_state(dev, state);
1207 } else
1208 error = -ENODEV;
1209
1210 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1211 dev->current_state = PCI_D0;
1212
1213 return error;
1214 }
1215 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1216
1217 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1218 {
1219 pm_request_resume(&pci_dev->dev);
1220 return 0;
1221 }
1222
1223 /**
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1225 * @bus: Top bus of the subtree to walk.
1226 */
1227 void pci_resume_bus(struct pci_bus *bus)
1228 {
1229 if (bus)
1230 pci_walk_bus(bus, pci_resume_one, NULL);
1231 }
1232
1233 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1234 {
1235 int delay = 1;
1236 u32 id;
1237
1238 /*
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 data to complete the read (except when
1243 * CRS SV is enabled and the read was for the Vendor ID; in that
1244 * case it synthesizes 0x0001 data).
1245 *
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1249 */
1250 pci_read_config_dword(dev, PCI_COMMAND, &id);
1251 while (id == ~0) {
1252 if (delay > timeout) {
1253 pci_warn(dev, "not ready %dms after %s; giving up\n",
1254 delay - 1, reset_type);
1255 return -ENOTTY;
1256 }
1257
1258 if (delay > 1000)
1259 pci_info(dev, "not ready %dms after %s; waiting\n",
1260 delay - 1, reset_type);
1261
1262 msleep(delay);
1263 delay *= 2;
1264 pci_read_config_dword(dev, PCI_COMMAND, &id);
1265 }
1266
1267 if (delay > 1000)
1268 pci_info(dev, "ready %dms after %s\n", delay - 1,
1269 reset_type);
1270
1271 return 0;
1272 }
1273
1274 /**
1275 * pci_power_up - Put the given device into D0
1276 * @dev: PCI device to power up
1277 */
1278 int pci_power_up(struct pci_dev *dev)
1279 {
1280 pci_platform_power_transition(dev, PCI_D0);
1281
1282 /*
1283 * Mandatory power management transition delays are handled in
1284 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1285 * corresponding bridge.
1286 */
1287 if (dev->runtime_d3cold) {
1288 /*
1289 * When powering on a bridge from D3cold, the whole hierarchy
1290 * may be powered on into D0uninitialized state, resume them to
1291 * give them a chance to suspend again
1292 */
1293 pci_resume_bus(dev->subordinate);
1294 }
1295
1296 return pci_raw_set_power_state(dev, PCI_D0);
1297 }
1298
1299 /**
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1301 * @dev: Device to handle
1302 * @data: pointer to state to be set
1303 */
1304 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1305 {
1306 pci_power_t state = *(pci_power_t *)data;
1307
1308 dev->current_state = state;
1309 return 0;
1310 }
1311
1312 /**
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1314 * @bus: Top bus of the subtree to walk.
1315 * @state: state to be set
1316 */
1317 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1318 {
1319 if (bus)
1320 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1321 }
1322
1323 /**
1324 * pci_set_power_state - Set the power state of a PCI device
1325 * @dev: PCI device to handle.
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1327 *
1328 * Transition a device to a new power state, using the platform firmware and/or
1329 * the device's PCI PM registers.
1330 *
1331 * RETURN VALUE:
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1335 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1336 * 0 if device already is in the requested state.
1337 * 0 if the transition is to D3 but D3 is not supported.
1338 * 0 if device's power state has been successfully changed.
1339 */
1340 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1341 {
1342 int error;
1343
1344 /* Bound the state we're entering */
1345 if (state > PCI_D3cold)
1346 state = PCI_D3cold;
1347 else if (state < PCI_D0)
1348 state = PCI_D0;
1349 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1350
1351 /*
1352 * If the device or the parent bridge do not support PCI
1353 * PM, ignore the request if we're doing anything other
1354 * than putting it into D0 (which would only happen on
1355 * boot).
1356 */
1357 return 0;
1358
1359 /* Check if we're already there */
1360 if (dev->current_state == state)
1361 return 0;
1362
1363 if (state == PCI_D0)
1364 return pci_power_up(dev);
1365
1366 /*
1367 * This device is quirked not to be put into D3, so don't put it in
1368 * D3
1369 */
1370 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1371 return 0;
1372
1373 /*
1374 * To put device in D3cold, we put device into D3hot in native
1375 * way, then put device into D3cold with platform ops
1376 */
1377 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1378 PCI_D3hot : state);
1379
1380 if (pci_platform_power_transition(dev, state))
1381 return error;
1382
1383 /* Powering off a bridge may power off the whole hierarchy */
1384 if (state == PCI_D3cold)
1385 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1386
1387 return 0;
1388 }
1389 EXPORT_SYMBOL(pci_set_power_state);
1390
1391 /**
1392 * pci_choose_state - Choose the power state of a PCI device
1393 * @dev: PCI device to be suspended
1394 * @state: target sleep state for the whole system. This is the value
1395 * that is passed to suspend() function.
1396 *
1397 * Returns PCI power state suitable for given device and given system
1398 * message.
1399 */
1400 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1401 {
1402 pci_power_t ret;
1403
1404 if (!dev->pm_cap)
1405 return PCI_D0;
1406
1407 ret = platform_pci_choose_state(dev);
1408 if (ret != PCI_POWER_ERROR)
1409 return ret;
1410
1411 switch (state.event) {
1412 case PM_EVENT_ON:
1413 return PCI_D0;
1414 case PM_EVENT_FREEZE:
1415 case PM_EVENT_PRETHAW:
1416 /* REVISIT both freeze and pre-thaw "should" use D0 */
1417 case PM_EVENT_SUSPEND:
1418 case PM_EVENT_HIBERNATE:
1419 return PCI_D3hot;
1420 default:
1421 pci_info(dev, "unrecognized suspend event %d\n",
1422 state.event);
1423 BUG();
1424 }
1425 return PCI_D0;
1426 }
1427 EXPORT_SYMBOL(pci_choose_state);
1428
1429 #define PCI_EXP_SAVE_REGS 7
1430
1431 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1432 u16 cap, bool extended)
1433 {
1434 struct pci_cap_saved_state *tmp;
1435
1436 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1437 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1438 return tmp;
1439 }
1440 return NULL;
1441 }
1442
1443 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1444 {
1445 return _pci_find_saved_cap(dev, cap, false);
1446 }
1447
1448 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1449 {
1450 return _pci_find_saved_cap(dev, cap, true);
1451 }
1452
1453 static int pci_save_pcie_state(struct pci_dev *dev)
1454 {
1455 int i = 0;
1456 struct pci_cap_saved_state *save_state;
1457 u16 *cap;
1458
1459 if (!pci_is_pcie(dev))
1460 return 0;
1461
1462 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1463 if (!save_state) {
1464 pci_err(dev, "buffer not found in %s\n", __func__);
1465 return -ENOMEM;
1466 }
1467
1468 cap = (u16 *)&save_state->cap.data[0];
1469 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1470 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1471 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1472 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1473 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1474 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1475 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1476
1477 return 0;
1478 }
1479
1480 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1481 {
1482 #ifdef CONFIG_PCIEASPM
1483 struct pci_dev *bridge;
1484 u32 ctl;
1485
1486 bridge = pci_upstream_bridge(dev);
1487 if (bridge && bridge->ltr_path) {
1488 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1489 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1490 pci_dbg(bridge, "re-enabling LTR\n");
1491 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1492 PCI_EXP_DEVCTL2_LTR_EN);
1493 }
1494 }
1495 #endif
1496 }
1497
1498 static void pci_restore_pcie_state(struct pci_dev *dev)
1499 {
1500 int i = 0;
1501 struct pci_cap_saved_state *save_state;
1502 u16 *cap;
1503
1504 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1505 if (!save_state)
1506 return;
1507
1508 /*
1509 * Downstream ports reset the LTR enable bit when link goes down.
1510 * Check and re-configure the bit here before restoring device.
1511 * PCIe r5.0, sec 7.5.3.16.
1512 */
1513 pci_bridge_reconfigure_ltr(dev);
1514
1515 cap = (u16 *)&save_state->cap.data[0];
1516 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1517 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1518 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1519 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1520 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1521 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1522 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1523 }
1524
1525 static int pci_save_pcix_state(struct pci_dev *dev)
1526 {
1527 int pos;
1528 struct pci_cap_saved_state *save_state;
1529
1530 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1531 if (!pos)
1532 return 0;
1533
1534 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1535 if (!save_state) {
1536 pci_err(dev, "buffer not found in %s\n", __func__);
1537 return -ENOMEM;
1538 }
1539
1540 pci_read_config_word(dev, pos + PCI_X_CMD,
1541 (u16 *)save_state->cap.data);
1542
1543 return 0;
1544 }
1545
1546 static void pci_restore_pcix_state(struct pci_dev *dev)
1547 {
1548 int i = 0, pos;
1549 struct pci_cap_saved_state *save_state;
1550 u16 *cap;
1551
1552 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1553 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1554 if (!save_state || !pos)
1555 return;
1556 cap = (u16 *)&save_state->cap.data[0];
1557
1558 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1559 }
1560
1561 static void pci_save_ltr_state(struct pci_dev *dev)
1562 {
1563 int ltr;
1564 struct pci_cap_saved_state *save_state;
1565 u16 *cap;
1566
1567 if (!pci_is_pcie(dev))
1568 return;
1569
1570 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1571 if (!ltr)
1572 return;
1573
1574 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1575 if (!save_state) {
1576 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1577 return;
1578 }
1579
1580 cap = (u16 *)&save_state->cap.data[0];
1581 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1582 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1583 }
1584
1585 static void pci_restore_ltr_state(struct pci_dev *dev)
1586 {
1587 struct pci_cap_saved_state *save_state;
1588 int ltr;
1589 u16 *cap;
1590
1591 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1592 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1593 if (!save_state || !ltr)
1594 return;
1595
1596 cap = (u16 *)&save_state->cap.data[0];
1597 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1598 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1599 }
1600
1601 /**
1602 * pci_save_state - save the PCI configuration space of a device before
1603 * suspending
1604 * @dev: PCI device that we're dealing with
1605 */
1606 int pci_save_state(struct pci_dev *dev)
1607 {
1608 int i;
1609 /* XXX: 100% dword access ok here? */
1610 for (i = 0; i < 16; i++) {
1611 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1612 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1613 i * 4, dev->saved_config_space[i]);
1614 }
1615 dev->state_saved = true;
1616
1617 i = pci_save_pcie_state(dev);
1618 if (i != 0)
1619 return i;
1620
1621 i = pci_save_pcix_state(dev);
1622 if (i != 0)
1623 return i;
1624
1625 pci_save_ltr_state(dev);
1626 pci_save_dpc_state(dev);
1627 pci_save_aer_state(dev);
1628 pci_save_ptm_state(dev);
1629 return pci_save_vc_state(dev);
1630 }
1631 EXPORT_SYMBOL(pci_save_state);
1632
1633 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1634 u32 saved_val, int retry, bool force)
1635 {
1636 u32 val;
1637
1638 pci_read_config_dword(pdev, offset, &val);
1639 if (!force && val == saved_val)
1640 return;
1641
1642 for (;;) {
1643 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1644 offset, val, saved_val);
1645 pci_write_config_dword(pdev, offset, saved_val);
1646 if (retry-- <= 0)
1647 return;
1648
1649 pci_read_config_dword(pdev, offset, &val);
1650 if (val == saved_val)
1651 return;
1652
1653 mdelay(1);
1654 }
1655 }
1656
1657 static void pci_restore_config_space_range(struct pci_dev *pdev,
1658 int start, int end, int retry,
1659 bool force)
1660 {
1661 int index;
1662
1663 for (index = end; index >= start; index--)
1664 pci_restore_config_dword(pdev, 4 * index,
1665 pdev->saved_config_space[index],
1666 retry, force);
1667 }
1668
1669 static void pci_restore_config_space(struct pci_dev *pdev)
1670 {
1671 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1672 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1673 /* Restore BARs before the command register. */
1674 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1675 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1676 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1677 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1678
1679 /*
1680 * Force rewriting of prefetch registers to avoid S3 resume
1681 * issues on Intel PCI bridges that occur when these
1682 * registers are not explicitly written.
1683 */
1684 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1685 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1686 } else {
1687 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1688 }
1689 }
1690
1691 static void pci_restore_rebar_state(struct pci_dev *pdev)
1692 {
1693 unsigned int pos, nbars, i;
1694 u32 ctrl;
1695
1696 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1697 if (!pos)
1698 return;
1699
1700 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1701 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1702 PCI_REBAR_CTRL_NBAR_SHIFT;
1703
1704 for (i = 0; i < nbars; i++, pos += 8) {
1705 struct resource *res;
1706 int bar_idx, size;
1707
1708 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1709 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1710 res = pdev->resource + bar_idx;
1711 size = pci_rebar_bytes_to_size(resource_size(res));
1712 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1713 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1714 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1715 }
1716 }
1717
1718 /**
1719 * pci_restore_state - Restore the saved state of a PCI device
1720 * @dev: PCI device that we're dealing with
1721 */
1722 void pci_restore_state(struct pci_dev *dev)
1723 {
1724 if (!dev->state_saved)
1725 return;
1726
1727 /*
1728 * Restore max latencies (in the LTR capability) before enabling
1729 * LTR itself (in the PCIe capability).
1730 */
1731 pci_restore_ltr_state(dev);
1732
1733 pci_restore_pcie_state(dev);
1734 pci_restore_pasid_state(dev);
1735 pci_restore_pri_state(dev);
1736 pci_restore_ats_state(dev);
1737 pci_restore_vc_state(dev);
1738 pci_restore_rebar_state(dev);
1739 pci_restore_dpc_state(dev);
1740 pci_restore_ptm_state(dev);
1741
1742 pci_aer_clear_status(dev);
1743 pci_restore_aer_state(dev);
1744
1745 pci_restore_config_space(dev);
1746
1747 pci_restore_pcix_state(dev);
1748 pci_restore_msi_state(dev);
1749
1750 /* Restore ACS and IOV configuration state */
1751 pci_enable_acs(dev);
1752 pci_restore_iov_state(dev);
1753
1754 dev->state_saved = false;
1755 }
1756 EXPORT_SYMBOL(pci_restore_state);
1757
1758 struct pci_saved_state {
1759 u32 config_space[16];
1760 struct pci_cap_saved_data cap[];
1761 };
1762
1763 /**
1764 * pci_store_saved_state - Allocate and return an opaque struct containing
1765 * the device saved state.
1766 * @dev: PCI device that we're dealing with
1767 *
1768 * Return NULL if no state or error.
1769 */
1770 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1771 {
1772 struct pci_saved_state *state;
1773 struct pci_cap_saved_state *tmp;
1774 struct pci_cap_saved_data *cap;
1775 size_t size;
1776
1777 if (!dev->state_saved)
1778 return NULL;
1779
1780 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1781
1782 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1783 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1784
1785 state = kzalloc(size, GFP_KERNEL);
1786 if (!state)
1787 return NULL;
1788
1789 memcpy(state->config_space, dev->saved_config_space,
1790 sizeof(state->config_space));
1791
1792 cap = state->cap;
1793 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1794 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1795 memcpy(cap, &tmp->cap, len);
1796 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1797 }
1798 /* Empty cap_save terminates list */
1799
1800 return state;
1801 }
1802 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1803
1804 /**
1805 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1806 * @dev: PCI device that we're dealing with
1807 * @state: Saved state returned from pci_store_saved_state()
1808 */
1809 int pci_load_saved_state(struct pci_dev *dev,
1810 struct pci_saved_state *state)
1811 {
1812 struct pci_cap_saved_data *cap;
1813
1814 dev->state_saved = false;
1815
1816 if (!state)
1817 return 0;
1818
1819 memcpy(dev->saved_config_space, state->config_space,
1820 sizeof(state->config_space));
1821
1822 cap = state->cap;
1823 while (cap->size) {
1824 struct pci_cap_saved_state *tmp;
1825
1826 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1827 if (!tmp || tmp->cap.size != cap->size)
1828 return -EINVAL;
1829
1830 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1831 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1832 sizeof(struct pci_cap_saved_data) + cap->size);
1833 }
1834
1835 dev->state_saved = true;
1836 return 0;
1837 }
1838 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1839
1840 /**
1841 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1842 * and free the memory allocated for it.
1843 * @dev: PCI device that we're dealing with
1844 * @state: Pointer to saved state returned from pci_store_saved_state()
1845 */
1846 int pci_load_and_free_saved_state(struct pci_dev *dev,
1847 struct pci_saved_state **state)
1848 {
1849 int ret = pci_load_saved_state(dev, *state);
1850 kfree(*state);
1851 *state = NULL;
1852 return ret;
1853 }
1854 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1855
1856 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1857 {
1858 return pci_enable_resources(dev, bars);
1859 }
1860
1861 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1862 {
1863 int err;
1864 struct pci_dev *bridge;
1865 u16 cmd;
1866 u8 pin;
1867
1868 err = pci_set_power_state(dev, PCI_D0);
1869 if (err < 0 && err != -EIO)
1870 return err;
1871
1872 bridge = pci_upstream_bridge(dev);
1873 if (bridge)
1874 pcie_aspm_powersave_config_link(bridge);
1875
1876 err = pcibios_enable_device(dev, bars);
1877 if (err < 0)
1878 return err;
1879 pci_fixup_device(pci_fixup_enable, dev);
1880
1881 if (dev->msi_enabled || dev->msix_enabled)
1882 return 0;
1883
1884 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1885 if (pin) {
1886 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1887 if (cmd & PCI_COMMAND_INTX_DISABLE)
1888 pci_write_config_word(dev, PCI_COMMAND,
1889 cmd & ~PCI_COMMAND_INTX_DISABLE);
1890 }
1891
1892 return 0;
1893 }
1894
1895 /**
1896 * pci_reenable_device - Resume abandoned device
1897 * @dev: PCI device to be resumed
1898 *
1899 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1900 * to be called by normal code, write proper resume handler and use it instead.
1901 */
1902 int pci_reenable_device(struct pci_dev *dev)
1903 {
1904 if (pci_is_enabled(dev))
1905 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1906 return 0;
1907 }
1908 EXPORT_SYMBOL(pci_reenable_device);
1909
1910 static void pci_enable_bridge(struct pci_dev *dev)
1911 {
1912 struct pci_dev *bridge;
1913 int retval;
1914
1915 bridge = pci_upstream_bridge(dev);
1916 if (bridge)
1917 pci_enable_bridge(bridge);
1918
1919 if (pci_is_enabled(dev)) {
1920 if (!dev->is_busmaster)
1921 pci_set_master(dev);
1922 return;
1923 }
1924
1925 retval = pci_enable_device(dev);
1926 if (retval)
1927 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1928 retval);
1929 pci_set_master(dev);
1930 }
1931
1932 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1933 {
1934 struct pci_dev *bridge;
1935 int err;
1936 int i, bars = 0;
1937
1938 /*
1939 * Power state could be unknown at this point, either due to a fresh
1940 * boot or a device removal call. So get the current power state
1941 * so that things like MSI message writing will behave as expected
1942 * (e.g. if the device really is in D0 at enable time).
1943 */
1944 pci_update_current_state(dev, dev->current_state);
1945
1946 if (atomic_inc_return(&dev->enable_cnt) > 1)
1947 return 0; /* already enabled */
1948
1949 bridge = pci_upstream_bridge(dev);
1950 if (bridge)
1951 pci_enable_bridge(bridge);
1952
1953 /* only skip sriov related */
1954 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1955 if (dev->resource[i].flags & flags)
1956 bars |= (1 << i);
1957 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1958 if (dev->resource[i].flags & flags)
1959 bars |= (1 << i);
1960
1961 err = do_pci_enable_device(dev, bars);
1962 if (err < 0)
1963 atomic_dec(&dev->enable_cnt);
1964 return err;
1965 }
1966
1967 /**
1968 * pci_enable_device_io - Initialize a device for use with IO space
1969 * @dev: PCI device to be initialized
1970 *
1971 * Initialize device before it's used by a driver. Ask low-level code
1972 * to enable I/O resources. Wake up the device if it was suspended.
1973 * Beware, this function can fail.
1974 */
1975 int pci_enable_device_io(struct pci_dev *dev)
1976 {
1977 return pci_enable_device_flags(dev, IORESOURCE_IO);
1978 }
1979 EXPORT_SYMBOL(pci_enable_device_io);
1980
1981 /**
1982 * pci_enable_device_mem - Initialize a device for use with Memory space
1983 * @dev: PCI device to be initialized
1984 *
1985 * Initialize device before it's used by a driver. Ask low-level code
1986 * to enable Memory resources. Wake up the device if it was suspended.
1987 * Beware, this function can fail.
1988 */
1989 int pci_enable_device_mem(struct pci_dev *dev)
1990 {
1991 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1992 }
1993 EXPORT_SYMBOL(pci_enable_device_mem);
1994
1995 /**
1996 * pci_enable_device - Initialize device before it's used by a driver.
1997 * @dev: PCI device to be initialized
1998 *
1999 * Initialize device before it's used by a driver. Ask low-level code
2000 * to enable I/O and memory. Wake up the device if it was suspended.
2001 * Beware, this function can fail.
2002 *
2003 * Note we don't actually enable the device many times if we call
2004 * this function repeatedly (we just increment the count).
2005 */
2006 int pci_enable_device(struct pci_dev *dev)
2007 {
2008 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2009 }
2010 EXPORT_SYMBOL(pci_enable_device);
2011
2012 /*
2013 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2014 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2015 * there's no need to track it separately. pci_devres is initialized
2016 * when a device is enabled using managed PCI device enable interface.
2017 */
2018 struct pci_devres {
2019 unsigned int enabled:1;
2020 unsigned int pinned:1;
2021 unsigned int orig_intx:1;
2022 unsigned int restore_intx:1;
2023 unsigned int mwi:1;
2024 u32 region_mask;
2025 };
2026
2027 static void pcim_release(struct device *gendev, void *res)
2028 {
2029 struct pci_dev *dev = to_pci_dev(gendev);
2030 struct pci_devres *this = res;
2031 int i;
2032
2033 if (dev->msi_enabled)
2034 pci_disable_msi(dev);
2035 if (dev->msix_enabled)
2036 pci_disable_msix(dev);
2037
2038 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2039 if (this->region_mask & (1 << i))
2040 pci_release_region(dev, i);
2041
2042 if (this->mwi)
2043 pci_clear_mwi(dev);
2044
2045 if (this->restore_intx)
2046 pci_intx(dev, this->orig_intx);
2047
2048 if (this->enabled && !this->pinned)
2049 pci_disable_device(dev);
2050 }
2051
2052 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2053 {
2054 struct pci_devres *dr, *new_dr;
2055
2056 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2057 if (dr)
2058 return dr;
2059
2060 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2061 if (!new_dr)
2062 return NULL;
2063 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2064 }
2065
2066 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2067 {
2068 if (pci_is_managed(pdev))
2069 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2070 return NULL;
2071 }
2072
2073 /**
2074 * pcim_enable_device - Managed pci_enable_device()
2075 * @pdev: PCI device to be initialized
2076 *
2077 * Managed pci_enable_device().
2078 */
2079 int pcim_enable_device(struct pci_dev *pdev)
2080 {
2081 struct pci_devres *dr;
2082 int rc;
2083
2084 dr = get_pci_dr(pdev);
2085 if (unlikely(!dr))
2086 return -ENOMEM;
2087 if (dr->enabled)
2088 return 0;
2089
2090 rc = pci_enable_device(pdev);
2091 if (!rc) {
2092 pdev->is_managed = 1;
2093 dr->enabled = 1;
2094 }
2095 return rc;
2096 }
2097 EXPORT_SYMBOL(pcim_enable_device);
2098
2099 /**
2100 * pcim_pin_device - Pin managed PCI device
2101 * @pdev: PCI device to pin
2102 *
2103 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2104 * driver detach. @pdev must have been enabled with
2105 * pcim_enable_device().
2106 */
2107 void pcim_pin_device(struct pci_dev *pdev)
2108 {
2109 struct pci_devres *dr;
2110
2111 dr = find_pci_dr(pdev);
2112 WARN_ON(!dr || !dr->enabled);
2113 if (dr)
2114 dr->pinned = 1;
2115 }
2116 EXPORT_SYMBOL(pcim_pin_device);
2117
2118 /*
2119 * pcibios_device_add - provide arch specific hooks when adding device dev
2120 * @dev: the PCI device being added
2121 *
2122 * Permits the platform to provide architecture specific functionality when
2123 * devices are added. This is the default implementation. Architecture
2124 * implementations can override this.
2125 */
2126 int __weak pcibios_device_add(struct pci_dev *dev)
2127 {
2128 return 0;
2129 }
2130
2131 /**
2132 * pcibios_release_device - provide arch specific hooks when releasing
2133 * device dev
2134 * @dev: the PCI device being released
2135 *
2136 * Permits the platform to provide architecture specific functionality when
2137 * devices are released. This is the default implementation. Architecture
2138 * implementations can override this.
2139 */
2140 void __weak pcibios_release_device(struct pci_dev *dev) {}
2141
2142 /**
2143 * pcibios_disable_device - disable arch specific PCI resources for device dev
2144 * @dev: the PCI device to disable
2145 *
2146 * Disables architecture specific PCI resources for the device. This
2147 * is the default implementation. Architecture implementations can
2148 * override this.
2149 */
2150 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2151
2152 /**
2153 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2154 * @irq: ISA IRQ to penalize
2155 * @active: IRQ active or not
2156 *
2157 * Permits the platform to provide architecture-specific functionality when
2158 * penalizing ISA IRQs. This is the default implementation. Architecture
2159 * implementations can override this.
2160 */
2161 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2162
2163 static void do_pci_disable_device(struct pci_dev *dev)
2164 {
2165 u16 pci_command;
2166
2167 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2168 if (pci_command & PCI_COMMAND_MASTER) {
2169 pci_command &= ~PCI_COMMAND_MASTER;
2170 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2171 }
2172
2173 pcibios_disable_device(dev);
2174 }
2175
2176 /**
2177 * pci_disable_enabled_device - Disable device without updating enable_cnt
2178 * @dev: PCI device to disable
2179 *
2180 * NOTE: This function is a backend of PCI power management routines and is
2181 * not supposed to be called drivers.
2182 */
2183 void pci_disable_enabled_device(struct pci_dev *dev)
2184 {
2185 if (pci_is_enabled(dev))
2186 do_pci_disable_device(dev);
2187 }
2188
2189 /**
2190 * pci_disable_device - Disable PCI device after use
2191 * @dev: PCI device to be disabled
2192 *
2193 * Signal to the system that the PCI device is not in use by the system
2194 * anymore. This only involves disabling PCI bus-mastering, if active.
2195 *
2196 * Note we don't actually disable the device until all callers of
2197 * pci_enable_device() have called pci_disable_device().
2198 */
2199 void pci_disable_device(struct pci_dev *dev)
2200 {
2201 struct pci_devres *dr;
2202
2203 dr = find_pci_dr(dev);
2204 if (dr)
2205 dr->enabled = 0;
2206
2207 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2208 "disabling already-disabled device");
2209
2210 if (atomic_dec_return(&dev->enable_cnt) != 0)
2211 return;
2212
2213 do_pci_disable_device(dev);
2214
2215 dev->is_busmaster = 0;
2216 }
2217 EXPORT_SYMBOL(pci_disable_device);
2218
2219 /**
2220 * pcibios_set_pcie_reset_state - set reset state for device dev
2221 * @dev: the PCIe device reset
2222 * @state: Reset state to enter into
2223 *
2224 * Set the PCIe reset state for the device. This is the default
2225 * implementation. Architecture implementations can override this.
2226 */
2227 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2228 enum pcie_reset_state state)
2229 {
2230 return -EINVAL;
2231 }
2232
2233 /**
2234 * pci_set_pcie_reset_state - set reset state for device dev
2235 * @dev: the PCIe device reset
2236 * @state: Reset state to enter into
2237 *
2238 * Sets the PCI reset state for the device.
2239 */
2240 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2241 {
2242 return pcibios_set_pcie_reset_state(dev, state);
2243 }
2244 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2245
2246 void pcie_clear_device_status(struct pci_dev *dev)
2247 {
2248 u16 sta;
2249
2250 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2251 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2252 }
2253
2254 /**
2255 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2256 * @dev: PCIe root port or event collector.
2257 */
2258 void pcie_clear_root_pme_status(struct pci_dev *dev)
2259 {
2260 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2261 }
2262
2263 /**
2264 * pci_check_pme_status - Check if given device has generated PME.
2265 * @dev: Device to check.
2266 *
2267 * Check the PME status of the device and if set, clear it and clear PME enable
2268 * (if set). Return 'true' if PME status and PME enable were both set or
2269 * 'false' otherwise.
2270 */
2271 bool pci_check_pme_status(struct pci_dev *dev)
2272 {
2273 int pmcsr_pos;
2274 u16 pmcsr;
2275 bool ret = false;
2276
2277 if (!dev->pm_cap)
2278 return false;
2279
2280 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2281 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2282 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2283 return false;
2284
2285 /* Clear PME status. */
2286 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2287 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2288 /* Disable PME to avoid interrupt flood. */
2289 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2290 ret = true;
2291 }
2292
2293 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2294
2295 return ret;
2296 }
2297
2298 /**
2299 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2300 * @dev: Device to handle.
2301 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2302 *
2303 * Check if @dev has generated PME and queue a resume request for it in that
2304 * case.
2305 */
2306 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2307 {
2308 if (pme_poll_reset && dev->pme_poll)
2309 dev->pme_poll = false;
2310
2311 if (pci_check_pme_status(dev)) {
2312 pci_wakeup_event(dev);
2313 pm_request_resume(&dev->dev);
2314 }
2315 return 0;
2316 }
2317
2318 /**
2319 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2320 * @bus: Top bus of the subtree to walk.
2321 */
2322 void pci_pme_wakeup_bus(struct pci_bus *bus)
2323 {
2324 if (bus)
2325 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2326 }
2327
2328
2329 /**
2330 * pci_pme_capable - check the capability of PCI device to generate PME#
2331 * @dev: PCI device to handle.
2332 * @state: PCI state from which device will issue PME#.
2333 */
2334 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2335 {
2336 if (!dev->pm_cap)
2337 return false;
2338
2339 return !!(dev->pme_support & (1 << state));
2340 }
2341 EXPORT_SYMBOL(pci_pme_capable);
2342
2343 static void pci_pme_list_scan(struct work_struct *work)
2344 {
2345 struct pci_pme_device *pme_dev, *n;
2346
2347 mutex_lock(&pci_pme_list_mutex);
2348 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2349 if (pme_dev->dev->pme_poll) {
2350 struct pci_dev *bridge;
2351
2352 bridge = pme_dev->dev->bus->self;
2353 /*
2354 * If bridge is in low power state, the
2355 * configuration space of subordinate devices
2356 * may be not accessible
2357 */
2358 if (bridge && bridge->current_state != PCI_D0)
2359 continue;
2360 /*
2361 * If the device is in D3cold it should not be
2362 * polled either.
2363 */
2364 if (pme_dev->dev->current_state == PCI_D3cold)
2365 continue;
2366
2367 pci_pme_wakeup(pme_dev->dev, NULL);
2368 } else {
2369 list_del(&pme_dev->list);
2370 kfree(pme_dev);
2371 }
2372 }
2373 if (!list_empty(&pci_pme_list))
2374 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2375 msecs_to_jiffies(PME_TIMEOUT));
2376 mutex_unlock(&pci_pme_list_mutex);
2377 }
2378
2379 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2380 {
2381 u16 pmcsr;
2382
2383 if (!dev->pme_support)
2384 return;
2385
2386 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2387 /* Clear PME_Status by writing 1 to it and enable PME# */
2388 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2389 if (!enable)
2390 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2391
2392 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2393 }
2394
2395 /**
2396 * pci_pme_restore - Restore PME configuration after config space restore.
2397 * @dev: PCI device to update.
2398 */
2399 void pci_pme_restore(struct pci_dev *dev)
2400 {
2401 u16 pmcsr;
2402
2403 if (!dev->pme_support)
2404 return;
2405
2406 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2407 if (dev->wakeup_prepared) {
2408 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2409 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2410 } else {
2411 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2412 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2413 }
2414 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2415 }
2416
2417 /**
2418 * pci_pme_active - enable or disable PCI device's PME# function
2419 * @dev: PCI device to handle.
2420 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2421 *
2422 * The caller must verify that the device is capable of generating PME# before
2423 * calling this function with @enable equal to 'true'.
2424 */
2425 void pci_pme_active(struct pci_dev *dev, bool enable)
2426 {
2427 __pci_pme_active(dev, enable);
2428
2429 /*
2430 * PCI (as opposed to PCIe) PME requires that the device have
2431 * its PME# line hooked up correctly. Not all hardware vendors
2432 * do this, so the PME never gets delivered and the device
2433 * remains asleep. The easiest way around this is to
2434 * periodically walk the list of suspended devices and check
2435 * whether any have their PME flag set. The assumption is that
2436 * we'll wake up often enough anyway that this won't be a huge
2437 * hit, and the power savings from the devices will still be a
2438 * win.
2439 *
2440 * Although PCIe uses in-band PME message instead of PME# line
2441 * to report PME, PME does not work for some PCIe devices in
2442 * reality. For example, there are devices that set their PME
2443 * status bits, but don't really bother to send a PME message;
2444 * there are PCI Express Root Ports that don't bother to
2445 * trigger interrupts when they receive PME messages from the
2446 * devices below. So PME poll is used for PCIe devices too.
2447 */
2448
2449 if (dev->pme_poll) {
2450 struct pci_pme_device *pme_dev;
2451 if (enable) {
2452 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2453 GFP_KERNEL);
2454 if (!pme_dev) {
2455 pci_warn(dev, "can't enable PME#\n");
2456 return;
2457 }
2458 pme_dev->dev = dev;
2459 mutex_lock(&pci_pme_list_mutex);
2460 list_add(&pme_dev->list, &pci_pme_list);
2461 if (list_is_singular(&pci_pme_list))
2462 queue_delayed_work(system_freezable_wq,
2463 &pci_pme_work,
2464 msecs_to_jiffies(PME_TIMEOUT));
2465 mutex_unlock(&pci_pme_list_mutex);
2466 } else {
2467 mutex_lock(&pci_pme_list_mutex);
2468 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2469 if (pme_dev->dev == dev) {
2470 list_del(&pme_dev->list);
2471 kfree(pme_dev);
2472 break;
2473 }
2474 }
2475 mutex_unlock(&pci_pme_list_mutex);
2476 }
2477 }
2478
2479 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2480 }
2481 EXPORT_SYMBOL(pci_pme_active);
2482
2483 /**
2484 * __pci_enable_wake - enable PCI device as wakeup event source
2485 * @dev: PCI device affected
2486 * @state: PCI state from which device will issue wakeup events
2487 * @enable: True to enable event generation; false to disable
2488 *
2489 * This enables the device as a wakeup event source, or disables it.
2490 * When such events involves platform-specific hooks, those hooks are
2491 * called automatically by this routine.
2492 *
2493 * Devices with legacy power management (no standard PCI PM capabilities)
2494 * always require such platform hooks.
2495 *
2496 * RETURN VALUE:
2497 * 0 is returned on success
2498 * -EINVAL is returned if device is not supposed to wake up the system
2499 * Error code depending on the platform is returned if both the platform and
2500 * the native mechanism fail to enable the generation of wake-up events
2501 */
2502 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2503 {
2504 int ret = 0;
2505
2506 /*
2507 * Bridges that are not power-manageable directly only signal
2508 * wakeup on behalf of subordinate devices which is set up
2509 * elsewhere, so skip them. However, bridges that are
2510 * power-manageable may signal wakeup for themselves (for example,
2511 * on a hotplug event) and they need to be covered here.
2512 */
2513 if (!pci_power_manageable(dev))
2514 return 0;
2515
2516 /* Don't do the same thing twice in a row for one device. */
2517 if (!!enable == !!dev->wakeup_prepared)
2518 return 0;
2519
2520 /*
2521 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2522 * Anderson we should be doing PME# wake enable followed by ACPI wake
2523 * enable. To disable wake-up we call the platform first, for symmetry.
2524 */
2525
2526 if (enable) {
2527 int error;
2528
2529 /*
2530 * Enable PME signaling if the device can signal PME from
2531 * D3cold regardless of whether or not it can signal PME from
2532 * the current target state, because that will allow it to
2533 * signal PME when the hierarchy above it goes into D3cold and
2534 * the device itself ends up in D3cold as a result of that.
2535 */
2536 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2537 pci_pme_active(dev, true);
2538 else
2539 ret = 1;
2540 error = platform_pci_set_wakeup(dev, true);
2541 if (ret)
2542 ret = error;
2543 if (!ret)
2544 dev->wakeup_prepared = true;
2545 } else {
2546 platform_pci_set_wakeup(dev, false);
2547 pci_pme_active(dev, false);
2548 dev->wakeup_prepared = false;
2549 }
2550
2551 return ret;
2552 }
2553
2554 /**
2555 * pci_enable_wake - change wakeup settings for a PCI device
2556 * @pci_dev: Target device
2557 * @state: PCI state from which device will issue wakeup events
2558 * @enable: Whether or not to enable event generation
2559 *
2560 * If @enable is set, check device_may_wakeup() for the device before calling
2561 * __pci_enable_wake() for it.
2562 */
2563 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2564 {
2565 if (enable && !device_may_wakeup(&pci_dev->dev))
2566 return -EINVAL;
2567
2568 return __pci_enable_wake(pci_dev, state, enable);
2569 }
2570 EXPORT_SYMBOL(pci_enable_wake);
2571
2572 /**
2573 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2574 * @dev: PCI device to prepare
2575 * @enable: True to enable wake-up event generation; false to disable
2576 *
2577 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2578 * and this function allows them to set that up cleanly - pci_enable_wake()
2579 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2580 * ordering constraints.
2581 *
2582 * This function only returns error code if the device is not allowed to wake
2583 * up the system from sleep or it is not capable of generating PME# from both
2584 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2585 */
2586 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2587 {
2588 return pci_pme_capable(dev, PCI_D3cold) ?
2589 pci_enable_wake(dev, PCI_D3cold, enable) :
2590 pci_enable_wake(dev, PCI_D3hot, enable);
2591 }
2592 EXPORT_SYMBOL(pci_wake_from_d3);
2593
2594 /**
2595 * pci_target_state - find an appropriate low power state for a given PCI dev
2596 * @dev: PCI device
2597 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2598 *
2599 * Use underlying platform code to find a supported low power state for @dev.
2600 * If the platform can't manage @dev, return the deepest state from which it
2601 * can generate wake events, based on any available PME info.
2602 */
2603 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2604 {
2605 pci_power_t target_state = PCI_D3hot;
2606
2607 if (platform_pci_power_manageable(dev)) {
2608 /*
2609 * Call the platform to find the target state for the device.
2610 */
2611 pci_power_t state = platform_pci_choose_state(dev);
2612
2613 switch (state) {
2614 case PCI_POWER_ERROR:
2615 case PCI_UNKNOWN:
2616 break;
2617 case PCI_D1:
2618 case PCI_D2:
2619 if (pci_no_d1d2(dev))
2620 break;
2621 fallthrough;
2622 default:
2623 target_state = state;
2624 }
2625
2626 return target_state;
2627 }
2628
2629 if (!dev->pm_cap)
2630 target_state = PCI_D0;
2631
2632 /*
2633 * If the device is in D3cold even though it's not power-manageable by
2634 * the platform, it may have been powered down by non-standard means.
2635 * Best to let it slumber.
2636 */
2637 if (dev->current_state == PCI_D3cold)
2638 target_state = PCI_D3cold;
2639
2640 if (wakeup && dev->pme_support) {
2641 pci_power_t state = target_state;
2642
2643 /*
2644 * Find the deepest state from which the device can generate
2645 * PME#.
2646 */
2647 while (state && !(dev->pme_support & (1 << state)))
2648 state--;
2649
2650 if (state)
2651 return state;
2652 else if (dev->pme_support & 1)
2653 return PCI_D0;
2654 }
2655
2656 return target_state;
2657 }
2658
2659 /**
2660 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2661 * into a sleep state
2662 * @dev: Device to handle.
2663 *
2664 * Choose the power state appropriate for the device depending on whether
2665 * it can wake up the system and/or is power manageable by the platform
2666 * (PCI_D3hot is the default) and put the device into that state.
2667 */
2668 int pci_prepare_to_sleep(struct pci_dev *dev)
2669 {
2670 bool wakeup = device_may_wakeup(&dev->dev);
2671 pci_power_t target_state = pci_target_state(dev, wakeup);
2672 int error;
2673
2674 if (target_state == PCI_POWER_ERROR)
2675 return -EIO;
2676
2677 /*
2678 * There are systems (for example, Intel mobile chips since Coffee
2679 * Lake) where the power drawn while suspended can be significantly
2680 * reduced by disabling PTM on PCIe root ports as this allows the
2681 * port to enter a lower-power PM state and the SoC to reach a
2682 * lower-power idle state as a whole.
2683 */
2684 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2685 pci_disable_ptm(dev);
2686
2687 pci_enable_wake(dev, target_state, wakeup);
2688
2689 error = pci_set_power_state(dev, target_state);
2690
2691 if (error) {
2692 pci_enable_wake(dev, target_state, false);
2693 pci_restore_ptm_state(dev);
2694 }
2695
2696 return error;
2697 }
2698 EXPORT_SYMBOL(pci_prepare_to_sleep);
2699
2700 /**
2701 * pci_back_from_sleep - turn PCI device on during system-wide transition
2702 * into working state
2703 * @dev: Device to handle.
2704 *
2705 * Disable device's system wake-up capability and put it into D0.
2706 */
2707 int pci_back_from_sleep(struct pci_dev *dev)
2708 {
2709 pci_enable_wake(dev, PCI_D0, false);
2710 return pci_set_power_state(dev, PCI_D0);
2711 }
2712 EXPORT_SYMBOL(pci_back_from_sleep);
2713
2714 /**
2715 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2716 * @dev: PCI device being suspended.
2717 *
2718 * Prepare @dev to generate wake-up events at run time and put it into a low
2719 * power state.
2720 */
2721 int pci_finish_runtime_suspend(struct pci_dev *dev)
2722 {
2723 pci_power_t target_state;
2724 int error;
2725
2726 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2727 if (target_state == PCI_POWER_ERROR)
2728 return -EIO;
2729
2730 dev->runtime_d3cold = target_state == PCI_D3cold;
2731
2732 /*
2733 * There are systems (for example, Intel mobile chips since Coffee
2734 * Lake) where the power drawn while suspended can be significantly
2735 * reduced by disabling PTM on PCIe root ports as this allows the
2736 * port to enter a lower-power PM state and the SoC to reach a
2737 * lower-power idle state as a whole.
2738 */
2739 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2740 pci_disable_ptm(dev);
2741
2742 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2743
2744 error = pci_set_power_state(dev, target_state);
2745
2746 if (error) {
2747 pci_enable_wake(dev, target_state, false);
2748 pci_restore_ptm_state(dev);
2749 dev->runtime_d3cold = false;
2750 }
2751
2752 return error;
2753 }
2754
2755 /**
2756 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2757 * @dev: Device to check.
2758 *
2759 * Return true if the device itself is capable of generating wake-up events
2760 * (through the platform or using the native PCIe PME) or if the device supports
2761 * PME and one of its upstream bridges can generate wake-up events.
2762 */
2763 bool pci_dev_run_wake(struct pci_dev *dev)
2764 {
2765 struct pci_bus *bus = dev->bus;
2766
2767 if (!dev->pme_support)
2768 return false;
2769
2770 /* PME-capable in principle, but not from the target power state */
2771 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2772 return false;
2773
2774 if (device_can_wakeup(&dev->dev))
2775 return true;
2776
2777 while (bus->parent) {
2778 struct pci_dev *bridge = bus->self;
2779
2780 if (device_can_wakeup(&bridge->dev))
2781 return true;
2782
2783 bus = bus->parent;
2784 }
2785
2786 /* We have reached the root bus. */
2787 if (bus->bridge)
2788 return device_can_wakeup(bus->bridge);
2789
2790 return false;
2791 }
2792 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2793
2794 /**
2795 * pci_dev_need_resume - Check if it is necessary to resume the device.
2796 * @pci_dev: Device to check.
2797 *
2798 * Return 'true' if the device is not runtime-suspended or it has to be
2799 * reconfigured due to wakeup settings difference between system and runtime
2800 * suspend, or the current power state of it is not suitable for the upcoming
2801 * (system-wide) transition.
2802 */
2803 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2804 {
2805 struct device *dev = &pci_dev->dev;
2806 pci_power_t target_state;
2807
2808 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2809 return true;
2810
2811 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2812
2813 /*
2814 * If the earlier platform check has not triggered, D3cold is just power
2815 * removal on top of D3hot, so no need to resume the device in that
2816 * case.
2817 */
2818 return target_state != pci_dev->current_state &&
2819 target_state != PCI_D3cold &&
2820 pci_dev->current_state != PCI_D3hot;
2821 }
2822
2823 /**
2824 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2825 * @pci_dev: Device to check.
2826 *
2827 * If the device is suspended and it is not configured for system wakeup,
2828 * disable PME for it to prevent it from waking up the system unnecessarily.
2829 *
2830 * Note that if the device's power state is D3cold and the platform check in
2831 * pci_dev_need_resume() has not triggered, the device's configuration need not
2832 * be changed.
2833 */
2834 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2835 {
2836 struct device *dev = &pci_dev->dev;
2837
2838 spin_lock_irq(&dev->power.lock);
2839
2840 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2841 pci_dev->current_state < PCI_D3cold)
2842 __pci_pme_active(pci_dev, false);
2843
2844 spin_unlock_irq(&dev->power.lock);
2845 }
2846
2847 /**
2848 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2849 * @pci_dev: Device to handle.
2850 *
2851 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2852 * it might have been disabled during the prepare phase of system suspend if
2853 * the device was not configured for system wakeup.
2854 */
2855 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2856 {
2857 struct device *dev = &pci_dev->dev;
2858
2859 if (!pci_dev_run_wake(pci_dev))
2860 return;
2861
2862 spin_lock_irq(&dev->power.lock);
2863
2864 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2865 __pci_pme_active(pci_dev, true);
2866
2867 spin_unlock_irq(&dev->power.lock);
2868 }
2869
2870 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2871 {
2872 struct device *dev = &pdev->dev;
2873 struct device *parent = dev->parent;
2874
2875 if (parent)
2876 pm_runtime_get_sync(parent);
2877 pm_runtime_get_noresume(dev);
2878 /*
2879 * pdev->current_state is set to PCI_D3cold during suspending,
2880 * so wait until suspending completes
2881 */
2882 pm_runtime_barrier(dev);
2883 /*
2884 * Only need to resume devices in D3cold, because config
2885 * registers are still accessible for devices suspended but
2886 * not in D3cold.
2887 */
2888 if (pdev->current_state == PCI_D3cold)
2889 pm_runtime_resume(dev);
2890 }
2891
2892 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2893 {
2894 struct device *dev = &pdev->dev;
2895 struct device *parent = dev->parent;
2896
2897 pm_runtime_put(dev);
2898 if (parent)
2899 pm_runtime_put_sync(parent);
2900 }
2901
2902 static const struct dmi_system_id bridge_d3_blacklist[] = {
2903 #ifdef CONFIG_X86
2904 {
2905 /*
2906 * Gigabyte X299 root port is not marked as hotplug capable
2907 * which allows Linux to power manage it. However, this
2908 * confuses the BIOS SMI handler so don't power manage root
2909 * ports on that system.
2910 */
2911 .ident = "X299 DESIGNARE EX-CF",
2912 .matches = {
2913 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2914 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2915 },
2916 },
2917 #endif
2918 { }
2919 };
2920
2921 /**
2922 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2923 * @bridge: Bridge to check
2924 *
2925 * This function checks if it is possible to move the bridge to D3.
2926 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2927 */
2928 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2929 {
2930 if (!pci_is_pcie(bridge))
2931 return false;
2932
2933 switch (pci_pcie_type(bridge)) {
2934 case PCI_EXP_TYPE_ROOT_PORT:
2935 case PCI_EXP_TYPE_UPSTREAM:
2936 case PCI_EXP_TYPE_DOWNSTREAM:
2937 if (pci_bridge_d3_disable)
2938 return false;
2939
2940 /*
2941 * Hotplug ports handled by firmware in System Management Mode
2942 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2943 */
2944 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2945 return false;
2946
2947 if (pci_bridge_d3_force)
2948 return true;
2949
2950 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2951 if (bridge->is_thunderbolt)
2952 return true;
2953
2954 /* Platform might know better if the bridge supports D3 */
2955 if (platform_pci_bridge_d3(bridge))
2956 return true;
2957
2958 /*
2959 * Hotplug ports handled natively by the OS were not validated
2960 * by vendors for runtime D3 at least until 2018 because there
2961 * was no OS support.
2962 */
2963 if (bridge->is_hotplug_bridge)
2964 return false;
2965
2966 if (dmi_check_system(bridge_d3_blacklist))
2967 return false;
2968
2969 /*
2970 * It should be safe to put PCIe ports from 2015 or newer
2971 * to D3.
2972 */
2973 if (dmi_get_bios_year() >= 2015)
2974 return true;
2975 break;
2976 }
2977
2978 return false;
2979 }
2980
2981 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2982 {
2983 bool *d3cold_ok = data;
2984
2985 if (/* The device needs to be allowed to go D3cold ... */
2986 dev->no_d3cold || !dev->d3cold_allowed ||
2987
2988 /* ... and if it is wakeup capable to do so from D3cold. */
2989 (device_may_wakeup(&dev->dev) &&
2990 !pci_pme_capable(dev, PCI_D3cold)) ||
2991
2992 /* If it is a bridge it must be allowed to go to D3. */
2993 !pci_power_manageable(dev))
2994
2995 *d3cold_ok = false;
2996
2997 return !*d3cold_ok;
2998 }
2999
3000 /*
3001 * pci_bridge_d3_update - Update bridge D3 capabilities
3002 * @dev: PCI device which is changed
3003 *
3004 * Update upstream bridge PM capabilities accordingly depending on if the
3005 * device PM configuration was changed or the device is being removed. The
3006 * change is also propagated upstream.
3007 */
3008 void pci_bridge_d3_update(struct pci_dev *dev)
3009 {
3010 bool remove = !device_is_registered(&dev->dev);
3011 struct pci_dev *bridge;
3012 bool d3cold_ok = true;
3013
3014 bridge = pci_upstream_bridge(dev);
3015 if (!bridge || !pci_bridge_d3_possible(bridge))
3016 return;
3017
3018 /*
3019 * If D3 is currently allowed for the bridge, removing one of its
3020 * children won't change that.
3021 */
3022 if (remove && bridge->bridge_d3)
3023 return;
3024
3025 /*
3026 * If D3 is currently allowed for the bridge and a child is added or
3027 * changed, disallowance of D3 can only be caused by that child, so
3028 * we only need to check that single device, not any of its siblings.
3029 *
3030 * If D3 is currently not allowed for the bridge, checking the device
3031 * first may allow us to skip checking its siblings.
3032 */
3033 if (!remove)
3034 pci_dev_check_d3cold(dev, &d3cold_ok);
3035
3036 /*
3037 * If D3 is currently not allowed for the bridge, this may be caused
3038 * either by the device being changed/removed or any of its siblings,
3039 * so we need to go through all children to find out if one of them
3040 * continues to block D3.
3041 */
3042 if (d3cold_ok && !bridge->bridge_d3)
3043 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3044 &d3cold_ok);
3045
3046 if (bridge->bridge_d3 != d3cold_ok) {
3047 bridge->bridge_d3 = d3cold_ok;
3048 /* Propagate change to upstream bridges */
3049 pci_bridge_d3_update(bridge);
3050 }
3051 }
3052
3053 /**
3054 * pci_d3cold_enable - Enable D3cold for device
3055 * @dev: PCI device to handle
3056 *
3057 * This function can be used in drivers to enable D3cold from the device
3058 * they handle. It also updates upstream PCI bridge PM capabilities
3059 * accordingly.
3060 */
3061 void pci_d3cold_enable(struct pci_dev *dev)
3062 {
3063 if (dev->no_d3cold) {
3064 dev->no_d3cold = false;
3065 pci_bridge_d3_update(dev);
3066 }
3067 }
3068 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3069
3070 /**
3071 * pci_d3cold_disable - Disable D3cold for device
3072 * @dev: PCI device to handle
3073 *
3074 * This function can be used in drivers to disable D3cold from the device
3075 * they handle. It also updates upstream PCI bridge PM capabilities
3076 * accordingly.
3077 */
3078 void pci_d3cold_disable(struct pci_dev *dev)
3079 {
3080 if (!dev->no_d3cold) {
3081 dev->no_d3cold = true;
3082 pci_bridge_d3_update(dev);
3083 }
3084 }
3085 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3086
3087 /**
3088 * pci_pm_init - Initialize PM functions of given PCI device
3089 * @dev: PCI device to handle.
3090 */
3091 void pci_pm_init(struct pci_dev *dev)
3092 {
3093 int pm;
3094 u16 status;
3095 u16 pmc;
3096
3097 pm_runtime_forbid(&dev->dev);
3098 pm_runtime_set_active(&dev->dev);
3099 pm_runtime_enable(&dev->dev);
3100 device_enable_async_suspend(&dev->dev);
3101 dev->wakeup_prepared = false;
3102
3103 dev->pm_cap = 0;
3104 dev->pme_support = 0;
3105
3106 /* find PCI PM capability in list */
3107 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3108 if (!pm)
3109 return;
3110 /* Check device's ability to generate PME# */
3111 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3112
3113 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3114 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3115 pmc & PCI_PM_CAP_VER_MASK);
3116 return;
3117 }
3118
3119 dev->pm_cap = pm;
3120 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3121 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3122 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3123 dev->d3cold_allowed = true;
3124
3125 dev->d1_support = false;
3126 dev->d2_support = false;
3127 if (!pci_no_d1d2(dev)) {
3128 if (pmc & PCI_PM_CAP_D1)
3129 dev->d1_support = true;
3130 if (pmc & PCI_PM_CAP_D2)
3131 dev->d2_support = true;
3132
3133 if (dev->d1_support || dev->d2_support)
3134 pci_info(dev, "supports%s%s\n",
3135 dev->d1_support ? " D1" : "",
3136 dev->d2_support ? " D2" : "");
3137 }
3138
3139 pmc &= PCI_PM_CAP_PME_MASK;
3140 if (pmc) {
3141 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3142 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3143 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3144 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3145 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3146 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3147 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3148 dev->pme_poll = true;
3149 /*
3150 * Make device's PM flags reflect the wake-up capability, but
3151 * let the user space enable it to wake up the system as needed.
3152 */
3153 device_set_wakeup_capable(&dev->dev, true);
3154 /* Disable the PME# generation functionality */
3155 pci_pme_active(dev, false);
3156 }
3157
3158 pci_read_config_word(dev, PCI_STATUS, &status);
3159 if (status & PCI_STATUS_IMM_READY)
3160 dev->imm_ready = 1;
3161 }
3162
3163 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3164 {
3165 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3166
3167 switch (prop) {
3168 case PCI_EA_P_MEM:
3169 case PCI_EA_P_VF_MEM:
3170 flags |= IORESOURCE_MEM;
3171 break;
3172 case PCI_EA_P_MEM_PREFETCH:
3173 case PCI_EA_P_VF_MEM_PREFETCH:
3174 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3175 break;
3176 case PCI_EA_P_IO:
3177 flags |= IORESOURCE_IO;
3178 break;
3179 default:
3180 return 0;
3181 }
3182
3183 return flags;
3184 }
3185
3186 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3187 u8 prop)
3188 {
3189 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3190 return &dev->resource[bei];
3191 #ifdef CONFIG_PCI_IOV
3192 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3193 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3194 return &dev->resource[PCI_IOV_RESOURCES +
3195 bei - PCI_EA_BEI_VF_BAR0];
3196 #endif
3197 else if (bei == PCI_EA_BEI_ROM)
3198 return &dev->resource[PCI_ROM_RESOURCE];
3199 else
3200 return NULL;
3201 }
3202
3203 /* Read an Enhanced Allocation (EA) entry */
3204 static int pci_ea_read(struct pci_dev *dev, int offset)
3205 {
3206 struct resource *res;
3207 int ent_size, ent_offset = offset;
3208 resource_size_t start, end;
3209 unsigned long flags;
3210 u32 dw0, bei, base, max_offset;
3211 u8 prop;
3212 bool support_64 = (sizeof(resource_size_t) >= 8);
3213
3214 pci_read_config_dword(dev, ent_offset, &dw0);
3215 ent_offset += 4;
3216
3217 /* Entry size field indicates DWORDs after 1st */
3218 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3219
3220 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3221 goto out;
3222
3223 bei = (dw0 & PCI_EA_BEI) >> 4;
3224 prop = (dw0 & PCI_EA_PP) >> 8;
3225
3226 /*
3227 * If the Property is in the reserved range, try the Secondary
3228 * Property instead.
3229 */
3230 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3231 prop = (dw0 & PCI_EA_SP) >> 16;
3232 if (prop > PCI_EA_P_BRIDGE_IO)
3233 goto out;
3234
3235 res = pci_ea_get_resource(dev, bei, prop);
3236 if (!res) {
3237 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3238 goto out;
3239 }
3240
3241 flags = pci_ea_flags(dev, prop);
3242 if (!flags) {
3243 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3244 goto out;
3245 }
3246
3247 /* Read Base */
3248 pci_read_config_dword(dev, ent_offset, &base);
3249 start = (base & PCI_EA_FIELD_MASK);
3250 ent_offset += 4;
3251
3252 /* Read MaxOffset */
3253 pci_read_config_dword(dev, ent_offset, &max_offset);
3254 ent_offset += 4;
3255
3256 /* Read Base MSBs (if 64-bit entry) */
3257 if (base & PCI_EA_IS_64) {
3258 u32 base_upper;
3259
3260 pci_read_config_dword(dev, ent_offset, &base_upper);
3261 ent_offset += 4;
3262
3263 flags |= IORESOURCE_MEM_64;
3264
3265 /* entry starts above 32-bit boundary, can't use */
3266 if (!support_64 && base_upper)
3267 goto out;
3268
3269 if (support_64)
3270 start |= ((u64)base_upper << 32);
3271 }
3272
3273 end = start + (max_offset | 0x03);
3274
3275 /* Read MaxOffset MSBs (if 64-bit entry) */
3276 if (max_offset & PCI_EA_IS_64) {
3277 u32 max_offset_upper;
3278
3279 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3280 ent_offset += 4;
3281
3282 flags |= IORESOURCE_MEM_64;
3283
3284 /* entry too big, can't use */
3285 if (!support_64 && max_offset_upper)
3286 goto out;
3287
3288 if (support_64)
3289 end += ((u64)max_offset_upper << 32);
3290 }
3291
3292 if (end < start) {
3293 pci_err(dev, "EA Entry crosses address boundary\n");
3294 goto out;
3295 }
3296
3297 if (ent_size != ent_offset - offset) {
3298 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3299 ent_size, ent_offset - offset);
3300 goto out;
3301 }
3302
3303 res->name = pci_name(dev);
3304 res->start = start;
3305 res->end = end;
3306 res->flags = flags;
3307
3308 if (bei <= PCI_EA_BEI_BAR5)
3309 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3310 bei, res, prop);
3311 else if (bei == PCI_EA_BEI_ROM)
3312 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3313 res, prop);
3314 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3315 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3316 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3317 else
3318 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3319 bei, res, prop);
3320
3321 out:
3322 return offset + ent_size;
3323 }
3324
3325 /* Enhanced Allocation Initialization */
3326 void pci_ea_init(struct pci_dev *dev)
3327 {
3328 int ea;
3329 u8 num_ent;
3330 int offset;
3331 int i;
3332
3333 /* find PCI EA capability in list */
3334 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3335 if (!ea)
3336 return;
3337
3338 /* determine the number of entries */
3339 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3340 &num_ent);
3341 num_ent &= PCI_EA_NUM_ENT_MASK;
3342
3343 offset = ea + PCI_EA_FIRST_ENT;
3344
3345 /* Skip DWORD 2 for type 1 functions */
3346 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3347 offset += 4;
3348
3349 /* parse each EA entry */
3350 for (i = 0; i < num_ent; ++i)
3351 offset = pci_ea_read(dev, offset);
3352 }
3353
3354 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3355 struct pci_cap_saved_state *new_cap)
3356 {
3357 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3358 }
3359
3360 /**
3361 * _pci_add_cap_save_buffer - allocate buffer for saving given
3362 * capability registers
3363 * @dev: the PCI device
3364 * @cap: the capability to allocate the buffer for
3365 * @extended: Standard or Extended capability ID
3366 * @size: requested size of the buffer
3367 */
3368 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3369 bool extended, unsigned int size)
3370 {
3371 int pos;
3372 struct pci_cap_saved_state *save_state;
3373
3374 if (extended)
3375 pos = pci_find_ext_capability(dev, cap);
3376 else
3377 pos = pci_find_capability(dev, cap);
3378
3379 if (!pos)
3380 return 0;
3381
3382 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3383 if (!save_state)
3384 return -ENOMEM;
3385
3386 save_state->cap.cap_nr = cap;
3387 save_state->cap.cap_extended = extended;
3388 save_state->cap.size = size;
3389 pci_add_saved_cap(dev, save_state);
3390
3391 return 0;
3392 }
3393
3394 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3395 {
3396 return _pci_add_cap_save_buffer(dev, cap, false, size);
3397 }
3398
3399 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3400 {
3401 return _pci_add_cap_save_buffer(dev, cap, true, size);
3402 }
3403
3404 /**
3405 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3406 * @dev: the PCI device
3407 */
3408 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3409 {
3410 int error;
3411
3412 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3413 PCI_EXP_SAVE_REGS * sizeof(u16));
3414 if (error)
3415 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3416
3417 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3418 if (error)
3419 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3420
3421 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3422 2 * sizeof(u16));
3423 if (error)
3424 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3425
3426 pci_allocate_vc_save_buffers(dev);
3427 }
3428
3429 void pci_free_cap_save_buffers(struct pci_dev *dev)
3430 {
3431 struct pci_cap_saved_state *tmp;
3432 struct hlist_node *n;
3433
3434 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3435 kfree(tmp);
3436 }
3437
3438 /**
3439 * pci_configure_ari - enable or disable ARI forwarding
3440 * @dev: the PCI device
3441 *
3442 * If @dev and its upstream bridge both support ARI, enable ARI in the
3443 * bridge. Otherwise, disable ARI in the bridge.
3444 */
3445 void pci_configure_ari(struct pci_dev *dev)
3446 {
3447 u32 cap;
3448 struct pci_dev *bridge;
3449
3450 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3451 return;
3452
3453 bridge = dev->bus->self;
3454 if (!bridge)
3455 return;
3456
3457 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3458 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3459 return;
3460
3461 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3462 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3463 PCI_EXP_DEVCTL2_ARI);
3464 bridge->ari_enabled = 1;
3465 } else {
3466 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3467 PCI_EXP_DEVCTL2_ARI);
3468 bridge->ari_enabled = 0;
3469 }
3470 }
3471
3472 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3473 {
3474 int pos;
3475 u16 cap, ctrl;
3476
3477 pos = pdev->acs_cap;
3478 if (!pos)
3479 return false;
3480
3481 /*
3482 * Except for egress control, capabilities are either required
3483 * or only required if controllable. Features missing from the
3484 * capability field can therefore be assumed as hard-wired enabled.
3485 */
3486 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3487 acs_flags &= (cap | PCI_ACS_EC);
3488
3489 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3490 return (ctrl & acs_flags) == acs_flags;
3491 }
3492
3493 /**
3494 * pci_acs_enabled - test ACS against required flags for a given device
3495 * @pdev: device to test
3496 * @acs_flags: required PCI ACS flags
3497 *
3498 * Return true if the device supports the provided flags. Automatically
3499 * filters out flags that are not implemented on multifunction devices.
3500 *
3501 * Note that this interface checks the effective ACS capabilities of the
3502 * device rather than the actual capabilities. For instance, most single
3503 * function endpoints are not required to support ACS because they have no
3504 * opportunity for peer-to-peer access. We therefore return 'true'
3505 * regardless of whether the device exposes an ACS capability. This makes
3506 * it much easier for callers of this function to ignore the actual type
3507 * or topology of the device when testing ACS support.
3508 */
3509 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3510 {
3511 int ret;
3512
3513 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3514 if (ret >= 0)
3515 return ret > 0;
3516
3517 /*
3518 * Conventional PCI and PCI-X devices never support ACS, either
3519 * effectively or actually. The shared bus topology implies that
3520 * any device on the bus can receive or snoop DMA.
3521 */
3522 if (!pci_is_pcie(pdev))
3523 return false;
3524
3525 switch (pci_pcie_type(pdev)) {
3526 /*
3527 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3528 * but since their primary interface is PCI/X, we conservatively
3529 * handle them as we would a non-PCIe device.
3530 */
3531 case PCI_EXP_TYPE_PCIE_BRIDGE:
3532 /*
3533 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3534 * applicable... must never implement an ACS Extended Capability...".
3535 * This seems arbitrary, but we take a conservative interpretation
3536 * of this statement.
3537 */
3538 case PCI_EXP_TYPE_PCI_BRIDGE:
3539 case PCI_EXP_TYPE_RC_EC:
3540 return false;
3541 /*
3542 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3543 * implement ACS in order to indicate their peer-to-peer capabilities,
3544 * regardless of whether they are single- or multi-function devices.
3545 */
3546 case PCI_EXP_TYPE_DOWNSTREAM:
3547 case PCI_EXP_TYPE_ROOT_PORT:
3548 return pci_acs_flags_enabled(pdev, acs_flags);
3549 /*
3550 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3551 * implemented by the remaining PCIe types to indicate peer-to-peer
3552 * capabilities, but only when they are part of a multifunction
3553 * device. The footnote for section 6.12 indicates the specific
3554 * PCIe types included here.
3555 */
3556 case PCI_EXP_TYPE_ENDPOINT:
3557 case PCI_EXP_TYPE_UPSTREAM:
3558 case PCI_EXP_TYPE_LEG_END:
3559 case PCI_EXP_TYPE_RC_END:
3560 if (!pdev->multifunction)
3561 break;
3562
3563 return pci_acs_flags_enabled(pdev, acs_flags);
3564 }
3565
3566 /*
3567 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3568 * to single function devices with the exception of downstream ports.
3569 */
3570 return true;
3571 }
3572
3573 /**
3574 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3575 * @start: starting downstream device
3576 * @end: ending upstream device or NULL to search to the root bus
3577 * @acs_flags: required flags
3578 *
3579 * Walk up a device tree from start to end testing PCI ACS support. If
3580 * any step along the way does not support the required flags, return false.
3581 */
3582 bool pci_acs_path_enabled(struct pci_dev *start,
3583 struct pci_dev *end, u16 acs_flags)
3584 {
3585 struct pci_dev *pdev, *parent = start;
3586
3587 do {
3588 pdev = parent;
3589
3590 if (!pci_acs_enabled(pdev, acs_flags))
3591 return false;
3592
3593 if (pci_is_root_bus(pdev->bus))
3594 return (end == NULL);
3595
3596 parent = pdev->bus->self;
3597 } while (pdev != end);
3598
3599 return true;
3600 }
3601
3602 /**
3603 * pci_acs_init - Initialize ACS if hardware supports it
3604 * @dev: the PCI device
3605 */
3606 void pci_acs_init(struct pci_dev *dev)
3607 {
3608 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3609
3610 /*
3611 * Attempt to enable ACS regardless of capability because some Root
3612 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3613 * the standard ACS capability but still support ACS via those
3614 * quirks.
3615 */
3616 pci_enable_acs(dev);
3617 }
3618
3619 /**
3620 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3621 * @pdev: PCI device
3622 * @bar: BAR to find
3623 *
3624 * Helper to find the position of the ctrl register for a BAR.
3625 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3626 * Returns -ENOENT if no ctrl register for the BAR could be found.
3627 */
3628 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3629 {
3630 unsigned int pos, nbars, i;
3631 u32 ctrl;
3632
3633 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3634 if (!pos)
3635 return -ENOTSUPP;
3636
3637 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3638 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3639 PCI_REBAR_CTRL_NBAR_SHIFT;
3640
3641 for (i = 0; i < nbars; i++, pos += 8) {
3642 int bar_idx;
3643
3644 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3645 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3646 if (bar_idx == bar)
3647 return pos;
3648 }
3649
3650 return -ENOENT;
3651 }
3652
3653 /**
3654 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3655 * @pdev: PCI device
3656 * @bar: BAR to query
3657 *
3658 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3659 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3660 */
3661 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3662 {
3663 int pos;
3664 u32 cap;
3665
3666 pos = pci_rebar_find_pos(pdev, bar);
3667 if (pos < 0)
3668 return 0;
3669
3670 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3671 cap &= PCI_REBAR_CAP_SIZES;
3672
3673 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3674 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3675 bar == 0 && cap == 0x7000)
3676 cap = 0x3f000;
3677
3678 return cap >> 4;
3679 }
3680 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3681
3682 /**
3683 * pci_rebar_get_current_size - get the current size of a BAR
3684 * @pdev: PCI device
3685 * @bar: BAR to set size to
3686 *
3687 * Read the size of a BAR from the resizable BAR config.
3688 * Returns size if found or negative error code.
3689 */
3690 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3691 {
3692 int pos;
3693 u32 ctrl;
3694
3695 pos = pci_rebar_find_pos(pdev, bar);
3696 if (pos < 0)
3697 return pos;
3698
3699 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3700 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3701 }
3702
3703 /**
3704 * pci_rebar_set_size - set a new size for a BAR
3705 * @pdev: PCI device
3706 * @bar: BAR to set size to
3707 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3708 *
3709 * Set the new size of a BAR as defined in the spec.
3710 * Returns zero if resizing was successful, error code otherwise.
3711 */
3712 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3713 {
3714 int pos;
3715 u32 ctrl;
3716
3717 pos = pci_rebar_find_pos(pdev, bar);
3718 if (pos < 0)
3719 return pos;
3720
3721 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3722 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3723 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3724 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3725 return 0;
3726 }
3727
3728 /**
3729 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3730 * @dev: the PCI device
3731 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3732 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3733 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3734 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3735 *
3736 * Return 0 if all upstream bridges support AtomicOp routing, egress
3737 * blocking is disabled on all upstream ports, and the root port supports
3738 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3739 * AtomicOp completion), or negative otherwise.
3740 */
3741 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3742 {
3743 struct pci_bus *bus = dev->bus;
3744 struct pci_dev *bridge;
3745 u32 cap, ctl2;
3746
3747 /*
3748 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3749 * in Device Control 2 is reserved in VFs and the PF value applies
3750 * to all associated VFs.
3751 */
3752 if (dev->is_virtfn)
3753 return -EINVAL;
3754
3755 if (!pci_is_pcie(dev))
3756 return -EINVAL;
3757
3758 /*
3759 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3760 * AtomicOp requesters. For now, we only support endpoints as
3761 * requesters and root ports as completers. No endpoints as
3762 * completers, and no peer-to-peer.
3763 */
3764
3765 switch (pci_pcie_type(dev)) {
3766 case PCI_EXP_TYPE_ENDPOINT:
3767 case PCI_EXP_TYPE_LEG_END:
3768 case PCI_EXP_TYPE_RC_END:
3769 break;
3770 default:
3771 return -EINVAL;
3772 }
3773
3774 while (bus->parent) {
3775 bridge = bus->self;
3776
3777 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3778
3779 switch (pci_pcie_type(bridge)) {
3780 /* Ensure switch ports support AtomicOp routing */
3781 case PCI_EXP_TYPE_UPSTREAM:
3782 case PCI_EXP_TYPE_DOWNSTREAM:
3783 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3784 return -EINVAL;
3785 break;
3786
3787 /* Ensure root port supports all the sizes we care about */
3788 case PCI_EXP_TYPE_ROOT_PORT:
3789 if ((cap & cap_mask) != cap_mask)
3790 return -EINVAL;
3791 break;
3792 }
3793
3794 /* Ensure upstream ports don't block AtomicOps on egress */
3795 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3796 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3797 &ctl2);
3798 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3799 return -EINVAL;
3800 }
3801
3802 bus = bus->parent;
3803 }
3804
3805 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3806 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3807 return 0;
3808 }
3809 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3810
3811 /**
3812 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3813 * @dev: the PCI device
3814 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3815 *
3816 * Perform INTx swizzling for a device behind one level of bridge. This is
3817 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3818 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3819 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3820 * the PCI Express Base Specification, Revision 2.1)
3821 */
3822 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3823 {
3824 int slot;
3825
3826 if (pci_ari_enabled(dev->bus))
3827 slot = 0;
3828 else
3829 slot = PCI_SLOT(dev->devfn);
3830
3831 return (((pin - 1) + slot) % 4) + 1;
3832 }
3833
3834 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3835 {
3836 u8 pin;
3837
3838 pin = dev->pin;
3839 if (!pin)
3840 return -1;
3841
3842 while (!pci_is_root_bus(dev->bus)) {
3843 pin = pci_swizzle_interrupt_pin(dev, pin);
3844 dev = dev->bus->self;
3845 }
3846 *bridge = dev;
3847 return pin;
3848 }
3849
3850 /**
3851 * pci_common_swizzle - swizzle INTx all the way to root bridge
3852 * @dev: the PCI device
3853 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3854 *
3855 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3856 * bridges all the way up to a PCI root bus.
3857 */
3858 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3859 {
3860 u8 pin = *pinp;
3861
3862 while (!pci_is_root_bus(dev->bus)) {
3863 pin = pci_swizzle_interrupt_pin(dev, pin);
3864 dev = dev->bus->self;
3865 }
3866 *pinp = pin;
3867 return PCI_SLOT(dev->devfn);
3868 }
3869 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3870
3871 /**
3872 * pci_release_region - Release a PCI bar
3873 * @pdev: PCI device whose resources were previously reserved by
3874 * pci_request_region()
3875 * @bar: BAR to release
3876 *
3877 * Releases the PCI I/O and memory resources previously reserved by a
3878 * successful call to pci_request_region(). Call this function only
3879 * after all use of the PCI regions has ceased.
3880 */
3881 void pci_release_region(struct pci_dev *pdev, int bar)
3882 {
3883 struct pci_devres *dr;
3884
3885 if (pci_resource_len(pdev, bar) == 0)
3886 return;
3887 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3888 release_region(pci_resource_start(pdev, bar),
3889 pci_resource_len(pdev, bar));
3890 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3891 release_mem_region(pci_resource_start(pdev, bar),
3892 pci_resource_len(pdev, bar));
3893
3894 dr = find_pci_dr(pdev);
3895 if (dr)
3896 dr->region_mask &= ~(1 << bar);
3897 }
3898 EXPORT_SYMBOL(pci_release_region);
3899
3900 /**
3901 * __pci_request_region - Reserved PCI I/O and memory resource
3902 * @pdev: PCI device whose resources are to be reserved
3903 * @bar: BAR to be reserved
3904 * @res_name: Name to be associated with resource.
3905 * @exclusive: whether the region access is exclusive or not
3906 *
3907 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3908 * being reserved by owner @res_name. Do not access any
3909 * address inside the PCI regions unless this call returns
3910 * successfully.
3911 *
3912 * If @exclusive is set, then the region is marked so that userspace
3913 * is explicitly not allowed to map the resource via /dev/mem or
3914 * sysfs MMIO access.
3915 *
3916 * Returns 0 on success, or %EBUSY on error. A warning
3917 * message is also printed on failure.
3918 */
3919 static int __pci_request_region(struct pci_dev *pdev, int bar,
3920 const char *res_name, int exclusive)
3921 {
3922 struct pci_devres *dr;
3923
3924 if (pci_resource_len(pdev, bar) == 0)
3925 return 0;
3926
3927 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3928 if (!request_region(pci_resource_start(pdev, bar),
3929 pci_resource_len(pdev, bar), res_name))
3930 goto err_out;
3931 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3932 if (!__request_mem_region(pci_resource_start(pdev, bar),
3933 pci_resource_len(pdev, bar), res_name,
3934 exclusive))
3935 goto err_out;
3936 }
3937
3938 dr = find_pci_dr(pdev);
3939 if (dr)
3940 dr->region_mask |= 1 << bar;
3941
3942 return 0;
3943
3944 err_out:
3945 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3946 &pdev->resource[bar]);
3947 return -EBUSY;
3948 }
3949
3950 /**
3951 * pci_request_region - Reserve PCI I/O and memory resource
3952 * @pdev: PCI device whose resources are to be reserved
3953 * @bar: BAR to be reserved
3954 * @res_name: Name to be associated with resource
3955 *
3956 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3957 * being reserved by owner @res_name. Do not access any
3958 * address inside the PCI regions unless this call returns
3959 * successfully.
3960 *
3961 * Returns 0 on success, or %EBUSY on error. A warning
3962 * message is also printed on failure.
3963 */
3964 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3965 {
3966 return __pci_request_region(pdev, bar, res_name, 0);
3967 }
3968 EXPORT_SYMBOL(pci_request_region);
3969
3970 /**
3971 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3972 * @pdev: PCI device whose resources were previously reserved
3973 * @bars: Bitmask of BARs to be released
3974 *
3975 * Release selected PCI I/O and memory resources previously reserved.
3976 * Call this function only after all use of the PCI regions has ceased.
3977 */
3978 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3979 {
3980 int i;
3981
3982 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3983 if (bars & (1 << i))
3984 pci_release_region(pdev, i);
3985 }
3986 EXPORT_SYMBOL(pci_release_selected_regions);
3987
3988 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3989 const char *res_name, int excl)
3990 {
3991 int i;
3992
3993 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3994 if (bars & (1 << i))
3995 if (__pci_request_region(pdev, i, res_name, excl))
3996 goto err_out;
3997 return 0;
3998
3999 err_out:
4000 while (--i >= 0)
4001 if (bars & (1 << i))
4002 pci_release_region(pdev, i);
4003
4004 return -EBUSY;
4005 }
4006
4007
4008 /**
4009 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4010 * @pdev: PCI device whose resources are to be reserved
4011 * @bars: Bitmask of BARs to be requested
4012 * @res_name: Name to be associated with resource
4013 */
4014 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4015 const char *res_name)
4016 {
4017 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4018 }
4019 EXPORT_SYMBOL(pci_request_selected_regions);
4020
4021 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4022 const char *res_name)
4023 {
4024 return __pci_request_selected_regions(pdev, bars, res_name,
4025 IORESOURCE_EXCLUSIVE);
4026 }
4027 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4028
4029 /**
4030 * pci_release_regions - Release reserved PCI I/O and memory resources
4031 * @pdev: PCI device whose resources were previously reserved by
4032 * pci_request_regions()
4033 *
4034 * Releases all PCI I/O and memory resources previously reserved by a
4035 * successful call to pci_request_regions(). Call this function only
4036 * after all use of the PCI regions has ceased.
4037 */
4038
4039 void pci_release_regions(struct pci_dev *pdev)
4040 {
4041 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4042 }
4043 EXPORT_SYMBOL(pci_release_regions);
4044
4045 /**
4046 * pci_request_regions - Reserve PCI I/O and memory resources
4047 * @pdev: PCI device whose resources are to be reserved
4048 * @res_name: Name to be associated with resource.
4049 *
4050 * Mark all PCI regions associated with PCI device @pdev as
4051 * being reserved by owner @res_name. Do not access any
4052 * address inside the PCI regions unless this call returns
4053 * successfully.
4054 *
4055 * Returns 0 on success, or %EBUSY on error. A warning
4056 * message is also printed on failure.
4057 */
4058 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4059 {
4060 return pci_request_selected_regions(pdev,
4061 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4062 }
4063 EXPORT_SYMBOL(pci_request_regions);
4064
4065 /**
4066 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4067 * @pdev: PCI device whose resources are to be reserved
4068 * @res_name: Name to be associated with resource.
4069 *
4070 * Mark all PCI regions associated with PCI device @pdev as being reserved
4071 * by owner @res_name. Do not access any address inside the PCI regions
4072 * unless this call returns successfully.
4073 *
4074 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4075 * and the sysfs MMIO access will not be allowed.
4076 *
4077 * Returns 0 on success, or %EBUSY on error. A warning message is also
4078 * printed on failure.
4079 */
4080 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4081 {
4082 return pci_request_selected_regions_exclusive(pdev,
4083 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4084 }
4085 EXPORT_SYMBOL(pci_request_regions_exclusive);
4086
4087 /*
4088 * Record the PCI IO range (expressed as CPU physical address + size).
4089 * Return a negative value if an error has occurred, zero otherwise
4090 */
4091 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4092 resource_size_t size)
4093 {
4094 int ret = 0;
4095 #ifdef PCI_IOBASE
4096 struct logic_pio_hwaddr *range;
4097
4098 if (!size || addr + size < addr)
4099 return -EINVAL;
4100
4101 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4102 if (!range)
4103 return -ENOMEM;
4104
4105 range->fwnode = fwnode;
4106 range->size = size;
4107 range->hw_start = addr;
4108 range->flags = LOGIC_PIO_CPU_MMIO;
4109
4110 ret = logic_pio_register_range(range);
4111 if (ret)
4112 kfree(range);
4113
4114 /* Ignore duplicates due to deferred probing */
4115 if (ret == -EEXIST)
4116 ret = 0;
4117 #endif
4118
4119 return ret;
4120 }
4121
4122 phys_addr_t pci_pio_to_address(unsigned long pio)
4123 {
4124 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4125
4126 #ifdef PCI_IOBASE
4127 if (pio >= MMIO_UPPER_LIMIT)
4128 return address;
4129
4130 address = logic_pio_to_hwaddr(pio);
4131 #endif
4132
4133 return address;
4134 }
4135 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4136
4137 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4138 {
4139 #ifdef PCI_IOBASE
4140 return logic_pio_trans_cpuaddr(address);
4141 #else
4142 if (address > IO_SPACE_LIMIT)
4143 return (unsigned long)-1;
4144
4145 return (unsigned long) address;
4146 #endif
4147 }
4148
4149 /**
4150 * pci_remap_iospace - Remap the memory mapped I/O space
4151 * @res: Resource describing the I/O space
4152 * @phys_addr: physical address of range to be mapped
4153 *
4154 * Remap the memory mapped I/O space described by the @res and the CPU
4155 * physical address @phys_addr into virtual address space. Only
4156 * architectures that have memory mapped IO functions defined (and the
4157 * PCI_IOBASE value defined) should call this function.
4158 */
4159 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4160 {
4161 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4162 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4163
4164 if (!(res->flags & IORESOURCE_IO))
4165 return -EINVAL;
4166
4167 if (res->end > IO_SPACE_LIMIT)
4168 return -EINVAL;
4169
4170 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4171 pgprot_device(PAGE_KERNEL));
4172 #else
4173 /*
4174 * This architecture does not have memory mapped I/O space,
4175 * so this function should never be called
4176 */
4177 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4178 return -ENODEV;
4179 #endif
4180 }
4181 EXPORT_SYMBOL(pci_remap_iospace);
4182
4183 /**
4184 * pci_unmap_iospace - Unmap the memory mapped I/O space
4185 * @res: resource to be unmapped
4186 *
4187 * Unmap the CPU virtual address @res from virtual address space. Only
4188 * architectures that have memory mapped IO functions defined (and the
4189 * PCI_IOBASE value defined) should call this function.
4190 */
4191 void pci_unmap_iospace(struct resource *res)
4192 {
4193 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4194 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4195
4196 vunmap_range(vaddr, vaddr + resource_size(res));
4197 #endif
4198 }
4199 EXPORT_SYMBOL(pci_unmap_iospace);
4200
4201 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4202 {
4203 struct resource **res = ptr;
4204
4205 pci_unmap_iospace(*res);
4206 }
4207
4208 /**
4209 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4210 * @dev: Generic device to remap IO address for
4211 * @res: Resource describing the I/O space
4212 * @phys_addr: physical address of range to be mapped
4213 *
4214 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4215 * detach.
4216 */
4217 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4218 phys_addr_t phys_addr)
4219 {
4220 const struct resource **ptr;
4221 int error;
4222
4223 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4224 if (!ptr)
4225 return -ENOMEM;
4226
4227 error = pci_remap_iospace(res, phys_addr);
4228 if (error) {
4229 devres_free(ptr);
4230 } else {
4231 *ptr = res;
4232 devres_add(dev, ptr);
4233 }
4234
4235 return error;
4236 }
4237 EXPORT_SYMBOL(devm_pci_remap_iospace);
4238
4239 /**
4240 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4241 * @dev: Generic device to remap IO address for
4242 * @offset: Resource address to map
4243 * @size: Size of map
4244 *
4245 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4246 * detach.
4247 */
4248 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4249 resource_size_t offset,
4250 resource_size_t size)
4251 {
4252 void __iomem **ptr, *addr;
4253
4254 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4255 if (!ptr)
4256 return NULL;
4257
4258 addr = pci_remap_cfgspace(offset, size);
4259 if (addr) {
4260 *ptr = addr;
4261 devres_add(dev, ptr);
4262 } else
4263 devres_free(ptr);
4264
4265 return addr;
4266 }
4267 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4268
4269 /**
4270 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4271 * @dev: generic device to handle the resource for
4272 * @res: configuration space resource to be handled
4273 *
4274 * Checks that a resource is a valid memory region, requests the memory
4275 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4276 * proper PCI configuration space memory attributes are guaranteed.
4277 *
4278 * All operations are managed and will be undone on driver detach.
4279 *
4280 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4281 * on failure. Usage example::
4282 *
4283 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4284 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4285 * if (IS_ERR(base))
4286 * return PTR_ERR(base);
4287 */
4288 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4289 struct resource *res)
4290 {
4291 resource_size_t size;
4292 const char *name;
4293 void __iomem *dest_ptr;
4294
4295 BUG_ON(!dev);
4296
4297 if (!res || resource_type(res) != IORESOURCE_MEM) {
4298 dev_err(dev, "invalid resource\n");
4299 return IOMEM_ERR_PTR(-EINVAL);
4300 }
4301
4302 size = resource_size(res);
4303
4304 if (res->name)
4305 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4306 res->name);
4307 else
4308 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4309 if (!name)
4310 return IOMEM_ERR_PTR(-ENOMEM);
4311
4312 if (!devm_request_mem_region(dev, res->start, size, name)) {
4313 dev_err(dev, "can't request region for resource %pR\n", res);
4314 return IOMEM_ERR_PTR(-EBUSY);
4315 }
4316
4317 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4318 if (!dest_ptr) {
4319 dev_err(dev, "ioremap failed for resource %pR\n", res);
4320 devm_release_mem_region(dev, res->start, size);
4321 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4322 }
4323
4324 return dest_ptr;
4325 }
4326 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4327
4328 static void __pci_set_master(struct pci_dev *dev, bool enable)
4329 {
4330 u16 old_cmd, cmd;
4331
4332 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4333 if (enable)
4334 cmd = old_cmd | PCI_COMMAND_MASTER;
4335 else
4336 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4337 if (cmd != old_cmd) {
4338 pci_dbg(dev, "%s bus mastering\n",
4339 enable ? "enabling" : "disabling");
4340 pci_write_config_word(dev, PCI_COMMAND, cmd);
4341 }
4342 dev->is_busmaster = enable;
4343 }
4344
4345 /**
4346 * pcibios_setup - process "pci=" kernel boot arguments
4347 * @str: string used to pass in "pci=" kernel boot arguments
4348 *
4349 * Process kernel boot arguments. This is the default implementation.
4350 * Architecture specific implementations can override this as necessary.
4351 */
4352 char * __weak __init pcibios_setup(char *str)
4353 {
4354 return str;
4355 }
4356
4357 /**
4358 * pcibios_set_master - enable PCI bus-mastering for device dev
4359 * @dev: the PCI device to enable
4360 *
4361 * Enables PCI bus-mastering for the device. This is the default
4362 * implementation. Architecture specific implementations can override
4363 * this if necessary.
4364 */
4365 void __weak pcibios_set_master(struct pci_dev *dev)
4366 {
4367 u8 lat;
4368
4369 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4370 if (pci_is_pcie(dev))
4371 return;
4372
4373 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4374 if (lat < 16)
4375 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4376 else if (lat > pcibios_max_latency)
4377 lat = pcibios_max_latency;
4378 else
4379 return;
4380
4381 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4382 }
4383
4384 /**
4385 * pci_set_master - enables bus-mastering for device dev
4386 * @dev: the PCI device to enable
4387 *
4388 * Enables bus-mastering on the device and calls pcibios_set_master()
4389 * to do the needed arch specific settings.
4390 */
4391 void pci_set_master(struct pci_dev *dev)
4392 {
4393 __pci_set_master(dev, true);
4394 pcibios_set_master(dev);
4395 }
4396 EXPORT_SYMBOL(pci_set_master);
4397
4398 /**
4399 * pci_clear_master - disables bus-mastering for device dev
4400 * @dev: the PCI device to disable
4401 */
4402 void pci_clear_master(struct pci_dev *dev)
4403 {
4404 __pci_set_master(dev, false);
4405 }
4406 EXPORT_SYMBOL(pci_clear_master);
4407
4408 /**
4409 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4410 * @dev: the PCI device for which MWI is to be enabled
4411 *
4412 * Helper function for pci_set_mwi.
4413 * Originally copied from drivers/net/acenic.c.
4414 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4415 *
4416 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4417 */
4418 int pci_set_cacheline_size(struct pci_dev *dev)
4419 {
4420 u8 cacheline_size;
4421
4422 if (!pci_cache_line_size)
4423 return -EINVAL;
4424
4425 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4426 equal to or multiple of the right value. */
4427 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4428 if (cacheline_size >= pci_cache_line_size &&
4429 (cacheline_size % pci_cache_line_size) == 0)
4430 return 0;
4431
4432 /* Write the correct value. */
4433 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4434 /* Read it back. */
4435 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4436 if (cacheline_size == pci_cache_line_size)
4437 return 0;
4438
4439 pci_dbg(dev, "cache line size of %d is not supported\n",
4440 pci_cache_line_size << 2);
4441
4442 return -EINVAL;
4443 }
4444 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4445
4446 /**
4447 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4448 * @dev: the PCI device for which MWI is enabled
4449 *
4450 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4451 *
4452 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4453 */
4454 int pci_set_mwi(struct pci_dev *dev)
4455 {
4456 #ifdef PCI_DISABLE_MWI
4457 return 0;
4458 #else
4459 int rc;
4460 u16 cmd;
4461
4462 rc = pci_set_cacheline_size(dev);
4463 if (rc)
4464 return rc;
4465
4466 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4467 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4468 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4469 cmd |= PCI_COMMAND_INVALIDATE;
4470 pci_write_config_word(dev, PCI_COMMAND, cmd);
4471 }
4472 return 0;
4473 #endif
4474 }
4475 EXPORT_SYMBOL(pci_set_mwi);
4476
4477 /**
4478 * pcim_set_mwi - a device-managed pci_set_mwi()
4479 * @dev: the PCI device for which MWI is enabled
4480 *
4481 * Managed pci_set_mwi().
4482 *
4483 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4484 */
4485 int pcim_set_mwi(struct pci_dev *dev)
4486 {
4487 struct pci_devres *dr;
4488
4489 dr = find_pci_dr(dev);
4490 if (!dr)
4491 return -ENOMEM;
4492
4493 dr->mwi = 1;
4494 return pci_set_mwi(dev);
4495 }
4496 EXPORT_SYMBOL(pcim_set_mwi);
4497
4498 /**
4499 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4500 * @dev: the PCI device for which MWI is enabled
4501 *
4502 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4503 * Callers are not required to check the return value.
4504 *
4505 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4506 */
4507 int pci_try_set_mwi(struct pci_dev *dev)
4508 {
4509 #ifdef PCI_DISABLE_MWI
4510 return 0;
4511 #else
4512 return pci_set_mwi(dev);
4513 #endif
4514 }
4515 EXPORT_SYMBOL(pci_try_set_mwi);
4516
4517 /**
4518 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4519 * @dev: the PCI device to disable
4520 *
4521 * Disables PCI Memory-Write-Invalidate transaction on the device
4522 */
4523 void pci_clear_mwi(struct pci_dev *dev)
4524 {
4525 #ifndef PCI_DISABLE_MWI
4526 u16 cmd;
4527
4528 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4529 if (cmd & PCI_COMMAND_INVALIDATE) {
4530 cmd &= ~PCI_COMMAND_INVALIDATE;
4531 pci_write_config_word(dev, PCI_COMMAND, cmd);
4532 }
4533 #endif
4534 }
4535 EXPORT_SYMBOL(pci_clear_mwi);
4536
4537 /**
4538 * pci_disable_parity - disable parity checking for device
4539 * @dev: the PCI device to operate on
4540 *
4541 * Disable parity checking for device @dev
4542 */
4543 void pci_disable_parity(struct pci_dev *dev)
4544 {
4545 u16 cmd;
4546
4547 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4548 if (cmd & PCI_COMMAND_PARITY) {
4549 cmd &= ~PCI_COMMAND_PARITY;
4550 pci_write_config_word(dev, PCI_COMMAND, cmd);
4551 }
4552 }
4553
4554 /**
4555 * pci_intx - enables/disables PCI INTx for device dev
4556 * @pdev: the PCI device to operate on
4557 * @enable: boolean: whether to enable or disable PCI INTx
4558 *
4559 * Enables/disables PCI INTx for device @pdev
4560 */
4561 void pci_intx(struct pci_dev *pdev, int enable)
4562 {
4563 u16 pci_command, new;
4564
4565 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4566
4567 if (enable)
4568 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4569 else
4570 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4571
4572 if (new != pci_command) {
4573 struct pci_devres *dr;
4574
4575 pci_write_config_word(pdev, PCI_COMMAND, new);
4576
4577 dr = find_pci_dr(pdev);
4578 if (dr && !dr->restore_intx) {
4579 dr->restore_intx = 1;
4580 dr->orig_intx = !enable;
4581 }
4582 }
4583 }
4584 EXPORT_SYMBOL_GPL(pci_intx);
4585
4586 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4587 {
4588 struct pci_bus *bus = dev->bus;
4589 bool mask_updated = true;
4590 u32 cmd_status_dword;
4591 u16 origcmd, newcmd;
4592 unsigned long flags;
4593 bool irq_pending;
4594
4595 /*
4596 * We do a single dword read to retrieve both command and status.
4597 * Document assumptions that make this possible.
4598 */
4599 BUILD_BUG_ON(PCI_COMMAND % 4);
4600 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4601
4602 raw_spin_lock_irqsave(&pci_lock, flags);
4603
4604 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4605
4606 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4607
4608 /*
4609 * Check interrupt status register to see whether our device
4610 * triggered the interrupt (when masking) or the next IRQ is
4611 * already pending (when unmasking).
4612 */
4613 if (mask != irq_pending) {
4614 mask_updated = false;
4615 goto done;
4616 }
4617
4618 origcmd = cmd_status_dword;
4619 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4620 if (mask)
4621 newcmd |= PCI_COMMAND_INTX_DISABLE;
4622 if (newcmd != origcmd)
4623 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4624
4625 done:
4626 raw_spin_unlock_irqrestore(&pci_lock, flags);
4627
4628 return mask_updated;
4629 }
4630
4631 /**
4632 * pci_check_and_mask_intx - mask INTx on pending interrupt
4633 * @dev: the PCI device to operate on
4634 *
4635 * Check if the device dev has its INTx line asserted, mask it and return
4636 * true in that case. False is returned if no interrupt was pending.
4637 */
4638 bool pci_check_and_mask_intx(struct pci_dev *dev)
4639 {
4640 return pci_check_and_set_intx_mask(dev, true);
4641 }
4642 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4643
4644 /**
4645 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4646 * @dev: the PCI device to operate on
4647 *
4648 * Check if the device dev has its INTx line asserted, unmask it if not and
4649 * return true. False is returned and the mask remains active if there was
4650 * still an interrupt pending.
4651 */
4652 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4653 {
4654 return pci_check_and_set_intx_mask(dev, false);
4655 }
4656 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4657
4658 /**
4659 * pci_wait_for_pending_transaction - wait for pending transaction
4660 * @dev: the PCI device to operate on
4661 *
4662 * Return 0 if transaction is pending 1 otherwise.
4663 */
4664 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4665 {
4666 if (!pci_is_pcie(dev))
4667 return 1;
4668
4669 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4670 PCI_EXP_DEVSTA_TRPND);
4671 }
4672 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4673
4674 /**
4675 * pcie_flr - initiate a PCIe function level reset
4676 * @dev: device to reset
4677 *
4678 * Initiate a function level reset unconditionally on @dev without
4679 * checking any flags and DEVCAP
4680 */
4681 int pcie_flr(struct pci_dev *dev)
4682 {
4683 if (!pci_wait_for_pending_transaction(dev))
4684 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4685
4686 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4687
4688 if (dev->imm_ready)
4689 return 0;
4690
4691 /*
4692 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4693 * 100ms, but may silently discard requests while the FLR is in
4694 * progress. Wait 100ms before trying to access the device.
4695 */
4696 msleep(100);
4697
4698 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4699 }
4700 EXPORT_SYMBOL_GPL(pcie_flr);
4701
4702 /**
4703 * pcie_reset_flr - initiate a PCIe function level reset
4704 * @dev: device to reset
4705 * @probe: if true, return 0 if device can be reset this way
4706 *
4707 * Initiate a function level reset on @dev.
4708 */
4709 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4710 {
4711 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4712 return -ENOTTY;
4713
4714 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4715 return -ENOTTY;
4716
4717 if (probe)
4718 return 0;
4719
4720 return pcie_flr(dev);
4721 }
4722 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4723
4724 static int pci_af_flr(struct pci_dev *dev, bool probe)
4725 {
4726 int pos;
4727 u8 cap;
4728
4729 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4730 if (!pos)
4731 return -ENOTTY;
4732
4733 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4734 return -ENOTTY;
4735
4736 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4737 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4738 return -ENOTTY;
4739
4740 if (probe)
4741 return 0;
4742
4743 /*
4744 * Wait for Transaction Pending bit to clear. A word-aligned test
4745 * is used, so we use the control offset rather than status and shift
4746 * the test bit to match.
4747 */
4748 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4749 PCI_AF_STATUS_TP << 8))
4750 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4751
4752 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4753
4754 if (dev->imm_ready)
4755 return 0;
4756
4757 /*
4758 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4759 * updated 27 July 2006; a device must complete an FLR within
4760 * 100ms, but may silently discard requests while the FLR is in
4761 * progress. Wait 100ms before trying to access the device.
4762 */
4763 msleep(100);
4764
4765 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4766 }
4767
4768 /**
4769 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4770 * @dev: Device to reset.
4771 * @probe: if true, return 0 if the device can be reset this way.
4772 *
4773 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4774 * unset, it will be reinitialized internally when going from PCI_D3hot to
4775 * PCI_D0. If that's the case and the device is not in a low-power state
4776 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4777 *
4778 * NOTE: This causes the caller to sleep for twice the device power transition
4779 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4780 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4781 * Moreover, only devices in D0 can be reset by this function.
4782 */
4783 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4784 {
4785 u16 csr;
4786
4787 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4788 return -ENOTTY;
4789
4790 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4791 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4792 return -ENOTTY;
4793
4794 if (probe)
4795 return 0;
4796
4797 if (dev->current_state != PCI_D0)
4798 return -EINVAL;
4799
4800 csr &= ~PCI_PM_CTRL_STATE_MASK;
4801 csr |= PCI_D3hot;
4802 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4803 pci_dev_d3_sleep(dev);
4804
4805 csr &= ~PCI_PM_CTRL_STATE_MASK;
4806 csr |= PCI_D0;
4807 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4808 pci_dev_d3_sleep(dev);
4809
4810 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4811 }
4812
4813 /**
4814 * pcie_wait_for_link_delay - Wait until link is active or inactive
4815 * @pdev: Bridge device
4816 * @active: waiting for active or inactive?
4817 * @delay: Delay to wait after link has become active (in ms)
4818 *
4819 * Use this to wait till link becomes active or inactive.
4820 */
4821 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4822 int delay)
4823 {
4824 int timeout = 1000;
4825 bool ret;
4826 u16 lnk_status;
4827
4828 /*
4829 * Some controllers might not implement link active reporting. In this
4830 * case, we wait for 1000 ms + any delay requested by the caller.
4831 */
4832 if (!pdev->link_active_reporting) {
4833 msleep(timeout + delay);
4834 return true;
4835 }
4836
4837 /*
4838 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4839 * after which we should expect an link active if the reset was
4840 * successful. If so, software must wait a minimum 100ms before sending
4841 * configuration requests to devices downstream this port.
4842 *
4843 * If the link fails to activate, either the device was physically
4844 * removed or the link is permanently failed.
4845 */
4846 if (active)
4847 msleep(20);
4848 for (;;) {
4849 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4850 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4851 if (ret == active)
4852 break;
4853 if (timeout <= 0)
4854 break;
4855 msleep(10);
4856 timeout -= 10;
4857 }
4858 if (active && ret)
4859 msleep(delay);
4860
4861 return ret == active;
4862 }
4863
4864 /**
4865 * pcie_wait_for_link - Wait until link is active or inactive
4866 * @pdev: Bridge device
4867 * @active: waiting for active or inactive?
4868 *
4869 * Use this to wait till link becomes active or inactive.
4870 */
4871 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4872 {
4873 return pcie_wait_for_link_delay(pdev, active, 100);
4874 }
4875
4876 /*
4877 * Find maximum D3cold delay required by all the devices on the bus. The
4878 * spec says 100 ms, but firmware can lower it and we allow drivers to
4879 * increase it as well.
4880 *
4881 * Called with @pci_bus_sem locked for reading.
4882 */
4883 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4884 {
4885 const struct pci_dev *pdev;
4886 int min_delay = 100;
4887 int max_delay = 0;
4888
4889 list_for_each_entry(pdev, &bus->devices, bus_list) {
4890 if (pdev->d3cold_delay < min_delay)
4891 min_delay = pdev->d3cold_delay;
4892 if (pdev->d3cold_delay > max_delay)
4893 max_delay = pdev->d3cold_delay;
4894 }
4895
4896 return max(min_delay, max_delay);
4897 }
4898
4899 /**
4900 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4901 * @dev: PCI bridge
4902 *
4903 * Handle necessary delays before access to the devices on the secondary
4904 * side of the bridge are permitted after D3cold to D0 transition.
4905 *
4906 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4907 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4908 * 4.3.2.
4909 */
4910 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4911 {
4912 struct pci_dev *child;
4913 int delay;
4914
4915 if (pci_dev_is_disconnected(dev))
4916 return;
4917
4918 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4919 return;
4920
4921 down_read(&pci_bus_sem);
4922
4923 /*
4924 * We only deal with devices that are present currently on the bus.
4925 * For any hot-added devices the access delay is handled in pciehp
4926 * board_added(). In case of ACPI hotplug the firmware is expected
4927 * to configure the devices before OS is notified.
4928 */
4929 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4930 up_read(&pci_bus_sem);
4931 return;
4932 }
4933
4934 /* Take d3cold_delay requirements into account */
4935 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4936 if (!delay) {
4937 up_read(&pci_bus_sem);
4938 return;
4939 }
4940
4941 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4942 bus_list);
4943 up_read(&pci_bus_sem);
4944
4945 /*
4946 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4947 * accessing the device after reset (that is 1000 ms + 100 ms). In
4948 * practice this should not be needed because we don't do power
4949 * management for them (see pci_bridge_d3_possible()).
4950 */
4951 if (!pci_is_pcie(dev)) {
4952 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4953 msleep(1000 + delay);
4954 return;
4955 }
4956
4957 /*
4958 * For PCIe downstream and root ports that do not support speeds
4959 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4960 * speeds (gen3) we need to wait first for the data link layer to
4961 * become active.
4962 *
4963 * However, 100 ms is the minimum and the PCIe spec says the
4964 * software must allow at least 1s before it can determine that the
4965 * device that did not respond is a broken device. There is
4966 * evidence that 100 ms is not always enough, for example certain
4967 * Titan Ridge xHCI controller does not always respond to
4968 * configuration requests if we only wait for 100 ms (see
4969 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4970 *
4971 * Therefore we wait for 100 ms and check for the device presence.
4972 * If it is still not present give it an additional 100 ms.
4973 */
4974 if (!pcie_downstream_port(dev))
4975 return;
4976
4977 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4978 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4979 msleep(delay);
4980 } else {
4981 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4982 delay);
4983 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4984 /* Did not train, no need to wait any further */
4985 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4986 return;
4987 }
4988 }
4989
4990 if (!pci_device_is_present(child)) {
4991 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4992 msleep(delay);
4993 }
4994 }
4995
4996 void pci_reset_secondary_bus(struct pci_dev *dev)
4997 {
4998 u16 ctrl;
4999
5000 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5001 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5002 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5003
5004 /*
5005 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5006 * this to 2ms to ensure that we meet the minimum requirement.
5007 */
5008 msleep(2);
5009
5010 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5011 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5012
5013 /*
5014 * Trhfa for conventional PCI is 2^25 clock cycles.
5015 * Assuming a minimum 33MHz clock this results in a 1s
5016 * delay before we can consider subordinate devices to
5017 * be re-initialized. PCIe has some ways to shorten this,
5018 * but we don't make use of them yet.
5019 */
5020 ssleep(1);
5021 }
5022
5023 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5024 {
5025 pci_reset_secondary_bus(dev);
5026 }
5027
5028 /**
5029 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5030 * @dev: Bridge device
5031 *
5032 * Use the bridge control register to assert reset on the secondary bus.
5033 * Devices on the secondary bus are left in power-on state.
5034 */
5035 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5036 {
5037 pcibios_reset_secondary_bus(dev);
5038
5039 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
5040 }
5041 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5042
5043 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5044 {
5045 struct pci_dev *pdev;
5046
5047 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5048 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5049 return -ENOTTY;
5050
5051 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5052 if (pdev != dev)
5053 return -ENOTTY;
5054
5055 if (probe)
5056 return 0;
5057
5058 return pci_bridge_secondary_bus_reset(dev->bus->self);
5059 }
5060
5061 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5062 {
5063 int rc = -ENOTTY;
5064
5065 if (!hotplug || !try_module_get(hotplug->owner))
5066 return rc;
5067
5068 if (hotplug->ops->reset_slot)
5069 rc = hotplug->ops->reset_slot(hotplug, probe);
5070
5071 module_put(hotplug->owner);
5072
5073 return rc;
5074 }
5075
5076 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5077 {
5078 if (dev->multifunction || dev->subordinate || !dev->slot ||
5079 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5080 return -ENOTTY;
5081
5082 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5083 }
5084
5085 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5086 {
5087 int rc;
5088
5089 rc = pci_dev_reset_slot_function(dev, probe);
5090 if (rc != -ENOTTY)
5091 return rc;
5092 return pci_parent_bus_reset(dev, probe);
5093 }
5094
5095 static void pci_dev_lock(struct pci_dev *dev)
5096 {
5097 pci_cfg_access_lock(dev);
5098 /* block PM suspend, driver probe, etc. */
5099 device_lock(&dev->dev);
5100 }
5101
5102 /* Return 1 on successful lock, 0 on contention */
5103 int pci_dev_trylock(struct pci_dev *dev)
5104 {
5105 if (pci_cfg_access_trylock(dev)) {
5106 if (device_trylock(&dev->dev))
5107 return 1;
5108 pci_cfg_access_unlock(dev);
5109 }
5110
5111 return 0;
5112 }
5113 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5114
5115 void pci_dev_unlock(struct pci_dev *dev)
5116 {
5117 device_unlock(&dev->dev);
5118 pci_cfg_access_unlock(dev);
5119 }
5120 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5121
5122 static void pci_dev_save_and_disable(struct pci_dev *dev)
5123 {
5124 struct pci_driver *drv = to_pci_driver(dev->dev.driver);
5125 const struct pci_error_handlers *err_handler =
5126 drv ? drv->err_handler : NULL;
5127
5128 /*
5129 * drv->err_handler->reset_prepare() is protected against races
5130 * with ->remove() by the device lock, which must be held by the
5131 * caller.
5132 */
5133 if (err_handler && err_handler->reset_prepare)
5134 err_handler->reset_prepare(dev);
5135
5136 /*
5137 * Wake-up device prior to save. PM registers default to D0 after
5138 * reset and a simple register restore doesn't reliably return
5139 * to a non-D0 state anyway.
5140 */
5141 pci_set_power_state(dev, PCI_D0);
5142
5143 pci_save_state(dev);
5144 /*
5145 * Disable the device by clearing the Command register, except for
5146 * INTx-disable which is set. This not only disables MMIO and I/O port
5147 * BARs, but also prevents the device from being Bus Master, preventing
5148 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5149 * compliant devices, INTx-disable prevents legacy interrupts.
5150 */
5151 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5152 }
5153
5154 static void pci_dev_restore(struct pci_dev *dev)
5155 {
5156 struct pci_driver *drv = to_pci_driver(dev->dev.driver);
5157 const struct pci_error_handlers *err_handler =
5158 drv ? drv->err_handler : NULL;
5159
5160 pci_restore_state(dev);
5161
5162 /*
5163 * drv->err_handler->reset_done() is protected against races with
5164 * ->remove() by the device lock, which must be held by the caller.
5165 */
5166 if (err_handler && err_handler->reset_done)
5167 err_handler->reset_done(dev);
5168 }
5169
5170 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5171 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5172 { },
5173 { pci_dev_specific_reset, .name = "device_specific" },
5174 { pci_dev_acpi_reset, .name = "acpi" },
5175 { pcie_reset_flr, .name = "flr" },
5176 { pci_af_flr, .name = "af_flr" },
5177 { pci_pm_reset, .name = "pm" },
5178 { pci_reset_bus_function, .name = "bus" },
5179 };
5180
5181 static ssize_t reset_method_show(struct device *dev,
5182 struct device_attribute *attr, char *buf)
5183 {
5184 struct pci_dev *pdev = to_pci_dev(dev);
5185 ssize_t len = 0;
5186 int i, m;
5187
5188 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5189 m = pdev->reset_methods[i];
5190 if (!m)
5191 break;
5192
5193 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5194 pci_reset_fn_methods[m].name);
5195 }
5196
5197 if (len)
5198 len += sysfs_emit_at(buf, len, "\n");
5199
5200 return len;
5201 }
5202
5203 static int reset_method_lookup(const char *name)
5204 {
5205 int m;
5206
5207 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5208 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5209 return m;
5210 }
5211
5212 return 0; /* not found */
5213 }
5214
5215 static ssize_t reset_method_store(struct device *dev,
5216 struct device_attribute *attr,
5217 const char *buf, size_t count)
5218 {
5219 struct pci_dev *pdev = to_pci_dev(dev);
5220 char *options, *name;
5221 int m, n;
5222 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5223
5224 if (sysfs_streq(buf, "")) {
5225 pdev->reset_methods[0] = 0;
5226 pci_warn(pdev, "All device reset methods disabled by user");
5227 return count;
5228 }
5229
5230 if (sysfs_streq(buf, "default")) {
5231 pci_init_reset_methods(pdev);
5232 return count;
5233 }
5234
5235 options = kstrndup(buf, count, GFP_KERNEL);
5236 if (!options)
5237 return -ENOMEM;
5238
5239 n = 0;
5240 while ((name = strsep(&options, " ")) != NULL) {
5241 if (sysfs_streq(name, ""))
5242 continue;
5243
5244 name = strim(name);
5245
5246 m = reset_method_lookup(name);
5247 if (!m) {
5248 pci_err(pdev, "Invalid reset method '%s'", name);
5249 goto error;
5250 }
5251
5252 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5253 pci_err(pdev, "Unsupported reset method '%s'", name);
5254 goto error;
5255 }
5256
5257 if (n == PCI_NUM_RESET_METHODS - 1) {
5258 pci_err(pdev, "Too many reset methods\n");
5259 goto error;
5260 }
5261
5262 reset_methods[n++] = m;
5263 }
5264
5265 reset_methods[n] = 0;
5266
5267 /* Warn if dev-specific supported but not highest priority */
5268 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5269 reset_methods[0] != 1)
5270 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5271 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5272 kfree(options);
5273 return count;
5274
5275 error:
5276 /* Leave previous methods unchanged */
5277 kfree(options);
5278 return -EINVAL;
5279 }
5280 static DEVICE_ATTR_RW(reset_method);
5281
5282 static struct attribute *pci_dev_reset_method_attrs[] = {
5283 &dev_attr_reset_method.attr,
5284 NULL,
5285 };
5286
5287 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5288 struct attribute *a, int n)
5289 {
5290 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5291
5292 if (!pci_reset_supported(pdev))
5293 return 0;
5294
5295 return a->mode;
5296 }
5297
5298 const struct attribute_group pci_dev_reset_method_attr_group = {
5299 .attrs = pci_dev_reset_method_attrs,
5300 .is_visible = pci_dev_reset_method_attr_is_visible,
5301 };
5302
5303 /**
5304 * __pci_reset_function_locked - reset a PCI device function while holding
5305 * the @dev mutex lock.
5306 * @dev: PCI device to reset
5307 *
5308 * Some devices allow an individual function to be reset without affecting
5309 * other functions in the same device. The PCI device must be responsive
5310 * to PCI config space in order to use this function.
5311 *
5312 * The device function is presumed to be unused and the caller is holding
5313 * the device mutex lock when this function is called.
5314 *
5315 * Resetting the device will make the contents of PCI configuration space
5316 * random, so any caller of this must be prepared to reinitialise the
5317 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5318 * etc.
5319 *
5320 * Returns 0 if the device function was successfully reset or negative if the
5321 * device doesn't support resetting a single function.
5322 */
5323 int __pci_reset_function_locked(struct pci_dev *dev)
5324 {
5325 int i, m, rc = -ENOTTY;
5326
5327 might_sleep();
5328
5329 /*
5330 * A reset method returns -ENOTTY if it doesn't support this device and
5331 * we should try the next method.
5332 *
5333 * If it returns 0 (success), we're finished. If it returns any other
5334 * error, we're also finished: this indicates that further reset
5335 * mechanisms might be broken on the device.
5336 */
5337 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5338 m = dev->reset_methods[i];
5339 if (!m)
5340 return -ENOTTY;
5341
5342 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5343 if (!rc)
5344 return 0;
5345 if (rc != -ENOTTY)
5346 return rc;
5347 }
5348
5349 return -ENOTTY;
5350 }
5351 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5352
5353 /**
5354 * pci_init_reset_methods - check whether device can be safely reset
5355 * and store supported reset mechanisms.
5356 * @dev: PCI device to check for reset mechanisms
5357 *
5358 * Some devices allow an individual function to be reset without affecting
5359 * other functions in the same device. The PCI device must be in D0-D3hot
5360 * state.
5361 *
5362 * Stores reset mechanisms supported by device in reset_methods byte array
5363 * which is a member of struct pci_dev.
5364 */
5365 void pci_init_reset_methods(struct pci_dev *dev)
5366 {
5367 int m, i, rc;
5368
5369 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5370
5371 might_sleep();
5372
5373 i = 0;
5374 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5375 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5376 if (!rc)
5377 dev->reset_methods[i++] = m;
5378 else if (rc != -ENOTTY)
5379 break;
5380 }
5381
5382 dev->reset_methods[i] = 0;
5383 }
5384
5385 /**
5386 * pci_reset_function - quiesce and reset a PCI device function
5387 * @dev: PCI device to reset
5388 *
5389 * Some devices allow an individual function to be reset without affecting
5390 * other functions in the same device. The PCI device must be responsive
5391 * to PCI config space in order to use this function.
5392 *
5393 * This function does not just reset the PCI portion of a device, but
5394 * clears all the state associated with the device. This function differs
5395 * from __pci_reset_function_locked() in that it saves and restores device state
5396 * over the reset and takes the PCI device lock.
5397 *
5398 * Returns 0 if the device function was successfully reset or negative if the
5399 * device doesn't support resetting a single function.
5400 */
5401 int pci_reset_function(struct pci_dev *dev)
5402 {
5403 int rc;
5404
5405 if (!pci_reset_supported(dev))
5406 return -ENOTTY;
5407
5408 pci_dev_lock(dev);
5409 pci_dev_save_and_disable(dev);
5410
5411 rc = __pci_reset_function_locked(dev);
5412
5413 pci_dev_restore(dev);
5414 pci_dev_unlock(dev);
5415
5416 return rc;
5417 }
5418 EXPORT_SYMBOL_GPL(pci_reset_function);
5419
5420 /**
5421 * pci_reset_function_locked - quiesce and reset a PCI device function
5422 * @dev: PCI device to reset
5423 *
5424 * Some devices allow an individual function to be reset without affecting
5425 * other functions in the same device. The PCI device must be responsive
5426 * to PCI config space in order to use this function.
5427 *
5428 * This function does not just reset the PCI portion of a device, but
5429 * clears all the state associated with the device. This function differs
5430 * from __pci_reset_function_locked() in that it saves and restores device state
5431 * over the reset. It also differs from pci_reset_function() in that it
5432 * requires the PCI device lock to be held.
5433 *
5434 * Returns 0 if the device function was successfully reset or negative if the
5435 * device doesn't support resetting a single function.
5436 */
5437 int pci_reset_function_locked(struct pci_dev *dev)
5438 {
5439 int rc;
5440
5441 if (!pci_reset_supported(dev))
5442 return -ENOTTY;
5443
5444 pci_dev_save_and_disable(dev);
5445
5446 rc = __pci_reset_function_locked(dev);
5447
5448 pci_dev_restore(dev);
5449
5450 return rc;
5451 }
5452 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5453
5454 /**
5455 * pci_try_reset_function - quiesce and reset a PCI device function
5456 * @dev: PCI device to reset
5457 *
5458 * Same as above, except return -EAGAIN if unable to lock device.
5459 */
5460 int pci_try_reset_function(struct pci_dev *dev)
5461 {
5462 int rc;
5463
5464 if (!pci_reset_supported(dev))
5465 return -ENOTTY;
5466
5467 if (!pci_dev_trylock(dev))
5468 return -EAGAIN;
5469
5470 pci_dev_save_and_disable(dev);
5471 rc = __pci_reset_function_locked(dev);
5472 pci_dev_restore(dev);
5473 pci_dev_unlock(dev);
5474
5475 return rc;
5476 }
5477 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5478
5479 /* Do any devices on or below this bus prevent a bus reset? */
5480 static bool pci_bus_resetable(struct pci_bus *bus)
5481 {
5482 struct pci_dev *dev;
5483
5484
5485 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5486 return false;
5487
5488 list_for_each_entry(dev, &bus->devices, bus_list) {
5489 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5490 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5491 return false;
5492 }
5493
5494 return true;
5495 }
5496
5497 /* Lock devices from the top of the tree down */
5498 static void pci_bus_lock(struct pci_bus *bus)
5499 {
5500 struct pci_dev *dev;
5501
5502 list_for_each_entry(dev, &bus->devices, bus_list) {
5503 pci_dev_lock(dev);
5504 if (dev->subordinate)
5505 pci_bus_lock(dev->subordinate);
5506 }
5507 }
5508
5509 /* Unlock devices from the bottom of the tree up */
5510 static void pci_bus_unlock(struct pci_bus *bus)
5511 {
5512 struct pci_dev *dev;
5513
5514 list_for_each_entry(dev, &bus->devices, bus_list) {
5515 if (dev->subordinate)
5516 pci_bus_unlock(dev->subordinate);
5517 pci_dev_unlock(dev);
5518 }
5519 }
5520
5521 /* Return 1 on successful lock, 0 on contention */
5522 static int pci_bus_trylock(struct pci_bus *bus)
5523 {
5524 struct pci_dev *dev;
5525
5526 list_for_each_entry(dev, &bus->devices, bus_list) {
5527 if (!pci_dev_trylock(dev))
5528 goto unlock;
5529 if (dev->subordinate) {
5530 if (!pci_bus_trylock(dev->subordinate)) {
5531 pci_dev_unlock(dev);
5532 goto unlock;
5533 }
5534 }
5535 }
5536 return 1;
5537
5538 unlock:
5539 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5540 if (dev->subordinate)
5541 pci_bus_unlock(dev->subordinate);
5542 pci_dev_unlock(dev);
5543 }
5544 return 0;
5545 }
5546
5547 /* Do any devices on or below this slot prevent a bus reset? */
5548 static bool pci_slot_resetable(struct pci_slot *slot)
5549 {
5550 struct pci_dev *dev;
5551
5552 if (slot->bus->self &&
5553 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5554 return false;
5555
5556 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5557 if (!dev->slot || dev->slot != slot)
5558 continue;
5559 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5560 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5561 return false;
5562 }
5563
5564 return true;
5565 }
5566
5567 /* Lock devices from the top of the tree down */
5568 static void pci_slot_lock(struct pci_slot *slot)
5569 {
5570 struct pci_dev *dev;
5571
5572 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5573 if (!dev->slot || dev->slot != slot)
5574 continue;
5575 pci_dev_lock(dev);
5576 if (dev->subordinate)
5577 pci_bus_lock(dev->subordinate);
5578 }
5579 }
5580
5581 /* Unlock devices from the bottom of the tree up */
5582 static void pci_slot_unlock(struct pci_slot *slot)
5583 {
5584 struct pci_dev *dev;
5585
5586 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5587 if (!dev->slot || dev->slot != slot)
5588 continue;
5589 if (dev->subordinate)
5590 pci_bus_unlock(dev->subordinate);
5591 pci_dev_unlock(dev);
5592 }
5593 }
5594
5595 /* Return 1 on successful lock, 0 on contention */
5596 static int pci_slot_trylock(struct pci_slot *slot)
5597 {
5598 struct pci_dev *dev;
5599
5600 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5601 if (!dev->slot || dev->slot != slot)
5602 continue;
5603 if (!pci_dev_trylock(dev))
5604 goto unlock;
5605 if (dev->subordinate) {
5606 if (!pci_bus_trylock(dev->subordinate)) {
5607 pci_dev_unlock(dev);
5608 goto unlock;
5609 }
5610 }
5611 }
5612 return 1;
5613
5614 unlock:
5615 list_for_each_entry_continue_reverse(dev,
5616 &slot->bus->devices, bus_list) {
5617 if (!dev->slot || dev->slot != slot)
5618 continue;
5619 if (dev->subordinate)
5620 pci_bus_unlock(dev->subordinate);
5621 pci_dev_unlock(dev);
5622 }
5623 return 0;
5624 }
5625
5626 /*
5627 * Save and disable devices from the top of the tree down while holding
5628 * the @dev mutex lock for the entire tree.
5629 */
5630 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5631 {
5632 struct pci_dev *dev;
5633
5634 list_for_each_entry(dev, &bus->devices, bus_list) {
5635 pci_dev_save_and_disable(dev);
5636 if (dev->subordinate)
5637 pci_bus_save_and_disable_locked(dev->subordinate);
5638 }
5639 }
5640
5641 /*
5642 * Restore devices from top of the tree down while holding @dev mutex lock
5643 * for the entire tree. Parent bridges need to be restored before we can
5644 * get to subordinate devices.
5645 */
5646 static void pci_bus_restore_locked(struct pci_bus *bus)
5647 {
5648 struct pci_dev *dev;
5649
5650 list_for_each_entry(dev, &bus->devices, bus_list) {
5651 pci_dev_restore(dev);
5652 if (dev->subordinate)
5653 pci_bus_restore_locked(dev->subordinate);
5654 }
5655 }
5656
5657 /*
5658 * Save and disable devices from the top of the tree down while holding
5659 * the @dev mutex lock for the entire tree.
5660 */
5661 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5662 {
5663 struct pci_dev *dev;
5664
5665 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5666 if (!dev->slot || dev->slot != slot)
5667 continue;
5668 pci_dev_save_and_disable(dev);
5669 if (dev->subordinate)
5670 pci_bus_save_and_disable_locked(dev->subordinate);
5671 }
5672 }
5673
5674 /*
5675 * Restore devices from top of the tree down while holding @dev mutex lock
5676 * for the entire tree. Parent bridges need to be restored before we can
5677 * get to subordinate devices.
5678 */
5679 static void pci_slot_restore_locked(struct pci_slot *slot)
5680 {
5681 struct pci_dev *dev;
5682
5683 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5684 if (!dev->slot || dev->slot != slot)
5685 continue;
5686 pci_dev_restore(dev);
5687 if (dev->subordinate)
5688 pci_bus_restore_locked(dev->subordinate);
5689 }
5690 }
5691
5692 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5693 {
5694 int rc;
5695
5696 if (!slot || !pci_slot_resetable(slot))
5697 return -ENOTTY;
5698
5699 if (!probe)
5700 pci_slot_lock(slot);
5701
5702 might_sleep();
5703
5704 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5705
5706 if (!probe)
5707 pci_slot_unlock(slot);
5708
5709 return rc;
5710 }
5711
5712 /**
5713 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5714 * @slot: PCI slot to probe
5715 *
5716 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5717 */
5718 int pci_probe_reset_slot(struct pci_slot *slot)
5719 {
5720 return pci_slot_reset(slot, PCI_RESET_PROBE);
5721 }
5722 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5723
5724 /**
5725 * __pci_reset_slot - Try to reset a PCI slot
5726 * @slot: PCI slot to reset
5727 *
5728 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5729 * independent of other slots. For instance, some slots may support slot power
5730 * control. In the case of a 1:1 bus to slot architecture, this function may
5731 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5732 * Generally a slot reset should be attempted before a bus reset. All of the
5733 * function of the slot and any subordinate buses behind the slot are reset
5734 * through this function. PCI config space of all devices in the slot and
5735 * behind the slot is saved before and restored after reset.
5736 *
5737 * Same as above except return -EAGAIN if the slot cannot be locked
5738 */
5739 static int __pci_reset_slot(struct pci_slot *slot)
5740 {
5741 int rc;
5742
5743 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5744 if (rc)
5745 return rc;
5746
5747 if (pci_slot_trylock(slot)) {
5748 pci_slot_save_and_disable_locked(slot);
5749 might_sleep();
5750 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5751 pci_slot_restore_locked(slot);
5752 pci_slot_unlock(slot);
5753 } else
5754 rc = -EAGAIN;
5755
5756 return rc;
5757 }
5758
5759 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5760 {
5761 int ret;
5762
5763 if (!bus->self || !pci_bus_resetable(bus))
5764 return -ENOTTY;
5765
5766 if (probe)
5767 return 0;
5768
5769 pci_bus_lock(bus);
5770
5771 might_sleep();
5772
5773 ret = pci_bridge_secondary_bus_reset(bus->self);
5774
5775 pci_bus_unlock(bus);
5776
5777 return ret;
5778 }
5779
5780 /**
5781 * pci_bus_error_reset - reset the bridge's subordinate bus
5782 * @bridge: The parent device that connects to the bus to reset
5783 *
5784 * This function will first try to reset the slots on this bus if the method is
5785 * available. If slot reset fails or is not available, this will fall back to a
5786 * secondary bus reset.
5787 */
5788 int pci_bus_error_reset(struct pci_dev *bridge)
5789 {
5790 struct pci_bus *bus = bridge->subordinate;
5791 struct pci_slot *slot;
5792
5793 if (!bus)
5794 return -ENOTTY;
5795
5796 mutex_lock(&pci_slot_mutex);
5797 if (list_empty(&bus->slots))
5798 goto bus_reset;
5799
5800 list_for_each_entry(slot, &bus->slots, list)
5801 if (pci_probe_reset_slot(slot))
5802 goto bus_reset;
5803
5804 list_for_each_entry(slot, &bus->slots, list)
5805 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5806 goto bus_reset;
5807
5808 mutex_unlock(&pci_slot_mutex);
5809 return 0;
5810 bus_reset:
5811 mutex_unlock(&pci_slot_mutex);
5812 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5813 }
5814
5815 /**
5816 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5817 * @bus: PCI bus to probe
5818 *
5819 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5820 */
5821 int pci_probe_reset_bus(struct pci_bus *bus)
5822 {
5823 return pci_bus_reset(bus, PCI_RESET_PROBE);
5824 }
5825 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5826
5827 /**
5828 * __pci_reset_bus - Try to reset a PCI bus
5829 * @bus: top level PCI bus to reset
5830 *
5831 * Same as above except return -EAGAIN if the bus cannot be locked
5832 */
5833 static int __pci_reset_bus(struct pci_bus *bus)
5834 {
5835 int rc;
5836
5837 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5838 if (rc)
5839 return rc;
5840
5841 if (pci_bus_trylock(bus)) {
5842 pci_bus_save_and_disable_locked(bus);
5843 might_sleep();
5844 rc = pci_bridge_secondary_bus_reset(bus->self);
5845 pci_bus_restore_locked(bus);
5846 pci_bus_unlock(bus);
5847 } else
5848 rc = -EAGAIN;
5849
5850 return rc;
5851 }
5852
5853 /**
5854 * pci_reset_bus - Try to reset a PCI bus
5855 * @pdev: top level PCI device to reset via slot/bus
5856 *
5857 * Same as above except return -EAGAIN if the bus cannot be locked
5858 */
5859 int pci_reset_bus(struct pci_dev *pdev)
5860 {
5861 return (!pci_probe_reset_slot(pdev->slot)) ?
5862 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5863 }
5864 EXPORT_SYMBOL_GPL(pci_reset_bus);
5865
5866 /**
5867 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5868 * @dev: PCI device to query
5869 *
5870 * Returns mmrbc: maximum designed memory read count in bytes or
5871 * appropriate error value.
5872 */
5873 int pcix_get_max_mmrbc(struct pci_dev *dev)
5874 {
5875 int cap;
5876 u32 stat;
5877
5878 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5879 if (!cap)
5880 return -EINVAL;
5881
5882 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5883 return -EINVAL;
5884
5885 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5886 }
5887 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5888
5889 /**
5890 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5891 * @dev: PCI device to query
5892 *
5893 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5894 * value.
5895 */
5896 int pcix_get_mmrbc(struct pci_dev *dev)
5897 {
5898 int cap;
5899 u16 cmd;
5900
5901 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5902 if (!cap)
5903 return -EINVAL;
5904
5905 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5906 return -EINVAL;
5907
5908 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5909 }
5910 EXPORT_SYMBOL(pcix_get_mmrbc);
5911
5912 /**
5913 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5914 * @dev: PCI device to query
5915 * @mmrbc: maximum memory read count in bytes
5916 * valid values are 512, 1024, 2048, 4096
5917 *
5918 * If possible sets maximum memory read byte count, some bridges have errata
5919 * that prevent this.
5920 */
5921 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5922 {
5923 int cap;
5924 u32 stat, v, o;
5925 u16 cmd;
5926
5927 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5928 return -EINVAL;
5929
5930 v = ffs(mmrbc) - 10;
5931
5932 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5933 if (!cap)
5934 return -EINVAL;
5935
5936 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5937 return -EINVAL;
5938
5939 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5940 return -E2BIG;
5941
5942 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5943 return -EINVAL;
5944
5945 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5946 if (o != v) {
5947 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5948 return -EIO;
5949
5950 cmd &= ~PCI_X_CMD_MAX_READ;
5951 cmd |= v << 2;
5952 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5953 return -EIO;
5954 }
5955 return 0;
5956 }
5957 EXPORT_SYMBOL(pcix_set_mmrbc);
5958
5959 /**
5960 * pcie_get_readrq - get PCI Express read request size
5961 * @dev: PCI device to query
5962 *
5963 * Returns maximum memory read request in bytes or appropriate error value.
5964 */
5965 int pcie_get_readrq(struct pci_dev *dev)
5966 {
5967 u16 ctl;
5968
5969 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5970
5971 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5972 }
5973 EXPORT_SYMBOL(pcie_get_readrq);
5974
5975 /**
5976 * pcie_set_readrq - set PCI Express maximum memory read request
5977 * @dev: PCI device to query
5978 * @rq: maximum memory read count in bytes
5979 * valid values are 128, 256, 512, 1024, 2048, 4096
5980 *
5981 * If possible sets maximum memory read request in bytes
5982 */
5983 int pcie_set_readrq(struct pci_dev *dev, int rq)
5984 {
5985 u16 v;
5986 int ret;
5987
5988 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5989 return -EINVAL;
5990
5991 /*
5992 * If using the "performance" PCIe config, we clamp the read rq
5993 * size to the max packet size to keep the host bridge from
5994 * generating requests larger than we can cope with.
5995 */
5996 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5997 int mps = pcie_get_mps(dev);
5998
5999 if (mps < rq)
6000 rq = mps;
6001 }
6002
6003 v = (ffs(rq) - 8) << 12;
6004
6005 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6006 PCI_EXP_DEVCTL_READRQ, v);
6007
6008 return pcibios_err_to_errno(ret);
6009 }
6010 EXPORT_SYMBOL(pcie_set_readrq);
6011
6012 /**
6013 * pcie_get_mps - get PCI Express maximum payload size
6014 * @dev: PCI device to query
6015 *
6016 * Returns maximum payload size in bytes
6017 */
6018 int pcie_get_mps(struct pci_dev *dev)
6019 {
6020 u16 ctl;
6021
6022 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6023
6024 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6025 }
6026 EXPORT_SYMBOL(pcie_get_mps);
6027
6028 /**
6029 * pcie_set_mps - set PCI Express maximum payload size
6030 * @dev: PCI device to query
6031 * @mps: maximum payload size in bytes
6032 * valid values are 128, 256, 512, 1024, 2048, 4096
6033 *
6034 * If possible sets maximum payload size
6035 */
6036 int pcie_set_mps(struct pci_dev *dev, int mps)
6037 {
6038 u16 v;
6039 int ret;
6040
6041 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6042 return -EINVAL;
6043
6044 v = ffs(mps) - 8;
6045 if (v > dev->pcie_mpss)
6046 return -EINVAL;
6047 v <<= 5;
6048
6049 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6050 PCI_EXP_DEVCTL_PAYLOAD, v);
6051
6052 return pcibios_err_to_errno(ret);
6053 }
6054 EXPORT_SYMBOL(pcie_set_mps);
6055
6056 /**
6057 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6058 * device and its bandwidth limitation
6059 * @dev: PCI device to query
6060 * @limiting_dev: storage for device causing the bandwidth limitation
6061 * @speed: storage for speed of limiting device
6062 * @width: storage for width of limiting device
6063 *
6064 * Walk up the PCI device chain and find the point where the minimum
6065 * bandwidth is available. Return the bandwidth available there and (if
6066 * limiting_dev, speed, and width pointers are supplied) information about
6067 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6068 * raw bandwidth.
6069 */
6070 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6071 enum pci_bus_speed *speed,
6072 enum pcie_link_width *width)
6073 {
6074 u16 lnksta;
6075 enum pci_bus_speed next_speed;
6076 enum pcie_link_width next_width;
6077 u32 bw, next_bw;
6078
6079 if (speed)
6080 *speed = PCI_SPEED_UNKNOWN;
6081 if (width)
6082 *width = PCIE_LNK_WIDTH_UNKNOWN;
6083
6084 bw = 0;
6085
6086 while (dev) {
6087 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6088
6089 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6090 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6091 PCI_EXP_LNKSTA_NLW_SHIFT;
6092
6093 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6094
6095 /* Check if current device limits the total bandwidth */
6096 if (!bw || next_bw <= bw) {
6097 bw = next_bw;
6098
6099 if (limiting_dev)
6100 *limiting_dev = dev;
6101 if (speed)
6102 *speed = next_speed;
6103 if (width)
6104 *width = next_width;
6105 }
6106
6107 dev = pci_upstream_bridge(dev);
6108 }
6109
6110 return bw;
6111 }
6112 EXPORT_SYMBOL(pcie_bandwidth_available);
6113
6114 /**
6115 * pcie_get_speed_cap - query for the PCI device's link speed capability
6116 * @dev: PCI device to query
6117 *
6118 * Query the PCI device speed capability. Return the maximum link speed
6119 * supported by the device.
6120 */
6121 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6122 {
6123 u32 lnkcap2, lnkcap;
6124
6125 /*
6126 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6127 * implementation note there recommends using the Supported Link
6128 * Speeds Vector in Link Capabilities 2 when supported.
6129 *
6130 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6131 * should use the Supported Link Speeds field in Link Capabilities,
6132 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6133 */
6134 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6135
6136 /* PCIe r3.0-compliant */
6137 if (lnkcap2)
6138 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6139
6140 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6141 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6142 return PCIE_SPEED_5_0GT;
6143 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6144 return PCIE_SPEED_2_5GT;
6145
6146 return PCI_SPEED_UNKNOWN;
6147 }
6148 EXPORT_SYMBOL(pcie_get_speed_cap);
6149
6150 /**
6151 * pcie_get_width_cap - query for the PCI device's link width capability
6152 * @dev: PCI device to query
6153 *
6154 * Query the PCI device width capability. Return the maximum link width
6155 * supported by the device.
6156 */
6157 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6158 {
6159 u32 lnkcap;
6160
6161 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6162 if (lnkcap)
6163 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6164
6165 return PCIE_LNK_WIDTH_UNKNOWN;
6166 }
6167 EXPORT_SYMBOL(pcie_get_width_cap);
6168
6169 /**
6170 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6171 * @dev: PCI device
6172 * @speed: storage for link speed
6173 * @width: storage for link width
6174 *
6175 * Calculate a PCI device's link bandwidth by querying for its link speed
6176 * and width, multiplying them, and applying encoding overhead. The result
6177 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6178 */
6179 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6180 enum pcie_link_width *width)
6181 {
6182 *speed = pcie_get_speed_cap(dev);
6183 *width = pcie_get_width_cap(dev);
6184
6185 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6186 return 0;
6187
6188 return *width * PCIE_SPEED2MBS_ENC(*speed);
6189 }
6190
6191 /**
6192 * __pcie_print_link_status - Report the PCI device's link speed and width
6193 * @dev: PCI device to query
6194 * @verbose: Print info even when enough bandwidth is available
6195 *
6196 * If the available bandwidth at the device is less than the device is
6197 * capable of, report the device's maximum possible bandwidth and the
6198 * upstream link that limits its performance. If @verbose, always print
6199 * the available bandwidth, even if the device isn't constrained.
6200 */
6201 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6202 {
6203 enum pcie_link_width width, width_cap;
6204 enum pci_bus_speed speed, speed_cap;
6205 struct pci_dev *limiting_dev = NULL;
6206 u32 bw_avail, bw_cap;
6207
6208 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6209 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6210
6211 if (bw_avail >= bw_cap && verbose)
6212 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6213 bw_cap / 1000, bw_cap % 1000,
6214 pci_speed_string(speed_cap), width_cap);
6215 else if (bw_avail < bw_cap)
6216 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6217 bw_avail / 1000, bw_avail % 1000,
6218 pci_speed_string(speed), width,
6219 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6220 bw_cap / 1000, bw_cap % 1000,
6221 pci_speed_string(speed_cap), width_cap);
6222 }
6223
6224 /**
6225 * pcie_print_link_status - Report the PCI device's link speed and width
6226 * @dev: PCI device to query
6227 *
6228 * Report the available bandwidth at the device.
6229 */
6230 void pcie_print_link_status(struct pci_dev *dev)
6231 {
6232 __pcie_print_link_status(dev, true);
6233 }
6234 EXPORT_SYMBOL(pcie_print_link_status);
6235
6236 /**
6237 * pci_select_bars - Make BAR mask from the type of resource
6238 * @dev: the PCI device for which BAR mask is made
6239 * @flags: resource type mask to be selected
6240 *
6241 * This helper routine makes bar mask from the type of resource.
6242 */
6243 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6244 {
6245 int i, bars = 0;
6246 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6247 if (pci_resource_flags(dev, i) & flags)
6248 bars |= (1 << i);
6249 return bars;
6250 }
6251 EXPORT_SYMBOL(pci_select_bars);
6252
6253 /* Some architectures require additional programming to enable VGA */
6254 static arch_set_vga_state_t arch_set_vga_state;
6255
6256 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6257 {
6258 arch_set_vga_state = func; /* NULL disables */
6259 }
6260
6261 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6262 unsigned int command_bits, u32 flags)
6263 {
6264 if (arch_set_vga_state)
6265 return arch_set_vga_state(dev, decode, command_bits,
6266 flags);
6267 return 0;
6268 }
6269
6270 /**
6271 * pci_set_vga_state - set VGA decode state on device and parents if requested
6272 * @dev: the PCI device
6273 * @decode: true = enable decoding, false = disable decoding
6274 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6275 * @flags: traverse ancestors and change bridges
6276 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6277 */
6278 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6279 unsigned int command_bits, u32 flags)
6280 {
6281 struct pci_bus *bus;
6282 struct pci_dev *bridge;
6283 u16 cmd;
6284 int rc;
6285
6286 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6287
6288 /* ARCH specific VGA enables */
6289 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6290 if (rc)
6291 return rc;
6292
6293 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6294 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6295 if (decode)
6296 cmd |= command_bits;
6297 else
6298 cmd &= ~command_bits;
6299 pci_write_config_word(dev, PCI_COMMAND, cmd);
6300 }
6301
6302 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6303 return 0;
6304
6305 bus = dev->bus;
6306 while (bus) {
6307 bridge = bus->self;
6308 if (bridge) {
6309 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6310 &cmd);
6311 if (decode)
6312 cmd |= PCI_BRIDGE_CTL_VGA;
6313 else
6314 cmd &= ~PCI_BRIDGE_CTL_VGA;
6315 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6316 cmd);
6317 }
6318 bus = bus->parent;
6319 }
6320 return 0;
6321 }
6322
6323 #ifdef CONFIG_ACPI
6324 bool pci_pr3_present(struct pci_dev *pdev)
6325 {
6326 struct acpi_device *adev;
6327
6328 if (acpi_disabled)
6329 return false;
6330
6331 adev = ACPI_COMPANION(&pdev->dev);
6332 if (!adev)
6333 return false;
6334
6335 return adev->power.flags.power_resources &&
6336 acpi_has_method(adev->handle, "_PR3");
6337 }
6338 EXPORT_SYMBOL_GPL(pci_pr3_present);
6339 #endif
6340
6341 /**
6342 * pci_add_dma_alias - Add a DMA devfn alias for a device
6343 * @dev: the PCI device for which alias is added
6344 * @devfn_from: alias slot and function
6345 * @nr_devfns: number of subsequent devfns to alias
6346 *
6347 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6348 * which is used to program permissible bus-devfn source addresses for DMA
6349 * requests in an IOMMU. These aliases factor into IOMMU group creation
6350 * and are useful for devices generating DMA requests beyond or different
6351 * from their logical bus-devfn. Examples include device quirks where the
6352 * device simply uses the wrong devfn, as well as non-transparent bridges
6353 * where the alias may be a proxy for devices in another domain.
6354 *
6355 * IOMMU group creation is performed during device discovery or addition,
6356 * prior to any potential DMA mapping and therefore prior to driver probing
6357 * (especially for userspace assigned devices where IOMMU group definition
6358 * cannot be left as a userspace activity). DMA aliases should therefore
6359 * be configured via quirks, such as the PCI fixup header quirk.
6360 */
6361 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6362 {
6363 int devfn_to;
6364
6365 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6366 devfn_to = devfn_from + nr_devfns - 1;
6367
6368 if (!dev->dma_alias_mask)
6369 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6370 if (!dev->dma_alias_mask) {
6371 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6372 return;
6373 }
6374
6375 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6376
6377 if (nr_devfns == 1)
6378 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6379 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6380 else if (nr_devfns > 1)
6381 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6382 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6383 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6384 }
6385
6386 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6387 {
6388 return (dev1->dma_alias_mask &&
6389 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6390 (dev2->dma_alias_mask &&
6391 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6392 pci_real_dma_dev(dev1) == dev2 ||
6393 pci_real_dma_dev(dev2) == dev1;
6394 }
6395
6396 bool pci_device_is_present(struct pci_dev *pdev)
6397 {
6398 u32 v;
6399
6400 if (pci_dev_is_disconnected(pdev))
6401 return false;
6402 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6403 }
6404 EXPORT_SYMBOL_GPL(pci_device_is_present);
6405
6406 void pci_ignore_hotplug(struct pci_dev *dev)
6407 {
6408 struct pci_dev *bridge = dev->bus->self;
6409
6410 dev->ignore_hotplug = 1;
6411 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6412 if (bridge)
6413 bridge->ignore_hotplug = 1;
6414 }
6415 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6416
6417 /**
6418 * pci_real_dma_dev - Get PCI DMA device for PCI device
6419 * @dev: the PCI device that may have a PCI DMA alias
6420 *
6421 * Permits the platform to provide architecture-specific functionality to
6422 * devices needing to alias DMA to another PCI device on another PCI bus. If
6423 * the PCI device is on the same bus, it is recommended to use
6424 * pci_add_dma_alias(). This is the default implementation. Architecture
6425 * implementations can override this.
6426 */
6427 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6428 {
6429 return dev;
6430 }
6431
6432 resource_size_t __weak pcibios_default_alignment(void)
6433 {
6434 return 0;
6435 }
6436
6437 /*
6438 * Arches that don't want to expose struct resource to userland as-is in
6439 * sysfs and /proc can implement their own pci_resource_to_user().
6440 */
6441 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6442 const struct resource *rsrc,
6443 resource_size_t *start, resource_size_t *end)
6444 {
6445 *start = rsrc->start;
6446 *end = rsrc->end;
6447 }
6448
6449 static char *resource_alignment_param;
6450 static DEFINE_SPINLOCK(resource_alignment_lock);
6451
6452 /**
6453 * pci_specified_resource_alignment - get resource alignment specified by user.
6454 * @dev: the PCI device to get
6455 * @resize: whether or not to change resources' size when reassigning alignment
6456 *
6457 * RETURNS: Resource alignment if it is specified.
6458 * Zero if it is not specified.
6459 */
6460 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6461 bool *resize)
6462 {
6463 int align_order, count;
6464 resource_size_t align = pcibios_default_alignment();
6465 const char *p;
6466 int ret;
6467
6468 spin_lock(&resource_alignment_lock);
6469 p = resource_alignment_param;
6470 if (!p || !*p)
6471 goto out;
6472 if (pci_has_flag(PCI_PROBE_ONLY)) {
6473 align = 0;
6474 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6475 goto out;
6476 }
6477
6478 while (*p) {
6479 count = 0;
6480 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6481 p[count] == '@') {
6482 p += count + 1;
6483 if (align_order > 63) {
6484 pr_err("PCI: Invalid requested alignment (order %d)\n",
6485 align_order);
6486 align_order = PAGE_SHIFT;
6487 }
6488 } else {
6489 align_order = PAGE_SHIFT;
6490 }
6491
6492 ret = pci_dev_str_match(dev, p, &p);
6493 if (ret == 1) {
6494 *resize = true;
6495 align = 1ULL << align_order;
6496 break;
6497 } else if (ret < 0) {
6498 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6499 p);
6500 break;
6501 }
6502
6503 if (*p != ';' && *p != ',') {
6504 /* End of param or invalid format */
6505 break;
6506 }
6507 p++;
6508 }
6509 out:
6510 spin_unlock(&resource_alignment_lock);
6511 return align;
6512 }
6513
6514 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6515 resource_size_t align, bool resize)
6516 {
6517 struct resource *r = &dev->resource[bar];
6518 resource_size_t size;
6519
6520 if (!(r->flags & IORESOURCE_MEM))
6521 return;
6522
6523 if (r->flags & IORESOURCE_PCI_FIXED) {
6524 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6525 bar, r, (unsigned long long)align);
6526 return;
6527 }
6528
6529 size = resource_size(r);
6530 if (size >= align)
6531 return;
6532
6533 /*
6534 * Increase the alignment of the resource. There are two ways we
6535 * can do this:
6536 *
6537 * 1) Increase the size of the resource. BARs are aligned on their
6538 * size, so when we reallocate space for this resource, we'll
6539 * allocate it with the larger alignment. This also prevents
6540 * assignment of any other BARs inside the alignment region, so
6541 * if we're requesting page alignment, this means no other BARs
6542 * will share the page.
6543 *
6544 * The disadvantage is that this makes the resource larger than
6545 * the hardware BAR, which may break drivers that compute things
6546 * based on the resource size, e.g., to find registers at a
6547 * fixed offset before the end of the BAR.
6548 *
6549 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6550 * set r->start to the desired alignment. By itself this
6551 * doesn't prevent other BARs being put inside the alignment
6552 * region, but if we realign *every* resource of every device in
6553 * the system, none of them will share an alignment region.
6554 *
6555 * When the user has requested alignment for only some devices via
6556 * the "pci=resource_alignment" argument, "resize" is true and we
6557 * use the first method. Otherwise we assume we're aligning all
6558 * devices and we use the second.
6559 */
6560
6561 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6562 bar, r, (unsigned long long)align);
6563
6564 if (resize) {
6565 r->start = 0;
6566 r->end = align - 1;
6567 } else {
6568 r->flags &= ~IORESOURCE_SIZEALIGN;
6569 r->flags |= IORESOURCE_STARTALIGN;
6570 r->start = align;
6571 r->end = r->start + size - 1;
6572 }
6573 r->flags |= IORESOURCE_UNSET;
6574 }
6575
6576 /*
6577 * This function disables memory decoding and releases memory resources
6578 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6579 * It also rounds up size to specified alignment.
6580 * Later on, the kernel will assign page-aligned memory resource back
6581 * to the device.
6582 */
6583 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6584 {
6585 int i;
6586 struct resource *r;
6587 resource_size_t align;
6588 u16 command;
6589 bool resize = false;
6590
6591 /*
6592 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6593 * 3.4.1.11. Their resources are allocated from the space
6594 * described by the VF BARx register in the PF's SR-IOV capability.
6595 * We can't influence their alignment here.
6596 */
6597 if (dev->is_virtfn)
6598 return;
6599
6600 /* check if specified PCI is target device to reassign */
6601 align = pci_specified_resource_alignment(dev, &resize);
6602 if (!align)
6603 return;
6604
6605 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6606 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6607 pci_warn(dev, "Can't reassign resources to host bridge\n");
6608 return;
6609 }
6610
6611 pci_read_config_word(dev, PCI_COMMAND, &command);
6612 command &= ~PCI_COMMAND_MEMORY;
6613 pci_write_config_word(dev, PCI_COMMAND, command);
6614
6615 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6616 pci_request_resource_alignment(dev, i, align, resize);
6617
6618 /*
6619 * Need to disable bridge's resource window,
6620 * to enable the kernel to reassign new resource
6621 * window later on.
6622 */
6623 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6624 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6625 r = &dev->resource[i];
6626 if (!(r->flags & IORESOURCE_MEM))
6627 continue;
6628 r->flags |= IORESOURCE_UNSET;
6629 r->end = resource_size(r) - 1;
6630 r->start = 0;
6631 }
6632 pci_disable_bridge_window(dev);
6633 }
6634 }
6635
6636 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6637 {
6638 size_t count = 0;
6639
6640 spin_lock(&resource_alignment_lock);
6641 if (resource_alignment_param)
6642 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6643 spin_unlock(&resource_alignment_lock);
6644
6645 return count;
6646 }
6647
6648 static ssize_t resource_alignment_store(struct bus_type *bus,
6649 const char *buf, size_t count)
6650 {
6651 char *param, *old, *end;
6652
6653 if (count >= (PAGE_SIZE - 1))
6654 return -EINVAL;
6655
6656 param = kstrndup(buf, count, GFP_KERNEL);
6657 if (!param)
6658 return -ENOMEM;
6659
6660 end = strchr(param, '\n');
6661 if (end)
6662 *end = '\0';
6663
6664 spin_lock(&resource_alignment_lock);
6665 old = resource_alignment_param;
6666 if (strlen(param)) {
6667 resource_alignment_param = param;
6668 } else {
6669 kfree(param);
6670 resource_alignment_param = NULL;
6671 }
6672 spin_unlock(&resource_alignment_lock);
6673
6674 kfree(old);
6675
6676 return count;
6677 }
6678
6679 static BUS_ATTR_RW(resource_alignment);
6680
6681 static int __init pci_resource_alignment_sysfs_init(void)
6682 {
6683 return bus_create_file(&pci_bus_type,
6684 &bus_attr_resource_alignment);
6685 }
6686 late_initcall(pci_resource_alignment_sysfs_init);
6687
6688 static void pci_no_domains(void)
6689 {
6690 #ifdef CONFIG_PCI_DOMAINS
6691 pci_domains_supported = 0;
6692 #endif
6693 }
6694
6695 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6696 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6697
6698 static int pci_get_new_domain_nr(void)
6699 {
6700 return atomic_inc_return(&__domain_nr);
6701 }
6702
6703 static int of_pci_bus_find_domain_nr(struct device *parent)
6704 {
6705 static int use_dt_domains = -1;
6706 int domain = -1;
6707
6708 if (parent)
6709 domain = of_get_pci_domain_nr(parent->of_node);
6710
6711 /*
6712 * Check DT domain and use_dt_domains values.
6713 *
6714 * If DT domain property is valid (domain >= 0) and
6715 * use_dt_domains != 0, the DT assignment is valid since this means
6716 * we have not previously allocated a domain number by using
6717 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6718 * 1, to indicate that we have just assigned a domain number from
6719 * DT.
6720 *
6721 * If DT domain property value is not valid (ie domain < 0), and we
6722 * have not previously assigned a domain number from DT
6723 * (use_dt_domains != 1) we should assign a domain number by
6724 * using the:
6725 *
6726 * pci_get_new_domain_nr()
6727 *
6728 * API and update the use_dt_domains value to keep track of method we
6729 * are using to assign domain numbers (use_dt_domains = 0).
6730 *
6731 * All other combinations imply we have a platform that is trying
6732 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6733 * which is a recipe for domain mishandling and it is prevented by
6734 * invalidating the domain value (domain = -1) and printing a
6735 * corresponding error.
6736 */
6737 if (domain >= 0 && use_dt_domains) {
6738 use_dt_domains = 1;
6739 } else if (domain < 0 && use_dt_domains != 1) {
6740 use_dt_domains = 0;
6741 domain = pci_get_new_domain_nr();
6742 } else {
6743 if (parent)
6744 pr_err("Node %pOF has ", parent->of_node);
6745 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6746 domain = -1;
6747 }
6748
6749 return domain;
6750 }
6751
6752 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6753 {
6754 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6755 acpi_pci_bus_find_domain_nr(bus);
6756 }
6757 #endif
6758
6759 /**
6760 * pci_ext_cfg_avail - can we access extended PCI config space?
6761 *
6762 * Returns 1 if we can access PCI extended config space (offsets
6763 * greater than 0xff). This is the default implementation. Architecture
6764 * implementations can override this.
6765 */
6766 int __weak pci_ext_cfg_avail(void)
6767 {
6768 return 1;
6769 }
6770
6771 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6772 {
6773 }
6774 EXPORT_SYMBOL(pci_fixup_cardbus);
6775
6776 static int __init pci_setup(char *str)
6777 {
6778 while (str) {
6779 char *k = strchr(str, ',');
6780 if (k)
6781 *k++ = 0;
6782 if (*str && (str = pcibios_setup(str)) && *str) {
6783 if (!strcmp(str, "nomsi")) {
6784 pci_no_msi();
6785 } else if (!strncmp(str, "noats", 5)) {
6786 pr_info("PCIe: ATS is disabled\n");
6787 pcie_ats_disabled = true;
6788 } else if (!strcmp(str, "noaer")) {
6789 pci_no_aer();
6790 } else if (!strcmp(str, "earlydump")) {
6791 pci_early_dump = true;
6792 } else if (!strncmp(str, "realloc=", 8)) {
6793 pci_realloc_get_opt(str + 8);
6794 } else if (!strncmp(str, "realloc", 7)) {
6795 pci_realloc_get_opt("on");
6796 } else if (!strcmp(str, "nodomains")) {
6797 pci_no_domains();
6798 } else if (!strncmp(str, "noari", 5)) {
6799 pcie_ari_disabled = true;
6800 } else if (!strncmp(str, "cbiosize=", 9)) {
6801 pci_cardbus_io_size = memparse(str + 9, &str);
6802 } else if (!strncmp(str, "cbmemsize=", 10)) {
6803 pci_cardbus_mem_size = memparse(str + 10, &str);
6804 } else if (!strncmp(str, "resource_alignment=", 19)) {
6805 resource_alignment_param = str + 19;
6806 } else if (!strncmp(str, "ecrc=", 5)) {
6807 pcie_ecrc_get_policy(str + 5);
6808 } else if (!strncmp(str, "hpiosize=", 9)) {
6809 pci_hotplug_io_size = memparse(str + 9, &str);
6810 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6811 pci_hotplug_mmio_size = memparse(str + 11, &str);
6812 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6813 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6814 } else if (!strncmp(str, "hpmemsize=", 10)) {
6815 pci_hotplug_mmio_size = memparse(str + 10, &str);
6816 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6817 } else if (!strncmp(str, "hpbussize=", 10)) {
6818 pci_hotplug_bus_size =
6819 simple_strtoul(str + 10, &str, 0);
6820 if (pci_hotplug_bus_size > 0xff)
6821 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6822 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6823 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6824 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6825 pcie_bus_config = PCIE_BUS_SAFE;
6826 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6827 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6828 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6829 pcie_bus_config = PCIE_BUS_PEER2PEER;
6830 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6831 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6832 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6833 disable_acs_redir_param = str + 18;
6834 } else {
6835 pr_err("PCI: Unknown option `%s'\n", str);
6836 }
6837 }
6838 str = k;
6839 }
6840 return 0;
6841 }
6842 early_param("pci", pci_setup);
6843
6844 /*
6845 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6846 * in pci_setup(), above, to point to data in the __initdata section which
6847 * will be freed after the init sequence is complete. We can't allocate memory
6848 * in pci_setup() because some architectures do not have any memory allocation
6849 * service available during an early_param() call. So we allocate memory and
6850 * copy the variable here before the init section is freed.
6851 *
6852 */
6853 static int __init pci_realloc_setup_params(void)
6854 {
6855 resource_alignment_param = kstrdup(resource_alignment_param,
6856 GFP_KERNEL);
6857 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6858
6859 return 0;
6860 }
6861 pure_initcall(pci_realloc_setup_params);