2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
34 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1)
37 u32 l0s
; /* L0s latency (nsec) */
38 u32 l1
; /* L1 latency (nsec) */
41 struct pcie_link_state
{
42 struct pci_dev
*pdev
; /* Upstream component of the Link */
43 struct pcie_link_state
*root
; /* pointer to the root port link */
44 struct pcie_link_state
*parent
; /* pointer to the parent Link state */
45 struct list_head sibling
; /* node in link_list */
46 struct list_head children
; /* list of child link states */
47 struct list_head link
; /* node in parent's children list */
50 u32 aspm_support
:3; /* Supported ASPM state */
51 u32 aspm_enabled
:3; /* Enabled ASPM state */
52 u32 aspm_capable
:3; /* Capable ASPM state with latency */
53 u32 aspm_default
:3; /* Default ASPM state by BIOS */
54 u32 aspm_disable
:3; /* Disabled ASPM state */
57 u32 clkpm_capable
:1; /* Clock PM capable? */
58 u32 clkpm_enabled
:1; /* Current Clock PM state */
59 u32 clkpm_default
:1; /* Default Clock PM state by BIOS */
62 struct aspm_latency latency_up
; /* Upstream direction exit latency */
63 struct aspm_latency latency_dw
; /* Downstream direction exit latency */
65 * Endpoint acceptable latencies. A pcie downstream port only
66 * has one slot under it, so at most there are 8 functions.
68 struct aspm_latency acceptable
[8];
71 static int aspm_disabled
, aspm_force
;
72 static bool aspm_support_enabled
= true;
73 static DEFINE_MUTEX(aspm_lock
);
74 static LIST_HEAD(link_list
);
76 #define POLICY_DEFAULT 0 /* BIOS default setting */
77 #define POLICY_PERFORMANCE 1 /* high performance */
78 #define POLICY_POWERSAVE 2 /* high power saving */
80 #ifdef CONFIG_PCIEASPM_PERFORMANCE
81 static int aspm_policy
= POLICY_PERFORMANCE
;
82 #elif defined CONFIG_PCIEASPM_POWERSAVE
83 static int aspm_policy
= POLICY_POWERSAVE
;
85 static int aspm_policy
;
88 static const char *policy_str
[] = {
89 [POLICY_DEFAULT
] = "default",
90 [POLICY_PERFORMANCE
] = "performance",
91 [POLICY_POWERSAVE
] = "powersave"
94 #define LINK_RETRAIN_TIMEOUT HZ
96 static int policy_to_aspm_state(struct pcie_link_state
*link
)
98 switch (aspm_policy
) {
99 case POLICY_PERFORMANCE
:
100 /* Disable ASPM and Clock PM */
102 case POLICY_POWERSAVE
:
103 /* Enable ASPM L0s/L1 */
104 return ASPM_STATE_ALL
;
106 return link
->aspm_default
;
111 static int policy_to_clkpm_state(struct pcie_link_state
*link
)
113 switch (aspm_policy
) {
114 case POLICY_PERFORMANCE
:
115 /* Disable ASPM and Clock PM */
117 case POLICY_POWERSAVE
:
118 /* Disable Clock PM */
121 return link
->clkpm_default
;
126 static void pcie_set_clkpm_nocheck(struct pcie_link_state
*link
, int enable
)
128 struct pci_dev
*child
;
129 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
131 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
133 pcie_capability_set_word(child
, PCI_EXP_LNKCTL
,
134 PCI_EXP_LNKCTL_CLKREQ_EN
);
136 pcie_capability_clear_word(child
, PCI_EXP_LNKCTL
,
137 PCI_EXP_LNKCTL_CLKREQ_EN
);
139 link
->clkpm_enabled
= !!enable
;
142 static void pcie_set_clkpm(struct pcie_link_state
*link
, int enable
)
144 /* Don't enable Clock PM if the link is not Clock PM capable */
145 if (!link
->clkpm_capable
&& enable
)
147 /* Need nothing if the specified equals to current state */
148 if (link
->clkpm_enabled
== enable
)
150 pcie_set_clkpm_nocheck(link
, enable
);
153 static void pcie_clkpm_cap_init(struct pcie_link_state
*link
, int blacklist
)
155 int capable
= 1, enabled
= 1;
158 struct pci_dev
*child
;
159 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
161 /* All functions should have the same cap and state, take the worst */
162 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
163 pcie_capability_read_dword(child
, PCI_EXP_LNKCAP
, ®32
);
164 if (!(reg32
& PCI_EXP_LNKCAP_CLKPM
)) {
169 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
170 if (!(reg16
& PCI_EXP_LNKCTL_CLKREQ_EN
))
173 link
->clkpm_enabled
= enabled
;
174 link
->clkpm_default
= enabled
;
175 link
->clkpm_capable
= (blacklist
) ? 0 : capable
;
179 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
180 * could use common clock. If they are, configure them to use the
181 * common clock. That will reduce the ASPM state exit latency.
183 static void pcie_aspm_configure_common_clock(struct pcie_link_state
*link
)
186 u16 reg16
, parent_reg
, child_reg
[8];
187 unsigned long start_jiffies
;
188 struct pci_dev
*child
, *parent
= link
->pdev
;
189 struct pci_bus
*linkbus
= parent
->subordinate
;
191 * All functions of a slot should have the same Slot Clock
192 * Configuration, so just check one function
194 child
= list_entry(linkbus
->devices
.next
, struct pci_dev
, bus_list
);
195 BUG_ON(!pci_is_pcie(child
));
197 /* Check downstream component if bit Slot Clock Configuration is 1 */
198 pcie_capability_read_word(child
, PCI_EXP_LNKSTA
, ®16
);
199 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
202 /* Check upstream component if bit Slot Clock Configuration is 1 */
203 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
204 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
207 /* Configure downstream component, all functions */
208 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
209 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
210 child_reg
[PCI_FUNC(child
->devfn
)] = reg16
;
212 reg16
|= PCI_EXP_LNKCTL_CCC
;
214 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
215 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
, reg16
);
218 /* Configure upstream component */
219 pcie_capability_read_word(parent
, PCI_EXP_LNKCTL
, ®16
);
222 reg16
|= PCI_EXP_LNKCTL_CCC
;
224 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
225 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
228 reg16
|= PCI_EXP_LNKCTL_RL
;
229 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
231 /* Wait for link training end. Break out after waiting for timeout */
232 start_jiffies
= jiffies
;
234 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
235 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
237 if (time_after(jiffies
, start_jiffies
+ LINK_RETRAIN_TIMEOUT
))
241 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
244 /* Training failed. Restore common clock configurations */
245 dev_printk(KERN_ERR
, &parent
->dev
,
246 "ASPM: Could not configure common clock\n");
247 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
248 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
,
249 child_reg
[PCI_FUNC(child
->devfn
)]);
250 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, parent_reg
);
253 /* Convert L0s latency encoding to ns */
254 static u32
calc_l0s_latency(u32 encoding
)
257 return (5 * 1000); /* > 4us */
258 return (64 << encoding
);
261 /* Convert L0s acceptable latency encoding to ns */
262 static u32
calc_l0s_acceptable(u32 encoding
)
266 return (64 << encoding
);
269 /* Convert L1 latency encoding to ns */
270 static u32
calc_l1_latency(u32 encoding
)
273 return (65 * 1000); /* > 64us */
274 return (1000 << encoding
);
277 /* Convert L1 acceptable latency encoding to ns */
278 static u32
calc_l1_acceptable(u32 encoding
)
282 return (1000 << encoding
);
285 struct aspm_register_info
{
288 u32 latency_encoding_l0s
;
289 u32 latency_encoding_l1
;
292 static void pcie_get_aspm_reg(struct pci_dev
*pdev
,
293 struct aspm_register_info
*info
)
298 pcie_capability_read_dword(pdev
, PCI_EXP_LNKCAP
, ®32
);
299 info
->support
= (reg32
& PCI_EXP_LNKCAP_ASPMS
) >> 10;
300 info
->latency_encoding_l0s
= (reg32
& PCI_EXP_LNKCAP_L0SEL
) >> 12;
301 info
->latency_encoding_l1
= (reg32
& PCI_EXP_LNKCAP_L1EL
) >> 15;
302 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, ®16
);
303 info
->enabled
= reg16
& PCI_EXP_LNKCTL_ASPMC
;
306 static void pcie_aspm_check_latency(struct pci_dev
*endpoint
)
308 u32 latency
, l1_switch_latency
= 0;
309 struct aspm_latency
*acceptable
;
310 struct pcie_link_state
*link
;
312 /* Device not in D0 doesn't need latency check */
313 if ((endpoint
->current_state
!= PCI_D0
) &&
314 (endpoint
->current_state
!= PCI_UNKNOWN
))
317 link
= endpoint
->bus
->self
->link_state
;
318 acceptable
= &link
->acceptable
[PCI_FUNC(endpoint
->devfn
)];
321 /* Check upstream direction L0s latency */
322 if ((link
->aspm_capable
& ASPM_STATE_L0S_UP
) &&
323 (link
->latency_up
.l0s
> acceptable
->l0s
))
324 link
->aspm_capable
&= ~ASPM_STATE_L0S_UP
;
326 /* Check downstream direction L0s latency */
327 if ((link
->aspm_capable
& ASPM_STATE_L0S_DW
) &&
328 (link
->latency_dw
.l0s
> acceptable
->l0s
))
329 link
->aspm_capable
&= ~ASPM_STATE_L0S_DW
;
332 * Every switch on the path to root complex need 1
333 * more microsecond for L1. Spec doesn't mention L0s.
335 latency
= max_t(u32
, link
->latency_up
.l1
, link
->latency_dw
.l1
);
336 if ((link
->aspm_capable
& ASPM_STATE_L1
) &&
337 (latency
+ l1_switch_latency
> acceptable
->l1
))
338 link
->aspm_capable
&= ~ASPM_STATE_L1
;
339 l1_switch_latency
+= 1000;
345 static void pcie_aspm_cap_init(struct pcie_link_state
*link
, int blacklist
)
347 struct pci_dev
*child
, *parent
= link
->pdev
;
348 struct pci_bus
*linkbus
= parent
->subordinate
;
349 struct aspm_register_info upreg
, dwreg
;
352 /* Set enabled/disable so that we will disable ASPM later */
353 link
->aspm_enabled
= ASPM_STATE_ALL
;
354 link
->aspm_disable
= ASPM_STATE_ALL
;
358 /* Configure common clock before checking latencies */
359 pcie_aspm_configure_common_clock(link
);
361 /* Get upstream/downstream components' register state */
362 pcie_get_aspm_reg(parent
, &upreg
);
363 child
= list_entry(linkbus
->devices
.next
, struct pci_dev
, bus_list
);
364 pcie_get_aspm_reg(child
, &dwreg
);
369 * Note that we must not enable L0s in either direction on a
370 * given link unless components on both sides of the link each
373 if (dwreg
.support
& upreg
.support
& PCIE_LINK_STATE_L0S
)
374 link
->aspm_support
|= ASPM_STATE_L0S
;
375 if (dwreg
.enabled
& PCIE_LINK_STATE_L0S
)
376 link
->aspm_enabled
|= ASPM_STATE_L0S_UP
;
377 if (upreg
.enabled
& PCIE_LINK_STATE_L0S
)
378 link
->aspm_enabled
|= ASPM_STATE_L0S_DW
;
379 link
->latency_up
.l0s
= calc_l0s_latency(upreg
.latency_encoding_l0s
);
380 link
->latency_dw
.l0s
= calc_l0s_latency(dwreg
.latency_encoding_l0s
);
383 if (upreg
.support
& dwreg
.support
& PCIE_LINK_STATE_L1
)
384 link
->aspm_support
|= ASPM_STATE_L1
;
385 if (upreg
.enabled
& dwreg
.enabled
& PCIE_LINK_STATE_L1
)
386 link
->aspm_enabled
|= ASPM_STATE_L1
;
387 link
->latency_up
.l1
= calc_l1_latency(upreg
.latency_encoding_l1
);
388 link
->latency_dw
.l1
= calc_l1_latency(dwreg
.latency_encoding_l1
);
390 /* Save default state */
391 link
->aspm_default
= link
->aspm_enabled
;
393 /* Setup initial capable state. Will be updated later */
394 link
->aspm_capable
= link
->aspm_support
;
396 * If the downstream component has pci bridge function, don't
399 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
400 if (pci_pcie_type(child
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
401 link
->aspm_disable
= ASPM_STATE_ALL
;
406 /* Get and check endpoint acceptable latencies */
407 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
409 struct aspm_latency
*acceptable
=
410 &link
->acceptable
[PCI_FUNC(child
->devfn
)];
412 if (pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
&&
413 pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
)
416 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
417 /* Calculate endpoint L0s acceptable latency */
418 encoding
= (reg32
& PCI_EXP_DEVCAP_L0S
) >> 6;
419 acceptable
->l0s
= calc_l0s_acceptable(encoding
);
420 /* Calculate endpoint L1 acceptable latency */
421 encoding
= (reg32
& PCI_EXP_DEVCAP_L1
) >> 9;
422 acceptable
->l1
= calc_l1_acceptable(encoding
);
424 pcie_aspm_check_latency(child
);
428 static void pcie_config_aspm_dev(struct pci_dev
*pdev
, u32 val
)
430 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_LNKCTL
, 0x3, val
);
433 static void pcie_config_aspm_link(struct pcie_link_state
*link
, u32 state
)
435 u32 upstream
= 0, dwstream
= 0;
436 struct pci_dev
*child
, *parent
= link
->pdev
;
437 struct pci_bus
*linkbus
= parent
->subordinate
;
439 /* Nothing to do if the link is already in the requested state */
440 state
&= (link
->aspm_capable
& ~link
->aspm_disable
);
441 if (link
->aspm_enabled
== state
)
443 /* Convert ASPM state to upstream/downstream ASPM register state */
444 if (state
& ASPM_STATE_L0S_UP
)
445 dwstream
|= PCIE_LINK_STATE_L0S
;
446 if (state
& ASPM_STATE_L0S_DW
)
447 upstream
|= PCIE_LINK_STATE_L0S
;
448 if (state
& ASPM_STATE_L1
) {
449 upstream
|= PCIE_LINK_STATE_L1
;
450 dwstream
|= PCIE_LINK_STATE_L1
;
453 * Spec 2.0 suggests all functions should be configured the
454 * same setting for ASPM. Enabling ASPM L1 should be done in
455 * upstream component first and then downstream, and vice
456 * versa for disabling ASPM L1. Spec doesn't mention L0S.
458 if (state
& ASPM_STATE_L1
)
459 pcie_config_aspm_dev(parent
, upstream
);
460 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
461 pcie_config_aspm_dev(child
, dwstream
);
462 if (!(state
& ASPM_STATE_L1
))
463 pcie_config_aspm_dev(parent
, upstream
);
465 link
->aspm_enabled
= state
;
468 static void pcie_config_aspm_path(struct pcie_link_state
*link
)
471 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
476 static void free_link_state(struct pcie_link_state
*link
)
478 link
->pdev
->link_state
= NULL
;
482 static int pcie_aspm_sanity_check(struct pci_dev
*pdev
)
484 struct pci_dev
*child
;
488 * Some functions in a slot might not all be PCIe functions,
489 * very strange. Disable ASPM for the whole slot
491 list_for_each_entry(child
, &pdev
->subordinate
->devices
, bus_list
) {
492 if (!pci_is_pcie(child
))
496 * If ASPM is disabled then we're not going to change
497 * the BIOS state. It's safe to continue even if it's a
505 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
506 * RBER bit to determine if a function is 1.1 version device
508 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
509 if (!(reg32
& PCI_EXP_DEVCAP_RBER
) && !aspm_force
) {
510 dev_printk(KERN_INFO
, &child
->dev
, "disabling ASPM"
511 " on pre-1.1 PCIe device. You can enable it"
512 " with 'pcie_aspm=force'\n");
519 static struct pcie_link_state
*alloc_pcie_link_state(struct pci_dev
*pdev
)
521 struct pcie_link_state
*link
;
523 link
= kzalloc(sizeof(*link
), GFP_KERNEL
);
526 INIT_LIST_HEAD(&link
->sibling
);
527 INIT_LIST_HEAD(&link
->children
);
528 INIT_LIST_HEAD(&link
->link
);
530 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_DOWNSTREAM
) {
531 struct pcie_link_state
*parent
;
532 parent
= pdev
->bus
->parent
->self
->link_state
;
537 link
->parent
= parent
;
538 list_add(&link
->link
, &parent
->children
);
540 /* Setup a pointer to the root port link */
544 link
->root
= link
->parent
->root
;
546 list_add(&link
->sibling
, &link_list
);
547 pdev
->link_state
= link
;
552 * pcie_aspm_init_link_state: Initiate PCI express link state.
553 * It is called after the pcie and its children devices are scaned.
554 * @pdev: the root port or switch downstream port
556 void pcie_aspm_init_link_state(struct pci_dev
*pdev
)
558 struct pcie_link_state
*link
;
559 int blacklist
= !!pcie_aspm_sanity_check(pdev
);
561 if (!pci_is_pcie(pdev
) || pdev
->link_state
)
563 if (pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
&&
564 pci_pcie_type(pdev
) != PCI_EXP_TYPE_DOWNSTREAM
)
567 /* VIA has a strange chipset, root port is under a bridge */
568 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
&&
572 down_read(&pci_bus_sem
);
573 if (list_empty(&pdev
->subordinate
->devices
))
576 mutex_lock(&aspm_lock
);
577 link
= alloc_pcie_link_state(pdev
);
581 * Setup initial ASPM state. Note that we need to configure
582 * upstream links also because capable state of them can be
583 * update through pcie_aspm_cap_init().
585 pcie_aspm_cap_init(link
, blacklist
);
587 /* Setup initial Clock PM state */
588 pcie_clkpm_cap_init(link
, blacklist
);
591 * At this stage drivers haven't had an opportunity to change the
592 * link policy setting. Enabling ASPM on broken hardware can cripple
593 * it even before the driver has had a chance to disable ASPM, so
594 * default to a safe level right now. If we're enabling ASPM beyond
595 * the BIOS's expectation, we'll do so once pci_enable_device() is
598 if (aspm_policy
!= POLICY_POWERSAVE
) {
599 pcie_config_aspm_path(link
);
600 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
604 mutex_unlock(&aspm_lock
);
606 up_read(&pci_bus_sem
);
609 /* Recheck latencies and update aspm_capable for links under the root */
610 static void pcie_update_aspm_capable(struct pcie_link_state
*root
)
612 struct pcie_link_state
*link
;
613 BUG_ON(root
->parent
);
614 list_for_each_entry(link
, &link_list
, sibling
) {
615 if (link
->root
!= root
)
617 link
->aspm_capable
= link
->aspm_support
;
619 list_for_each_entry(link
, &link_list
, sibling
) {
620 struct pci_dev
*child
;
621 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
622 if (link
->root
!= root
)
624 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
625 if ((pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
) &&
626 (pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
))
628 pcie_aspm_check_latency(child
);
633 /* @pdev: the endpoint device */
634 void pcie_aspm_exit_link_state(struct pci_dev
*pdev
)
636 struct pci_dev
*parent
= pdev
->bus
->self
;
637 struct pcie_link_state
*link
, *root
, *parent_link
;
639 if (!pci_is_pcie(pdev
) || !parent
|| !parent
->link_state
)
641 if ((pci_pcie_type(parent
) != PCI_EXP_TYPE_ROOT_PORT
) &&
642 (pci_pcie_type(parent
) != PCI_EXP_TYPE_DOWNSTREAM
))
645 down_read(&pci_bus_sem
);
646 mutex_lock(&aspm_lock
);
648 * All PCIe functions are in one slot, remove one function will remove
649 * the whole slot, so just wait until we are the last function left.
651 if (!list_is_last(&pdev
->bus_list
, &parent
->subordinate
->devices
))
654 link
= parent
->link_state
;
656 parent_link
= link
->parent
;
658 /* All functions are removed, so just disable ASPM for the link */
659 pcie_config_aspm_link(link
, 0);
660 list_del(&link
->sibling
);
661 list_del(&link
->link
);
662 /* Clock PM is for endpoint device */
663 free_link_state(link
);
665 /* Recheck latencies and configure upstream links */
667 pcie_update_aspm_capable(root
);
668 pcie_config_aspm_path(parent_link
);
671 mutex_unlock(&aspm_lock
);
672 up_read(&pci_bus_sem
);
675 /* @pdev: the root port or switch downstream port */
676 void pcie_aspm_pm_state_change(struct pci_dev
*pdev
)
678 struct pcie_link_state
*link
= pdev
->link_state
;
680 if (aspm_disabled
|| !pci_is_pcie(pdev
) || !link
)
682 if ((pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
) &&
683 (pci_pcie_type(pdev
) != PCI_EXP_TYPE_DOWNSTREAM
))
686 * Devices changed PM state, we should recheck if latency
687 * meets all functions' requirement
689 down_read(&pci_bus_sem
);
690 mutex_lock(&aspm_lock
);
691 pcie_update_aspm_capable(link
->root
);
692 pcie_config_aspm_path(link
);
693 mutex_unlock(&aspm_lock
);
694 up_read(&pci_bus_sem
);
697 void pcie_aspm_powersave_config_link(struct pci_dev
*pdev
)
699 struct pcie_link_state
*link
= pdev
->link_state
;
701 if (aspm_disabled
|| !pci_is_pcie(pdev
) || !link
)
704 if (aspm_policy
!= POLICY_POWERSAVE
)
707 if ((pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
) &&
708 (pci_pcie_type(pdev
) != PCI_EXP_TYPE_DOWNSTREAM
))
711 down_read(&pci_bus_sem
);
712 mutex_lock(&aspm_lock
);
713 pcie_config_aspm_path(link
);
714 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
715 mutex_unlock(&aspm_lock
);
716 up_read(&pci_bus_sem
);
720 * pci_disable_link_state - disable pci device's link state, so the link will
721 * never enter specific states
723 static void __pci_disable_link_state(struct pci_dev
*pdev
, int state
, bool sem
,
726 struct pci_dev
*parent
= pdev
->bus
->self
;
727 struct pcie_link_state
*link
;
729 if (aspm_disabled
&& !force
)
732 if (!pci_is_pcie(pdev
))
735 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
||
736 pci_pcie_type(pdev
) == PCI_EXP_TYPE_DOWNSTREAM
)
738 if (!parent
|| !parent
->link_state
)
742 down_read(&pci_bus_sem
);
743 mutex_lock(&aspm_lock
);
744 link
= parent
->link_state
;
745 if (state
& PCIE_LINK_STATE_L0S
)
746 link
->aspm_disable
|= ASPM_STATE_L0S
;
747 if (state
& PCIE_LINK_STATE_L1
)
748 link
->aspm_disable
|= ASPM_STATE_L1
;
749 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
751 if (state
& PCIE_LINK_STATE_CLKPM
) {
752 link
->clkpm_capable
= 0;
753 pcie_set_clkpm(link
, 0);
755 mutex_unlock(&aspm_lock
);
757 up_read(&pci_bus_sem
);
760 void pci_disable_link_state_locked(struct pci_dev
*pdev
, int state
)
762 __pci_disable_link_state(pdev
, state
, false, false);
764 EXPORT_SYMBOL(pci_disable_link_state_locked
);
766 void pci_disable_link_state(struct pci_dev
*pdev
, int state
)
768 __pci_disable_link_state(pdev
, state
, true, false);
770 EXPORT_SYMBOL(pci_disable_link_state
);
772 void pcie_clear_aspm(struct pci_bus
*bus
)
774 struct pci_dev
*child
;
777 * Clear any ASPM setup that the firmware has carried out on this bus
779 list_for_each_entry(child
, &bus
->devices
, bus_list
) {
780 __pci_disable_link_state(child
, PCIE_LINK_STATE_L0S
|
782 PCIE_LINK_STATE_CLKPM
,
787 static int pcie_aspm_set_policy(const char *val
, struct kernel_param
*kp
)
790 struct pcie_link_state
*link
;
794 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
795 if (!strncmp(val
, policy_str
[i
], strlen(policy_str
[i
])))
797 if (i
>= ARRAY_SIZE(policy_str
))
799 if (i
== aspm_policy
)
802 down_read(&pci_bus_sem
);
803 mutex_lock(&aspm_lock
);
805 list_for_each_entry(link
, &link_list
, sibling
) {
806 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
807 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
809 mutex_unlock(&aspm_lock
);
810 up_read(&pci_bus_sem
);
814 static int pcie_aspm_get_policy(char *buffer
, struct kernel_param
*kp
)
817 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
818 if (i
== aspm_policy
)
819 cnt
+= sprintf(buffer
+ cnt
, "[%s] ", policy_str
[i
]);
821 cnt
+= sprintf(buffer
+ cnt
, "%s ", policy_str
[i
]);
825 module_param_call(policy
, pcie_aspm_set_policy
, pcie_aspm_get_policy
,
828 #ifdef CONFIG_PCIEASPM_DEBUG
829 static ssize_t
link_state_show(struct device
*dev
,
830 struct device_attribute
*attr
,
833 struct pci_dev
*pci_device
= to_pci_dev(dev
);
834 struct pcie_link_state
*link_state
= pci_device
->link_state
;
836 return sprintf(buf
, "%d\n", link_state
->aspm_enabled
);
839 static ssize_t
link_state_store(struct device
*dev
,
840 struct device_attribute
*attr
,
844 struct pci_dev
*pdev
= to_pci_dev(dev
);
845 struct pcie_link_state
*link
, *root
= pdev
->link_state
->root
;
846 u32 val
= buf
[0] - '0', state
= 0;
850 if (n
< 1 || val
> 3)
853 /* Convert requested state to ASPM state */
854 if (val
& PCIE_LINK_STATE_L0S
)
855 state
|= ASPM_STATE_L0S
;
856 if (val
& PCIE_LINK_STATE_L1
)
857 state
|= ASPM_STATE_L1
;
859 down_read(&pci_bus_sem
);
860 mutex_lock(&aspm_lock
);
861 list_for_each_entry(link
, &link_list
, sibling
) {
862 if (link
->root
!= root
)
864 pcie_config_aspm_link(link
, state
);
866 mutex_unlock(&aspm_lock
);
867 up_read(&pci_bus_sem
);
871 static ssize_t
clk_ctl_show(struct device
*dev
,
872 struct device_attribute
*attr
,
875 struct pci_dev
*pci_device
= to_pci_dev(dev
);
876 struct pcie_link_state
*link_state
= pci_device
->link_state
;
878 return sprintf(buf
, "%d\n", link_state
->clkpm_enabled
);
881 static ssize_t
clk_ctl_store(struct device
*dev
,
882 struct device_attribute
*attr
,
886 struct pci_dev
*pdev
= to_pci_dev(dev
);
893 down_read(&pci_bus_sem
);
894 mutex_lock(&aspm_lock
);
895 pcie_set_clkpm_nocheck(pdev
->link_state
, !!state
);
896 mutex_unlock(&aspm_lock
);
897 up_read(&pci_bus_sem
);
902 static DEVICE_ATTR(link_state
, 0644, link_state_show
, link_state_store
);
903 static DEVICE_ATTR(clk_ctl
, 0644, clk_ctl_show
, clk_ctl_store
);
905 static char power_group
[] = "power";
906 void pcie_aspm_create_sysfs_dev_files(struct pci_dev
*pdev
)
908 struct pcie_link_state
*link_state
= pdev
->link_state
;
910 if (!pci_is_pcie(pdev
) ||
911 (pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
&&
912 pci_pcie_type(pdev
) != PCI_EXP_TYPE_DOWNSTREAM
) || !link_state
)
915 if (link_state
->aspm_support
)
916 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
917 &dev_attr_link_state
.attr
, power_group
);
918 if (link_state
->clkpm_capable
)
919 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
920 &dev_attr_clk_ctl
.attr
, power_group
);
923 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev
*pdev
)
925 struct pcie_link_state
*link_state
= pdev
->link_state
;
927 if (!pci_is_pcie(pdev
) ||
928 (pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
&&
929 pci_pcie_type(pdev
) != PCI_EXP_TYPE_DOWNSTREAM
) || !link_state
)
932 if (link_state
->aspm_support
)
933 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
934 &dev_attr_link_state
.attr
, power_group
);
935 if (link_state
->clkpm_capable
)
936 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
937 &dev_attr_clk_ctl
.attr
, power_group
);
941 static int __init
pcie_aspm_disable(char *str
)
943 if (!strcmp(str
, "off")) {
944 aspm_policy
= POLICY_DEFAULT
;
946 aspm_support_enabled
= false;
947 printk(KERN_INFO
"PCIe ASPM is disabled\n");
948 } else if (!strcmp(str
, "force")) {
950 printk(KERN_INFO
"PCIe ASPM is forcibly enabled\n");
955 __setup("pcie_aspm=", pcie_aspm_disable
);
957 void pcie_no_aspm(void)
960 * Disabling ASPM is intended to prevent the kernel from modifying
961 * existing hardware state, not to clear existing state. To that end:
962 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
963 * (b) prevent userspace from changing policy
966 aspm_policy
= POLICY_DEFAULT
;
972 * pcie_aspm_enabled - is PCIe ASPM enabled?
974 * Returns true if ASPM has not been disabled by the command-line option
977 int pcie_aspm_enabled(void)
979 return !aspm_disabled
;
981 EXPORT_SYMBOL(pcie_aspm_enabled
);
983 bool pcie_aspm_support_enabled(void)
985 return aspm_support_enabled
;
987 EXPORT_SYMBOL(pcie_aspm_support_enabled
);