2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
21 #include <linux/pci-aspm.h>
24 #ifdef MODULE_PARAM_PREFIX
25 #undef MODULE_PARAM_PREFIX
27 #define MODULE_PARAM_PREFIX "pcie_aspm."
29 /* Note: those are not register definitions */
30 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
31 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
32 #define ASPM_STATE_L1 (4) /* L1 state */
33 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
34 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
35 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
36 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
37 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
39 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
41 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
42 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
46 * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
47 * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
48 * Not sure is there is a way to "calculate" this on the fly, but maybe we
49 * could turn it into a parameter in future. This value has been taken from
50 * the following files from Intel's coreboot (which is the only code I found
52 * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
53 * https://review.coreboot.org/#/c/8832/
55 #define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
58 u32 l0s
; /* L0s latency (nsec) */
59 u32 l1
; /* L1 latency (nsec) */
62 struct pcie_link_state
{
63 struct pci_dev
*pdev
; /* Upstream component of the Link */
64 struct pci_dev
*downstream
; /* Downstream component, function 0 */
65 struct pcie_link_state
*root
; /* pointer to the root port link */
66 struct pcie_link_state
*parent
; /* pointer to the parent Link state */
67 struct list_head sibling
; /* node in link_list */
68 struct list_head children
; /* list of child link states */
69 struct list_head link
; /* node in parent's children list */
72 u32 aspm_support
:7; /* Supported ASPM state */
73 u32 aspm_enabled
:7; /* Enabled ASPM state */
74 u32 aspm_capable
:7; /* Capable ASPM state with latency */
75 u32 aspm_default
:7; /* Default ASPM state by BIOS */
76 u32 aspm_disable
:7; /* Disabled ASPM state */
79 u32 clkpm_capable
:1; /* Clock PM capable? */
80 u32 clkpm_enabled
:1; /* Current Clock PM state */
81 u32 clkpm_default
:1; /* Default Clock PM state by BIOS */
84 struct aspm_latency latency_up
; /* Upstream direction exit latency */
85 struct aspm_latency latency_dw
; /* Downstream direction exit latency */
87 * Endpoint acceptable latencies. A pcie downstream port only
88 * has one slot under it, so at most there are 8 functions.
90 struct aspm_latency acceptable
[8];
92 /* L1 PM Substate info */
94 u32 up_cap_ptr
; /* L1SS cap ptr in upstream dev */
95 u32 dw_cap_ptr
; /* L1SS cap ptr in downstream dev */
96 u32 ctl1
; /* value to be programmed in ctl1 */
97 u32 ctl2
; /* value to be programmed in ctl2 */
101 static int aspm_disabled
, aspm_force
;
102 static bool aspm_support_enabled
= true;
103 static DEFINE_MUTEX(aspm_lock
);
104 static LIST_HEAD(link_list
);
106 #define POLICY_DEFAULT 0 /* BIOS default setting */
107 #define POLICY_PERFORMANCE 1 /* high performance */
108 #define POLICY_POWERSAVE 2 /* high power saving */
109 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
111 #ifdef CONFIG_PCIEASPM_PERFORMANCE
112 static int aspm_policy
= POLICY_PERFORMANCE
;
113 #elif defined CONFIG_PCIEASPM_POWERSAVE
114 static int aspm_policy
= POLICY_POWERSAVE
;
115 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
116 static int aspm_policy
= POLICY_POWER_SUPERSAVE
;
118 static int aspm_policy
;
121 static const char *policy_str
[] = {
122 [POLICY_DEFAULT
] = "default",
123 [POLICY_PERFORMANCE
] = "performance",
124 [POLICY_POWERSAVE
] = "powersave",
125 [POLICY_POWER_SUPERSAVE
] = "powersupersave"
128 #define LINK_RETRAIN_TIMEOUT HZ
130 static int policy_to_aspm_state(struct pcie_link_state
*link
)
132 switch (aspm_policy
) {
133 case POLICY_PERFORMANCE
:
134 /* Disable ASPM and Clock PM */
136 case POLICY_POWERSAVE
:
137 /* Enable ASPM L0s/L1 */
138 return (ASPM_STATE_L0S
| ASPM_STATE_L1
);
139 case POLICY_POWER_SUPERSAVE
:
140 /* Enable Everything */
141 return ASPM_STATE_ALL
;
143 return link
->aspm_default
;
148 static int policy_to_clkpm_state(struct pcie_link_state
*link
)
150 switch (aspm_policy
) {
151 case POLICY_PERFORMANCE
:
152 /* Disable ASPM and Clock PM */
154 case POLICY_POWERSAVE
:
155 case POLICY_POWER_SUPERSAVE
:
156 /* Enable Clock PM */
159 return link
->clkpm_default
;
164 static void pcie_set_clkpm_nocheck(struct pcie_link_state
*link
, int enable
)
166 struct pci_dev
*child
;
167 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
168 u32 val
= enable
? PCI_EXP_LNKCTL_CLKREQ_EN
: 0;
170 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
171 pcie_capability_clear_and_set_word(child
, PCI_EXP_LNKCTL
,
172 PCI_EXP_LNKCTL_CLKREQ_EN
,
174 link
->clkpm_enabled
= !!enable
;
177 static void pcie_set_clkpm(struct pcie_link_state
*link
, int enable
)
179 /* Don't enable Clock PM if the link is not Clock PM capable */
180 if (!link
->clkpm_capable
)
182 /* Need nothing if the specified equals to current state */
183 if (link
->clkpm_enabled
== enable
)
185 pcie_set_clkpm_nocheck(link
, enable
);
188 static void pcie_clkpm_cap_init(struct pcie_link_state
*link
, int blacklist
)
190 int capable
= 1, enabled
= 1;
193 struct pci_dev
*child
;
194 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
196 /* All functions should have the same cap and state, take the worst */
197 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
198 pcie_capability_read_dword(child
, PCI_EXP_LNKCAP
, ®32
);
199 if (!(reg32
& PCI_EXP_LNKCAP_CLKPM
)) {
204 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
205 if (!(reg16
& PCI_EXP_LNKCTL_CLKREQ_EN
))
208 link
->clkpm_enabled
= enabled
;
209 link
->clkpm_default
= enabled
;
210 link
->clkpm_capable
= (blacklist
) ? 0 : capable
;
214 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
215 * could use common clock. If they are, configure them to use the
216 * common clock. That will reduce the ASPM state exit latency.
218 static void pcie_aspm_configure_common_clock(struct pcie_link_state
*link
)
221 u16 reg16
, parent_reg
, child_reg
[8];
222 unsigned long start_jiffies
;
223 struct pci_dev
*child
, *parent
= link
->pdev
;
224 struct pci_bus
*linkbus
= parent
->subordinate
;
226 * All functions of a slot should have the same Slot Clock
227 * Configuration, so just check one function
229 child
= list_entry(linkbus
->devices
.next
, struct pci_dev
, bus_list
);
230 BUG_ON(!pci_is_pcie(child
));
232 /* Check downstream component if bit Slot Clock Configuration is 1 */
233 pcie_capability_read_word(child
, PCI_EXP_LNKSTA
, ®16
);
234 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
237 /* Check upstream component if bit Slot Clock Configuration is 1 */
238 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
239 if (!(reg16
& PCI_EXP_LNKSTA_SLC
))
242 /* Configure downstream component, all functions */
243 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
244 pcie_capability_read_word(child
, PCI_EXP_LNKCTL
, ®16
);
245 child_reg
[PCI_FUNC(child
->devfn
)] = reg16
;
247 reg16
|= PCI_EXP_LNKCTL_CCC
;
249 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
250 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
, reg16
);
253 /* Configure upstream component */
254 pcie_capability_read_word(parent
, PCI_EXP_LNKCTL
, ®16
);
257 reg16
|= PCI_EXP_LNKCTL_CCC
;
259 reg16
&= ~PCI_EXP_LNKCTL_CCC
;
260 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
263 reg16
|= PCI_EXP_LNKCTL_RL
;
264 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, reg16
);
266 /* Wait for link training end. Break out after waiting for timeout */
267 start_jiffies
= jiffies
;
269 pcie_capability_read_word(parent
, PCI_EXP_LNKSTA
, ®16
);
270 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
272 if (time_after(jiffies
, start_jiffies
+ LINK_RETRAIN_TIMEOUT
))
276 if (!(reg16
& PCI_EXP_LNKSTA_LT
))
279 /* Training failed. Restore common clock configurations */
280 dev_err(&parent
->dev
, "ASPM: Could not configure common clock\n");
281 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
282 pcie_capability_write_word(child
, PCI_EXP_LNKCTL
,
283 child_reg
[PCI_FUNC(child
->devfn
)]);
284 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL
, parent_reg
);
287 /* Convert L0s latency encoding to ns */
288 static u32
calc_l0s_latency(u32 encoding
)
291 return (5 * 1000); /* > 4us */
292 return (64 << encoding
);
295 /* Convert L0s acceptable latency encoding to ns */
296 static u32
calc_l0s_acceptable(u32 encoding
)
300 return (64 << encoding
);
303 /* Convert L1 latency encoding to ns */
304 static u32
calc_l1_latency(u32 encoding
)
307 return (65 * 1000); /* > 64us */
308 return (1000 << encoding
);
311 /* Convert L1 acceptable latency encoding to ns */
312 static u32
calc_l1_acceptable(u32 encoding
)
316 return (1000 << encoding
);
319 /* Convert L1SS T_pwr encoding to usec */
320 static u32
calc_l1ss_pwron(struct pci_dev
*pdev
, u32 scale
, u32 val
)
330 dev_err(&pdev
->dev
, "%s: Invalid T_PwrOn scale: %u\n",
335 struct aspm_register_info
{
338 u32 latency_encoding_l0s
;
339 u32 latency_encoding_l1
;
348 static void pcie_get_aspm_reg(struct pci_dev
*pdev
,
349 struct aspm_register_info
*info
)
354 pcie_capability_read_dword(pdev
, PCI_EXP_LNKCAP
, ®32
);
355 info
->support
= (reg32
& PCI_EXP_LNKCAP_ASPMS
) >> 10;
356 info
->latency_encoding_l0s
= (reg32
& PCI_EXP_LNKCAP_L0SEL
) >> 12;
357 info
->latency_encoding_l1
= (reg32
& PCI_EXP_LNKCAP_L1EL
) >> 15;
358 pcie_capability_read_word(pdev
, PCI_EXP_LNKCTL
, ®16
);
359 info
->enabled
= reg16
& PCI_EXP_LNKCTL_ASPMC
;
361 /* Read L1 PM substate capabilities */
362 info
->l1ss_cap
= info
->l1ss_ctl1
= info
->l1ss_ctl2
= 0;
363 info
->l1ss_cap_ptr
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_L1SS
);
364 if (!info
->l1ss_cap_ptr
)
366 pci_read_config_dword(pdev
, info
->l1ss_cap_ptr
+ PCI_L1SS_CAP
,
368 if (!(info
->l1ss_cap
& PCI_L1SS_CAP_L1_PM_SS
)) {
372 pci_read_config_dword(pdev
, info
->l1ss_cap_ptr
+ PCI_L1SS_CTL1
,
374 pci_read_config_dword(pdev
, info
->l1ss_cap_ptr
+ PCI_L1SS_CTL2
,
378 static void pcie_aspm_check_latency(struct pci_dev
*endpoint
)
380 u32 latency
, l1_switch_latency
= 0;
381 struct aspm_latency
*acceptable
;
382 struct pcie_link_state
*link
;
384 /* Device not in D0 doesn't need latency check */
385 if ((endpoint
->current_state
!= PCI_D0
) &&
386 (endpoint
->current_state
!= PCI_UNKNOWN
))
389 link
= endpoint
->bus
->self
->link_state
;
390 acceptable
= &link
->acceptable
[PCI_FUNC(endpoint
->devfn
)];
393 /* Check upstream direction L0s latency */
394 if ((link
->aspm_capable
& ASPM_STATE_L0S_UP
) &&
395 (link
->latency_up
.l0s
> acceptable
->l0s
))
396 link
->aspm_capable
&= ~ASPM_STATE_L0S_UP
;
398 /* Check downstream direction L0s latency */
399 if ((link
->aspm_capable
& ASPM_STATE_L0S_DW
) &&
400 (link
->latency_dw
.l0s
> acceptable
->l0s
))
401 link
->aspm_capable
&= ~ASPM_STATE_L0S_DW
;
404 * Every switch on the path to root complex need 1
405 * more microsecond for L1. Spec doesn't mention L0s.
407 * The exit latencies for L1 substates are not advertised
408 * by a device. Since the spec also doesn't mention a way
409 * to determine max latencies introduced by enabling L1
410 * substates on the components, it is not clear how to do
411 * a L1 substate exit latency check. We assume that the
412 * L1 exit latencies advertised by a device include L1
413 * substate latencies (and hence do not do any check).
415 latency
= max_t(u32
, link
->latency_up
.l1
, link
->latency_dw
.l1
);
416 if ((link
->aspm_capable
& ASPM_STATE_L1
) &&
417 (latency
+ l1_switch_latency
> acceptable
->l1
))
418 link
->aspm_capable
&= ~ASPM_STATE_L1
;
419 l1_switch_latency
+= 1000;
426 * The L1 PM substate capability is only implemented in function 0 in a
427 * multi function device.
429 static struct pci_dev
*pci_function_0(struct pci_bus
*linkbus
)
431 struct pci_dev
*child
;
433 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
434 if (PCI_FUNC(child
->devfn
) == 0)
439 /* Calculate L1.2 PM substate timing parameters */
440 static void aspm_calc_l1ss_info(struct pcie_link_state
*link
,
441 struct aspm_register_info
*upreg
,
442 struct aspm_register_info
*dwreg
)
444 u32 val1
, val2
, scale1
, scale2
;
446 link
->l1ss
.up_cap_ptr
= upreg
->l1ss_cap_ptr
;
447 link
->l1ss
.dw_cap_ptr
= dwreg
->l1ss_cap_ptr
;
448 link
->l1ss
.ctl1
= link
->l1ss
.ctl2
= 0;
450 if (!(link
->aspm_support
& ASPM_STATE_L1_2_MASK
))
453 /* Choose the greater of the two T_cmn_mode_rstr_time */
454 val1
= (upreg
->l1ss_cap
>> 8) & 0xFF;
455 val2
= (upreg
->l1ss_cap
>> 8) & 0xFF;
457 link
->l1ss
.ctl1
|= val1
<< 8;
459 link
->l1ss
.ctl1
|= val2
<< 8;
461 * We currently use LTR L1.2 threshold to be fixed constant picked from
464 link
->l1ss
.ctl1
|= LTR_L1_2_THRESHOLD_BITS
;
466 /* Choose the greater of the two T_pwr_on */
467 val1
= (upreg
->l1ss_cap
>> 19) & 0x1F;
468 scale1
= (upreg
->l1ss_cap
>> 16) & 0x03;
469 val2
= (dwreg
->l1ss_cap
>> 19) & 0x1F;
470 scale2
= (dwreg
->l1ss_cap
>> 16) & 0x03;
472 if (calc_l1ss_pwron(link
->pdev
, scale1
, val1
) >
473 calc_l1ss_pwron(link
->downstream
, scale2
, val2
))
474 link
->l1ss
.ctl2
|= scale1
| (val1
<< 3);
476 link
->l1ss
.ctl2
|= scale2
| (val2
<< 3);
479 static void pcie_aspm_cap_init(struct pcie_link_state
*link
, int blacklist
)
481 struct pci_dev
*child
, *parent
= link
->pdev
;
482 struct pci_bus
*linkbus
= parent
->subordinate
;
483 struct aspm_register_info upreg
, dwreg
;
486 /* Set enabled/disable so that we will disable ASPM later */
487 link
->aspm_enabled
= ASPM_STATE_ALL
;
488 link
->aspm_disable
= ASPM_STATE_ALL
;
492 /* Get upstream/downstream components' register state */
493 pcie_get_aspm_reg(parent
, &upreg
);
494 child
= pci_function_0(linkbus
);
495 pcie_get_aspm_reg(child
, &dwreg
);
496 link
->downstream
= child
;
499 * If ASPM not supported, don't mess with the clocks and link,
502 if (!(upreg
.support
& dwreg
.support
))
505 /* Configure common clock before checking latencies */
506 pcie_aspm_configure_common_clock(link
);
509 * Re-read upstream/downstream components' register state
510 * after clock configuration
512 pcie_get_aspm_reg(parent
, &upreg
);
513 pcie_get_aspm_reg(child
, &dwreg
);
518 * Note that we must not enable L0s in either direction on a
519 * given link unless components on both sides of the link each
522 if (dwreg
.support
& upreg
.support
& PCIE_LINK_STATE_L0S
)
523 link
->aspm_support
|= ASPM_STATE_L0S
;
524 if (dwreg
.enabled
& PCIE_LINK_STATE_L0S
)
525 link
->aspm_enabled
|= ASPM_STATE_L0S_UP
;
526 if (upreg
.enabled
& PCIE_LINK_STATE_L0S
)
527 link
->aspm_enabled
|= ASPM_STATE_L0S_DW
;
528 link
->latency_up
.l0s
= calc_l0s_latency(upreg
.latency_encoding_l0s
);
529 link
->latency_dw
.l0s
= calc_l0s_latency(dwreg
.latency_encoding_l0s
);
532 if (upreg
.support
& dwreg
.support
& PCIE_LINK_STATE_L1
)
533 link
->aspm_support
|= ASPM_STATE_L1
;
534 if (upreg
.enabled
& dwreg
.enabled
& PCIE_LINK_STATE_L1
)
535 link
->aspm_enabled
|= ASPM_STATE_L1
;
536 link
->latency_up
.l1
= calc_l1_latency(upreg
.latency_encoding_l1
);
537 link
->latency_dw
.l1
= calc_l1_latency(dwreg
.latency_encoding_l1
);
539 /* Setup L1 substate */
540 if (upreg
.l1ss_cap
& dwreg
.l1ss_cap
& PCI_L1SS_CAP_ASPM_L1_1
)
541 link
->aspm_support
|= ASPM_STATE_L1_1
;
542 if (upreg
.l1ss_cap
& dwreg
.l1ss_cap
& PCI_L1SS_CAP_ASPM_L1_2
)
543 link
->aspm_support
|= ASPM_STATE_L1_2
;
544 if (upreg
.l1ss_cap
& dwreg
.l1ss_cap
& PCI_L1SS_CAP_PCIPM_L1_1
)
545 link
->aspm_support
|= ASPM_STATE_L1_1_PCIPM
;
546 if (upreg
.l1ss_cap
& dwreg
.l1ss_cap
& PCI_L1SS_CAP_PCIPM_L1_2
)
547 link
->aspm_support
|= ASPM_STATE_L1_2_PCIPM
;
549 if (upreg
.l1ss_ctl1
& dwreg
.l1ss_ctl1
& PCI_L1SS_CTL1_ASPM_L1_1
)
550 link
->aspm_enabled
|= ASPM_STATE_L1_1
;
551 if (upreg
.l1ss_ctl1
& dwreg
.l1ss_ctl1
& PCI_L1SS_CTL1_ASPM_L1_2
)
552 link
->aspm_enabled
|= ASPM_STATE_L1_2
;
553 if (upreg
.l1ss_ctl1
& dwreg
.l1ss_ctl1
& PCI_L1SS_CTL1_PCIPM_L1_1
)
554 link
->aspm_enabled
|= ASPM_STATE_L1_1_PCIPM
;
555 if (upreg
.l1ss_ctl1
& dwreg
.l1ss_ctl1
& PCI_L1SS_CTL1_PCIPM_L1_2
)
556 link
->aspm_enabled
|= ASPM_STATE_L1_2_PCIPM
;
558 if (link
->aspm_support
& ASPM_STATE_L1SS
)
559 aspm_calc_l1ss_info(link
, &upreg
, &dwreg
);
561 /* Save default state */
562 link
->aspm_default
= link
->aspm_enabled
;
564 /* Setup initial capable state. Will be updated later */
565 link
->aspm_capable
= link
->aspm_support
;
567 * If the downstream component has pci bridge function, don't
570 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
571 if (pci_pcie_type(child
) == PCI_EXP_TYPE_PCI_BRIDGE
) {
572 link
->aspm_disable
= ASPM_STATE_ALL
;
577 /* Get and check endpoint acceptable latencies */
578 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
580 struct aspm_latency
*acceptable
=
581 &link
->acceptable
[PCI_FUNC(child
->devfn
)];
583 if (pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
&&
584 pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
)
587 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
588 /* Calculate endpoint L0s acceptable latency */
589 encoding
= (reg32
& PCI_EXP_DEVCAP_L0S
) >> 6;
590 acceptable
->l0s
= calc_l0s_acceptable(encoding
);
591 /* Calculate endpoint L1 acceptable latency */
592 encoding
= (reg32
& PCI_EXP_DEVCAP_L1
) >> 9;
593 acceptable
->l1
= calc_l1_acceptable(encoding
);
595 pcie_aspm_check_latency(child
);
599 static void pci_clear_and_set_dword(struct pci_dev
*pdev
, int pos
,
604 pci_read_config_dword(pdev
, pos
, &val
);
607 pci_write_config_dword(pdev
, pos
, val
);
610 /* Configure the ASPM L1 substates */
611 static void pcie_config_aspm_l1ss(struct pcie_link_state
*link
, u32 state
)
614 struct pci_dev
*child
= link
->downstream
, *parent
= link
->pdev
;
615 u32 up_cap_ptr
= link
->l1ss
.up_cap_ptr
;
616 u32 dw_cap_ptr
= link
->l1ss
.dw_cap_ptr
;
618 enable_req
= (link
->aspm_enabled
^ state
) & state
;
621 * Here are the rules specified in the PCIe spec for enabling L1SS:
622 * - When enabling L1.x, enable bit at parent first, then at child
623 * - When disabling L1.x, disable bit at child first, then at parent
624 * - When enabling ASPM L1.x, need to disable L1
625 * (at child followed by parent).
626 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
629 * To keep it simple, disable all L1SS bits first, and later enable
633 /* Disable all L1 substates */
634 pci_clear_and_set_dword(child
, dw_cap_ptr
+ PCI_L1SS_CTL1
,
635 PCI_L1SS_CTL1_L1SS_MASK
, 0);
636 pci_clear_and_set_dword(parent
, up_cap_ptr
+ PCI_L1SS_CTL1
,
637 PCI_L1SS_CTL1_L1SS_MASK
, 0);
639 * If needed, disable L1, and it gets enabled later
640 * in pcie_config_aspm_link().
642 if (enable_req
& (ASPM_STATE_L1_1
| ASPM_STATE_L1_2
)) {
643 pcie_capability_clear_and_set_word(child
, PCI_EXP_LNKCTL
,
644 PCI_EXP_LNKCTL_ASPM_L1
, 0);
645 pcie_capability_clear_and_set_word(parent
, PCI_EXP_LNKCTL
,
646 PCI_EXP_LNKCTL_ASPM_L1
, 0);
649 if (enable_req
& ASPM_STATE_L1_2_MASK
) {
651 /* Program T_pwr_on in both ports */
652 pci_write_config_dword(parent
, up_cap_ptr
+ PCI_L1SS_CTL2
,
654 pci_write_config_dword(child
, dw_cap_ptr
+ PCI_L1SS_CTL2
,
657 /* Program T_cmn_mode in parent */
658 pci_clear_and_set_dword(parent
, up_cap_ptr
+ PCI_L1SS_CTL1
,
659 0xFF00, link
->l1ss
.ctl1
);
661 /* Program LTR L1.2 threshold in both ports */
662 pci_clear_and_set_dword(parent
, dw_cap_ptr
+ PCI_L1SS_CTL1
,
663 0xE3FF0000, link
->l1ss
.ctl1
);
664 pci_clear_and_set_dword(child
, dw_cap_ptr
+ PCI_L1SS_CTL1
,
665 0xE3FF0000, link
->l1ss
.ctl1
);
669 if (state
& ASPM_STATE_L1_1
)
670 val
|= PCI_L1SS_CTL1_ASPM_L1_1
;
671 if (state
& ASPM_STATE_L1_2
)
672 val
|= PCI_L1SS_CTL1_ASPM_L1_2
;
673 if (state
& ASPM_STATE_L1_1_PCIPM
)
674 val
|= PCI_L1SS_CTL1_PCIPM_L1_1
;
675 if (state
& ASPM_STATE_L1_2_PCIPM
)
676 val
|= PCI_L1SS_CTL1_PCIPM_L1_2
;
678 /* Enable what we need to enable */
679 pci_clear_and_set_dword(parent
, up_cap_ptr
+ PCI_L1SS_CTL1
,
680 PCI_L1SS_CAP_L1_PM_SS
, val
);
681 pci_clear_and_set_dword(child
, dw_cap_ptr
+ PCI_L1SS_CTL1
,
682 PCI_L1SS_CAP_L1_PM_SS
, val
);
685 static void pcie_config_aspm_dev(struct pci_dev
*pdev
, u32 val
)
687 pcie_capability_clear_and_set_word(pdev
, PCI_EXP_LNKCTL
,
688 PCI_EXP_LNKCTL_ASPMC
, val
);
691 static void pcie_config_aspm_link(struct pcie_link_state
*link
, u32 state
)
693 u32 upstream
= 0, dwstream
= 0;
694 struct pci_dev
*child
= link
->downstream
, *parent
= link
->pdev
;
695 struct pci_bus
*linkbus
= parent
->subordinate
;
697 /* Enable only the states that were not explicitly disabled */
698 state
&= (link
->aspm_capable
& ~link
->aspm_disable
);
700 /* Can't enable any substates if L1 is not enabled */
701 if (!(state
& ASPM_STATE_L1
))
702 state
&= ~ASPM_STATE_L1SS
;
704 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
705 if (parent
->current_state
!= PCI_D0
|| child
->current_state
!= PCI_D0
) {
706 state
&= ~ASPM_STATE_L1_SS_PCIPM
;
707 state
|= (link
->aspm_enabled
& ASPM_STATE_L1_SS_PCIPM
);
710 /* Nothing to do if the link is already in the requested state */
711 if (link
->aspm_enabled
== state
)
713 /* Convert ASPM state to upstream/downstream ASPM register state */
714 if (state
& ASPM_STATE_L0S_UP
)
715 dwstream
|= PCI_EXP_LNKCTL_ASPM_L0S
;
716 if (state
& ASPM_STATE_L0S_DW
)
717 upstream
|= PCI_EXP_LNKCTL_ASPM_L0S
;
718 if (state
& ASPM_STATE_L1
) {
719 upstream
|= PCI_EXP_LNKCTL_ASPM_L1
;
720 dwstream
|= PCI_EXP_LNKCTL_ASPM_L1
;
723 if (link
->aspm_capable
& ASPM_STATE_L1SS
)
724 pcie_config_aspm_l1ss(link
, state
);
727 * Spec 2.0 suggests all functions should be configured the
728 * same setting for ASPM. Enabling ASPM L1 should be done in
729 * upstream component first and then downstream, and vice
730 * versa for disabling ASPM L1. Spec doesn't mention L0S.
732 if (state
& ASPM_STATE_L1
)
733 pcie_config_aspm_dev(parent
, upstream
);
734 list_for_each_entry(child
, &linkbus
->devices
, bus_list
)
735 pcie_config_aspm_dev(child
, dwstream
);
736 if (!(state
& ASPM_STATE_L1
))
737 pcie_config_aspm_dev(parent
, upstream
);
739 link
->aspm_enabled
= state
;
742 static void pcie_config_aspm_path(struct pcie_link_state
*link
)
745 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
750 static void free_link_state(struct pcie_link_state
*link
)
752 link
->pdev
->link_state
= NULL
;
756 static int pcie_aspm_sanity_check(struct pci_dev
*pdev
)
758 struct pci_dev
*child
;
762 * Some functions in a slot might not all be PCIe functions,
763 * very strange. Disable ASPM for the whole slot
765 list_for_each_entry(child
, &pdev
->subordinate
->devices
, bus_list
) {
766 if (!pci_is_pcie(child
))
770 * If ASPM is disabled then we're not going to change
771 * the BIOS state. It's safe to continue even if it's a
779 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
780 * RBER bit to determine if a function is 1.1 version device
782 pcie_capability_read_dword(child
, PCI_EXP_DEVCAP
, ®32
);
783 if (!(reg32
& PCI_EXP_DEVCAP_RBER
) && !aspm_force
) {
784 dev_info(&child
->dev
, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
791 static struct pcie_link_state
*alloc_pcie_link_state(struct pci_dev
*pdev
)
793 struct pcie_link_state
*link
;
795 link
= kzalloc(sizeof(*link
), GFP_KERNEL
);
798 INIT_LIST_HEAD(&link
->sibling
);
799 INIT_LIST_HEAD(&link
->children
);
800 INIT_LIST_HEAD(&link
->link
);
802 if (pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
) {
803 struct pcie_link_state
*parent
;
804 parent
= pdev
->bus
->parent
->self
->link_state
;
809 link
->parent
= parent
;
810 list_add(&link
->link
, &parent
->children
);
812 /* Setup a pointer to the root port link */
816 link
->root
= link
->parent
->root
;
818 list_add(&link
->sibling
, &link_list
);
819 pdev
->link_state
= link
;
824 * pcie_aspm_init_link_state: Initiate PCI express link state.
825 * It is called after the pcie and its children devices are scanned.
826 * @pdev: the root port or switch downstream port
828 void pcie_aspm_init_link_state(struct pci_dev
*pdev
)
830 struct pcie_link_state
*link
;
831 int blacklist
= !!pcie_aspm_sanity_check(pdev
);
833 if (!aspm_support_enabled
)
836 if (pdev
->link_state
)
840 * We allocate pcie_link_state for the component on the upstream
841 * end of a Link, so there's nothing to do unless this device has a
842 * Link on its secondary side.
844 if (!pdev
->has_secondary_link
)
847 /* VIA has a strange chipset, root port is under a bridge */
848 if (pci_pcie_type(pdev
) == PCI_EXP_TYPE_ROOT_PORT
&&
852 down_read(&pci_bus_sem
);
853 if (list_empty(&pdev
->subordinate
->devices
))
856 mutex_lock(&aspm_lock
);
857 link
= alloc_pcie_link_state(pdev
);
861 * Setup initial ASPM state. Note that we need to configure
862 * upstream links also because capable state of them can be
863 * update through pcie_aspm_cap_init().
865 pcie_aspm_cap_init(link
, blacklist
);
867 /* Setup initial Clock PM state */
868 pcie_clkpm_cap_init(link
, blacklist
);
871 * At this stage drivers haven't had an opportunity to change the
872 * link policy setting. Enabling ASPM on broken hardware can cripple
873 * it even before the driver has had a chance to disable ASPM, so
874 * default to a safe level right now. If we're enabling ASPM beyond
875 * the BIOS's expectation, we'll do so once pci_enable_device() is
878 if (aspm_policy
!= POLICY_POWERSAVE
&&
879 aspm_policy
!= POLICY_POWER_SUPERSAVE
) {
880 pcie_config_aspm_path(link
);
881 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
885 mutex_unlock(&aspm_lock
);
887 up_read(&pci_bus_sem
);
890 /* Recheck latencies and update aspm_capable for links under the root */
891 static void pcie_update_aspm_capable(struct pcie_link_state
*root
)
893 struct pcie_link_state
*link
;
894 BUG_ON(root
->parent
);
895 list_for_each_entry(link
, &link_list
, sibling
) {
896 if (link
->root
!= root
)
898 link
->aspm_capable
= link
->aspm_support
;
900 list_for_each_entry(link
, &link_list
, sibling
) {
901 struct pci_dev
*child
;
902 struct pci_bus
*linkbus
= link
->pdev
->subordinate
;
903 if (link
->root
!= root
)
905 list_for_each_entry(child
, &linkbus
->devices
, bus_list
) {
906 if ((pci_pcie_type(child
) != PCI_EXP_TYPE_ENDPOINT
) &&
907 (pci_pcie_type(child
) != PCI_EXP_TYPE_LEG_END
))
909 pcie_aspm_check_latency(child
);
914 /* @pdev: the endpoint device */
915 void pcie_aspm_exit_link_state(struct pci_dev
*pdev
)
917 struct pci_dev
*parent
= pdev
->bus
->self
;
918 struct pcie_link_state
*link
, *root
, *parent_link
;
920 if (!parent
|| !parent
->link_state
)
923 down_read(&pci_bus_sem
);
924 mutex_lock(&aspm_lock
);
926 * All PCIe functions are in one slot, remove one function will remove
927 * the whole slot, so just wait until we are the last function left.
929 if (!list_is_last(&pdev
->bus_list
, &parent
->subordinate
->devices
))
932 link
= parent
->link_state
;
934 parent_link
= link
->parent
;
936 /* All functions are removed, so just disable ASPM for the link */
937 pcie_config_aspm_link(link
, 0);
938 list_del(&link
->sibling
);
939 list_del(&link
->link
);
940 /* Clock PM is for endpoint device */
941 free_link_state(link
);
943 /* Recheck latencies and configure upstream links */
945 pcie_update_aspm_capable(root
);
946 pcie_config_aspm_path(parent_link
);
949 mutex_unlock(&aspm_lock
);
950 up_read(&pci_bus_sem
);
953 /* @pdev: the root port or switch downstream port */
954 void pcie_aspm_pm_state_change(struct pci_dev
*pdev
)
956 struct pcie_link_state
*link
= pdev
->link_state
;
958 if (aspm_disabled
|| !link
)
961 * Devices changed PM state, we should recheck if latency
962 * meets all functions' requirement
964 down_read(&pci_bus_sem
);
965 mutex_lock(&aspm_lock
);
966 pcie_update_aspm_capable(link
->root
);
967 pcie_config_aspm_path(link
);
968 mutex_unlock(&aspm_lock
);
969 up_read(&pci_bus_sem
);
972 void pcie_aspm_powersave_config_link(struct pci_dev
*pdev
)
974 struct pcie_link_state
*link
= pdev
->link_state
;
976 if (aspm_disabled
|| !link
)
979 if (aspm_policy
!= POLICY_POWERSAVE
&&
980 aspm_policy
!= POLICY_POWER_SUPERSAVE
)
983 down_read(&pci_bus_sem
);
984 mutex_lock(&aspm_lock
);
985 pcie_config_aspm_path(link
);
986 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
987 mutex_unlock(&aspm_lock
);
988 up_read(&pci_bus_sem
);
991 static void __pci_disable_link_state(struct pci_dev
*pdev
, int state
, bool sem
)
993 struct pci_dev
*parent
= pdev
->bus
->self
;
994 struct pcie_link_state
*link
;
996 if (!pci_is_pcie(pdev
))
999 if (pdev
->has_secondary_link
)
1001 if (!parent
|| !parent
->link_state
)
1005 * A driver requested that ASPM be disabled on this device, but
1006 * if we don't have permission to manage ASPM (e.g., on ACPI
1007 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1008 * the _OSC method), we can't honor that request. Windows has
1009 * a similar mechanism using "PciASPMOptOut", which is also
1010 * ignored in this situation.
1012 if (aspm_disabled
) {
1013 dev_warn(&pdev
->dev
, "can't disable ASPM; OS doesn't have ASPM control\n");
1018 down_read(&pci_bus_sem
);
1019 mutex_lock(&aspm_lock
);
1020 link
= parent
->link_state
;
1021 if (state
& PCIE_LINK_STATE_L0S
)
1022 link
->aspm_disable
|= ASPM_STATE_L0S
;
1023 if (state
& PCIE_LINK_STATE_L1
)
1024 link
->aspm_disable
|= ASPM_STATE_L1
;
1025 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
1027 if (state
& PCIE_LINK_STATE_CLKPM
) {
1028 link
->clkpm_capable
= 0;
1029 pcie_set_clkpm(link
, 0);
1031 mutex_unlock(&aspm_lock
);
1033 up_read(&pci_bus_sem
);
1036 void pci_disable_link_state_locked(struct pci_dev
*pdev
, int state
)
1038 __pci_disable_link_state(pdev
, state
, false);
1040 EXPORT_SYMBOL(pci_disable_link_state_locked
);
1043 * pci_disable_link_state - Disable device's link state, so the link will
1044 * never enter specific states. Note that if the BIOS didn't grant ASPM
1045 * control to the OS, this does nothing because we can't touch the LNKCTL
1049 * @state: ASPM link state to disable
1051 void pci_disable_link_state(struct pci_dev
*pdev
, int state
)
1053 __pci_disable_link_state(pdev
, state
, true);
1055 EXPORT_SYMBOL(pci_disable_link_state
);
1057 static int pcie_aspm_set_policy(const char *val
, struct kernel_param
*kp
)
1060 struct pcie_link_state
*link
;
1064 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
1065 if (!strncmp(val
, policy_str
[i
], strlen(policy_str
[i
])))
1067 if (i
>= ARRAY_SIZE(policy_str
))
1069 if (i
== aspm_policy
)
1072 down_read(&pci_bus_sem
);
1073 mutex_lock(&aspm_lock
);
1075 list_for_each_entry(link
, &link_list
, sibling
) {
1076 pcie_config_aspm_link(link
, policy_to_aspm_state(link
));
1077 pcie_set_clkpm(link
, policy_to_clkpm_state(link
));
1079 mutex_unlock(&aspm_lock
);
1080 up_read(&pci_bus_sem
);
1084 static int pcie_aspm_get_policy(char *buffer
, struct kernel_param
*kp
)
1087 for (i
= 0; i
< ARRAY_SIZE(policy_str
); i
++)
1088 if (i
== aspm_policy
)
1089 cnt
+= sprintf(buffer
+ cnt
, "[%s] ", policy_str
[i
]);
1091 cnt
+= sprintf(buffer
+ cnt
, "%s ", policy_str
[i
]);
1095 module_param_call(policy
, pcie_aspm_set_policy
, pcie_aspm_get_policy
,
1098 #ifdef CONFIG_PCIEASPM_DEBUG
1099 static ssize_t
link_state_show(struct device
*dev
,
1100 struct device_attribute
*attr
,
1103 struct pci_dev
*pci_device
= to_pci_dev(dev
);
1104 struct pcie_link_state
*link_state
= pci_device
->link_state
;
1106 return sprintf(buf
, "%d\n", link_state
->aspm_enabled
);
1109 static ssize_t
link_state_store(struct device
*dev
,
1110 struct device_attribute
*attr
,
1114 struct pci_dev
*pdev
= to_pci_dev(dev
);
1115 struct pcie_link_state
*link
, *root
= pdev
->link_state
->root
;
1121 if (kstrtouint(buf
, 10, &state
))
1123 if ((state
& ~ASPM_STATE_ALL
) != 0)
1126 down_read(&pci_bus_sem
);
1127 mutex_lock(&aspm_lock
);
1128 list_for_each_entry(link
, &link_list
, sibling
) {
1129 if (link
->root
!= root
)
1131 pcie_config_aspm_link(link
, state
);
1133 mutex_unlock(&aspm_lock
);
1134 up_read(&pci_bus_sem
);
1138 static ssize_t
clk_ctl_show(struct device
*dev
,
1139 struct device_attribute
*attr
,
1142 struct pci_dev
*pci_device
= to_pci_dev(dev
);
1143 struct pcie_link_state
*link_state
= pci_device
->link_state
;
1145 return sprintf(buf
, "%d\n", link_state
->clkpm_enabled
);
1148 static ssize_t
clk_ctl_store(struct device
*dev
,
1149 struct device_attribute
*attr
,
1153 struct pci_dev
*pdev
= to_pci_dev(dev
);
1156 if (strtobool(buf
, &state
))
1159 down_read(&pci_bus_sem
);
1160 mutex_lock(&aspm_lock
);
1161 pcie_set_clkpm_nocheck(pdev
->link_state
, state
);
1162 mutex_unlock(&aspm_lock
);
1163 up_read(&pci_bus_sem
);
1168 static DEVICE_ATTR_RW(link_state
);
1169 static DEVICE_ATTR_RW(clk_ctl
);
1171 static char power_group
[] = "power";
1172 void pcie_aspm_create_sysfs_dev_files(struct pci_dev
*pdev
)
1174 struct pcie_link_state
*link_state
= pdev
->link_state
;
1179 if (link_state
->aspm_support
)
1180 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
1181 &dev_attr_link_state
.attr
, power_group
);
1182 if (link_state
->clkpm_capable
)
1183 sysfs_add_file_to_group(&pdev
->dev
.kobj
,
1184 &dev_attr_clk_ctl
.attr
, power_group
);
1187 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev
*pdev
)
1189 struct pcie_link_state
*link_state
= pdev
->link_state
;
1194 if (link_state
->aspm_support
)
1195 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
1196 &dev_attr_link_state
.attr
, power_group
);
1197 if (link_state
->clkpm_capable
)
1198 sysfs_remove_file_from_group(&pdev
->dev
.kobj
,
1199 &dev_attr_clk_ctl
.attr
, power_group
);
1203 static int __init
pcie_aspm_disable(char *str
)
1205 if (!strcmp(str
, "off")) {
1206 aspm_policy
= POLICY_DEFAULT
;
1208 aspm_support_enabled
= false;
1209 printk(KERN_INFO
"PCIe ASPM is disabled\n");
1210 } else if (!strcmp(str
, "force")) {
1212 printk(KERN_INFO
"PCIe ASPM is forcibly enabled\n");
1217 __setup("pcie_aspm=", pcie_aspm_disable
);
1219 void pcie_no_aspm(void)
1222 * Disabling ASPM is intended to prevent the kernel from modifying
1223 * existing hardware state, not to clear existing state. To that end:
1224 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1225 * (b) prevent userspace from changing policy
1228 aspm_policy
= POLICY_DEFAULT
;
1233 bool pcie_aspm_support_enabled(void)
1235 return aspm_support_enabled
;
1237 EXPORT_SYMBOL(pcie_aspm_support_enabled
);