2 * PCI Express Downstream Port Containment services driver
3 * Author: Keith Busch <keith.busch@intel.com>
5 * Copyright (C) 2016 Intel Corp.
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/delay.h>
13 #include <linux/interrupt.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/pcieport_if.h>
19 struct rp_pio_header_log_regs
{
26 struct dpc_rp_pio_regs
{
33 struct rp_pio_header_log_regs header_log
;
35 u32 tlp_prefix_log
[4];
41 struct pcie_device
*dev
;
42 struct work_struct work
;
48 static const char * const rp_pio_error_string
[] = {
49 "Configuration Request received UR Completion", /* Bit Position 0 */
50 "Configuration Request received CA Completion", /* Bit Position 1 */
51 "Configuration Request Completion Timeout", /* Bit Position 2 */
57 "I/O Request received UR Completion", /* Bit Position 8 */
58 "I/O Request received CA Completion", /* Bit Position 9 */
59 "I/O Request Completion Timeout", /* Bit Position 10 */
65 "Memory Request received UR Completion", /* Bit Position 16 */
66 "Memory Request received CA Completion", /* Bit Position 17 */
67 "Memory Request Completion Timeout", /* Bit Position 18 */
70 static int dpc_wait_rp_inactive(struct dpc_dev
*dpc
)
72 unsigned long timeout
= jiffies
+ HZ
;
73 struct pci_dev
*pdev
= dpc
->dev
->port
;
74 struct device
*dev
= &dpc
->dev
->device
;
77 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_STATUS
, &status
);
78 while (status
& PCI_EXP_DPC_RP_BUSY
&&
79 !time_after(jiffies
, timeout
)) {
81 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_STATUS
, &status
);
83 if (status
& PCI_EXP_DPC_RP_BUSY
) {
84 dev_warn(dev
, "DPC root port still busy\n");
90 static void dpc_wait_link_inactive(struct dpc_dev
*dpc
)
92 unsigned long timeout
= jiffies
+ HZ
;
93 struct pci_dev
*pdev
= dpc
->dev
->port
;
94 struct device
*dev
= &dpc
->dev
->device
;
97 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
98 while (lnk_status
& PCI_EXP_LNKSTA_DLLLA
&&
99 !time_after(jiffies
, timeout
)) {
101 pcie_capability_read_word(pdev
, PCI_EXP_LNKSTA
, &lnk_status
);
103 if (lnk_status
& PCI_EXP_LNKSTA_DLLLA
)
104 dev_warn(dev
, "Link state not disabled for DPC event\n");
107 static void interrupt_event_handler(struct work_struct
*work
)
109 struct dpc_dev
*dpc
= container_of(work
, struct dpc_dev
, work
);
110 struct pci_dev
*dev
, *temp
, *pdev
= dpc
->dev
->port
;
111 struct pci_bus
*parent
= pdev
->subordinate
;
113 pci_lock_rescan_remove();
114 list_for_each_entry_safe_reverse(dev
, temp
, &parent
->devices
,
117 pci_dev_set_disconnected(dev
, NULL
);
118 if (pci_has_subordinate(dev
))
119 pci_walk_bus(dev
->subordinate
,
120 pci_dev_set_disconnected
, NULL
);
121 pci_stop_and_remove_bus_device(dev
);
124 pci_unlock_rescan_remove();
126 dpc_wait_link_inactive(dpc
);
127 if (dpc
->rp
&& dpc_wait_rp_inactive(dpc
))
129 if (dpc
->rp
&& dpc
->rp_pio_status
) {
130 pci_write_config_dword(pdev
,
131 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_STATUS
,
133 dpc
->rp_pio_status
= 0;
136 pci_write_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_STATUS
,
137 PCI_EXP_DPC_STATUS_TRIGGER
| PCI_EXP_DPC_STATUS_INTERRUPT
);
140 static void dpc_rp_pio_print_tlp_header(struct device
*dev
,
141 struct rp_pio_header_log_regs
*t
)
143 dev_err(dev
, "TLP Header: %#010x %#010x %#010x %#010x\n",
144 t
->dw0
, t
->dw1
, t
->dw2
, t
->dw3
);
147 static void dpc_rp_pio_print_error(struct dpc_dev
*dpc
,
148 struct dpc_rp_pio_regs
*rp_pio
)
150 struct device
*dev
= &dpc
->dev
->device
;
154 dev_err(dev
, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
155 rp_pio
->status
, rp_pio
->mask
);
157 dev_err(dev
, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
158 rp_pio
->severity
, rp_pio
->syserror
, rp_pio
->exception
);
160 status
= (rp_pio
->status
& ~rp_pio
->mask
);
162 for (i
= 0; i
< ARRAY_SIZE(rp_pio_error_string
); i
++) {
163 if (!(status
& (1 << i
)))
166 dev_err(dev
, "[%2d] %s%s\n", i
, rp_pio_error_string
[i
],
167 rp_pio
->first_error
== i
? " (First)" : "");
170 dpc_rp_pio_print_tlp_header(dev
, &rp_pio
->header_log
);
171 if (rp_pio
->log_size
== 4)
173 dev_err(dev
, "RP PIO ImpSpec Log %#010x\n", rp_pio
->impspec_log
);
175 for (i
= 0; i
< rp_pio
->log_size
- 5; i
++)
176 dev_err(dev
, "TLP Prefix Header: dw%d, %#010x\n", i
,
177 rp_pio
->tlp_prefix_log
[i
]);
180 static void dpc_rp_pio_get_info(struct dpc_dev
*dpc
,
181 struct dpc_rp_pio_regs
*rp_pio
)
183 struct pci_dev
*pdev
= dpc
->dev
->port
;
184 struct device
*dev
= &dpc
->dev
->device
;
189 pci_read_config_dword(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_STATUS
,
191 pci_read_config_dword(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_MASK
,
194 pci_read_config_dword(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_SEVERITY
,
196 pci_read_config_dword(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_SYSERROR
,
198 pci_read_config_dword(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_EXCEPTION
,
201 /* Get First Error Pointer */
202 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_STATUS
, &status
);
203 rp_pio
->first_error
= (status
& 0x1f00) >> 8;
205 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CAP
, &cap
);
206 rp_pio
->log_size
= (cap
& PCI_EXP_DPC_RP_PIO_LOG_SIZE
) >> 8;
207 if (rp_pio
->log_size
< 4 || rp_pio
->log_size
> 9) {
208 dev_err(dev
, "RP PIO log size %u is invalid\n",
213 pci_read_config_dword(pdev
,
214 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_HEADER_LOG
,
215 &rp_pio
->header_log
.dw0
);
216 pci_read_config_dword(pdev
,
217 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_HEADER_LOG
+ 4,
218 &rp_pio
->header_log
.dw1
);
219 pci_read_config_dword(pdev
,
220 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_HEADER_LOG
+ 8,
221 &rp_pio
->header_log
.dw2
);
222 pci_read_config_dword(pdev
,
223 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_HEADER_LOG
+ 12,
224 &rp_pio
->header_log
.dw3
);
225 if (rp_pio
->log_size
== 4)
228 pci_read_config_dword(pdev
,
229 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG
,
230 &rp_pio
->impspec_log
);
231 for (i
= 0; i
< rp_pio
->log_size
- 5; i
++)
232 pci_read_config_dword(pdev
,
233 dpc
->cap_pos
+ PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG
,
234 &rp_pio
->tlp_prefix_log
[i
]);
237 static void dpc_process_rp_pio_error(struct dpc_dev
*dpc
)
239 struct dpc_rp_pio_regs rp_pio_regs
;
241 dpc_rp_pio_get_info(dpc
, &rp_pio_regs
);
242 dpc_rp_pio_print_error(dpc
, &rp_pio_regs
);
244 dpc
->rp_pio_status
= rp_pio_regs
.status
;
247 static irqreturn_t
dpc_irq(int irq
, void *context
)
249 struct dpc_dev
*dpc
= (struct dpc_dev
*)context
;
250 struct pci_dev
*pdev
= dpc
->dev
->port
;
251 struct device
*dev
= &dpc
->dev
->device
;
254 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_STATUS
, &status
);
255 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_SOURCE_ID
,
257 if (!status
|| status
== (u16
)(~0))
260 dev_info(dev
, "DPC containment event, status:%#06x source:%#06x\n",
263 if (status
& PCI_EXP_DPC_STATUS_TRIGGER
) {
264 u16 reason
= (status
>> 1) & 0x3;
265 u16 ext_reason
= (status
>> 5) & 0x3;
267 dev_warn(dev
, "DPC %s detected, remove downstream devices\n",
268 (reason
== 0) ? "unmasked uncorrectable error" :
269 (reason
== 1) ? "ERR_NONFATAL" :
270 (reason
== 2) ? "ERR_FATAL" :
271 (ext_reason
== 0) ? "RP PIO error" :
272 (ext_reason
== 1) ? "software trigger" :
274 /* show RP PIO error detail information */
275 if (reason
== 3 && ext_reason
== 0)
276 dpc_process_rp_pio_error(dpc
);
278 schedule_work(&dpc
->work
);
283 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
284 static int dpc_probe(struct pcie_device
*dev
)
287 struct pci_dev
*pdev
= dev
->port
;
288 struct device
*device
= &dev
->device
;
292 dpc
= devm_kzalloc(device
, sizeof(*dpc
), GFP_KERNEL
);
296 dpc
->cap_pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_DPC
);
298 INIT_WORK(&dpc
->work
, interrupt_event_handler
);
299 set_service_data(dev
, dpc
);
301 status
= devm_request_irq(device
, dev
->irq
, dpc_irq
, IRQF_SHARED
,
304 dev_warn(device
, "request IRQ%d failed: %d\n", dev
->irq
,
309 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CAP
, &cap
);
310 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CTL
, &ctl
);
312 dpc
->rp
= (cap
& PCI_EXP_DPC_CAP_RP_EXT
);
314 ctl
= (ctl
& 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL
| PCI_EXP_DPC_CTL_INT_EN
;
315 pci_write_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CTL
, ctl
);
317 dev_info(device
, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
318 cap
& 0xf, FLAG(cap
, PCI_EXP_DPC_CAP_RP_EXT
),
319 FLAG(cap
, PCI_EXP_DPC_CAP_POISONED_TLP
),
320 FLAG(cap
, PCI_EXP_DPC_CAP_SW_TRIGGER
), (cap
>> 8) & 0xf,
321 FLAG(cap
, PCI_EXP_DPC_CAP_DL_ACTIVE
));
325 static void dpc_remove(struct pcie_device
*dev
)
327 struct dpc_dev
*dpc
= get_service_data(dev
);
328 struct pci_dev
*pdev
= dev
->port
;
331 pci_read_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CTL
, &ctl
);
332 ctl
&= ~(PCI_EXP_DPC_CTL_EN_NONFATAL
| PCI_EXP_DPC_CTL_INT_EN
);
333 pci_write_config_word(pdev
, dpc
->cap_pos
+ PCI_EXP_DPC_CTL
, ctl
);
336 static struct pcie_port_service_driver dpcdriver
= {
338 .port_type
= PCIE_ANY_PORT
,
339 .service
= PCIE_PORT_SERVICE_DPC
,
341 .remove
= dpc_remove
,
344 static int __init
dpc_service_init(void)
346 return pcie_port_service_register(&dpcdriver
);
348 device_initcall(dpc_service_init
);