2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <linux/iommu.h>
14 #include <acpi/acpi_hest.h>
18 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
19 #define CARDBUS_RESERVE_BUSNR 3
21 /* Ugh. Need to stop exporting this to modules. */
22 LIST_HEAD(pci_root_buses
);
23 EXPORT_SYMBOL(pci_root_buses
);
26 static int find_anything(struct device
*dev
, void *data
)
32 * Some device drivers need know if pci is initiated.
33 * Basically, we think pci is not initiated when there
34 * is no device to be found on the pci_bus_type.
36 int no_pci_devices(void)
41 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
42 no_devices
= (dev
== NULL
);
46 EXPORT_SYMBOL(no_pci_devices
);
49 * PCI Bus Class Devices
51 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
53 struct device_attribute
*attr
,
57 const struct cpumask
*cpumask
;
59 cpumask
= cpumask_of_pcibus(to_pci_bus(dev
));
61 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
) :
62 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
68 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
69 struct device_attribute
*attr
,
72 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
75 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
76 struct device_attribute
*attr
,
79 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
82 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
83 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
88 static void release_pcibus_dev(struct device
*dev
)
90 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
93 put_device(pci_bus
->bridge
);
97 static struct class pcibus_class
= {
99 .dev_release
= &release_pcibus_dev
,
102 static int __init
pcibus_class_init(void)
104 return class_register(&pcibus_class
);
106 postcore_initcall(pcibus_class_init
);
109 * Translate the low bits of the PCI base
110 * to the resource type
112 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
114 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
115 return IORESOURCE_IO
;
117 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
118 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
120 return IORESOURCE_MEM
;
123 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
125 u64 size
= mask
& maxbase
; /* Find the significant bits */
129 /* Get the lowest of them to find the decode size, and
130 from that the extent. */
131 size
= (size
& ~(size
-1)) - 1;
133 /* base == maxbase can be valid only if the BAR has
134 already been programmed with all 1s. */
135 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
141 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
143 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
144 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
148 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
150 if (res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
151 return pci_bar_mem64
;
152 return pci_bar_mem32
;
156 * pci_read_base - read a PCI BAR
157 * @dev: the PCI device
158 * @type: type of the BAR
159 * @res: resource buffer to be filled in
160 * @pos: BAR position in the config space
162 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
164 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
165 struct resource
*res
, unsigned int pos
)
169 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
171 res
->name
= pci_name(dev
);
173 pci_read_config_dword(dev
, pos
, &l
);
174 pci_write_config_dword(dev
, pos
, l
| mask
);
175 pci_read_config_dword(dev
, pos
, &sz
);
176 pci_write_config_dword(dev
, pos
, l
);
179 * All bits set in sz means the device isn't working properly.
180 * If the BAR isn't implemented, all bits must be 0. If it's a
181 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
184 if (!sz
|| sz
== 0xffffffff)
188 * I don't know how l can have all bits set. Copied from old code.
189 * Maybe it fixes a bug on some ancient platform.
194 if (type
== pci_bar_unknown
) {
195 type
= decode_bar(res
, l
);
196 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
197 if (type
== pci_bar_io
) {
198 l
&= PCI_BASE_ADDRESS_IO_MASK
;
199 mask
= PCI_BASE_ADDRESS_IO_MASK
& IO_SPACE_LIMIT
;
201 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
202 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
205 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
206 l
&= PCI_ROM_ADDRESS_MASK
;
207 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
210 if (type
== pci_bar_mem64
) {
213 u64 mask64
= mask
| (u64
)~0 << 32;
215 pci_read_config_dword(dev
, pos
+ 4, &l
);
216 pci_write_config_dword(dev
, pos
+ 4, ~0);
217 pci_read_config_dword(dev
, pos
+ 4, &sz
);
218 pci_write_config_dword(dev
, pos
+ 4, l
);
220 l64
|= ((u64
)l
<< 32);
221 sz64
|= ((u64
)sz
<< 32);
223 sz64
= pci_size(l64
, sz64
, mask64
);
228 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
229 dev_err(&dev
->dev
, "reg %x: can't handle 64-bit BAR\n",
234 res
->flags
|= IORESOURCE_MEM_64
;
235 if ((sizeof(resource_size_t
) < 8) && l
) {
236 /* Address above 32-bit boundary; disable the BAR */
237 pci_write_config_dword(dev
, pos
, 0);
238 pci_write_config_dword(dev
, pos
+ 4, 0);
243 res
->end
= l64
+ sz64
;
244 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n",
248 sz
= pci_size(l
, sz
, mask
);
256 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n", pos
, res
);
260 return (type
== pci_bar_mem64
) ? 1 : 0;
266 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
268 unsigned int pos
, reg
;
270 for (pos
= 0; pos
< howmany
; pos
++) {
271 struct resource
*res
= &dev
->resource
[pos
];
272 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
273 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
277 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
278 dev
->rom_base_reg
= rom
;
279 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
280 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
281 IORESOURCE_SIZEALIGN
;
282 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
286 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
288 struct pci_dev
*dev
= child
->self
;
289 u8 io_base_lo
, io_limit_lo
;
290 u16 mem_base_lo
, mem_limit_lo
;
291 unsigned long base
, limit
;
292 struct resource
*res
;
295 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
298 dev_info(&dev
->dev
, "PCI bridge to [bus %02x-%02x]%s\n",
299 child
->secondary
, child
->subordinate
,
300 dev
->transparent
? " (subtractive decode)": "");
302 if (dev
->transparent
) {
303 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
304 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
307 res
= child
->resource
[0];
308 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
309 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
310 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
311 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
313 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
314 u16 io_base_hi
, io_limit_hi
;
315 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
316 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
317 base
|= (io_base_hi
<< 16);
318 limit
|= (io_limit_hi
<< 16);
322 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
326 res
->end
= limit
+ 0xfff;
327 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
330 res
= child
->resource
[1];
331 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
332 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
333 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
334 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
336 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
338 res
->end
= limit
+ 0xfffff;
339 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
342 res
= child
->resource
[2];
343 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
344 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
345 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
346 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
348 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
349 u32 mem_base_hi
, mem_limit_hi
;
350 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
351 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
358 if (mem_base_hi
<= mem_limit_hi
) {
359 #if BITS_PER_LONG == 64
360 base
|= ((long) mem_base_hi
) << 32;
361 limit
|= ((long) mem_limit_hi
) << 32;
363 if (mem_base_hi
|| mem_limit_hi
) {
364 dev_err(&dev
->dev
, "can't handle 64-bit "
365 "address space for bridge\n");
372 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
373 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
374 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
375 res
->flags
|= IORESOURCE_MEM_64
;
377 res
->end
= limit
+ 0xfffff;
378 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
382 static struct pci_bus
* pci_alloc_bus(void)
386 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
388 INIT_LIST_HEAD(&b
->node
);
389 INIT_LIST_HEAD(&b
->children
);
390 INIT_LIST_HEAD(&b
->devices
);
391 INIT_LIST_HEAD(&b
->slots
);
396 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
397 struct pci_dev
*bridge
, int busnr
)
399 struct pci_bus
*child
;
403 * Allocate a new bus, and inherit stuff from the parent..
405 child
= pci_alloc_bus();
409 child
->parent
= parent
;
410 child
->ops
= parent
->ops
;
411 child
->sysdata
= parent
->sysdata
;
412 child
->bus_flags
= parent
->bus_flags
;
414 /* initialize some portions of the bus device, but don't register it
415 * now as the parent is not properly set up yet. This device will get
416 * registered later in pci_bus_add_devices()
418 child
->dev
.class = &pcibus_class
;
419 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
422 * Set up the primary, secondary and subordinate
425 child
->number
= child
->secondary
= busnr
;
426 child
->primary
= parent
->secondary
;
427 child
->subordinate
= 0xff;
432 child
->self
= bridge
;
433 child
->bridge
= get_device(&bridge
->dev
);
435 /* Set up default resource pointers and names.. */
436 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
437 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
438 child
->resource
[i
]->name
= child
->name
;
440 bridge
->subordinate
= child
;
445 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
447 struct pci_bus
*child
;
449 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
451 down_write(&pci_bus_sem
);
452 list_add_tail(&child
->node
, &parent
->children
);
453 up_write(&pci_bus_sem
);
458 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
460 struct pci_bus
*parent
= child
->parent
;
462 /* Attempts to fix that up are really dangerous unless
463 we're going to re-assign all bus numbers. */
464 if (!pcibios_assign_all_busses())
467 while (parent
->parent
&& parent
->subordinate
< max
) {
468 parent
->subordinate
= max
;
469 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
470 parent
= parent
->parent
;
475 * If it's a bridge, configure it and scan the bus behind it.
476 * For CardBus bridges, we don't scan behind as the devices will
477 * be handled by the bridge driver itself.
479 * We need to process bridges in two passes -- first we scan those
480 * already configured by the BIOS and after we are done with all of
481 * them, we proceed to assigning numbers to the remaining buses in
482 * order to avoid overlaps between old and new bus numbers.
484 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
486 struct pci_bus
*child
;
487 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
492 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
494 dev_dbg(&dev
->dev
, "scanning behind bridge, config %06x, pass %d\n",
495 buses
& 0xffffff, pass
);
497 /* Check if setup is sensible at all */
499 ((buses
& 0xff) != bus
->number
|| ((buses
>> 8) & 0xff) <= bus
->number
)) {
500 dev_dbg(&dev
->dev
, "bus configuration invalid, reconfiguring\n");
504 /* Disable MasterAbortMode during probing to avoid reporting
505 of bus errors (in some architectures) */
506 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
507 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
508 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
510 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
&& !broken
) {
511 unsigned int cmax
, busnr
;
513 * Bus already configured by firmware, process it in the first
514 * pass and just note the configuration.
518 busnr
= (buses
>> 8) & 0xFF;
521 * If we already got to this bus through a different bridge,
522 * don't re-add it. This can happen with the i450NX chipset.
524 * However, we continue to descend down the hierarchy and
525 * scan remaining child buses.
527 child
= pci_find_bus(pci_domain_nr(bus
), busnr
);
529 child
= pci_add_new_bus(bus
, dev
, busnr
);
532 child
->primary
= buses
& 0xFF;
533 child
->subordinate
= (buses
>> 16) & 0xFF;
534 child
->bridge_ctl
= bctl
;
537 cmax
= pci_scan_child_bus(child
);
540 if (child
->subordinate
> max
)
541 max
= child
->subordinate
;
544 * We need to assign a number to this bus which we always
545 * do in the second pass.
548 if (pcibios_assign_all_busses() || broken
)
549 /* Temporarily disable forwarding of the
550 configuration cycles on all bridges in
551 this bus segment to avoid possible
552 conflicts in the second pass between two
553 bridges programmed with overlapping
555 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
561 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
563 /* Prevent assigning a bus number that already exists.
564 * This can happen when a bridge is hot-plugged */
565 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
567 child
= pci_add_new_bus(bus
, dev
, ++max
);
568 buses
= (buses
& 0xff000000)
569 | ((unsigned int)(child
->primary
) << 0)
570 | ((unsigned int)(child
->secondary
) << 8)
571 | ((unsigned int)(child
->subordinate
) << 16);
574 * yenta.c forces a secondary latency timer of 176.
575 * Copy that behaviour here.
578 buses
&= ~0xff000000;
579 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
583 * We need to blast all three values with a single write.
585 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
588 child
->bridge_ctl
= bctl
;
590 * Adjust subordinate busnr in parent buses.
591 * We do this before scanning for children because
592 * some devices may not be detected if the bios
595 pci_fixup_parent_subordinate_busnr(child
, max
);
596 /* Now we can scan all subordinate buses... */
597 max
= pci_scan_child_bus(child
);
599 * now fix it up again since we have found
600 * the real value of max.
602 pci_fixup_parent_subordinate_busnr(child
, max
);
605 * For CardBus bridges, we leave 4 bus numbers
606 * as cards with a PCI-to-PCI bridge can be
609 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
610 struct pci_bus
*parent
= bus
;
611 if (pci_find_bus(pci_domain_nr(bus
),
614 while (parent
->parent
) {
615 if ((!pcibios_assign_all_busses()) &&
616 (parent
->subordinate
> max
) &&
617 (parent
->subordinate
<= max
+i
)) {
620 parent
= parent
->parent
;
624 * Often, there are two cardbus bridges
625 * -- try to leave one valid bus number
633 pci_fixup_parent_subordinate_busnr(child
, max
);
636 * Set the subordinate bus number to its real value.
638 child
->subordinate
= max
;
639 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
643 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
644 pci_domain_nr(bus
), child
->number
);
646 /* Has only triggered on CardBus, fixup is in yenta_socket */
647 while (bus
->parent
) {
648 if ((child
->subordinate
> bus
->subordinate
) ||
649 (child
->number
> bus
->subordinate
) ||
650 (child
->number
< bus
->number
) ||
651 (child
->subordinate
< bus
->number
)) {
652 dev_info(&child
->dev
, "[bus %02x-%02x] %s "
653 "hidden behind%s bridge %s [bus %02x-%02x]\n",
654 child
->number
, child
->subordinate
,
655 (bus
->number
> child
->subordinate
&&
656 bus
->subordinate
< child
->number
) ?
657 "wholly" : "partially",
658 bus
->self
->transparent
? " transparent" : "",
660 bus
->number
, bus
->subordinate
);
666 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
672 * Read interrupt line and base address registers.
673 * The architecture-dependent code can tweak these, of course.
675 static void pci_read_irq(struct pci_dev
*dev
)
679 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
682 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
686 static void set_pcie_port_type(struct pci_dev
*pdev
)
691 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
695 pdev
->pcie_cap
= pos
;
696 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
697 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
700 static void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
706 pos
= pci_pcie_cap(pdev
);
709 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
710 if (!(reg16
& PCI_EXP_FLAGS_SLOT
))
712 pci_read_config_dword(pdev
, pos
+ PCI_EXP_SLTCAP
, ®32
);
713 if (reg32
& PCI_EXP_SLTCAP_HPC
)
714 pdev
->is_hotplug_bridge
= 1;
717 static void set_pci_aer_firmware_first(struct pci_dev
*pdev
)
719 if (acpi_hest_firmware_first_pci(pdev
))
720 pdev
->aer_firmware_first
= 1;
723 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
726 * pci_setup_device - fill in class and map information of a device
727 * @dev: the device structure to fill
729 * Initialize the device structure with information about the device's
730 * vendor,class,memory and IO-space addresses,IRQ lines etc.
731 * Called at initialisation of the PCI subsystem and by CardBus services.
732 * Returns 0 on success and negative if unknown type of device (not normal,
733 * bridge or CardBus).
735 int pci_setup_device(struct pci_dev
*dev
)
739 struct pci_slot
*slot
;
742 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
745 dev
->sysdata
= dev
->bus
->sysdata
;
746 dev
->dev
.parent
= dev
->bus
->bridge
;
747 dev
->dev
.bus
= &pci_bus_type
;
748 dev
->hdr_type
= hdr_type
& 0x7f;
749 dev
->multifunction
= !!(hdr_type
& 0x80);
750 dev
->error_state
= pci_channel_io_normal
;
751 set_pcie_port_type(dev
);
752 set_pci_aer_firmware_first(dev
);
754 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
755 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
758 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
759 set this higher, assuming the system even supports it. */
760 dev
->dma_mask
= 0xffffffff;
762 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
763 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
764 PCI_FUNC(dev
->devfn
));
766 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
767 dev
->revision
= class & 0xff;
768 class >>= 8; /* upper 3 bytes */
772 dev_dbg(&dev
->dev
, "found [%04x:%04x] class %06x header type %02x\n",
773 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
775 /* need to have dev->class ready */
776 dev
->cfg_size
= pci_cfg_space_size(dev
);
778 /* "Unknown power state" */
779 dev
->current_state
= PCI_UNKNOWN
;
781 /* Early fixups, before probing the BARs */
782 pci_fixup_device(pci_fixup_early
, dev
);
783 /* device class may be changed after fixup */
784 class = dev
->class >> 8;
786 switch (dev
->hdr_type
) { /* header type */
787 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
788 if (class == PCI_CLASS_BRIDGE_PCI
)
791 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
792 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
793 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
796 * Do the ugly legacy mode stuff here rather than broken chip
797 * quirk code. Legacy mode ATA controllers have fixed
798 * addresses. These are not always echoed in BAR0-3, and
799 * BAR0-3 in a few cases contain junk!
801 if (class == PCI_CLASS_STORAGE_IDE
) {
803 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
804 if ((progif
& 1) == 0) {
805 dev
->resource
[0].start
= 0x1F0;
806 dev
->resource
[0].end
= 0x1F7;
807 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
808 dev
->resource
[1].start
= 0x3F6;
809 dev
->resource
[1].end
= 0x3F6;
810 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
812 if ((progif
& 4) == 0) {
813 dev
->resource
[2].start
= 0x170;
814 dev
->resource
[2].end
= 0x177;
815 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
816 dev
->resource
[3].start
= 0x376;
817 dev
->resource
[3].end
= 0x376;
818 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
823 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
824 if (class != PCI_CLASS_BRIDGE_PCI
)
826 /* The PCI-to-PCI bridge spec requires that subtractive
827 decoding (i.e. transparent) bridge must have programming
828 interface code of 0x01. */
830 dev
->transparent
= ((dev
->class & 0xff) == 1);
831 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
832 set_pcie_hotplug_bridge(dev
);
833 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
835 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
836 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
840 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
841 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
844 pci_read_bases(dev
, 1, 0);
845 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
846 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
849 default: /* unknown header */
850 dev_err(&dev
->dev
, "unknown header type %02x, "
851 "ignoring device\n", dev
->hdr_type
);
855 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
856 "type %02x)\n", class, dev
->hdr_type
);
857 dev
->class = PCI_CLASS_NOT_DEFINED
;
860 /* We found a fine healthy device, go go go... */
864 static void pci_release_capabilities(struct pci_dev
*dev
)
866 pci_vpd_release(dev
);
867 pci_iov_release(dev
);
871 * pci_release_dev - free a pci device structure when all users of it are finished.
872 * @dev: device that's been disconnected
874 * Will be called only by the device core when all users of this pci device are
877 static void pci_release_dev(struct device
*dev
)
879 struct pci_dev
*pci_dev
;
881 pci_dev
= to_pci_dev(dev
);
882 pci_release_capabilities(pci_dev
);
887 * pci_cfg_space_size - get the configuration space size of the PCI device.
890 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
891 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
892 * access it. Maybe we don't have a way to generate extended config space
893 * accesses, or the device is behind a reverse Express bridge. So we try
894 * reading the dword at 0x100 which must either be 0 or a valid extended
897 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
900 int pos
= PCI_CFG_SPACE_SIZE
;
902 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
904 if (status
== 0xffffffff)
907 return PCI_CFG_SPACE_EXP_SIZE
;
910 return PCI_CFG_SPACE_SIZE
;
913 int pci_cfg_space_size(struct pci_dev
*dev
)
919 class = dev
->class >> 8;
920 if (class == PCI_CLASS_BRIDGE_HOST
)
921 return pci_cfg_space_size_ext(dev
);
923 pos
= pci_pcie_cap(dev
);
925 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
929 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
930 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
934 return pci_cfg_space_size_ext(dev
);
937 return PCI_CFG_SPACE_SIZE
;
940 static void pci_release_bus_bridge_dev(struct device
*dev
)
945 struct pci_dev
*alloc_pci_dev(void)
949 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
953 INIT_LIST_HEAD(&dev
->bus_list
);
957 EXPORT_SYMBOL(alloc_pci_dev
);
960 * Read the config data for a PCI device, sanity-check it
961 * and fill in the dev structure...
963 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
969 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
972 /* some broken boards return 0 or ~0 if a slot is empty: */
973 if (l
== 0xffffffff || l
== 0x00000000 ||
974 l
== 0x0000ffff || l
== 0xffff0000)
977 /* Configuration request Retry Status */
978 while (l
== 0xffff0001) {
981 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
983 /* Card hasn't responded in 60 seconds? Must be stuck. */
984 if (delay
> 60 * 1000) {
985 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
986 "responding\n", pci_domain_nr(bus
),
987 bus
->number
, PCI_SLOT(devfn
),
993 dev
= alloc_pci_dev();
999 dev
->vendor
= l
& 0xffff;
1000 dev
->device
= (l
>> 16) & 0xffff;
1002 if (pci_setup_device(dev
)) {
1010 static void pci_init_capabilities(struct pci_dev
*dev
)
1012 /* MSI/MSI-X list */
1013 pci_msi_init_pci_dev(dev
);
1015 /* Buffers for saving PCIe and PCI-X capabilities */
1016 pci_allocate_cap_save_buffers(dev
);
1018 /* Power Management */
1020 platform_pci_wakeup_init(dev
);
1022 /* Vital Product Data */
1023 pci_vpd_pci22_init(dev
);
1025 /* Alternative Routing-ID Forwarding */
1026 pci_enable_ari(dev
);
1028 /* Single Root I/O Virtualization */
1031 /* Enable ACS P2P upstream forwarding */
1032 if (iommu_found() || xen_initial_domain())
1033 pci_enable_acs(dev
);
1036 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1038 device_initialize(&dev
->dev
);
1039 dev
->dev
.release
= pci_release_dev
;
1042 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1043 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1044 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1046 pci_set_dma_max_seg_size(dev
, 65536);
1047 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1049 /* Fix up broken headers */
1050 pci_fixup_device(pci_fixup_header
, dev
);
1052 /* Clear the state_saved flag. */
1053 dev
->state_saved
= false;
1055 /* Initialize various capabilities */
1056 pci_init_capabilities(dev
);
1059 * Add the device to our list of discovered devices
1060 * and the bus list for fixup functions, etc.
1062 down_write(&pci_bus_sem
);
1063 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1064 up_write(&pci_bus_sem
);
1067 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1069 struct pci_dev
*dev
;
1071 dev
= pci_get_slot(bus
, devfn
);
1077 dev
= pci_scan_device(bus
, devfn
);
1081 pci_device_add(dev
, bus
);
1085 EXPORT_SYMBOL(pci_scan_single_device
);
1088 * pci_scan_slot - scan a PCI slot on a bus for devices.
1089 * @bus: PCI bus to scan
1090 * @devfn: slot number to scan (must have zero function.)
1092 * Scan a PCI slot on the specified PCI bus for devices, adding
1093 * discovered devices to the @bus->devices list. New devices
1094 * will not have is_added set.
1096 * Returns the number of new devices found.
1098 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1101 struct pci_dev
*dev
;
1103 dev
= pci_scan_single_device(bus
, devfn
);
1104 if (dev
&& !dev
->is_added
) /* new device? */
1107 if (dev
&& dev
->multifunction
) {
1108 for (fn
= 1; fn
< 8; fn
++) {
1109 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1113 dev
->multifunction
= 1;
1118 /* only one slot has pcie device */
1119 if (bus
->self
&& nr
)
1120 pcie_aspm_init_link_state(bus
->self
);
1125 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1127 unsigned int devfn
, pass
, max
= bus
->secondary
;
1128 struct pci_dev
*dev
;
1130 dev_dbg(&bus
->dev
, "scanning bus\n");
1132 /* Go find them, Rover! */
1133 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1134 pci_scan_slot(bus
, devfn
);
1136 /* Reserve buses for SR-IOV capability. */
1137 max
+= pci_iov_bus_range(bus
);
1140 * After performing arch-dependent fixup of the bus, look behind
1141 * all PCI-to-PCI bridges on this bus.
1143 if (!bus
->is_added
) {
1144 dev_dbg(&bus
->dev
, "fixups for bus\n");
1145 pcibios_fixup_bus(bus
);
1146 if (pci_is_root_bus(bus
))
1150 for (pass
=0; pass
< 2; pass
++)
1151 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1152 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1153 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1154 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1158 * We've scanned the bus and so we know all about what's on
1159 * the other side of any bridges that may be on this bus plus
1162 * Return how far we've got finding sub-buses.
1164 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1168 struct pci_bus
* pci_create_bus(struct device
*parent
,
1169 int bus
, struct pci_ops
*ops
, void *sysdata
)
1172 struct pci_bus
*b
, *b2
;
1175 b
= pci_alloc_bus();
1179 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1185 b
->sysdata
= sysdata
;
1188 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1190 /* If we already got to this bus through a different bridge, ignore it */
1191 dev_dbg(&b2
->dev
, "bus already known\n");
1195 down_write(&pci_bus_sem
);
1196 list_add_tail(&b
->node
, &pci_root_buses
);
1197 up_write(&pci_bus_sem
);
1199 dev
->parent
= parent
;
1200 dev
->release
= pci_release_bus_bridge_dev
;
1201 dev_set_name(dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1202 error
= device_register(dev
);
1205 b
->bridge
= get_device(dev
);
1208 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1210 b
->dev
.class = &pcibus_class
;
1211 b
->dev
.parent
= b
->bridge
;
1212 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1213 error
= device_register(&b
->dev
);
1215 goto class_dev_reg_err
;
1216 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1218 goto dev_create_file_err
;
1220 /* Create legacy_io and legacy_mem files for this bus */
1221 pci_create_legacy_files(b
);
1223 b
->number
= b
->secondary
= bus
;
1224 b
->resource
[0] = &ioport_resource
;
1225 b
->resource
[1] = &iomem_resource
;
1229 dev_create_file_err
:
1230 device_unregister(&b
->dev
);
1232 device_unregister(dev
);
1234 down_write(&pci_bus_sem
);
1236 up_write(&pci_bus_sem
);
1243 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1244 int bus
, struct pci_ops
*ops
, void *sysdata
)
1248 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1250 b
->subordinate
= pci_scan_child_bus(b
);
1253 EXPORT_SYMBOL(pci_scan_bus_parented
);
1255 #ifdef CONFIG_HOTPLUG
1257 * pci_rescan_bus - scan a PCI bus for devices.
1258 * @bus: PCI bus to scan
1260 * Scan a PCI bus and child buses for new devices, adds them,
1263 * Returns the max number of subordinate bus discovered.
1265 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1268 struct pci_dev
*dev
;
1270 max
= pci_scan_child_bus(bus
);
1272 down_read(&pci_bus_sem
);
1273 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1274 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1275 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1276 if (dev
->subordinate
)
1277 pci_bus_size_bridges(dev
->subordinate
);
1278 up_read(&pci_bus_sem
);
1280 pci_bus_assign_resources(bus
);
1281 pci_enable_bridges(bus
);
1282 pci_bus_add_devices(bus
);
1286 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1288 EXPORT_SYMBOL(pci_add_new_bus
);
1289 EXPORT_SYMBOL(pci_scan_slot
);
1290 EXPORT_SYMBOL(pci_scan_bridge
);
1291 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1294 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1296 const struct pci_dev
*a
= to_pci_dev(d_a
);
1297 const struct pci_dev
*b
= to_pci_dev(d_b
);
1299 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1300 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1302 if (a
->bus
->number
< b
->bus
->number
) return -1;
1303 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1305 if (a
->devfn
< b
->devfn
) return -1;
1306 else if (a
->devfn
> b
->devfn
) return 1;
1311 void __init
pci_sort_breadthfirst(void)
1313 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);