2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <asm-generic/pci-bridge.h>
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
25 static struct resource busn_resource
= {
29 .flags
= IORESOURCE_BUS
,
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses
);
34 EXPORT_SYMBOL(pci_root_buses
);
36 static LIST_HEAD(pci_domain_busn_res_list
);
38 struct pci_domain_busn_res
{
39 struct list_head list
;
44 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
46 struct pci_domain_busn_res
*r
;
48 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
49 if (r
->domain_nr
== domain_nr
)
52 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
56 r
->domain_nr
= domain_nr
;
59 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
61 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
66 static int find_anything(struct device
*dev
, void *data
)
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
76 int no_pci_devices(void)
81 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
82 no_devices
= (dev
== NULL
);
86 EXPORT_SYMBOL(no_pci_devices
);
91 static void release_pcibus_dev(struct device
*dev
)
93 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
95 put_device(pci_bus
->bridge
);
96 pci_bus_remove_resources(pci_bus
);
97 pci_release_bus_of_node(pci_bus
);
101 static struct class pcibus_class
= {
103 .dev_release
= &release_pcibus_dev
,
104 .dev_groups
= pcibus_groups
,
107 static int __init
pcibus_class_init(void)
109 return class_register(&pcibus_class
);
111 postcore_initcall(pcibus_class_init
);
113 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
115 u64 size
= mask
& maxbase
; /* Find the significant bits */
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size
= (size
& ~(size
-1)) - 1;
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
131 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
136 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
137 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
138 flags
|= IORESOURCE_IO
;
142 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
143 flags
|= IORESOURCE_MEM
;
144 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
145 flags
|= IORESOURCE_PREFETCH
;
147 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
155 flags
|= IORESOURCE_MEM_64
;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
176 struct resource
*res
, unsigned int pos
)
179 u64 l64
, sz64
, mask64
;
181 struct pci_bus_region region
, inverted_region
;
183 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev
->mmio_always_on
) {
187 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
188 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
189 pci_write_config_word(dev
, PCI_COMMAND
,
190 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
194 res
->name
= pci_name(dev
);
196 pci_read_config_dword(dev
, pos
, &l
);
197 pci_write_config_dword(dev
, pos
, l
| mask
);
198 pci_read_config_dword(dev
, pos
, &sz
);
199 pci_write_config_dword(dev
, pos
, l
);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz
== 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type
== pci_bar_unknown
) {
218 res
->flags
= decode_bar(dev
, l
);
219 res
->flags
|= IORESOURCE_SIZEALIGN
;
220 if (res
->flags
& IORESOURCE_IO
) {
221 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
222 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
223 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
225 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
226 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
227 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
230 if (l
& PCI_ROM_ADDRESS_ENABLE
)
231 res
->flags
|= IORESOURCE_ROM_ENABLE
;
232 l64
= l
& PCI_ROM_ADDRESS_MASK
;
233 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
234 mask64
= (u32
)PCI_ROM_ADDRESS_MASK
;
237 if (res
->flags
& IORESOURCE_MEM_64
) {
238 pci_read_config_dword(dev
, pos
+ 4, &l
);
239 pci_write_config_dword(dev
, pos
+ 4, ~0);
240 pci_read_config_dword(dev
, pos
+ 4, &sz
);
241 pci_write_config_dword(dev
, pos
+ 4, l
);
243 l64
|= ((u64
)l
<< 32);
244 sz64
|= ((u64
)sz
<< 32);
245 mask64
|= ((u64
)~0 << 32);
248 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
249 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
254 sz64
= pci_size(l64
, sz64
, mask64
);
256 dev_info(&dev
->dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
261 if (res
->flags
& IORESOURCE_MEM_64
) {
262 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
263 && sz64
> 0x100000000ULL
) {
264 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
267 dev_err(&dev
->dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos
, (unsigned long long)sz64
);
272 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
273 /* Above 32-bit boundary; try to reallocate */
274 res
->flags
|= IORESOURCE_UNSET
;
277 dev_info(&dev
->dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos
, (unsigned long long)l64
);
284 region
.end
= l64
+ sz64
;
286 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
287 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
295 * resource_to_bus(bus_to_resource(A)) == A
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
300 if (inverted_region
.start
!= region
.start
) {
301 res
->flags
|= IORESOURCE_UNSET
;
303 res
->end
= region
.end
- region
.start
;
304 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos
, (unsigned long long)region
.start
);
315 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
317 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
320 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
322 unsigned int pos
, reg
;
324 if (dev
->non_compliant_bars
)
327 for (pos
= 0; pos
< howmany
; pos
++) {
328 struct resource
*res
= &dev
->resource
[pos
];
329 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
330 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
334 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
335 dev
->rom_base_reg
= rom
;
336 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
337 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
338 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
342 static void pci_read_bridge_io(struct pci_bus
*child
)
344 struct pci_dev
*dev
= child
->self
;
345 u8 io_base_lo
, io_limit_lo
;
346 unsigned long io_mask
, io_granularity
, base
, limit
;
347 struct pci_bus_region region
;
348 struct resource
*res
;
350 io_mask
= PCI_IO_RANGE_MASK
;
351 io_granularity
= 0x1000;
352 if (dev
->io_window_1k
) {
353 /* Support 1K I/O space granularity */
354 io_mask
= PCI_IO_1K_RANGE_MASK
;
355 io_granularity
= 0x400;
358 res
= child
->resource
[0];
359 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
360 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
361 base
= (io_base_lo
& io_mask
) << 8;
362 limit
= (io_limit_lo
& io_mask
) << 8;
364 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
365 u16 io_base_hi
, io_limit_hi
;
367 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
368 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
369 base
|= ((unsigned long) io_base_hi
<< 16);
370 limit
|= ((unsigned long) io_limit_hi
<< 16);
374 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
376 region
.end
= limit
+ io_granularity
- 1;
377 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
378 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
382 static void pci_read_bridge_mmio(struct pci_bus
*child
)
384 struct pci_dev
*dev
= child
->self
;
385 u16 mem_base_lo
, mem_limit_lo
;
386 unsigned long base
, limit
;
387 struct pci_bus_region region
;
388 struct resource
*res
;
390 res
= child
->resource
[1];
391 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
392 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
393 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
394 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
396 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
398 region
.end
= limit
+ 0xfffff;
399 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
400 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
404 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
406 struct pci_dev
*dev
= child
->self
;
407 u16 mem_base_lo
, mem_limit_lo
;
409 pci_bus_addr_t base
, limit
;
410 struct pci_bus_region region
;
411 struct resource
*res
;
413 res
= child
->resource
[2];
414 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
415 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
416 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
417 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
419 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
420 u32 mem_base_hi
, mem_limit_hi
;
422 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
423 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
430 if (mem_base_hi
<= mem_limit_hi
) {
431 base64
|= (u64
) mem_base_hi
<< 32;
432 limit64
|= (u64
) mem_limit_hi
<< 32;
436 base
= (pci_bus_addr_t
) base64
;
437 limit
= (pci_bus_addr_t
) limit64
;
439 if (base
!= base64
) {
440 dev_err(&dev
->dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64
);
446 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
447 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
448 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
449 res
->flags
|= IORESOURCE_MEM_64
;
451 region
.end
= limit
+ 0xfffff;
452 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
453 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
457 void pci_read_bridge_bases(struct pci_bus
*child
)
459 struct pci_dev
*dev
= child
->self
;
460 struct resource
*res
;
463 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
466 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
468 dev
->transparent
? " (subtractive decode)" : "");
470 pci_bus_remove_resources(child
);
471 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
472 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
474 pci_read_bridge_io(child
);
475 pci_read_bridge_mmio(child
);
476 pci_read_bridge_mmio_pref(child
);
478 if (dev
->transparent
) {
479 pci_bus_for_each_resource(child
->parent
, res
, i
) {
480 if (res
&& res
->flags
) {
481 pci_bus_add_resource(child
, res
,
482 PCI_SUBTRACTIVE_DECODE
);
483 dev_printk(KERN_DEBUG
, &dev
->dev
,
484 " bridge window %pR (subtractive decode)\n",
491 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
495 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
499 INIT_LIST_HEAD(&b
->node
);
500 INIT_LIST_HEAD(&b
->children
);
501 INIT_LIST_HEAD(&b
->devices
);
502 INIT_LIST_HEAD(&b
->slots
);
503 INIT_LIST_HEAD(&b
->resources
);
504 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
505 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
506 #ifdef CONFIG_PCI_DOMAINS_GENERIC
508 b
->domain_nr
= parent
->domain_nr
;
513 static void pci_release_host_bridge_dev(struct device
*dev
)
515 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
517 if (bridge
->release_fn
)
518 bridge
->release_fn(bridge
);
520 pci_free_resource_list(&bridge
->windows
);
525 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
527 struct pci_host_bridge
*bridge
;
529 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
533 INIT_LIST_HEAD(&bridge
->windows
);
538 static const unsigned char pcix_bus_speed
[] = {
539 PCI_SPEED_UNKNOWN
, /* 0 */
540 PCI_SPEED_66MHz_PCIX
, /* 1 */
541 PCI_SPEED_100MHz_PCIX
, /* 2 */
542 PCI_SPEED_133MHz_PCIX
, /* 3 */
543 PCI_SPEED_UNKNOWN
, /* 4 */
544 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
545 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
546 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
547 PCI_SPEED_UNKNOWN
, /* 8 */
548 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
549 PCI_SPEED_100MHz_PCIX_266
, /* A */
550 PCI_SPEED_133MHz_PCIX_266
, /* B */
551 PCI_SPEED_UNKNOWN
, /* C */
552 PCI_SPEED_66MHz_PCIX_533
, /* D */
553 PCI_SPEED_100MHz_PCIX_533
, /* E */
554 PCI_SPEED_133MHz_PCIX_533
/* F */
557 const unsigned char pcie_link_speed
[] = {
558 PCI_SPEED_UNKNOWN
, /* 0 */
559 PCIE_SPEED_2_5GT
, /* 1 */
560 PCIE_SPEED_5_0GT
, /* 2 */
561 PCIE_SPEED_8_0GT
, /* 3 */
562 PCI_SPEED_UNKNOWN
, /* 4 */
563 PCI_SPEED_UNKNOWN
, /* 5 */
564 PCI_SPEED_UNKNOWN
, /* 6 */
565 PCI_SPEED_UNKNOWN
, /* 7 */
566 PCI_SPEED_UNKNOWN
, /* 8 */
567 PCI_SPEED_UNKNOWN
, /* 9 */
568 PCI_SPEED_UNKNOWN
, /* A */
569 PCI_SPEED_UNKNOWN
, /* B */
570 PCI_SPEED_UNKNOWN
, /* C */
571 PCI_SPEED_UNKNOWN
, /* D */
572 PCI_SPEED_UNKNOWN
, /* E */
573 PCI_SPEED_UNKNOWN
/* F */
576 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
578 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
580 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
582 static unsigned char agp_speeds
[] = {
590 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
596 else if (agpstat
& 2)
598 else if (agpstat
& 1)
610 return agp_speeds
[index
];
613 static void pci_set_bus_speed(struct pci_bus
*bus
)
615 struct pci_dev
*bridge
= bus
->self
;
618 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
620 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
624 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
625 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
627 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
628 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
631 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
634 enum pci_bus_speed max
;
636 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
639 if (status
& PCI_X_SSTATUS_533MHZ
) {
640 max
= PCI_SPEED_133MHz_PCIX_533
;
641 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
642 max
= PCI_SPEED_133MHz_PCIX_266
;
643 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
644 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
645 max
= PCI_SPEED_133MHz_PCIX_ECC
;
647 max
= PCI_SPEED_133MHz_PCIX
;
649 max
= PCI_SPEED_66MHz_PCIX
;
652 bus
->max_bus_speed
= max
;
653 bus
->cur_bus_speed
= pcix_bus_speed
[
654 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
659 if (pci_is_pcie(bridge
)) {
663 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
664 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
666 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
667 pcie_update_link_speed(bus
, linksta
);
671 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
673 struct irq_domain
*d
;
676 * Any firmware interface that can resolve the msi_domain
677 * should be called from here.
679 d
= pci_host_bridge_of_msi_domain(bus
);
681 d
= pci_host_bridge_acpi_msi_domain(bus
);
683 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
685 * If no IRQ domain was found via the OF tree, try looking it up
686 * directly through the fwnode_handle.
689 struct fwnode_handle
*fwnode
= pci_root_bus_fwnode(bus
);
692 d
= irq_find_matching_fwnode(fwnode
,
700 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
702 struct irq_domain
*d
;
706 * The bus can be a root bus, a subordinate bus, or a virtual bus
707 * created by an SR-IOV device. Walk up to the first bridge device
708 * found or derive the domain from the host bridge.
710 for (b
= bus
, d
= NULL
; !d
&& !pci_is_root_bus(b
); b
= b
->parent
) {
712 d
= dev_get_msi_domain(&b
->self
->dev
);
716 d
= pci_host_bridge_msi_domain(b
);
718 dev_set_msi_domain(&bus
->dev
, d
);
721 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
722 struct pci_dev
*bridge
, int busnr
)
724 struct pci_bus
*child
;
729 * Allocate a new bus, and inherit stuff from the parent..
731 child
= pci_alloc_bus(parent
);
735 child
->parent
= parent
;
736 child
->ops
= parent
->ops
;
737 child
->msi
= parent
->msi
;
738 child
->sysdata
= parent
->sysdata
;
739 child
->bus_flags
= parent
->bus_flags
;
741 /* initialize some portions of the bus device, but don't register it
742 * now as the parent is not properly set up yet.
744 child
->dev
.class = &pcibus_class
;
745 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
748 * Set up the primary, secondary and subordinate
751 child
->number
= child
->busn_res
.start
= busnr
;
752 child
->primary
= parent
->busn_res
.start
;
753 child
->busn_res
.end
= 0xff;
756 child
->dev
.parent
= parent
->bridge
;
760 child
->self
= bridge
;
761 child
->bridge
= get_device(&bridge
->dev
);
762 child
->dev
.parent
= child
->bridge
;
763 pci_set_bus_of_node(child
);
764 pci_set_bus_speed(child
);
766 /* Set up default resource pointers and names.. */
767 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
768 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
769 child
->resource
[i
]->name
= child
->name
;
771 bridge
->subordinate
= child
;
774 pci_set_bus_msi_domain(child
);
775 ret
= device_register(&child
->dev
);
778 pcibios_add_bus(child
);
780 /* Create legacy_io and legacy_mem files for this bus */
781 pci_create_legacy_files(child
);
786 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
789 struct pci_bus
*child
;
791 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
793 down_write(&pci_bus_sem
);
794 list_add_tail(&child
->node
, &parent
->children
);
795 up_write(&pci_bus_sem
);
799 EXPORT_SYMBOL(pci_add_new_bus
);
801 static void pci_enable_crs(struct pci_dev
*pdev
)
805 /* Enable CRS Software Visibility if supported */
806 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
807 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
808 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
809 PCI_EXP_RTCTL_CRSSVE
);
813 * If it's a bridge, configure it and scan the bus behind it.
814 * For CardBus bridges, we don't scan behind as the devices will
815 * be handled by the bridge driver itself.
817 * We need to process bridges in two passes -- first we scan those
818 * already configured by the BIOS and after we are done with all of
819 * them, we proceed to assigning numbers to the remaining buses in
820 * order to avoid overlaps between old and new bus numbers.
822 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
824 struct pci_bus
*child
;
825 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
828 u8 primary
, secondary
, subordinate
;
831 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
832 primary
= buses
& 0xFF;
833 secondary
= (buses
>> 8) & 0xFF;
834 subordinate
= (buses
>> 16) & 0xFF;
836 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
837 secondary
, subordinate
, pass
);
839 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
840 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
841 primary
= bus
->number
;
844 /* Check if setup is sensible at all */
846 (primary
!= bus
->number
|| secondary
<= bus
->number
||
847 secondary
> subordinate
)) {
848 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
849 secondary
, subordinate
);
853 /* Disable MasterAbortMode during probing to avoid reporting
854 of bus errors (in some architectures) */
855 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
856 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
857 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
861 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
862 !is_cardbus
&& !broken
) {
865 * Bus already configured by firmware, process it in the first
866 * pass and just note the configuration.
872 * The bus might already exist for two reasons: Either we are
873 * rescanning the bus or the bus is reachable through more than
874 * one bridge. The second case can happen with the i450NX
877 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
879 child
= pci_add_new_bus(bus
, dev
, secondary
);
882 child
->primary
= primary
;
883 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
884 child
->bridge_ctl
= bctl
;
887 cmax
= pci_scan_child_bus(child
);
888 if (cmax
> subordinate
)
889 dev_warn(&dev
->dev
, "bridge has subordinate %02x but max busn %02x\n",
891 /* subordinate should equal child->busn_res.end */
892 if (subordinate
> max
)
896 * We need to assign a number to this bus which we always
897 * do in the second pass.
900 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
901 /* Temporarily disable forwarding of the
902 configuration cycles on all bridges in
903 this bus segment to avoid possible
904 conflicts in the second pass between two
905 bridges programmed with overlapping
907 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
913 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
915 /* Prevent assigning a bus number that already exists.
916 * This can happen when a bridge is hot-plugged, so in
917 * this case we only re-scan this bus. */
918 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
920 child
= pci_add_new_bus(bus
, dev
, max
+1);
923 pci_bus_insert_busn_res(child
, max
+1, 0xff);
926 buses
= (buses
& 0xff000000)
927 | ((unsigned int)(child
->primary
) << 0)
928 | ((unsigned int)(child
->busn_res
.start
) << 8)
929 | ((unsigned int)(child
->busn_res
.end
) << 16);
932 * yenta.c forces a secondary latency timer of 176.
933 * Copy that behaviour here.
936 buses
&= ~0xff000000;
937 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
941 * We need to blast all three values with a single write.
943 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
946 child
->bridge_ctl
= bctl
;
947 max
= pci_scan_child_bus(child
);
950 * For CardBus bridges, we leave 4 bus numbers
951 * as cards with a PCI-to-PCI bridge can be
954 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
955 struct pci_bus
*parent
= bus
;
956 if (pci_find_bus(pci_domain_nr(bus
),
959 while (parent
->parent
) {
960 if ((!pcibios_assign_all_busses()) &&
961 (parent
->busn_res
.end
> max
) &&
962 (parent
->busn_res
.end
<= max
+i
)) {
965 parent
= parent
->parent
;
969 * Often, there are two cardbus bridges
970 * -- try to leave one valid bus number
980 * Set the subordinate bus number to its real value.
982 pci_bus_update_busn_res_end(child
, max
);
983 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
987 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
988 pci_domain_nr(bus
), child
->number
);
990 /* Has only triggered on CardBus, fixup is in yenta_socket */
991 while (bus
->parent
) {
992 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
993 (child
->number
> bus
->busn_res
.end
) ||
994 (child
->number
< bus
->number
) ||
995 (child
->busn_res
.end
< bus
->number
)) {
996 dev_info(&child
->dev
, "%pR %s hidden behind%s bridge %s %pR\n",
998 (bus
->number
> child
->busn_res
.end
&&
999 bus
->busn_res
.end
< child
->number
) ?
1000 "wholly" : "partially",
1001 bus
->self
->transparent
? " transparent" : "",
1002 dev_name(&bus
->dev
),
1009 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
1013 EXPORT_SYMBOL(pci_scan_bridge
);
1016 * Read interrupt line and base address registers.
1017 * The architecture-dependent code can tweak these, of course.
1019 static void pci_read_irq(struct pci_dev
*dev
)
1023 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1026 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1030 void set_pcie_port_type(struct pci_dev
*pdev
)
1035 struct pci_dev
*parent
;
1037 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1041 pdev
->pcie_cap
= pos
;
1042 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1043 pdev
->pcie_flags_reg
= reg16
;
1044 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
1045 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
1048 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1049 * of a Link. No PCIe component has two Links. Two Links are
1050 * connected by a Switch that has a Port on each Link and internal
1051 * logic to connect the two Ports.
1053 type
= pci_pcie_type(pdev
);
1054 if (type
== PCI_EXP_TYPE_ROOT_PORT
||
1055 type
== PCI_EXP_TYPE_PCIE_BRIDGE
)
1056 pdev
->has_secondary_link
= 1;
1057 else if (type
== PCI_EXP_TYPE_UPSTREAM
||
1058 type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1059 parent
= pci_upstream_bridge(pdev
);
1062 * Usually there's an upstream device (Root Port or Switch
1063 * Downstream Port), but we can't assume one exists.
1065 if (parent
&& !parent
->has_secondary_link
)
1066 pdev
->has_secondary_link
= 1;
1070 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1074 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1075 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1076 pdev
->is_hotplug_bridge
= 1;
1080 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1083 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1084 * when forwarding a type1 configuration request the bridge must check that
1085 * the extended register address field is zero. The bridge is not permitted
1086 * to forward the transactions and must handle it as an Unsupported Request.
1087 * Some bridges do not follow this rule and simply drop the extended register
1088 * bits, resulting in the standard config space being aliased, every 256
1089 * bytes across the entire configuration space. Test for this condition by
1090 * comparing the first dword of each potential alias to the vendor/device ID.
1092 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1093 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1095 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1097 #ifdef CONFIG_PCI_QUIRKS
1101 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1103 for (pos
= PCI_CFG_SPACE_SIZE
;
1104 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1105 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1117 * pci_cfg_space_size - get the configuration space size of the PCI device.
1120 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1121 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1122 * access it. Maybe we don't have a way to generate extended config space
1123 * accesses, or the device is behind a reverse Express bridge. So we try
1124 * reading the dword at 0x100 which must either be 0 or a valid extended
1125 * capability header.
1127 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1130 int pos
= PCI_CFG_SPACE_SIZE
;
1132 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1134 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1137 return PCI_CFG_SPACE_EXP_SIZE
;
1140 return PCI_CFG_SPACE_SIZE
;
1143 int pci_cfg_space_size(struct pci_dev
*dev
)
1149 class = dev
->class >> 8;
1150 if (class == PCI_CLASS_BRIDGE_HOST
)
1151 return pci_cfg_space_size_ext(dev
);
1153 if (!pci_is_pcie(dev
)) {
1154 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1158 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1159 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1163 return pci_cfg_space_size_ext(dev
);
1166 return PCI_CFG_SPACE_SIZE
;
1169 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1171 void pci_msi_setup_pci_dev(struct pci_dev
*dev
)
1174 * Disable the MSI hardware to avoid screaming interrupts
1175 * during boot. This is the power on reset default so
1176 * usually this should be a noop.
1178 dev
->msi_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
1180 pci_msi_set_enable(dev
, 0);
1182 dev
->msix_cap
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
1184 pci_msix_clear_and_set_ctrl(dev
, PCI_MSIX_FLAGS_ENABLE
, 0);
1188 * pci_setup_device - fill in class and map information of a device
1189 * @dev: the device structure to fill
1191 * Initialize the device structure with information about the device's
1192 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1193 * Called at initialisation of the PCI subsystem and by CardBus services.
1194 * Returns 0 on success and negative if unknown type of device (not normal,
1195 * bridge or CardBus).
1197 int pci_setup_device(struct pci_dev
*dev
)
1203 struct pci_bus_region region
;
1204 struct resource
*res
;
1206 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1209 dev
->sysdata
= dev
->bus
->sysdata
;
1210 dev
->dev
.parent
= dev
->bus
->bridge
;
1211 dev
->dev
.bus
= &pci_bus_type
;
1212 dev
->hdr_type
= hdr_type
& 0x7f;
1213 dev
->multifunction
= !!(hdr_type
& 0x80);
1214 dev
->error_state
= pci_channel_io_normal
;
1215 set_pcie_port_type(dev
);
1217 pci_dev_assign_slot(dev
);
1218 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1219 set this higher, assuming the system even supports it. */
1220 dev
->dma_mask
= 0xffffffff;
1222 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1223 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1224 PCI_FUNC(dev
->devfn
));
1226 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1227 dev
->revision
= class & 0xff;
1228 dev
->class = class >> 8; /* upper 3 bytes */
1230 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1231 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1233 /* need to have dev->class ready */
1234 dev
->cfg_size
= pci_cfg_space_size(dev
);
1236 /* "Unknown power state" */
1237 dev
->current_state
= PCI_UNKNOWN
;
1239 pci_msi_setup_pci_dev(dev
);
1241 /* Early fixups, before probing the BARs */
1242 pci_fixup_device(pci_fixup_early
, dev
);
1243 /* device class may be changed after fixup */
1244 class = dev
->class >> 8;
1246 if (dev
->non_compliant_bars
) {
1247 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1248 if (cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) {
1249 dev_info(&dev
->dev
, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1250 cmd
&= ~PCI_COMMAND_IO
;
1251 cmd
&= ~PCI_COMMAND_MEMORY
;
1252 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1256 switch (dev
->hdr_type
) { /* header type */
1257 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1258 if (class == PCI_CLASS_BRIDGE_PCI
)
1261 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1262 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1263 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1266 * Do the ugly legacy mode stuff here rather than broken chip
1267 * quirk code. Legacy mode ATA controllers have fixed
1268 * addresses. These are not always echoed in BAR0-3, and
1269 * BAR0-3 in a few cases contain junk!
1271 if (class == PCI_CLASS_STORAGE_IDE
) {
1273 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1274 if ((progif
& 1) == 0) {
1275 region
.start
= 0x1F0;
1277 res
= &dev
->resource
[0];
1278 res
->flags
= LEGACY_IO_RESOURCE
;
1279 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1280 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1282 region
.start
= 0x3F6;
1284 res
= &dev
->resource
[1];
1285 res
->flags
= LEGACY_IO_RESOURCE
;
1286 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1287 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1290 if ((progif
& 4) == 0) {
1291 region
.start
= 0x170;
1293 res
= &dev
->resource
[2];
1294 res
->flags
= LEGACY_IO_RESOURCE
;
1295 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1296 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1298 region
.start
= 0x376;
1300 res
= &dev
->resource
[3];
1301 res
->flags
= LEGACY_IO_RESOURCE
;
1302 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1303 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1309 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1310 if (class != PCI_CLASS_BRIDGE_PCI
)
1312 /* The PCI-to-PCI bridge spec requires that subtractive
1313 decoding (i.e. transparent) bridge must have programming
1314 interface code of 0x01. */
1316 dev
->transparent
= ((dev
->class & 0xff) == 1);
1317 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1318 set_pcie_hotplug_bridge(dev
);
1319 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1321 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1322 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1326 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1327 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1330 pci_read_bases(dev
, 1, 0);
1331 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1332 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1335 default: /* unknown header */
1336 dev_err(&dev
->dev
, "unknown header type %02x, ignoring device\n",
1341 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1342 dev
->class, dev
->hdr_type
);
1343 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
1346 /* We found a fine healthy device, go go go... */
1350 static void pci_configure_mps(struct pci_dev
*dev
)
1352 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
1355 if (!pci_is_pcie(dev
) || !bridge
|| !pci_is_pcie(bridge
))
1358 mps
= pcie_get_mps(dev
);
1359 p_mps
= pcie_get_mps(bridge
);
1364 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1365 dev_warn(&dev
->dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1366 mps
, pci_name(bridge
), p_mps
);
1371 * Fancier MPS configuration is done later by
1372 * pcie_bus_configure_settings()
1374 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
1377 rc
= pcie_set_mps(dev
, p_mps
);
1379 dev_warn(&dev
->dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1384 dev_info(&dev
->dev
, "Max Payload Size set to %d (was %d, max %d)\n",
1385 p_mps
, mps
, 128 << dev
->pcie_mpss
);
1388 static struct hpp_type0 pci_default_type0
= {
1390 .cache_line_size
= 8,
1391 .latency_timer
= 0x40,
1396 static void program_hpp_type0(struct pci_dev
*dev
, struct hpp_type0
*hpp
)
1398 u16 pci_cmd
, pci_bctl
;
1401 hpp
= &pci_default_type0
;
1403 if (hpp
->revision
> 1) {
1405 "PCI settings rev %d not supported; using defaults\n",
1407 hpp
= &pci_default_type0
;
1410 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, hpp
->cache_line_size
);
1411 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, hpp
->latency_timer
);
1412 pci_read_config_word(dev
, PCI_COMMAND
, &pci_cmd
);
1413 if (hpp
->enable_serr
)
1414 pci_cmd
|= PCI_COMMAND_SERR
;
1415 if (hpp
->enable_perr
)
1416 pci_cmd
|= PCI_COMMAND_PARITY
;
1417 pci_write_config_word(dev
, PCI_COMMAND
, pci_cmd
);
1419 /* Program bridge control value */
1420 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1421 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
,
1422 hpp
->latency_timer
);
1423 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &pci_bctl
);
1424 if (hpp
->enable_serr
)
1425 pci_bctl
|= PCI_BRIDGE_CTL_SERR
;
1426 if (hpp
->enable_perr
)
1427 pci_bctl
|= PCI_BRIDGE_CTL_PARITY
;
1428 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, pci_bctl
);
1432 static void program_hpp_type1(struct pci_dev
*dev
, struct hpp_type1
*hpp
)
1435 dev_warn(&dev
->dev
, "PCI-X settings not supported\n");
1438 static bool pcie_root_rcb_set(struct pci_dev
*dev
)
1440 struct pci_dev
*rp
= pcie_find_root_port(dev
);
1446 pcie_capability_read_word(rp
, PCI_EXP_LNKCTL
, &lnkctl
);
1447 if (lnkctl
& PCI_EXP_LNKCTL_RCB
)
1453 static void program_hpp_type2(struct pci_dev
*dev
, struct hpp_type2
*hpp
)
1461 if (hpp
->revision
> 1) {
1462 dev_warn(&dev
->dev
, "PCIe settings rev %d not supported\n",
1468 * Don't allow _HPX to change MPS or MRRS settings. We manage
1469 * those to make sure they're consistent with the rest of the
1472 hpp
->pci_exp_devctl_and
|= PCI_EXP_DEVCTL_PAYLOAD
|
1473 PCI_EXP_DEVCTL_READRQ
;
1474 hpp
->pci_exp_devctl_or
&= ~(PCI_EXP_DEVCTL_PAYLOAD
|
1475 PCI_EXP_DEVCTL_READRQ
);
1477 /* Initialize Device Control Register */
1478 pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
1479 ~hpp
->pci_exp_devctl_and
, hpp
->pci_exp_devctl_or
);
1481 /* Initialize Link Control Register */
1482 if (pcie_cap_has_lnkctl(dev
)) {
1485 * If the Root Port supports Read Completion Boundary of
1486 * 128, set RCB to 128. Otherwise, clear it.
1488 hpp
->pci_exp_lnkctl_and
|= PCI_EXP_LNKCTL_RCB
;
1489 hpp
->pci_exp_lnkctl_or
&= ~PCI_EXP_LNKCTL_RCB
;
1490 if (pcie_root_rcb_set(dev
))
1491 hpp
->pci_exp_lnkctl_or
|= PCI_EXP_LNKCTL_RCB
;
1493 pcie_capability_clear_and_set_word(dev
, PCI_EXP_LNKCTL
,
1494 ~hpp
->pci_exp_lnkctl_and
, hpp
->pci_exp_lnkctl_or
);
1497 /* Find Advanced Error Reporting Enhanced Capability */
1498 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
1502 /* Initialize Uncorrectable Error Mask Register */
1503 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, ®32
);
1504 reg32
= (reg32
& hpp
->unc_err_mask_and
) | hpp
->unc_err_mask_or
;
1505 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, reg32
);
1507 /* Initialize Uncorrectable Error Severity Register */
1508 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, ®32
);
1509 reg32
= (reg32
& hpp
->unc_err_sever_and
) | hpp
->unc_err_sever_or
;
1510 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, reg32
);
1512 /* Initialize Correctable Error Mask Register */
1513 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®32
);
1514 reg32
= (reg32
& hpp
->cor_err_mask_and
) | hpp
->cor_err_mask_or
;
1515 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg32
);
1517 /* Initialize Advanced Error Capabilities and Control Register */
1518 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
1519 reg32
= (reg32
& hpp
->adv_err_cap_and
) | hpp
->adv_err_cap_or
;
1520 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
1523 * FIXME: The following two registers are not supported yet.
1525 * o Secondary Uncorrectable Error Severity Register
1526 * o Secondary Uncorrectable Error Mask Register
1530 static void pci_configure_device(struct pci_dev
*dev
)
1532 struct hotplug_params hpp
;
1535 pci_configure_mps(dev
);
1537 memset(&hpp
, 0, sizeof(hpp
));
1538 ret
= pci_get_hp_params(dev
, &hpp
);
1542 program_hpp_type2(dev
, hpp
.t2
);
1543 program_hpp_type1(dev
, hpp
.t1
);
1544 program_hpp_type0(dev
, hpp
.t0
);
1547 static void pci_release_capabilities(struct pci_dev
*dev
)
1549 pci_vpd_release(dev
);
1550 pci_iov_release(dev
);
1551 pci_free_cap_save_buffers(dev
);
1555 * pci_release_dev - free a pci device structure when all users of it are finished.
1556 * @dev: device that's been disconnected
1558 * Will be called only by the device core when all users of this pci device are
1561 static void pci_release_dev(struct device
*dev
)
1563 struct pci_dev
*pci_dev
;
1565 pci_dev
= to_pci_dev(dev
);
1566 pci_release_capabilities(pci_dev
);
1567 pci_release_of_node(pci_dev
);
1568 pcibios_release_device(pci_dev
);
1569 pci_bus_put(pci_dev
->bus
);
1570 kfree(pci_dev
->driver_override
);
1574 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1576 struct pci_dev
*dev
;
1578 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1582 INIT_LIST_HEAD(&dev
->bus_list
);
1583 dev
->dev
.type
= &pci_dev_type
;
1584 dev
->bus
= pci_bus_get(bus
);
1588 EXPORT_SYMBOL(pci_alloc_dev
);
1590 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1595 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1598 /* some broken boards return 0 or ~0 if a slot is empty: */
1599 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1600 *l
== 0x0000ffff || *l
== 0xffff0000)
1604 * Configuration Request Retry Status. Some root ports return the
1605 * actual device ID instead of the synthetic ID (0xFFFF) required
1606 * by the PCIe spec. Ignore the device ID and only check for
1609 while ((*l
& 0xffff) == 0x0001) {
1615 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1617 /* Card hasn't responded in 60 seconds? Must be stuck. */
1618 if (delay
> crs_timeout
) {
1619 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not responding\n",
1620 pci_domain_nr(bus
), bus
->number
, PCI_SLOT(devfn
),
1628 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1631 * Read the config data for a PCI device, sanity-check it
1632 * and fill in the dev structure...
1634 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1636 struct pci_dev
*dev
;
1639 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1642 dev
= pci_alloc_dev(bus
);
1647 dev
->vendor
= l
& 0xffff;
1648 dev
->device
= (l
>> 16) & 0xffff;
1650 pci_set_of_node(dev
);
1652 if (pci_setup_device(dev
)) {
1653 pci_bus_put(dev
->bus
);
1661 static void pci_init_capabilities(struct pci_dev
*dev
)
1663 /* Enhanced Allocation */
1666 /* MSI/MSI-X list */
1667 pci_msi_init_pci_dev(dev
);
1669 /* Buffers for saving PCIe and PCI-X capabilities */
1670 pci_allocate_cap_save_buffers(dev
);
1672 /* Power Management */
1675 /* Vital Product Data */
1676 pci_vpd_pci22_init(dev
);
1678 /* Alternative Routing-ID Forwarding */
1679 pci_configure_ari(dev
);
1681 /* Single Root I/O Virtualization */
1684 /* Address Translation Services */
1687 /* Enable ACS P2P upstream forwarding */
1688 pci_enable_acs(dev
);
1690 pci_cleanup_aer_error_status_regs(dev
);
1694 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1695 * devices. Firmware interfaces that can select the MSI domain on a
1696 * per-device basis should be called from here.
1698 static struct irq_domain
*pci_dev_msi_domain(struct pci_dev
*dev
)
1700 struct irq_domain
*d
;
1703 * If a domain has been set through the pcibios_add_device
1704 * callback, then this is the one (platform code knows best).
1706 d
= dev_get_msi_domain(&dev
->dev
);
1711 * Let's see if we have a firmware interface able to provide
1714 d
= pci_msi_get_device_domain(dev
);
1721 static void pci_set_msi_domain(struct pci_dev
*dev
)
1723 struct irq_domain
*d
;
1726 * If the platform or firmware interfaces cannot supply a
1727 * device-specific MSI domain, then inherit the default domain
1728 * from the host bridge itself.
1730 d
= pci_dev_msi_domain(dev
);
1732 d
= dev_get_msi_domain(&dev
->bus
->dev
);
1734 dev_set_msi_domain(&dev
->dev
, d
);
1738 * pci_dma_configure - Setup DMA configuration
1739 * @dev: ptr to pci_dev struct of the PCI device
1741 * Function to update PCI devices's DMA configuration using the same
1742 * info from the OF node or ACPI node of host bridge's parent (if any).
1744 static void pci_dma_configure(struct pci_dev
*dev
)
1746 struct device
*bridge
= pci_get_host_bridge_device(dev
);
1748 if (IS_ENABLED(CONFIG_OF
) &&
1749 bridge
->parent
&& bridge
->parent
->of_node
) {
1750 of_dma_configure_masks(&dev
->dev
, bridge
->parent
->of_node
);
1751 of_dma_configure_ops(&dev
->dev
, bridge
->parent
->of_node
);
1752 } else if (has_acpi_companion(bridge
)) {
1753 struct acpi_device
*adev
= to_acpi_device_node(bridge
->fwnode
);
1754 enum dev_dma_attr attr
= acpi_get_dma_attr(adev
);
1756 if (attr
== DEV_DMA_NOT_SUPPORTED
)
1757 dev_warn(&dev
->dev
, "DMA not supported.\n");
1759 arch_setup_dma_ops(&dev
->dev
, 0, 0, NULL
,
1760 attr
== DEV_DMA_COHERENT
);
1763 pci_put_host_bridge_device(bridge
);
1766 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1770 pci_configure_device(dev
);
1772 device_initialize(&dev
->dev
);
1773 dev
->dev
.release
= pci_release_dev
;
1775 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1776 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1777 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1778 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1779 pci_dma_configure(dev
);
1781 pci_set_dma_max_seg_size(dev
, 65536);
1782 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1784 /* Fix up broken headers */
1785 pci_fixup_device(pci_fixup_header
, dev
);
1787 /* moved out from quirk header fixup code */
1788 pci_reassigndev_resource_alignment(dev
);
1790 /* Clear the state_saved flag. */
1791 dev
->state_saved
= false;
1793 /* Initialize various capabilities */
1794 pci_init_capabilities(dev
);
1797 * Add the device to our list of discovered devices
1798 * and the bus list for fixup functions, etc.
1800 down_write(&pci_bus_sem
);
1801 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1802 up_write(&pci_bus_sem
);
1804 ret
= pcibios_add_device(dev
);
1807 /* Setup MSI irq domain */
1808 pci_set_msi_domain(dev
);
1810 /* Notifier could use PCI capabilities */
1811 dev
->match_driver
= false;
1812 ret
= device_add(&dev
->dev
);
1816 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1818 struct pci_dev
*dev
;
1820 dev
= pci_get_slot(bus
, devfn
);
1826 dev
= pci_scan_device(bus
, devfn
);
1830 pci_device_add(dev
, bus
);
1834 EXPORT_SYMBOL(pci_scan_single_device
);
1836 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1842 if (pci_ari_enabled(bus
)) {
1845 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1849 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1850 next_fn
= PCI_ARI_CAP_NFN(cap
);
1852 return 0; /* protect against malformed list */
1857 /* dev may be NULL for non-contiguous multifunction devices */
1858 if (!dev
|| dev
->multifunction
)
1859 return (fn
+ 1) % 8;
1864 static int only_one_child(struct pci_bus
*bus
)
1866 struct pci_dev
*parent
= bus
->self
;
1868 if (!parent
|| !pci_is_pcie(parent
))
1870 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1872 if (parent
->has_secondary_link
&&
1873 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1879 * pci_scan_slot - scan a PCI slot on a bus for devices.
1880 * @bus: PCI bus to scan
1881 * @devfn: slot number to scan (must have zero function.)
1883 * Scan a PCI slot on the specified PCI bus for devices, adding
1884 * discovered devices to the @bus->devices list. New devices
1885 * will not have is_added set.
1887 * Returns the number of new devices found.
1889 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1891 unsigned fn
, nr
= 0;
1892 struct pci_dev
*dev
;
1894 if (only_one_child(bus
) && (devfn
> 0))
1895 return 0; /* Already scanned the entire slot */
1897 dev
= pci_scan_single_device(bus
, devfn
);
1903 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1904 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1908 dev
->multifunction
= 1;
1912 /* only one slot has pcie device */
1913 if (bus
->self
&& nr
)
1914 pcie_aspm_init_link_state(bus
->self
);
1918 EXPORT_SYMBOL(pci_scan_slot
);
1920 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1924 if (!pci_is_pcie(dev
))
1928 * We don't have a way to change MPS settings on devices that have
1929 * drivers attached. A hot-added device might support only the minimum
1930 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1931 * where devices may be hot-added, we limit the fabric MPS to 128 so
1932 * hot-added devices will work correctly.
1934 * However, if we hot-add a device to a slot directly below a Root
1935 * Port, it's impossible for there to be other existing devices below
1936 * the port. We don't limit the MPS in this case because we can
1937 * reconfigure MPS on both the Root Port and the hot-added device,
1938 * and there are no other devices involved.
1940 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1942 if (dev
->is_hotplug_bridge
&&
1943 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1946 if (*smpss
> dev
->pcie_mpss
)
1947 *smpss
= dev
->pcie_mpss
;
1952 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1956 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1957 mps
= 128 << dev
->pcie_mpss
;
1959 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1961 /* For "Performance", the assumption is made that
1962 * downstream communication will never be larger than
1963 * the MRRS. So, the MPS only needs to be configured
1964 * for the upstream communication. This being the case,
1965 * walk from the top down and set the MPS of the child
1966 * to that of the parent bus.
1968 * Configure the device MPS with the smaller of the
1969 * device MPSS or the bridge MPS (which is assumed to be
1970 * properly configured at this point to the largest
1971 * allowable MPS based on its parent bus).
1973 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1976 rc
= pcie_set_mps(dev
, mps
);
1978 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1981 static void pcie_write_mrrs(struct pci_dev
*dev
)
1985 /* In the "safe" case, do not configure the MRRS. There appear to be
1986 * issues with setting MRRS to 0 on a number of devices.
1988 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1991 /* For Max performance, the MRRS must be set to the largest supported
1992 * value. However, it cannot be configured larger than the MPS the
1993 * device or the bus can support. This should already be properly
1994 * configured by a prior call to pcie_write_mps.
1996 mrrs
= pcie_get_mps(dev
);
1998 /* MRRS is a R/W register. Invalid values can be written, but a
1999 * subsequent read will verify if the value is acceptable or not.
2000 * If the MRRS value provided is not acceptable (e.g., too large),
2001 * shrink the value until it is acceptable to the HW.
2003 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
2004 rc
= pcie_set_readrq(dev
, mrrs
);
2008 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
2013 dev_err(&dev
->dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2016 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
2020 if (!pci_is_pcie(dev
))
2023 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
2024 pcie_bus_config
== PCIE_BUS_DEFAULT
)
2027 mps
= 128 << *(u8
*)data
;
2028 orig_mps
= pcie_get_mps(dev
);
2030 pcie_write_mps(dev
, mps
);
2031 pcie_write_mrrs(dev
);
2033 dev_info(&dev
->dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2034 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
2035 orig_mps
, pcie_get_readrq(dev
));
2040 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2041 * parents then children fashion. If this changes, then this code will not
2044 void pcie_bus_configure_settings(struct pci_bus
*bus
)
2051 if (!pci_is_pcie(bus
->self
))
2054 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2055 * to be aware of the MPS of the destination. To work around this,
2056 * simply force the MPS of the entire system to the smallest possible.
2058 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2061 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
2062 smpss
= bus
->self
->pcie_mpss
;
2064 pcie_find_smpss(bus
->self
, &smpss
);
2065 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
2068 pcie_bus_configure_set(bus
->self
, &smpss
);
2069 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
2071 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
2073 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
2075 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
2076 struct pci_dev
*dev
;
2078 dev_dbg(&bus
->dev
, "scanning bus\n");
2080 /* Go find them, Rover! */
2081 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
2082 pci_scan_slot(bus
, devfn
);
2084 /* Reserve buses for SR-IOV capability. */
2085 max
+= pci_iov_bus_range(bus
);
2088 * After performing arch-dependent fixup of the bus, look behind
2089 * all PCI-to-PCI bridges on this bus.
2091 if (!bus
->is_added
) {
2092 dev_dbg(&bus
->dev
, "fixups for bus\n");
2093 pcibios_fixup_bus(bus
);
2097 for (pass
= 0; pass
< 2; pass
++)
2098 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
2099 if (pci_is_bridge(dev
))
2100 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
2104 * We've scanned the bus and so we know all about what's on
2105 * the other side of any bridges that may be on this bus plus
2108 * Return how far we've got finding sub-buses.
2110 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
2113 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
2116 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2117 * @bridge: Host bridge to set up.
2119 * Default empty implementation. Replace with an architecture-specific setup
2120 * routine, if necessary.
2122 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
2127 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
2131 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
2135 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
2136 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2139 struct pci_host_bridge
*bridge
;
2140 struct pci_bus
*b
, *b2
;
2141 struct resource_entry
*window
, *n
;
2142 struct resource
*res
;
2143 resource_size_t offset
;
2147 b
= pci_alloc_bus(NULL
);
2151 b
->sysdata
= sysdata
;
2153 b
->number
= b
->busn_res
.start
= bus
;
2154 pci_bus_assign_domain_nr(b
, parent
);
2155 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
2157 /* If we already got to this bus through a different bridge, ignore it */
2158 dev_dbg(&b2
->dev
, "bus already known\n");
2162 bridge
= pci_alloc_host_bridge(b
);
2166 bridge
->dev
.parent
= parent
;
2167 bridge
->dev
.release
= pci_release_host_bridge_dev
;
2168 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
2169 error
= pcibios_root_bridge_prepare(bridge
);
2175 error
= device_register(&bridge
->dev
);
2177 put_device(&bridge
->dev
);
2180 b
->bridge
= get_device(&bridge
->dev
);
2181 device_enable_async_suspend(b
->bridge
);
2182 pci_set_bus_of_node(b
);
2183 pci_set_bus_msi_domain(b
);
2186 set_dev_node(b
->bridge
, pcibus_to_node(b
));
2188 b
->dev
.class = &pcibus_class
;
2189 b
->dev
.parent
= b
->bridge
;
2190 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
2191 error
= device_register(&b
->dev
);
2193 goto class_dev_reg_err
;
2197 /* Create legacy_io and legacy_mem files for this bus */
2198 pci_create_legacy_files(b
);
2201 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2203 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
2205 /* Add initial resources to the bus */
2206 resource_list_for_each_entry_safe(window
, n
, resources
) {
2207 list_move_tail(&window
->node
, &bridge
->windows
);
2209 offset
= window
->offset
;
2210 if (res
->flags
& IORESOURCE_BUS
)
2211 pci_bus_insert_busn_res(b
, bus
, res
->end
);
2213 pci_bus_add_resource(b
, res
, 0);
2215 if (resource_type(res
) == IORESOURCE_IO
)
2216 fmt
= " (bus address [%#06llx-%#06llx])";
2218 fmt
= " (bus address [%#010llx-%#010llx])";
2219 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
2220 (unsigned long long) (res
->start
- offset
),
2221 (unsigned long long) (res
->end
- offset
));
2224 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
2227 down_write(&pci_bus_sem
);
2228 list_add_tail(&b
->node
, &pci_root_buses
);
2229 up_write(&pci_bus_sem
);
2234 put_device(&bridge
->dev
);
2235 device_unregister(&bridge
->dev
);
2240 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
2242 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
2244 struct resource
*res
= &b
->busn_res
;
2245 struct resource
*parent_res
, *conflict
;
2249 res
->flags
= IORESOURCE_BUS
;
2251 if (!pci_is_root_bus(b
))
2252 parent_res
= &b
->parent
->busn_res
;
2254 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
2255 res
->flags
|= IORESOURCE_PCI_FIXED
;
2258 conflict
= request_resource_conflict(parent_res
, res
);
2261 dev_printk(KERN_DEBUG
, &b
->dev
,
2262 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2263 res
, pci_is_root_bus(b
) ? "domain " : "",
2264 parent_res
, conflict
->name
, conflict
);
2266 return conflict
== NULL
;
2269 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
2271 struct resource
*res
= &b
->busn_res
;
2272 struct resource old_res
= *res
;
2273 resource_size_t size
;
2276 if (res
->start
> bus_max
)
2279 size
= bus_max
- res
->start
+ 1;
2280 ret
= adjust_resource(res
, res
->start
, size
);
2281 dev_printk(KERN_DEBUG
, &b
->dev
,
2282 "busn_res: %pR end %s updated to %02x\n",
2283 &old_res
, ret
? "can not be" : "is", bus_max
);
2285 if (!ret
&& !res
->parent
)
2286 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
2291 void pci_bus_release_busn_res(struct pci_bus
*b
)
2293 struct resource
*res
= &b
->busn_res
;
2296 if (!res
->flags
|| !res
->parent
)
2299 ret
= release_resource(res
);
2300 dev_printk(KERN_DEBUG
, &b
->dev
,
2301 "busn_res: %pR %s released\n",
2302 res
, ret
? "can not be" : "is");
2305 struct pci_bus
*pci_scan_root_bus_msi(struct device
*parent
, int bus
,
2306 struct pci_ops
*ops
, void *sysdata
,
2307 struct list_head
*resources
, struct msi_controller
*msi
)
2309 struct resource_entry
*window
;
2314 resource_list_for_each_entry(window
, resources
)
2315 if (window
->res
->flags
& IORESOURCE_BUS
) {
2320 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
2328 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2330 pci_bus_insert_busn_res(b
, bus
, 255);
2333 max
= pci_scan_child_bus(b
);
2336 pci_bus_update_busn_res_end(b
, max
);
2341 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
2342 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2344 return pci_scan_root_bus_msi(parent
, bus
, ops
, sysdata
, resources
,
2347 EXPORT_SYMBOL(pci_scan_root_bus
);
2349 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
2352 LIST_HEAD(resources
);
2355 pci_add_resource(&resources
, &ioport_resource
);
2356 pci_add_resource(&resources
, &iomem_resource
);
2357 pci_add_resource(&resources
, &busn_resource
);
2358 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
2360 pci_scan_child_bus(b
);
2362 pci_free_resource_list(&resources
);
2366 EXPORT_SYMBOL(pci_scan_bus
);
2369 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2370 * @bridge: PCI bridge for the bus to scan
2372 * Scan a PCI bus and child buses for new devices, add them,
2373 * and enable them, resizing bridge mmio/io resource if necessary
2374 * and possible. The caller must ensure the child devices are already
2375 * removed for resizing to occur.
2377 * Returns the max number of subordinate bus discovered.
2379 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
2382 struct pci_bus
*bus
= bridge
->subordinate
;
2384 max
= pci_scan_child_bus(bus
);
2386 pci_assign_unassigned_bridge_resources(bridge
);
2388 pci_bus_add_devices(bus
);
2394 * pci_rescan_bus - scan a PCI bus for devices.
2395 * @bus: PCI bus to scan
2397 * Scan a PCI bus and child buses for new devices, adds them,
2400 * Returns the max number of subordinate bus discovered.
2402 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
2406 max
= pci_scan_child_bus(bus
);
2407 pci_assign_unassigned_bus_resources(bus
);
2408 pci_bus_add_devices(bus
);
2412 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
2415 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2416 * routines should always be executed under this mutex.
2418 static DEFINE_MUTEX(pci_rescan_remove_lock
);
2420 void pci_lock_rescan_remove(void)
2422 mutex_lock(&pci_rescan_remove_lock
);
2424 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
2426 void pci_unlock_rescan_remove(void)
2428 mutex_unlock(&pci_rescan_remove_lock
);
2430 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
2432 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
2433 const struct device
*d_b
)
2435 const struct pci_dev
*a
= to_pci_dev(d_a
);
2436 const struct pci_dev
*b
= to_pci_dev(d_b
);
2438 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2439 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2441 if (a
->bus
->number
< b
->bus
->number
) return -1;
2442 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2444 if (a
->devfn
< b
->devfn
) return -1;
2445 else if (a
->devfn
> b
->devfn
) return 1;
2450 void __init
pci_sort_breadthfirst(void)
2452 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);