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Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
[mirror_ubuntu-focal-kernel.git] / drivers / pci / probe.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI detection and setup code
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/of_device.h>
11 #include <linux/of_pci.h>
12 #include <linux/pci_hotplug.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/cpumask.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/hypervisor.h>
19 #include <linux/irqdomain.h>
20 #include <linux/pm_runtime.h>
21 #include "pci.h"
22
23 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
24 #define CARDBUS_RESERVE_BUSNR 3
25
26 static struct resource busn_resource = {
27 .name = "PCI busn",
28 .start = 0,
29 .end = 255,
30 .flags = IORESOURCE_BUS,
31 };
32
33 /* Ugh. Need to stop exporting this to modules. */
34 LIST_HEAD(pci_root_buses);
35 EXPORT_SYMBOL(pci_root_buses);
36
37 static LIST_HEAD(pci_domain_busn_res_list);
38
39 struct pci_domain_busn_res {
40 struct list_head list;
41 struct resource res;
42 int domain_nr;
43 };
44
45 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 {
47 struct pci_domain_busn_res *r;
48
49 list_for_each_entry(r, &pci_domain_busn_res_list, list)
50 if (r->domain_nr == domain_nr)
51 return &r->res;
52
53 r = kzalloc(sizeof(*r), GFP_KERNEL);
54 if (!r)
55 return NULL;
56
57 r->domain_nr = domain_nr;
58 r->res.start = 0;
59 r->res.end = 0xff;
60 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61
62 list_add_tail(&r->list, &pci_domain_busn_res_list);
63
64 return &r->res;
65 }
66
67 static int find_anything(struct device *dev, const void *data)
68 {
69 return 1;
70 }
71
72 /*
73 * Some device drivers need know if PCI is initiated.
74 * Basically, we think PCI is not initiated when there
75 * is no device to be found on the pci_bus_type.
76 */
77 int no_pci_devices(void)
78 {
79 struct device *dev;
80 int no_devices;
81
82 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
83 no_devices = (dev == NULL);
84 put_device(dev);
85 return no_devices;
86 }
87 EXPORT_SYMBOL(no_pci_devices);
88
89 /*
90 * PCI Bus Class
91 */
92 static void release_pcibus_dev(struct device *dev)
93 {
94 struct pci_bus *pci_bus = to_pci_bus(dev);
95
96 put_device(pci_bus->bridge);
97 pci_bus_remove_resources(pci_bus);
98 pci_release_bus_of_node(pci_bus);
99 kfree(pci_bus);
100 }
101
102 static struct class pcibus_class = {
103 .name = "pci_bus",
104 .dev_release = &release_pcibus_dev,
105 .dev_groups = pcibus_groups,
106 };
107
108 static int __init pcibus_class_init(void)
109 {
110 return class_register(&pcibus_class);
111 }
112 postcore_initcall(pcibus_class_init);
113
114 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
115 {
116 u64 size = mask & maxbase; /* Find the significant bits */
117 if (!size)
118 return 0;
119
120 /*
121 * Get the lowest of them to find the decode size, and from that
122 * the extent.
123 */
124 size = size & ~(size-1);
125
126 /*
127 * base == maxbase can be valid only if the BAR has already been
128 * programmed with all 1s.
129 */
130 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
131 return 0;
132
133 return size;
134 }
135
136 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
137 {
138 u32 mem_type;
139 unsigned long flags;
140
141 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
142 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
143 flags |= IORESOURCE_IO;
144 return flags;
145 }
146
147 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
148 flags |= IORESOURCE_MEM;
149 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
150 flags |= IORESOURCE_PREFETCH;
151
152 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
153 switch (mem_type) {
154 case PCI_BASE_ADDRESS_MEM_TYPE_32:
155 break;
156 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
157 /* 1M mem BAR treated as 32-bit BAR */
158 break;
159 case PCI_BASE_ADDRESS_MEM_TYPE_64:
160 flags |= IORESOURCE_MEM_64;
161 break;
162 default:
163 /* mem unknown type treated as 32-bit BAR */
164 break;
165 }
166 return flags;
167 }
168
169 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
170
171 /**
172 * pci_read_base - Read a PCI BAR
173 * @dev: the PCI device
174 * @type: type of the BAR
175 * @res: resource buffer to be filled in
176 * @pos: BAR position in the config space
177 *
178 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
179 */
180 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
181 struct resource *res, unsigned int pos)
182 {
183 u32 l = 0, sz = 0, mask;
184 u64 l64, sz64, mask64;
185 u16 orig_cmd;
186 struct pci_bus_region region, inverted_region;
187
188 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
189
190 /* No printks while decoding is disabled! */
191 if (!dev->mmio_always_on) {
192 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
193 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
194 pci_write_config_word(dev, PCI_COMMAND,
195 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
196 }
197 }
198
199 res->name = pci_name(dev);
200
201 pci_read_config_dword(dev, pos, &l);
202 pci_write_config_dword(dev, pos, l | mask);
203 pci_read_config_dword(dev, pos, &sz);
204 pci_write_config_dword(dev, pos, l);
205
206 /*
207 * All bits set in sz means the device isn't working properly.
208 * If the BAR isn't implemented, all bits must be 0. If it's a
209 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
210 * 1 must be clear.
211 */
212 if (sz == 0xffffffff)
213 sz = 0;
214
215 /*
216 * I don't know how l can have all bits set. Copied from old code.
217 * Maybe it fixes a bug on some ancient platform.
218 */
219 if (l == 0xffffffff)
220 l = 0;
221
222 if (type == pci_bar_unknown) {
223 res->flags = decode_bar(dev, l);
224 res->flags |= IORESOURCE_SIZEALIGN;
225 if (res->flags & IORESOURCE_IO) {
226 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
227 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
228 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
229 } else {
230 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
231 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
232 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
233 }
234 } else {
235 if (l & PCI_ROM_ADDRESS_ENABLE)
236 res->flags |= IORESOURCE_ROM_ENABLE;
237 l64 = l & PCI_ROM_ADDRESS_MASK;
238 sz64 = sz & PCI_ROM_ADDRESS_MASK;
239 mask64 = PCI_ROM_ADDRESS_MASK;
240 }
241
242 if (res->flags & IORESOURCE_MEM_64) {
243 pci_read_config_dword(dev, pos + 4, &l);
244 pci_write_config_dword(dev, pos + 4, ~0);
245 pci_read_config_dword(dev, pos + 4, &sz);
246 pci_write_config_dword(dev, pos + 4, l);
247
248 l64 |= ((u64)l << 32);
249 sz64 |= ((u64)sz << 32);
250 mask64 |= ((u64)~0 << 32);
251 }
252
253 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
254 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
255
256 if (!sz64)
257 goto fail;
258
259 sz64 = pci_size(l64, sz64, mask64);
260 if (!sz64) {
261 pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
262 pos);
263 goto fail;
264 }
265
266 if (res->flags & IORESOURCE_MEM_64) {
267 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
268 && sz64 > 0x100000000ULL) {
269 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
270 res->start = 0;
271 res->end = 0;
272 pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
273 pos, (unsigned long long)sz64);
274 goto out;
275 }
276
277 if ((sizeof(pci_bus_addr_t) < 8) && l) {
278 /* Above 32-bit boundary; try to reallocate */
279 res->flags |= IORESOURCE_UNSET;
280 res->start = 0;
281 res->end = sz64 - 1;
282 pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
283 pos, (unsigned long long)l64);
284 goto out;
285 }
286 }
287
288 region.start = l64;
289 region.end = l64 + sz64 - 1;
290
291 pcibios_bus_to_resource(dev->bus, res, &region);
292 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
293
294 /*
295 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
296 * the corresponding resource address (the physical address used by
297 * the CPU. Converting that resource address back to a bus address
298 * should yield the original BAR value:
299 *
300 * resource_to_bus(bus_to_resource(A)) == A
301 *
302 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
303 * be claimed by the device.
304 */
305 if (inverted_region.start != region.start) {
306 res->flags |= IORESOURCE_UNSET;
307 res->start = 0;
308 res->end = region.end - region.start;
309 pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
310 pos, (unsigned long long)region.start);
311 }
312
313 goto out;
314
315
316 fail:
317 res->flags = 0;
318 out:
319 if (res->flags)
320 pci_info(dev, "reg 0x%x: %pR\n", pos, res);
321
322 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
323 }
324
325 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
326 {
327 unsigned int pos, reg;
328
329 if (dev->non_compliant_bars)
330 return;
331
332 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
333 if (dev->is_virtfn)
334 return;
335
336 for (pos = 0; pos < howmany; pos++) {
337 struct resource *res = &dev->resource[pos];
338 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
339 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
340 }
341
342 if (rom) {
343 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
344 dev->rom_base_reg = rom;
345 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
346 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
347 __pci_read_base(dev, pci_bar_mem32, res, rom);
348 }
349 }
350
351 static void pci_read_bridge_windows(struct pci_dev *bridge)
352 {
353 u16 io;
354 u32 pmem, tmp;
355
356 pci_read_config_word(bridge, PCI_IO_BASE, &io);
357 if (!io) {
358 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
359 pci_read_config_word(bridge, PCI_IO_BASE, &io);
360 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
361 }
362 if (io)
363 bridge->io_window = 1;
364
365 /*
366 * DECchip 21050 pass 2 errata: the bridge may miss an address
367 * disconnect boundary by one PCI data phase. Workaround: do not
368 * use prefetching on this device.
369 */
370 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
371 return;
372
373 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
374 if (!pmem) {
375 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
376 0xffe0fff0);
377 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
378 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
379 }
380 if (!pmem)
381 return;
382
383 bridge->pref_window = 1;
384
385 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
386
387 /*
388 * Bridge claims to have a 64-bit prefetchable memory
389 * window; verify that the upper bits are actually
390 * writable.
391 */
392 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
393 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
394 0xffffffff);
395 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
396 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
397 if (tmp)
398 bridge->pref_64_window = 1;
399 }
400 }
401
402 static void pci_read_bridge_io(struct pci_bus *child)
403 {
404 struct pci_dev *dev = child->self;
405 u8 io_base_lo, io_limit_lo;
406 unsigned long io_mask, io_granularity, base, limit;
407 struct pci_bus_region region;
408 struct resource *res;
409
410 io_mask = PCI_IO_RANGE_MASK;
411 io_granularity = 0x1000;
412 if (dev->io_window_1k) {
413 /* Support 1K I/O space granularity */
414 io_mask = PCI_IO_1K_RANGE_MASK;
415 io_granularity = 0x400;
416 }
417
418 res = child->resource[0];
419 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
420 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
421 base = (io_base_lo & io_mask) << 8;
422 limit = (io_limit_lo & io_mask) << 8;
423
424 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
425 u16 io_base_hi, io_limit_hi;
426
427 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
428 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
429 base |= ((unsigned long) io_base_hi << 16);
430 limit |= ((unsigned long) io_limit_hi << 16);
431 }
432
433 if (base <= limit) {
434 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
435 region.start = base;
436 region.end = limit + io_granularity - 1;
437 pcibios_bus_to_resource(dev->bus, res, &region);
438 pci_info(dev, " bridge window %pR\n", res);
439 }
440 }
441
442 static void pci_read_bridge_mmio(struct pci_bus *child)
443 {
444 struct pci_dev *dev = child->self;
445 u16 mem_base_lo, mem_limit_lo;
446 unsigned long base, limit;
447 struct pci_bus_region region;
448 struct resource *res;
449
450 res = child->resource[1];
451 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
452 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
453 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
454 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
455 if (base <= limit) {
456 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
457 region.start = base;
458 region.end = limit + 0xfffff;
459 pcibios_bus_to_resource(dev->bus, res, &region);
460 pci_info(dev, " bridge window %pR\n", res);
461 }
462 }
463
464 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
465 {
466 struct pci_dev *dev = child->self;
467 u16 mem_base_lo, mem_limit_lo;
468 u64 base64, limit64;
469 pci_bus_addr_t base, limit;
470 struct pci_bus_region region;
471 struct resource *res;
472
473 res = child->resource[2];
474 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
475 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
476 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
477 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
478
479 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
480 u32 mem_base_hi, mem_limit_hi;
481
482 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
483 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
484
485 /*
486 * Some bridges set the base > limit by default, and some
487 * (broken) BIOSes do not initialize them. If we find
488 * this, just assume they are not being used.
489 */
490 if (mem_base_hi <= mem_limit_hi) {
491 base64 |= (u64) mem_base_hi << 32;
492 limit64 |= (u64) mem_limit_hi << 32;
493 }
494 }
495
496 base = (pci_bus_addr_t) base64;
497 limit = (pci_bus_addr_t) limit64;
498
499 if (base != base64) {
500 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
501 (unsigned long long) base64);
502 return;
503 }
504
505 if (base <= limit) {
506 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
507 IORESOURCE_MEM | IORESOURCE_PREFETCH;
508 if (res->flags & PCI_PREF_RANGE_TYPE_64)
509 res->flags |= IORESOURCE_MEM_64;
510 region.start = base;
511 region.end = limit + 0xfffff;
512 pcibios_bus_to_resource(dev->bus, res, &region);
513 pci_info(dev, " bridge window %pR\n", res);
514 }
515 }
516
517 void pci_read_bridge_bases(struct pci_bus *child)
518 {
519 struct pci_dev *dev = child->self;
520 struct resource *res;
521 int i;
522
523 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
524 return;
525
526 pci_info(dev, "PCI bridge to %pR%s\n",
527 &child->busn_res,
528 dev->transparent ? " (subtractive decode)" : "");
529
530 pci_bus_remove_resources(child);
531 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
532 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
533
534 pci_read_bridge_io(child);
535 pci_read_bridge_mmio(child);
536 pci_read_bridge_mmio_pref(child);
537
538 if (dev->transparent) {
539 pci_bus_for_each_resource(child->parent, res, i) {
540 if (res && res->flags) {
541 pci_bus_add_resource(child, res,
542 PCI_SUBTRACTIVE_DECODE);
543 pci_info(dev, " bridge window %pR (subtractive decode)\n",
544 res);
545 }
546 }
547 }
548 }
549
550 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
551 {
552 struct pci_bus *b;
553
554 b = kzalloc(sizeof(*b), GFP_KERNEL);
555 if (!b)
556 return NULL;
557
558 INIT_LIST_HEAD(&b->node);
559 INIT_LIST_HEAD(&b->children);
560 INIT_LIST_HEAD(&b->devices);
561 INIT_LIST_HEAD(&b->slots);
562 INIT_LIST_HEAD(&b->resources);
563 b->max_bus_speed = PCI_SPEED_UNKNOWN;
564 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
565 #ifdef CONFIG_PCI_DOMAINS_GENERIC
566 if (parent)
567 b->domain_nr = parent->domain_nr;
568 #endif
569 return b;
570 }
571
572 static void devm_pci_release_host_bridge_dev(struct device *dev)
573 {
574 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
575
576 if (bridge->release_fn)
577 bridge->release_fn(bridge);
578
579 pci_free_resource_list(&bridge->windows);
580 }
581
582 static void pci_release_host_bridge_dev(struct device *dev)
583 {
584 devm_pci_release_host_bridge_dev(dev);
585 kfree(to_pci_host_bridge(dev));
586 }
587
588 static void pci_init_host_bridge(struct pci_host_bridge *bridge)
589 {
590 INIT_LIST_HEAD(&bridge->windows);
591 INIT_LIST_HEAD(&bridge->dma_ranges);
592
593 /*
594 * We assume we can manage these PCIe features. Some systems may
595 * reserve these for use by the platform itself, e.g., an ACPI BIOS
596 * may implement its own AER handling and use _OSC to prevent the
597 * OS from interfering.
598 */
599 bridge->native_aer = 1;
600 bridge->native_pcie_hotplug = 1;
601 bridge->native_shpc_hotplug = 1;
602 bridge->native_pme = 1;
603 bridge->native_ltr = 1;
604 }
605
606 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
607 {
608 struct pci_host_bridge *bridge;
609
610 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
611 if (!bridge)
612 return NULL;
613
614 pci_init_host_bridge(bridge);
615 bridge->dev.release = pci_release_host_bridge_dev;
616
617 return bridge;
618 }
619 EXPORT_SYMBOL(pci_alloc_host_bridge);
620
621 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
622 size_t priv)
623 {
624 struct pci_host_bridge *bridge;
625
626 bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
627 if (!bridge)
628 return NULL;
629
630 pci_init_host_bridge(bridge);
631 bridge->dev.release = devm_pci_release_host_bridge_dev;
632
633 return bridge;
634 }
635 EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
636
637 void pci_free_host_bridge(struct pci_host_bridge *bridge)
638 {
639 pci_free_resource_list(&bridge->windows);
640 pci_free_resource_list(&bridge->dma_ranges);
641
642 kfree(bridge);
643 }
644 EXPORT_SYMBOL(pci_free_host_bridge);
645
646 static const unsigned char pcix_bus_speed[] = {
647 PCI_SPEED_UNKNOWN, /* 0 */
648 PCI_SPEED_66MHz_PCIX, /* 1 */
649 PCI_SPEED_100MHz_PCIX, /* 2 */
650 PCI_SPEED_133MHz_PCIX, /* 3 */
651 PCI_SPEED_UNKNOWN, /* 4 */
652 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
653 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
654 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
655 PCI_SPEED_UNKNOWN, /* 8 */
656 PCI_SPEED_66MHz_PCIX_266, /* 9 */
657 PCI_SPEED_100MHz_PCIX_266, /* A */
658 PCI_SPEED_133MHz_PCIX_266, /* B */
659 PCI_SPEED_UNKNOWN, /* C */
660 PCI_SPEED_66MHz_PCIX_533, /* D */
661 PCI_SPEED_100MHz_PCIX_533, /* E */
662 PCI_SPEED_133MHz_PCIX_533 /* F */
663 };
664
665 const unsigned char pcie_link_speed[] = {
666 PCI_SPEED_UNKNOWN, /* 0 */
667 PCIE_SPEED_2_5GT, /* 1 */
668 PCIE_SPEED_5_0GT, /* 2 */
669 PCIE_SPEED_8_0GT, /* 3 */
670 PCIE_SPEED_16_0GT, /* 4 */
671 PCIE_SPEED_32_0GT, /* 5 */
672 PCI_SPEED_UNKNOWN, /* 6 */
673 PCI_SPEED_UNKNOWN, /* 7 */
674 PCI_SPEED_UNKNOWN, /* 8 */
675 PCI_SPEED_UNKNOWN, /* 9 */
676 PCI_SPEED_UNKNOWN, /* A */
677 PCI_SPEED_UNKNOWN, /* B */
678 PCI_SPEED_UNKNOWN, /* C */
679 PCI_SPEED_UNKNOWN, /* D */
680 PCI_SPEED_UNKNOWN, /* E */
681 PCI_SPEED_UNKNOWN /* F */
682 };
683
684 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
685 {
686 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
687 }
688 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
689
690 static unsigned char agp_speeds[] = {
691 AGP_UNKNOWN,
692 AGP_1X,
693 AGP_2X,
694 AGP_4X,
695 AGP_8X
696 };
697
698 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
699 {
700 int index = 0;
701
702 if (agpstat & 4)
703 index = 3;
704 else if (agpstat & 2)
705 index = 2;
706 else if (agpstat & 1)
707 index = 1;
708 else
709 goto out;
710
711 if (agp3) {
712 index += 2;
713 if (index == 5)
714 index = 0;
715 }
716
717 out:
718 return agp_speeds[index];
719 }
720
721 static void pci_set_bus_speed(struct pci_bus *bus)
722 {
723 struct pci_dev *bridge = bus->self;
724 int pos;
725
726 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
727 if (!pos)
728 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
729 if (pos) {
730 u32 agpstat, agpcmd;
731
732 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
733 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
734
735 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
736 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
737 }
738
739 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
740 if (pos) {
741 u16 status;
742 enum pci_bus_speed max;
743
744 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
745 &status);
746
747 if (status & PCI_X_SSTATUS_533MHZ) {
748 max = PCI_SPEED_133MHz_PCIX_533;
749 } else if (status & PCI_X_SSTATUS_266MHZ) {
750 max = PCI_SPEED_133MHz_PCIX_266;
751 } else if (status & PCI_X_SSTATUS_133MHZ) {
752 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
753 max = PCI_SPEED_133MHz_PCIX_ECC;
754 else
755 max = PCI_SPEED_133MHz_PCIX;
756 } else {
757 max = PCI_SPEED_66MHz_PCIX;
758 }
759
760 bus->max_bus_speed = max;
761 bus->cur_bus_speed = pcix_bus_speed[
762 (status & PCI_X_SSTATUS_FREQ) >> 6];
763
764 return;
765 }
766
767 if (pci_is_pcie(bridge)) {
768 u32 linkcap;
769 u16 linksta;
770
771 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
772 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
773 bridge->link_active_reporting = !!(linkcap & PCI_EXP_LNKCAP_DLLLARC);
774
775 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
776 pcie_update_link_speed(bus, linksta);
777 }
778 }
779
780 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
781 {
782 struct irq_domain *d;
783
784 /*
785 * Any firmware interface that can resolve the msi_domain
786 * should be called from here.
787 */
788 d = pci_host_bridge_of_msi_domain(bus);
789 if (!d)
790 d = pci_host_bridge_acpi_msi_domain(bus);
791
792 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
793 /*
794 * If no IRQ domain was found via the OF tree, try looking it up
795 * directly through the fwnode_handle.
796 */
797 if (!d) {
798 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
799
800 if (fwnode)
801 d = irq_find_matching_fwnode(fwnode,
802 DOMAIN_BUS_PCI_MSI);
803 }
804 #endif
805
806 return d;
807 }
808
809 static void pci_set_bus_msi_domain(struct pci_bus *bus)
810 {
811 struct irq_domain *d;
812 struct pci_bus *b;
813
814 /*
815 * The bus can be a root bus, a subordinate bus, or a virtual bus
816 * created by an SR-IOV device. Walk up to the first bridge device
817 * found or derive the domain from the host bridge.
818 */
819 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
820 if (b->self)
821 d = dev_get_msi_domain(&b->self->dev);
822 }
823
824 if (!d)
825 d = pci_host_bridge_msi_domain(b);
826
827 dev_set_msi_domain(&bus->dev, d);
828 }
829
830 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
831 {
832 struct device *parent = bridge->dev.parent;
833 struct resource_entry *window, *n;
834 struct pci_bus *bus, *b;
835 resource_size_t offset;
836 LIST_HEAD(resources);
837 struct resource *res;
838 char addr[64], *fmt;
839 const char *name;
840 int err;
841
842 bus = pci_alloc_bus(NULL);
843 if (!bus)
844 return -ENOMEM;
845
846 bridge->bus = bus;
847
848 /* Temporarily move resources off the list */
849 list_splice_init(&bridge->windows, &resources);
850 bus->sysdata = bridge->sysdata;
851 bus->msi = bridge->msi;
852 bus->ops = bridge->ops;
853 bus->number = bus->busn_res.start = bridge->busnr;
854 #ifdef CONFIG_PCI_DOMAINS_GENERIC
855 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
856 #endif
857
858 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
859 if (b) {
860 /* Ignore it if we already got here via a different bridge */
861 dev_dbg(&b->dev, "bus already known\n");
862 err = -EEXIST;
863 goto free;
864 }
865
866 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
867 bridge->busnr);
868
869 err = pcibios_root_bridge_prepare(bridge);
870 if (err)
871 goto free;
872
873 err = device_register(&bridge->dev);
874 if (err)
875 put_device(&bridge->dev);
876
877 bus->bridge = get_device(&bridge->dev);
878 device_enable_async_suspend(bus->bridge);
879 pci_set_bus_of_node(bus);
880 pci_set_bus_msi_domain(bus);
881
882 if (!parent)
883 set_dev_node(bus->bridge, pcibus_to_node(bus));
884
885 bus->dev.class = &pcibus_class;
886 bus->dev.parent = bus->bridge;
887
888 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
889 name = dev_name(&bus->dev);
890
891 err = device_register(&bus->dev);
892 if (err)
893 goto unregister;
894
895 pcibios_add_bus(bus);
896
897 /* Create legacy_io and legacy_mem files for this bus */
898 pci_create_legacy_files(bus);
899
900 if (parent)
901 dev_info(parent, "PCI host bridge to bus %s\n", name);
902 else
903 pr_info("PCI host bridge to bus %s\n", name);
904
905 /* Add initial resources to the bus */
906 resource_list_for_each_entry_safe(window, n, &resources) {
907 list_move_tail(&window->node, &bridge->windows);
908 offset = window->offset;
909 res = window->res;
910
911 if (res->flags & IORESOURCE_BUS)
912 pci_bus_insert_busn_res(bus, bus->number, res->end);
913 else
914 pci_bus_add_resource(bus, res, 0);
915
916 if (offset) {
917 if (resource_type(res) == IORESOURCE_IO)
918 fmt = " (bus address [%#06llx-%#06llx])";
919 else
920 fmt = " (bus address [%#010llx-%#010llx])";
921
922 snprintf(addr, sizeof(addr), fmt,
923 (unsigned long long)(res->start - offset),
924 (unsigned long long)(res->end - offset));
925 } else
926 addr[0] = '\0';
927
928 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
929 }
930
931 down_write(&pci_bus_sem);
932 list_add_tail(&bus->node, &pci_root_buses);
933 up_write(&pci_bus_sem);
934
935 return 0;
936
937 unregister:
938 put_device(&bridge->dev);
939 device_unregister(&bridge->dev);
940
941 free:
942 kfree(bus);
943 return err;
944 }
945
946 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
947 {
948 int pos;
949 u32 status;
950
951 /*
952 * If extended config space isn't accessible on a bridge's primary
953 * bus, we certainly can't access it on the secondary bus.
954 */
955 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
956 return false;
957
958 /*
959 * PCIe Root Ports and switch ports are PCIe on both sides, so if
960 * extended config space is accessible on the primary, it's also
961 * accessible on the secondary.
962 */
963 if (pci_is_pcie(bridge) &&
964 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
965 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
966 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
967 return true;
968
969 /*
970 * For the other bridge types:
971 * - PCI-to-PCI bridges
972 * - PCIe-to-PCI/PCI-X forward bridges
973 * - PCI/PCI-X-to-PCIe reverse bridges
974 * extended config space on the secondary side is only accessible
975 * if the bridge supports PCI-X Mode 2.
976 */
977 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
978 if (!pos)
979 return false;
980
981 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
982 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
983 }
984
985 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
986 struct pci_dev *bridge, int busnr)
987 {
988 struct pci_bus *child;
989 int i;
990 int ret;
991
992 /* Allocate a new bus and inherit stuff from the parent */
993 child = pci_alloc_bus(parent);
994 if (!child)
995 return NULL;
996
997 child->parent = parent;
998 child->ops = parent->ops;
999 child->msi = parent->msi;
1000 child->sysdata = parent->sysdata;
1001 child->bus_flags = parent->bus_flags;
1002
1003 /*
1004 * Initialize some portions of the bus device, but don't register
1005 * it now as the parent is not properly set up yet.
1006 */
1007 child->dev.class = &pcibus_class;
1008 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1009
1010 /* Set up the primary, secondary and subordinate bus numbers */
1011 child->number = child->busn_res.start = busnr;
1012 child->primary = parent->busn_res.start;
1013 child->busn_res.end = 0xff;
1014
1015 if (!bridge) {
1016 child->dev.parent = parent->bridge;
1017 goto add_dev;
1018 }
1019
1020 child->self = bridge;
1021 child->bridge = get_device(&bridge->dev);
1022 child->dev.parent = child->bridge;
1023 pci_set_bus_of_node(child);
1024 pci_set_bus_speed(child);
1025
1026 /*
1027 * Check whether extended config space is accessible on the child
1028 * bus. Note that we currently assume it is always accessible on
1029 * the root bus.
1030 */
1031 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1032 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1033 pci_info(child, "extended config space not accessible\n");
1034 }
1035
1036 /* Set up default resource pointers and names */
1037 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1038 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1039 child->resource[i]->name = child->name;
1040 }
1041 bridge->subordinate = child;
1042
1043 add_dev:
1044 pci_set_bus_msi_domain(child);
1045 ret = device_register(&child->dev);
1046 WARN_ON(ret < 0);
1047
1048 pcibios_add_bus(child);
1049
1050 if (child->ops->add_bus) {
1051 ret = child->ops->add_bus(child);
1052 if (WARN_ON(ret < 0))
1053 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1054 }
1055
1056 /* Create legacy_io and legacy_mem files for this bus */
1057 pci_create_legacy_files(child);
1058
1059 return child;
1060 }
1061
1062 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1063 int busnr)
1064 {
1065 struct pci_bus *child;
1066
1067 child = pci_alloc_child_bus(parent, dev, busnr);
1068 if (child) {
1069 down_write(&pci_bus_sem);
1070 list_add_tail(&child->node, &parent->children);
1071 up_write(&pci_bus_sem);
1072 }
1073 return child;
1074 }
1075 EXPORT_SYMBOL(pci_add_new_bus);
1076
1077 static void pci_enable_crs(struct pci_dev *pdev)
1078 {
1079 u16 root_cap = 0;
1080
1081 /* Enable CRS Software Visibility if supported */
1082 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1083 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
1084 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1085 PCI_EXP_RTCTL_CRSSVE);
1086 }
1087
1088 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1089 unsigned int available_buses);
1090 /**
1091 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1092 * numbers from EA capability.
1093 * @dev: Bridge
1094 * @sec: updated with secondary bus number from EA
1095 * @sub: updated with subordinate bus number from EA
1096 *
1097 * If @dev is a bridge with EA capability, update @sec and @sub with
1098 * fixed bus numbers from the capability and return true. Otherwise,
1099 * return false.
1100 */
1101 static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1102 {
1103 int ea, offset;
1104 u32 dw;
1105
1106 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1107 return false;
1108
1109 /* find PCI EA capability in list */
1110 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1111 if (!ea)
1112 return false;
1113
1114 offset = ea + PCI_EA_FIRST_ENT;
1115 pci_read_config_dword(dev, offset, &dw);
1116 *sec = dw & PCI_EA_SEC_BUS_MASK;
1117 *sub = (dw & PCI_EA_SUB_BUS_MASK) >> PCI_EA_SUB_BUS_SHIFT;
1118 return true;
1119 }
1120
1121 /*
1122 * pci_scan_bridge_extend() - Scan buses behind a bridge
1123 * @bus: Parent bus the bridge is on
1124 * @dev: Bridge itself
1125 * @max: Starting subordinate number of buses behind this bridge
1126 * @available_buses: Total number of buses available for this bridge and
1127 * the devices below. After the minimal bus space has
1128 * been allocated the remaining buses will be
1129 * distributed equally between hotplug-capable bridges.
1130 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1131 * that need to be reconfigured.
1132 *
1133 * If it's a bridge, configure it and scan the bus behind it.
1134 * For CardBus bridges, we don't scan behind as the devices will
1135 * be handled by the bridge driver itself.
1136 *
1137 * We need to process bridges in two passes -- first we scan those
1138 * already configured by the BIOS and after we are done with all of
1139 * them, we proceed to assigning numbers to the remaining buses in
1140 * order to avoid overlaps between old and new bus numbers.
1141 *
1142 * Return: New subordinate number covering all buses behind this bridge.
1143 */
1144 static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1145 int max, unsigned int available_buses,
1146 int pass)
1147 {
1148 struct pci_bus *child;
1149 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1150 u32 buses, i, j = 0;
1151 u16 bctl;
1152 u8 primary, secondary, subordinate;
1153 int broken = 0;
1154 bool fixed_buses;
1155 u8 fixed_sec, fixed_sub;
1156 int next_busnr;
1157
1158 /*
1159 * Make sure the bridge is powered on to be able to access config
1160 * space of devices below it.
1161 */
1162 pm_runtime_get_sync(&dev->dev);
1163
1164 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1165 primary = buses & 0xFF;
1166 secondary = (buses >> 8) & 0xFF;
1167 subordinate = (buses >> 16) & 0xFF;
1168
1169 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1170 secondary, subordinate, pass);
1171
1172 if (!primary && (primary != bus->number) && secondary && subordinate) {
1173 pci_warn(dev, "Primary bus is hard wired to 0\n");
1174 primary = bus->number;
1175 }
1176
1177 /* Check if setup is sensible at all */
1178 if (!pass &&
1179 (primary != bus->number || secondary <= bus->number ||
1180 secondary > subordinate)) {
1181 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1182 secondary, subordinate);
1183 broken = 1;
1184 }
1185
1186 /*
1187 * Disable Master-Abort Mode during probing to avoid reporting of
1188 * bus errors in some architectures.
1189 */
1190 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1191 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1192 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1193
1194 pci_enable_crs(dev);
1195
1196 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1197 !is_cardbus && !broken) {
1198 unsigned int cmax;
1199
1200 /*
1201 * Bus already configured by firmware, process it in the
1202 * first pass and just note the configuration.
1203 */
1204 if (pass)
1205 goto out;
1206
1207 /*
1208 * The bus might already exist for two reasons: Either we
1209 * are rescanning the bus or the bus is reachable through
1210 * more than one bridge. The second case can happen with
1211 * the i450NX chipset.
1212 */
1213 child = pci_find_bus(pci_domain_nr(bus), secondary);
1214 if (!child) {
1215 child = pci_add_new_bus(bus, dev, secondary);
1216 if (!child)
1217 goto out;
1218 child->primary = primary;
1219 pci_bus_insert_busn_res(child, secondary, subordinate);
1220 child->bridge_ctl = bctl;
1221 }
1222
1223 cmax = pci_scan_child_bus(child);
1224 if (cmax > subordinate)
1225 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1226 subordinate, cmax);
1227
1228 /* Subordinate should equal child->busn_res.end */
1229 if (subordinate > max)
1230 max = subordinate;
1231 } else {
1232
1233 /*
1234 * We need to assign a number to this bus which we always
1235 * do in the second pass.
1236 */
1237 if (!pass) {
1238 if (pcibios_assign_all_busses() || broken || is_cardbus)
1239
1240 /*
1241 * Temporarily disable forwarding of the
1242 * configuration cycles on all bridges in
1243 * this bus segment to avoid possible
1244 * conflicts in the second pass between two
1245 * bridges programmed with overlapping bus
1246 * ranges.
1247 */
1248 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1249 buses & ~0xffffff);
1250 goto out;
1251 }
1252
1253 /* Clear errors */
1254 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1255
1256 /* Read bus numbers from EA Capability (if present) */
1257 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1258 if (fixed_buses)
1259 next_busnr = fixed_sec;
1260 else
1261 next_busnr = max + 1;
1262
1263 /*
1264 * Prevent assigning a bus number that already exists.
1265 * This can happen when a bridge is hot-plugged, so in this
1266 * case we only re-scan this bus.
1267 */
1268 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1269 if (!child) {
1270 child = pci_add_new_bus(bus, dev, next_busnr);
1271 if (!child)
1272 goto out;
1273 pci_bus_insert_busn_res(child, next_busnr,
1274 bus->busn_res.end);
1275 }
1276 max++;
1277 if (available_buses)
1278 available_buses--;
1279
1280 buses = (buses & 0xff000000)
1281 | ((unsigned int)(child->primary) << 0)
1282 | ((unsigned int)(child->busn_res.start) << 8)
1283 | ((unsigned int)(child->busn_res.end) << 16);
1284
1285 /*
1286 * yenta.c forces a secondary latency timer of 176.
1287 * Copy that behaviour here.
1288 */
1289 if (is_cardbus) {
1290 buses &= ~0xff000000;
1291 buses |= CARDBUS_LATENCY_TIMER << 24;
1292 }
1293
1294 /* We need to blast all three values with a single write */
1295 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1296
1297 if (!is_cardbus) {
1298 child->bridge_ctl = bctl;
1299 max = pci_scan_child_bus_extend(child, available_buses);
1300 } else {
1301
1302 /*
1303 * For CardBus bridges, we leave 4 bus numbers as
1304 * cards with a PCI-to-PCI bridge can be inserted
1305 * later.
1306 */
1307 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1308 struct pci_bus *parent = bus;
1309 if (pci_find_bus(pci_domain_nr(bus),
1310 max+i+1))
1311 break;
1312 while (parent->parent) {
1313 if ((!pcibios_assign_all_busses()) &&
1314 (parent->busn_res.end > max) &&
1315 (parent->busn_res.end <= max+i)) {
1316 j = 1;
1317 }
1318 parent = parent->parent;
1319 }
1320 if (j) {
1321
1322 /*
1323 * Often, there are two CardBus
1324 * bridges -- try to leave one
1325 * valid bus number for each one.
1326 */
1327 i /= 2;
1328 break;
1329 }
1330 }
1331 max += i;
1332 }
1333
1334 /*
1335 * Set subordinate bus number to its real value.
1336 * If fixed subordinate bus number exists from EA
1337 * capability then use it.
1338 */
1339 if (fixed_buses)
1340 max = fixed_sub;
1341 pci_bus_update_busn_res_end(child, max);
1342 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1343 }
1344
1345 sprintf(child->name,
1346 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1347 pci_domain_nr(bus), child->number);
1348
1349 /* Check that all devices are accessible */
1350 while (bus->parent) {
1351 if ((child->busn_res.end > bus->busn_res.end) ||
1352 (child->number > bus->busn_res.end) ||
1353 (child->number < bus->number) ||
1354 (child->busn_res.end < bus->number)) {
1355 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1356 &child->busn_res);
1357 break;
1358 }
1359 bus = bus->parent;
1360 }
1361
1362 out:
1363 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1364
1365 pm_runtime_put(&dev->dev);
1366
1367 return max;
1368 }
1369
1370 /*
1371 * pci_scan_bridge() - Scan buses behind a bridge
1372 * @bus: Parent bus the bridge is on
1373 * @dev: Bridge itself
1374 * @max: Starting subordinate number of buses behind this bridge
1375 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1376 * that need to be reconfigured.
1377 *
1378 * If it's a bridge, configure it and scan the bus behind it.
1379 * For CardBus bridges, we don't scan behind as the devices will
1380 * be handled by the bridge driver itself.
1381 *
1382 * We need to process bridges in two passes -- first we scan those
1383 * already configured by the BIOS and after we are done with all of
1384 * them, we proceed to assigning numbers to the remaining buses in
1385 * order to avoid overlaps between old and new bus numbers.
1386 *
1387 * Return: New subordinate number covering all buses behind this bridge.
1388 */
1389 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1390 {
1391 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1392 }
1393 EXPORT_SYMBOL(pci_scan_bridge);
1394
1395 /*
1396 * Read interrupt line and base address registers.
1397 * The architecture-dependent code can tweak these, of course.
1398 */
1399 static void pci_read_irq(struct pci_dev *dev)
1400 {
1401 unsigned char irq;
1402
1403 /* VFs are not allowed to use INTx, so skip the config reads */
1404 if (dev->is_virtfn) {
1405 dev->pin = 0;
1406 dev->irq = 0;
1407 return;
1408 }
1409
1410 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1411 dev->pin = irq;
1412 if (irq)
1413 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1414 dev->irq = irq;
1415 }
1416
1417 void set_pcie_port_type(struct pci_dev *pdev)
1418 {
1419 int pos;
1420 u16 reg16;
1421 int type;
1422 struct pci_dev *parent;
1423
1424 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1425 if (!pos)
1426 return;
1427
1428 pdev->pcie_cap = pos;
1429 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1430 pdev->pcie_flags_reg = reg16;
1431 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1432 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1433
1434 /*
1435 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1436 * of a Link. No PCIe component has two Links. Two Links are
1437 * connected by a Switch that has a Port on each Link and internal
1438 * logic to connect the two Ports.
1439 */
1440 type = pci_pcie_type(pdev);
1441 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1442 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1443 pdev->has_secondary_link = 1;
1444 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1445 type == PCI_EXP_TYPE_DOWNSTREAM) {
1446 parent = pci_upstream_bridge(pdev);
1447
1448 /*
1449 * Usually there's an upstream device (Root Port or Switch
1450 * Downstream Port), but we can't assume one exists.
1451 */
1452 if (parent && !parent->has_secondary_link)
1453 pdev->has_secondary_link = 1;
1454 }
1455 }
1456
1457 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1458 {
1459 u32 reg32;
1460
1461 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1462 if (reg32 & PCI_EXP_SLTCAP_HPC)
1463 pdev->is_hotplug_bridge = 1;
1464 }
1465
1466 static void set_pcie_thunderbolt(struct pci_dev *dev)
1467 {
1468 int vsec = 0;
1469 u32 header;
1470
1471 while ((vsec = pci_find_next_ext_capability(dev, vsec,
1472 PCI_EXT_CAP_ID_VNDR))) {
1473 pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER, &header);
1474
1475 /* Is the device part of a Thunderbolt controller? */
1476 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
1477 PCI_VNDR_HEADER_ID(header) == PCI_VSEC_ID_INTEL_TBT) {
1478 dev->is_thunderbolt = 1;
1479 return;
1480 }
1481 }
1482 }
1483
1484 static void set_pcie_untrusted(struct pci_dev *dev)
1485 {
1486 struct pci_dev *parent;
1487
1488 /*
1489 * If the upstream bridge is untrusted we treat this device
1490 * untrusted as well.
1491 */
1492 parent = pci_upstream_bridge(dev);
1493 if (parent && parent->untrusted)
1494 dev->untrusted = true;
1495 }
1496
1497 /**
1498 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1499 * @dev: PCI device
1500 *
1501 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1502 * when forwarding a type1 configuration request the bridge must check that
1503 * the extended register address field is zero. The bridge is not permitted
1504 * to forward the transactions and must handle it as an Unsupported Request.
1505 * Some bridges do not follow this rule and simply drop the extended register
1506 * bits, resulting in the standard config space being aliased, every 256
1507 * bytes across the entire configuration space. Test for this condition by
1508 * comparing the first dword of each potential alias to the vendor/device ID.
1509 * Known offenders:
1510 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1511 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1512 */
1513 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1514 {
1515 #ifdef CONFIG_PCI_QUIRKS
1516 int pos;
1517 u32 header, tmp;
1518
1519 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1520
1521 for (pos = PCI_CFG_SPACE_SIZE;
1522 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1523 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1524 || header != tmp)
1525 return false;
1526 }
1527
1528 return true;
1529 #else
1530 return false;
1531 #endif
1532 }
1533
1534 /**
1535 * pci_cfg_space_size - Get the configuration space size of the PCI device
1536 * @dev: PCI device
1537 *
1538 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1539 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1540 * access it. Maybe we don't have a way to generate extended config space
1541 * accesses, or the device is behind a reverse Express bridge. So we try
1542 * reading the dword at 0x100 which must either be 0 or a valid extended
1543 * capability header.
1544 */
1545 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1546 {
1547 u32 status;
1548 int pos = PCI_CFG_SPACE_SIZE;
1549
1550 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1551 return PCI_CFG_SPACE_SIZE;
1552 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1553 return PCI_CFG_SPACE_SIZE;
1554
1555 return PCI_CFG_SPACE_EXP_SIZE;
1556 }
1557
1558 int pci_cfg_space_size(struct pci_dev *dev)
1559 {
1560 int pos;
1561 u32 status;
1562 u16 class;
1563
1564 #ifdef CONFIG_PCI_IOV
1565 /*
1566 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1567 * implement a PCIe capability and therefore must implement extended
1568 * config space. We can skip the NO_EXTCFG test below and the
1569 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1570 * the fact that the SR-IOV capability on the PF resides in extended
1571 * config space and must be accessible and non-aliased to have enabled
1572 * support for this VF. This is a micro performance optimization for
1573 * systems supporting many VFs.
1574 */
1575 if (dev->is_virtfn)
1576 return PCI_CFG_SPACE_EXP_SIZE;
1577 #endif
1578
1579 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1580 return PCI_CFG_SPACE_SIZE;
1581
1582 class = dev->class >> 8;
1583 if (class == PCI_CLASS_BRIDGE_HOST)
1584 return pci_cfg_space_size_ext(dev);
1585
1586 if (pci_is_pcie(dev))
1587 return pci_cfg_space_size_ext(dev);
1588
1589 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1590 if (!pos)
1591 return PCI_CFG_SPACE_SIZE;
1592
1593 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1594 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1595 return pci_cfg_space_size_ext(dev);
1596
1597 return PCI_CFG_SPACE_SIZE;
1598 }
1599
1600 static u32 pci_class(struct pci_dev *dev)
1601 {
1602 u32 class;
1603
1604 #ifdef CONFIG_PCI_IOV
1605 if (dev->is_virtfn)
1606 return dev->physfn->sriov->class;
1607 #endif
1608 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1609 return class;
1610 }
1611
1612 static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1613 {
1614 #ifdef CONFIG_PCI_IOV
1615 if (dev->is_virtfn) {
1616 *vendor = dev->physfn->sriov->subsystem_vendor;
1617 *device = dev->physfn->sriov->subsystem_device;
1618 return;
1619 }
1620 #endif
1621 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1622 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1623 }
1624
1625 static u8 pci_hdr_type(struct pci_dev *dev)
1626 {
1627 u8 hdr_type;
1628
1629 #ifdef CONFIG_PCI_IOV
1630 if (dev->is_virtfn)
1631 return dev->physfn->sriov->hdr_type;
1632 #endif
1633 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1634 return hdr_type;
1635 }
1636
1637 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1638
1639 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1640 {
1641 /*
1642 * Disable the MSI hardware to avoid screaming interrupts
1643 * during boot. This is the power on reset default so
1644 * usually this should be a noop.
1645 */
1646 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1647 if (dev->msi_cap)
1648 pci_msi_set_enable(dev, 0);
1649
1650 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1651 if (dev->msix_cap)
1652 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1653 }
1654
1655 /**
1656 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1657 * @dev: PCI device
1658 *
1659 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1660 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1661 */
1662 static int pci_intx_mask_broken(struct pci_dev *dev)
1663 {
1664 u16 orig, toggle, new;
1665
1666 pci_read_config_word(dev, PCI_COMMAND, &orig);
1667 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1668 pci_write_config_word(dev, PCI_COMMAND, toggle);
1669 pci_read_config_word(dev, PCI_COMMAND, &new);
1670
1671 pci_write_config_word(dev, PCI_COMMAND, orig);
1672
1673 /*
1674 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1675 * r2.3, so strictly speaking, a device is not *broken* if it's not
1676 * writable. But we'll live with the misnomer for now.
1677 */
1678 if (new != toggle)
1679 return 1;
1680 return 0;
1681 }
1682
1683 static void early_dump_pci_device(struct pci_dev *pdev)
1684 {
1685 u32 value[256 / 4];
1686 int i;
1687
1688 pci_info(pdev, "config space:\n");
1689
1690 for (i = 0; i < 256; i += 4)
1691 pci_read_config_dword(pdev, i, &value[i / 4]);
1692
1693 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1694 value, 256, false);
1695 }
1696
1697 /**
1698 * pci_setup_device - Fill in class and map information of a device
1699 * @dev: the device structure to fill
1700 *
1701 * Initialize the device structure with information about the device's
1702 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1703 * Called at initialisation of the PCI subsystem and by CardBus services.
1704 * Returns 0 on success and negative if unknown type of device (not normal,
1705 * bridge or CardBus).
1706 */
1707 int pci_setup_device(struct pci_dev *dev)
1708 {
1709 u32 class;
1710 u16 cmd;
1711 u8 hdr_type;
1712 int pos = 0;
1713 struct pci_bus_region region;
1714 struct resource *res;
1715
1716 hdr_type = pci_hdr_type(dev);
1717
1718 dev->sysdata = dev->bus->sysdata;
1719 dev->dev.parent = dev->bus->bridge;
1720 dev->dev.bus = &pci_bus_type;
1721 dev->hdr_type = hdr_type & 0x7f;
1722 dev->multifunction = !!(hdr_type & 0x80);
1723 dev->error_state = pci_channel_io_normal;
1724 set_pcie_port_type(dev);
1725
1726 pci_dev_assign_slot(dev);
1727
1728 /*
1729 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1730 * set this higher, assuming the system even supports it.
1731 */
1732 dev->dma_mask = 0xffffffff;
1733
1734 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1735 dev->bus->number, PCI_SLOT(dev->devfn),
1736 PCI_FUNC(dev->devfn));
1737
1738 class = pci_class(dev);
1739
1740 dev->revision = class & 0xff;
1741 dev->class = class >> 8; /* upper 3 bytes */
1742
1743 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
1744 dev->vendor, dev->device, dev->hdr_type, dev->class);
1745
1746 if (pci_early_dump)
1747 early_dump_pci_device(dev);
1748
1749 /* Need to have dev->class ready */
1750 dev->cfg_size = pci_cfg_space_size(dev);
1751
1752 /* Need to have dev->cfg_size ready */
1753 set_pcie_thunderbolt(dev);
1754
1755 set_pcie_untrusted(dev);
1756
1757 /* "Unknown power state" */
1758 dev->current_state = PCI_UNKNOWN;
1759
1760 /* Early fixups, before probing the BARs */
1761 pci_fixup_device(pci_fixup_early, dev);
1762
1763 /* Device class may be changed after fixup */
1764 class = dev->class >> 8;
1765
1766 if (dev->non_compliant_bars) {
1767 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1768 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1769 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1770 cmd &= ~PCI_COMMAND_IO;
1771 cmd &= ~PCI_COMMAND_MEMORY;
1772 pci_write_config_word(dev, PCI_COMMAND, cmd);
1773 }
1774 }
1775
1776 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1777
1778 switch (dev->hdr_type) { /* header type */
1779 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1780 if (class == PCI_CLASS_BRIDGE_PCI)
1781 goto bad;
1782 pci_read_irq(dev);
1783 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1784
1785 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
1786
1787 /*
1788 * Do the ugly legacy mode stuff here rather than broken chip
1789 * quirk code. Legacy mode ATA controllers have fixed
1790 * addresses. These are not always echoed in BAR0-3, and
1791 * BAR0-3 in a few cases contain junk!
1792 */
1793 if (class == PCI_CLASS_STORAGE_IDE) {
1794 u8 progif;
1795 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1796 if ((progif & 1) == 0) {
1797 region.start = 0x1F0;
1798 region.end = 0x1F7;
1799 res = &dev->resource[0];
1800 res->flags = LEGACY_IO_RESOURCE;
1801 pcibios_bus_to_resource(dev->bus, res, &region);
1802 pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
1803 res);
1804 region.start = 0x3F6;
1805 region.end = 0x3F6;
1806 res = &dev->resource[1];
1807 res->flags = LEGACY_IO_RESOURCE;
1808 pcibios_bus_to_resource(dev->bus, res, &region);
1809 pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
1810 res);
1811 }
1812 if ((progif & 4) == 0) {
1813 region.start = 0x170;
1814 region.end = 0x177;
1815 res = &dev->resource[2];
1816 res->flags = LEGACY_IO_RESOURCE;
1817 pcibios_bus_to_resource(dev->bus, res, &region);
1818 pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
1819 res);
1820 region.start = 0x376;
1821 region.end = 0x376;
1822 res = &dev->resource[3];
1823 res->flags = LEGACY_IO_RESOURCE;
1824 pcibios_bus_to_resource(dev->bus, res, &region);
1825 pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1826 res);
1827 }
1828 }
1829 break;
1830
1831 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1832 /*
1833 * The PCI-to-PCI bridge spec requires that subtractive
1834 * decoding (i.e. transparent) bridge must have programming
1835 * interface code of 0x01.
1836 */
1837 pci_read_irq(dev);
1838 dev->transparent = ((dev->class & 0xff) == 1);
1839 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1840 pci_read_bridge_windows(dev);
1841 set_pcie_hotplug_bridge(dev);
1842 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1843 if (pos) {
1844 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1845 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1846 }
1847 break;
1848
1849 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1850 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1851 goto bad;
1852 pci_read_irq(dev);
1853 pci_read_bases(dev, 1, 0);
1854 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1855 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1856 break;
1857
1858 default: /* unknown header */
1859 pci_err(dev, "unknown header type %02x, ignoring device\n",
1860 dev->hdr_type);
1861 return -EIO;
1862
1863 bad:
1864 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1865 dev->class, dev->hdr_type);
1866 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1867 }
1868
1869 /* We found a fine healthy device, go go go... */
1870 return 0;
1871 }
1872
1873 static void pci_configure_mps(struct pci_dev *dev)
1874 {
1875 struct pci_dev *bridge = pci_upstream_bridge(dev);
1876 int mps, mpss, p_mps, rc;
1877
1878 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1879 return;
1880
1881 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1882 if (dev->is_virtfn)
1883 return;
1884
1885 mps = pcie_get_mps(dev);
1886 p_mps = pcie_get_mps(bridge);
1887
1888 if (mps == p_mps)
1889 return;
1890
1891 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1892 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1893 mps, pci_name(bridge), p_mps);
1894 return;
1895 }
1896
1897 /*
1898 * Fancier MPS configuration is done later by
1899 * pcie_bus_configure_settings()
1900 */
1901 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1902 return;
1903
1904 mpss = 128 << dev->pcie_mpss;
1905 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
1906 pcie_set_mps(bridge, mpss);
1907 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1908 mpss, p_mps, 128 << bridge->pcie_mpss);
1909 p_mps = pcie_get_mps(bridge);
1910 }
1911
1912 rc = pcie_set_mps(dev, p_mps);
1913 if (rc) {
1914 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1915 p_mps);
1916 return;
1917 }
1918
1919 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
1920 p_mps, mps, mpss);
1921 }
1922
1923 static struct hpp_type0 pci_default_type0 = {
1924 .revision = 1,
1925 .cache_line_size = 8,
1926 .latency_timer = 0x40,
1927 .enable_serr = 0,
1928 .enable_perr = 0,
1929 };
1930
1931 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1932 {
1933 u16 pci_cmd, pci_bctl;
1934
1935 if (!hpp)
1936 hpp = &pci_default_type0;
1937
1938 if (hpp->revision > 1) {
1939 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
1940 hpp->revision);
1941 hpp = &pci_default_type0;
1942 }
1943
1944 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1945 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1946 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1947 if (hpp->enable_serr)
1948 pci_cmd |= PCI_COMMAND_SERR;
1949 if (hpp->enable_perr)
1950 pci_cmd |= PCI_COMMAND_PARITY;
1951 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1952
1953 /* Program bridge control value */
1954 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1955 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1956 hpp->latency_timer);
1957 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1958 if (hpp->enable_perr)
1959 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1960 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1961 }
1962 }
1963
1964 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1965 {
1966 int pos;
1967
1968 if (!hpp)
1969 return;
1970
1971 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1972 if (!pos)
1973 return;
1974
1975 pci_warn(dev, "PCI-X settings not supported\n");
1976 }
1977
1978 static bool pcie_root_rcb_set(struct pci_dev *dev)
1979 {
1980 struct pci_dev *rp = pcie_find_root_port(dev);
1981 u16 lnkctl;
1982
1983 if (!rp)
1984 return false;
1985
1986 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1987 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1988 return true;
1989
1990 return false;
1991 }
1992
1993 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1994 {
1995 int pos;
1996 u32 reg32;
1997
1998 if (!hpp)
1999 return;
2000
2001 if (!pci_is_pcie(dev))
2002 return;
2003
2004 if (hpp->revision > 1) {
2005 pci_warn(dev, "PCIe settings rev %d not supported\n",
2006 hpp->revision);
2007 return;
2008 }
2009
2010 /*
2011 * Don't allow _HPX to change MPS or MRRS settings. We manage
2012 * those to make sure they're consistent with the rest of the
2013 * platform.
2014 */
2015 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
2016 PCI_EXP_DEVCTL_READRQ;
2017 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
2018 PCI_EXP_DEVCTL_READRQ);
2019
2020 /* Initialize Device Control Register */
2021 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
2022 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
2023
2024 /* Initialize Link Control Register */
2025 if (pcie_cap_has_lnkctl(dev)) {
2026
2027 /*
2028 * If the Root Port supports Read Completion Boundary of
2029 * 128, set RCB to 128. Otherwise, clear it.
2030 */
2031 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
2032 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
2033 if (pcie_root_rcb_set(dev))
2034 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
2035
2036 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
2037 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
2038 }
2039
2040 /* Find Advanced Error Reporting Enhanced Capability */
2041 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
2042 if (!pos)
2043 return;
2044
2045 /* Initialize Uncorrectable Error Mask Register */
2046 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
2047 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
2048 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
2049
2050 /* Initialize Uncorrectable Error Severity Register */
2051 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
2052 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
2053 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
2054
2055 /* Initialize Correctable Error Mask Register */
2056 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
2057 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
2058 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
2059
2060 /* Initialize Advanced Error Capabilities and Control Register */
2061 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
2062 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
2063
2064 /* Don't enable ECRC generation or checking if unsupported */
2065 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
2066 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
2067 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
2068 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
2069 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
2070
2071 /*
2072 * FIXME: The following two registers are not supported yet.
2073 *
2074 * o Secondary Uncorrectable Error Severity Register
2075 * o Secondary Uncorrectable Error Mask Register
2076 */
2077 }
2078
2079 static u16 hpx3_device_type(struct pci_dev *dev)
2080 {
2081 u16 pcie_type = pci_pcie_type(dev);
2082 const int pcie_to_hpx3_type[] = {
2083 [PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT,
2084 [PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END,
2085 [PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END,
2086 [PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC,
2087 [PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT,
2088 [PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM,
2089 [PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM,
2090 [PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE,
2091 [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE,
2092 };
2093
2094 if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type))
2095 return 0;
2096
2097 return pcie_to_hpx3_type[pcie_type];
2098 }
2099
2100 static u8 hpx3_function_type(struct pci_dev *dev)
2101 {
2102 if (dev->is_virtfn)
2103 return HPX_FN_SRIOV_VIRT;
2104 else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0)
2105 return HPX_FN_SRIOV_PHYS;
2106 else
2107 return HPX_FN_NORMAL;
2108 }
2109
2110 static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id)
2111 {
2112 u8 cap_ver = hpx3_cap_id & 0xf;
2113
2114 if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id)
2115 return true;
2116 else if (cap_ver == pcie_cap_id)
2117 return true;
2118
2119 return false;
2120 }
2121
2122 static void program_hpx_type3_register(struct pci_dev *dev,
2123 const struct hpx_type3 *reg)
2124 {
2125 u32 match_reg, write_reg, header, orig_value;
2126 u16 pos;
2127
2128 if (!(hpx3_device_type(dev) & reg->device_type))
2129 return;
2130
2131 if (!(hpx3_function_type(dev) & reg->function_type))
2132 return;
2133
2134 switch (reg->config_space_location) {
2135 case HPX_CFG_PCICFG:
2136 pos = 0;
2137 break;
2138 case HPX_CFG_PCIE_CAP:
2139 pos = pci_find_capability(dev, reg->pci_exp_cap_id);
2140 if (pos == 0)
2141 return;
2142
2143 break;
2144 case HPX_CFG_PCIE_CAP_EXT:
2145 pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id);
2146 if (pos == 0)
2147 return;
2148
2149 pci_read_config_dword(dev, pos, &header);
2150 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header),
2151 reg->pci_exp_cap_ver))
2152 return;
2153
2154 break;
2155 case HPX_CFG_VEND_CAP: /* Fall through */
2156 case HPX_CFG_DVSEC: /* Fall through */
2157 default:
2158 pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location");
2159 return;
2160 }
2161
2162 pci_read_config_dword(dev, pos + reg->match_offset, &match_reg);
2163
2164 if ((match_reg & reg->match_mask_and) != reg->match_value)
2165 return;
2166
2167 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
2168 orig_value = write_reg;
2169 write_reg &= reg->reg_mask_and;
2170 write_reg |= reg->reg_mask_or;
2171
2172 if (orig_value == write_reg)
2173 return;
2174
2175 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
2176
2177 pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
2178 pos, orig_value, write_reg);
2179 }
2180
2181 static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx3)
2182 {
2183 if (!hpx3)
2184 return;
2185
2186 if (!pci_is_pcie(dev))
2187 return;
2188
2189 program_hpx_type3_register(dev, hpx3);
2190 }
2191
2192 int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2193 {
2194 struct pci_host_bridge *host;
2195 u32 cap;
2196 u16 ctl;
2197 int ret;
2198
2199 if (!pci_is_pcie(dev))
2200 return 0;
2201
2202 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2203 if (ret)
2204 return 0;
2205
2206 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2207 return 0;
2208
2209 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2210 if (ret)
2211 return 0;
2212
2213 host = pci_find_host_bridge(dev->bus);
2214 if (!host)
2215 return 0;
2216
2217 /*
2218 * If some device in the hierarchy doesn't handle Extended Tags
2219 * correctly, make sure they're disabled.
2220 */
2221 if (host->no_ext_tags) {
2222 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2223 pci_info(dev, "disabling Extended Tags\n");
2224 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2225 PCI_EXP_DEVCTL_EXT_TAG);
2226 }
2227 return 0;
2228 }
2229
2230 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2231 pci_info(dev, "enabling Extended Tags\n");
2232 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2233 PCI_EXP_DEVCTL_EXT_TAG);
2234 }
2235 return 0;
2236 }
2237
2238 /**
2239 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2240 * @dev: PCI device to query
2241 *
2242 * Returns true if the device has enabled relaxed ordering attribute.
2243 */
2244 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2245 {
2246 u16 v;
2247
2248 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2249
2250 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2251 }
2252 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2253
2254 static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2255 {
2256 struct pci_dev *root;
2257
2258 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2259 if (dev->is_virtfn)
2260 return;
2261
2262 if (!pcie_relaxed_ordering_enabled(dev))
2263 return;
2264
2265 /*
2266 * For now, we only deal with Relaxed Ordering issues with Root
2267 * Ports. Peer-to-Peer DMA is another can of worms.
2268 */
2269 root = pci_find_pcie_root_port(dev);
2270 if (!root)
2271 return;
2272
2273 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2274 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2275 PCI_EXP_DEVCTL_RELAX_EN);
2276 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2277 }
2278 }
2279
2280 static void pci_configure_ltr(struct pci_dev *dev)
2281 {
2282 #ifdef CONFIG_PCIEASPM
2283 struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
2284 struct pci_dev *bridge;
2285 u32 cap, ctl;
2286
2287 if (!pci_is_pcie(dev))
2288 return;
2289
2290 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2291 if (!(cap & PCI_EXP_DEVCAP2_LTR))
2292 return;
2293
2294 pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
2295 if (ctl & PCI_EXP_DEVCTL2_LTR_EN) {
2296 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
2297 dev->ltr_path = 1;
2298 return;
2299 }
2300
2301 bridge = pci_upstream_bridge(dev);
2302 if (bridge && bridge->ltr_path)
2303 dev->ltr_path = 1;
2304
2305 return;
2306 }
2307
2308 if (!host->native_ltr)
2309 return;
2310
2311 /*
2312 * Software must not enable LTR in an Endpoint unless the Root
2313 * Complex and all intermediate Switches indicate support for LTR.
2314 * PCIe r4.0, sec 6.18.
2315 */
2316 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
2317 ((bridge = pci_upstream_bridge(dev)) &&
2318 bridge->ltr_path)) {
2319 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2320 PCI_EXP_DEVCTL2_LTR_EN);
2321 dev->ltr_path = 1;
2322 }
2323 #endif
2324 }
2325
2326 static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2327 {
2328 #ifdef CONFIG_PCI_PASID
2329 struct pci_dev *bridge;
2330 int pcie_type;
2331 u32 cap;
2332
2333 if (!pci_is_pcie(dev))
2334 return;
2335
2336 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2337 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2338 return;
2339
2340 pcie_type = pci_pcie_type(dev);
2341 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2342 pcie_type == PCI_EXP_TYPE_RC_END)
2343 dev->eetlp_prefix_path = 1;
2344 else {
2345 bridge = pci_upstream_bridge(dev);
2346 if (bridge && bridge->eetlp_prefix_path)
2347 dev->eetlp_prefix_path = 1;
2348 }
2349 #endif
2350 }
2351
2352 static void pci_configure_serr(struct pci_dev *dev)
2353 {
2354 u16 control;
2355
2356 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2357
2358 /*
2359 * A bridge will not forward ERR_ messages coming from an
2360 * endpoint unless SERR# forwarding is enabled.
2361 */
2362 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2363 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2364 control |= PCI_BRIDGE_CTL_SERR;
2365 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2366 }
2367 }
2368 }
2369
2370 static void pci_configure_device(struct pci_dev *dev)
2371 {
2372 static const struct hotplug_program_ops hp_ops = {
2373 .program_type0 = program_hpp_type0,
2374 .program_type1 = program_hpp_type1,
2375 .program_type2 = program_hpp_type2,
2376 .program_type3 = program_hpx_type3,
2377 };
2378
2379 pci_configure_mps(dev);
2380 pci_configure_extended_tags(dev, NULL);
2381 pci_configure_relaxed_ordering(dev);
2382 pci_configure_ltr(dev);
2383 pci_configure_eetlp_prefix(dev);
2384 pci_configure_serr(dev);
2385
2386 pci_acpi_program_hp_params(dev, &hp_ops);
2387 }
2388
2389 static void pci_release_capabilities(struct pci_dev *dev)
2390 {
2391 pci_aer_exit(dev);
2392 pci_vpd_release(dev);
2393 pci_iov_release(dev);
2394 pci_free_cap_save_buffers(dev);
2395 }
2396
2397 /**
2398 * pci_release_dev - Free a PCI device structure when all users of it are
2399 * finished
2400 * @dev: device that's been disconnected
2401 *
2402 * Will be called only by the device core when all users of this PCI device are
2403 * done.
2404 */
2405 static void pci_release_dev(struct device *dev)
2406 {
2407 struct pci_dev *pci_dev;
2408
2409 pci_dev = to_pci_dev(dev);
2410 pci_release_capabilities(pci_dev);
2411 pci_release_of_node(pci_dev);
2412 pcibios_release_device(pci_dev);
2413 pci_bus_put(pci_dev->bus);
2414 kfree(pci_dev->driver_override);
2415 bitmap_free(pci_dev->dma_alias_mask);
2416 kfree(pci_dev);
2417 }
2418
2419 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2420 {
2421 struct pci_dev *dev;
2422
2423 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2424 if (!dev)
2425 return NULL;
2426
2427 INIT_LIST_HEAD(&dev->bus_list);
2428 dev->dev.type = &pci_dev_type;
2429 dev->bus = pci_bus_get(bus);
2430
2431 return dev;
2432 }
2433 EXPORT_SYMBOL(pci_alloc_dev);
2434
2435 static bool pci_bus_crs_vendor_id(u32 l)
2436 {
2437 return (l & 0xffff) == 0x0001;
2438 }
2439
2440 static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
2441 int timeout)
2442 {
2443 int delay = 1;
2444
2445 if (!pci_bus_crs_vendor_id(*l))
2446 return true; /* not a CRS completion */
2447
2448 if (!timeout)
2449 return false; /* CRS, but caller doesn't want to wait */
2450
2451 /*
2452 * We got the reserved Vendor ID that indicates a completion with
2453 * Configuration Request Retry Status (CRS). Retry until we get a
2454 * valid Vendor ID or we time out.
2455 */
2456 while (pci_bus_crs_vendor_id(*l)) {
2457 if (delay > timeout) {
2458 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2459 pci_domain_nr(bus), bus->number,
2460 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2461
2462 return false;
2463 }
2464 if (delay >= 1000)
2465 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2466 pci_domain_nr(bus), bus->number,
2467 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2468
2469 msleep(delay);
2470 delay *= 2;
2471
2472 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2473 return false;
2474 }
2475
2476 if (delay >= 1000)
2477 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2478 pci_domain_nr(bus), bus->number,
2479 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2480
2481 return true;
2482 }
2483
2484 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2485 int timeout)
2486 {
2487 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2488 return false;
2489
2490 /* Some broken boards return 0 or ~0 if a slot is empty: */
2491 if (*l == 0xffffffff || *l == 0x00000000 ||
2492 *l == 0x0000ffff || *l == 0xffff0000)
2493 return false;
2494
2495 if (pci_bus_crs_vendor_id(*l))
2496 return pci_bus_wait_crs(bus, devfn, l, timeout);
2497
2498 return true;
2499 }
2500
2501 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2502 int timeout)
2503 {
2504 #ifdef CONFIG_PCI_QUIRKS
2505 struct pci_dev *bridge = bus->self;
2506
2507 /*
2508 * Certain IDT switches have an issue where they improperly trigger
2509 * ACS Source Validation errors on completions for config reads.
2510 */
2511 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2512 bridge->device == 0x80b5)
2513 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2514 #endif
2515
2516 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2517 }
2518 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2519
2520 /*
2521 * Read the config data for a PCI device, sanity-check it,
2522 * and fill in the dev structure.
2523 */
2524 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2525 {
2526 struct pci_dev *dev;
2527 u32 l;
2528
2529 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2530 return NULL;
2531
2532 dev = pci_alloc_dev(bus);
2533 if (!dev)
2534 return NULL;
2535
2536 dev->devfn = devfn;
2537 dev->vendor = l & 0xffff;
2538 dev->device = (l >> 16) & 0xffff;
2539
2540 pci_set_of_node(dev);
2541
2542 if (pci_setup_device(dev)) {
2543 pci_bus_put(dev->bus);
2544 kfree(dev);
2545 return NULL;
2546 }
2547
2548 return dev;
2549 }
2550
2551 void pcie_report_downtraining(struct pci_dev *dev)
2552 {
2553 if (!pci_is_pcie(dev))
2554 return;
2555
2556 /* Look from the device up to avoid downstream ports with no devices */
2557 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2558 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2559 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2560 return;
2561
2562 /* Multi-function PCIe devices share the same link/status */
2563 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2564 return;
2565
2566 /* Print link status only if the device is constrained by the fabric */
2567 __pcie_print_link_status(dev, false);
2568 }
2569
2570 static void pci_init_capabilities(struct pci_dev *dev)
2571 {
2572 /* Enhanced Allocation */
2573 pci_ea_init(dev);
2574
2575 /* Setup MSI caps & disable MSI/MSI-X interrupts */
2576 pci_msi_setup_pci_dev(dev);
2577
2578 /* Buffers for saving PCIe and PCI-X capabilities */
2579 pci_allocate_cap_save_buffers(dev);
2580
2581 /* Power Management */
2582 pci_pm_init(dev);
2583
2584 /* Vital Product Data */
2585 pci_vpd_init(dev);
2586
2587 /* Alternative Routing-ID Forwarding */
2588 pci_configure_ari(dev);
2589
2590 /* Single Root I/O Virtualization */
2591 pci_iov_init(dev);
2592
2593 /* Address Translation Services */
2594 pci_ats_init(dev);
2595
2596 /* Enable ACS P2P upstream forwarding */
2597 pci_enable_acs(dev);
2598
2599 /* Precision Time Measurement */
2600 pci_ptm_init(dev);
2601
2602 /* Advanced Error Reporting */
2603 pci_aer_init(dev);
2604
2605 pcie_report_downtraining(dev);
2606
2607 if (pci_probe_reset_function(dev) == 0)
2608 dev->reset_fn = 1;
2609 }
2610
2611 /*
2612 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2613 * devices. Firmware interfaces that can select the MSI domain on a
2614 * per-device basis should be called from here.
2615 */
2616 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2617 {
2618 struct irq_domain *d;
2619
2620 /*
2621 * If a domain has been set through the pcibios_add_device()
2622 * callback, then this is the one (platform code knows best).
2623 */
2624 d = dev_get_msi_domain(&dev->dev);
2625 if (d)
2626 return d;
2627
2628 /*
2629 * Let's see if we have a firmware interface able to provide
2630 * the domain.
2631 */
2632 d = pci_msi_get_device_domain(dev);
2633 if (d)
2634 return d;
2635
2636 return NULL;
2637 }
2638
2639 static void pci_set_msi_domain(struct pci_dev *dev)
2640 {
2641 struct irq_domain *d;
2642
2643 /*
2644 * If the platform or firmware interfaces cannot supply a
2645 * device-specific MSI domain, then inherit the default domain
2646 * from the host bridge itself.
2647 */
2648 d = pci_dev_msi_domain(dev);
2649 if (!d)
2650 d = dev_get_msi_domain(&dev->bus->dev);
2651
2652 dev_set_msi_domain(&dev->dev, d);
2653 }
2654
2655 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2656 {
2657 int ret;
2658
2659 pci_configure_device(dev);
2660
2661 device_initialize(&dev->dev);
2662 dev->dev.release = pci_release_dev;
2663
2664 set_dev_node(&dev->dev, pcibus_to_node(bus));
2665 dev->dev.dma_mask = &dev->dma_mask;
2666 dev->dev.dma_parms = &dev->dma_parms;
2667 dev->dev.coherent_dma_mask = 0xffffffffull;
2668
2669 dma_set_max_seg_size(&dev->dev, 65536);
2670 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2671
2672 /* Fix up broken headers */
2673 pci_fixup_device(pci_fixup_header, dev);
2674
2675 /* Moved out from quirk header fixup code */
2676 pci_reassigndev_resource_alignment(dev);
2677
2678 /* Clear the state_saved flag */
2679 dev->state_saved = false;
2680
2681 /* Initialize various capabilities */
2682 pci_init_capabilities(dev);
2683
2684 /*
2685 * Add the device to our list of discovered devices
2686 * and the bus list for fixup functions, etc.
2687 */
2688 down_write(&pci_bus_sem);
2689 list_add_tail(&dev->bus_list, &bus->devices);
2690 up_write(&pci_bus_sem);
2691
2692 ret = pcibios_add_device(dev);
2693 WARN_ON(ret < 0);
2694
2695 /* Set up MSI IRQ domain */
2696 pci_set_msi_domain(dev);
2697
2698 /* Notifier could use PCI capabilities */
2699 dev->match_driver = false;
2700 ret = device_add(&dev->dev);
2701 WARN_ON(ret < 0);
2702 }
2703
2704 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2705 {
2706 struct pci_dev *dev;
2707
2708 dev = pci_get_slot(bus, devfn);
2709 if (dev) {
2710 pci_dev_put(dev);
2711 return dev;
2712 }
2713
2714 dev = pci_scan_device(bus, devfn);
2715 if (!dev)
2716 return NULL;
2717
2718 pci_device_add(dev, bus);
2719
2720 return dev;
2721 }
2722 EXPORT_SYMBOL(pci_scan_single_device);
2723
2724 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
2725 {
2726 int pos;
2727 u16 cap = 0;
2728 unsigned next_fn;
2729
2730 if (pci_ari_enabled(bus)) {
2731 if (!dev)
2732 return 0;
2733 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2734 if (!pos)
2735 return 0;
2736
2737 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2738 next_fn = PCI_ARI_CAP_NFN(cap);
2739 if (next_fn <= fn)
2740 return 0; /* protect against malformed list */
2741
2742 return next_fn;
2743 }
2744
2745 /* dev may be NULL for non-contiguous multifunction devices */
2746 if (!dev || dev->multifunction)
2747 return (fn + 1) % 8;
2748
2749 return 0;
2750 }
2751
2752 static int only_one_child(struct pci_bus *bus)
2753 {
2754 struct pci_dev *bridge = bus->self;
2755
2756 /*
2757 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2758 * we scan for all possible devices, not just Device 0.
2759 */
2760 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2761 return 0;
2762
2763 /*
2764 * A PCIe Downstream Port normally leads to a Link with only Device
2765 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2766 * only for Device 0 in that situation.
2767 *
2768 * Checking has_secondary_link is a hack to identify Downstream
2769 * Ports because sometimes Switches are configured such that the
2770 * PCIe Port Type labels are backwards.
2771 */
2772 if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
2773 return 1;
2774
2775 return 0;
2776 }
2777
2778 /**
2779 * pci_scan_slot - Scan a PCI slot on a bus for devices
2780 * @bus: PCI bus to scan
2781 * @devfn: slot number to scan (must have zero function)
2782 *
2783 * Scan a PCI slot on the specified PCI bus for devices, adding
2784 * discovered devices to the @bus->devices list. New devices
2785 * will not have is_added set.
2786 *
2787 * Returns the number of new devices found.
2788 */
2789 int pci_scan_slot(struct pci_bus *bus, int devfn)
2790 {
2791 unsigned fn, nr = 0;
2792 struct pci_dev *dev;
2793
2794 if (only_one_child(bus) && (devfn > 0))
2795 return 0; /* Already scanned the entire slot */
2796
2797 dev = pci_scan_single_device(bus, devfn);
2798 if (!dev)
2799 return 0;
2800 if (!pci_dev_is_added(dev))
2801 nr++;
2802
2803 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2804 dev = pci_scan_single_device(bus, devfn + fn);
2805 if (dev) {
2806 if (!pci_dev_is_added(dev))
2807 nr++;
2808 dev->multifunction = 1;
2809 }
2810 }
2811
2812 /* Only one slot has PCIe device */
2813 if (bus->self && nr)
2814 pcie_aspm_init_link_state(bus->self);
2815
2816 return nr;
2817 }
2818 EXPORT_SYMBOL(pci_scan_slot);
2819
2820 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2821 {
2822 u8 *smpss = data;
2823
2824 if (!pci_is_pcie(dev))
2825 return 0;
2826
2827 /*
2828 * We don't have a way to change MPS settings on devices that have
2829 * drivers attached. A hot-added device might support only the minimum
2830 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2831 * where devices may be hot-added, we limit the fabric MPS to 128 so
2832 * hot-added devices will work correctly.
2833 *
2834 * However, if we hot-add a device to a slot directly below a Root
2835 * Port, it's impossible for there to be other existing devices below
2836 * the port. We don't limit the MPS in this case because we can
2837 * reconfigure MPS on both the Root Port and the hot-added device,
2838 * and there are no other devices involved.
2839 *
2840 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2841 */
2842 if (dev->is_hotplug_bridge &&
2843 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2844 *smpss = 0;
2845
2846 if (*smpss > dev->pcie_mpss)
2847 *smpss = dev->pcie_mpss;
2848
2849 return 0;
2850 }
2851
2852 static void pcie_write_mps(struct pci_dev *dev, int mps)
2853 {
2854 int rc;
2855
2856 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2857 mps = 128 << dev->pcie_mpss;
2858
2859 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2860 dev->bus->self)
2861
2862 /*
2863 * For "Performance", the assumption is made that
2864 * downstream communication will never be larger than
2865 * the MRRS. So, the MPS only needs to be configured
2866 * for the upstream communication. This being the case,
2867 * walk from the top down and set the MPS of the child
2868 * to that of the parent bus.
2869 *
2870 * Configure the device MPS with the smaller of the
2871 * device MPSS or the bridge MPS (which is assumed to be
2872 * properly configured at this point to the largest
2873 * allowable MPS based on its parent bus).
2874 */
2875 mps = min(mps, pcie_get_mps(dev->bus->self));
2876 }
2877
2878 rc = pcie_set_mps(dev, mps);
2879 if (rc)
2880 pci_err(dev, "Failed attempting to set the MPS\n");
2881 }
2882
2883 static void pcie_write_mrrs(struct pci_dev *dev)
2884 {
2885 int rc, mrrs;
2886
2887 /*
2888 * In the "safe" case, do not configure the MRRS. There appear to be
2889 * issues with setting MRRS to 0 on a number of devices.
2890 */
2891 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2892 return;
2893
2894 /*
2895 * For max performance, the MRRS must be set to the largest supported
2896 * value. However, it cannot be configured larger than the MPS the
2897 * device or the bus can support. This should already be properly
2898 * configured by a prior call to pcie_write_mps().
2899 */
2900 mrrs = pcie_get_mps(dev);
2901
2902 /*
2903 * MRRS is a R/W register. Invalid values can be written, but a
2904 * subsequent read will verify if the value is acceptable or not.
2905 * If the MRRS value provided is not acceptable (e.g., too large),
2906 * shrink the value until it is acceptable to the HW.
2907 */
2908 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2909 rc = pcie_set_readrq(dev, mrrs);
2910 if (!rc)
2911 break;
2912
2913 pci_warn(dev, "Failed attempting to set the MRRS\n");
2914 mrrs /= 2;
2915 }
2916
2917 if (mrrs < 128)
2918 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2919 }
2920
2921 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2922 {
2923 int mps, orig_mps;
2924
2925 if (!pci_is_pcie(dev))
2926 return 0;
2927
2928 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2929 pcie_bus_config == PCIE_BUS_DEFAULT)
2930 return 0;
2931
2932 mps = 128 << *(u8 *)data;
2933 orig_mps = pcie_get_mps(dev);
2934
2935 pcie_write_mps(dev, mps);
2936 pcie_write_mrrs(dev);
2937
2938 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2939 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2940 orig_mps, pcie_get_readrq(dev));
2941
2942 return 0;
2943 }
2944
2945 /*
2946 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2947 * parents then children fashion. If this changes, then this code will not
2948 * work as designed.
2949 */
2950 void pcie_bus_configure_settings(struct pci_bus *bus)
2951 {
2952 u8 smpss = 0;
2953
2954 if (!bus->self)
2955 return;
2956
2957 if (!pci_is_pcie(bus->self))
2958 return;
2959
2960 /*
2961 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2962 * to be aware of the MPS of the destination. To work around this,
2963 * simply force the MPS of the entire system to the smallest possible.
2964 */
2965 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2966 smpss = 0;
2967
2968 if (pcie_bus_config == PCIE_BUS_SAFE) {
2969 smpss = bus->self->pcie_mpss;
2970
2971 pcie_find_smpss(bus->self, &smpss);
2972 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2973 }
2974
2975 pcie_bus_configure_set(bus->self, &smpss);
2976 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2977 }
2978 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2979
2980 /*
2981 * Called after each bus is probed, but before its children are examined. This
2982 * is marked as __weak because multiple architectures define it.
2983 */
2984 void __weak pcibios_fixup_bus(struct pci_bus *bus)
2985 {
2986 /* nothing to do, expected to be removed in the future */
2987 }
2988
2989 /**
2990 * pci_scan_child_bus_extend() - Scan devices below a bus
2991 * @bus: Bus to scan for devices
2992 * @available_buses: Total number of buses available (%0 does not try to
2993 * extend beyond the minimal)
2994 *
2995 * Scans devices below @bus including subordinate buses. Returns new
2996 * subordinate number including all the found devices. Passing
2997 * @available_buses causes the remaining bus space to be distributed
2998 * equally between hotplug-capable bridges to allow future extension of the
2999 * hierarchy.
3000 */
3001 static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
3002 unsigned int available_buses)
3003 {
3004 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
3005 unsigned int start = bus->busn_res.start;
3006 unsigned int devfn, fn, cmax, max = start;
3007 struct pci_dev *dev;
3008 int nr_devs;
3009
3010 dev_dbg(&bus->dev, "scanning bus\n");
3011
3012 /* Go find them, Rover! */
3013 for (devfn = 0; devfn < 256; devfn += 8) {
3014 nr_devs = pci_scan_slot(bus, devfn);
3015
3016 /*
3017 * The Jailhouse hypervisor may pass individual functions of a
3018 * multi-function device to a guest without passing function 0.
3019 * Look for them as well.
3020 */
3021 if (jailhouse_paravirt() && nr_devs == 0) {
3022 for (fn = 1; fn < 8; fn++) {
3023 dev = pci_scan_single_device(bus, devfn + fn);
3024 if (dev)
3025 dev->multifunction = 1;
3026 }
3027 }
3028 }
3029
3030 /* Reserve buses for SR-IOV capability */
3031 used_buses = pci_iov_bus_range(bus);
3032 max += used_buses;
3033
3034 /*
3035 * After performing arch-dependent fixup of the bus, look behind
3036 * all PCI-to-PCI bridges on this bus.
3037 */
3038 if (!bus->is_added) {
3039 dev_dbg(&bus->dev, "fixups for bus\n");
3040 pcibios_fixup_bus(bus);
3041 bus->is_added = 1;
3042 }
3043
3044 /*
3045 * Calculate how many hotplug bridges and normal bridges there
3046 * are on this bus. We will distribute the additional available
3047 * buses between hotplug bridges.
3048 */
3049 for_each_pci_bridge(dev, bus) {
3050 if (dev->is_hotplug_bridge)
3051 hotplug_bridges++;
3052 else
3053 normal_bridges++;
3054 }
3055
3056 /*
3057 * Scan bridges that are already configured. We don't touch them
3058 * unless they are misconfigured (which will be done in the second
3059 * scan below).
3060 */
3061 for_each_pci_bridge(dev, bus) {
3062 cmax = max;
3063 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
3064
3065 /*
3066 * Reserve one bus for each bridge now to avoid extending
3067 * hotplug bridges too much during the second scan below.
3068 */
3069 used_buses++;
3070 if (cmax - max > 1)
3071 used_buses += cmax - max - 1;
3072 }
3073
3074 /* Scan bridges that need to be reconfigured */
3075 for_each_pci_bridge(dev, bus) {
3076 unsigned int buses = 0;
3077
3078 if (!hotplug_bridges && normal_bridges == 1) {
3079
3080 /*
3081 * There is only one bridge on the bus (upstream
3082 * port) so it gets all available buses which it
3083 * can then distribute to the possible hotplug
3084 * bridges below.
3085 */
3086 buses = available_buses;
3087 } else if (dev->is_hotplug_bridge) {
3088
3089 /*
3090 * Distribute the extra buses between hotplug
3091 * bridges if any.
3092 */
3093 buses = available_buses / hotplug_bridges;
3094 buses = min(buses, available_buses - used_buses + 1);
3095 }
3096
3097 cmax = max;
3098 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
3099 /* One bus is already accounted so don't add it again */
3100 if (max - cmax > 1)
3101 used_buses += max - cmax - 1;
3102 }
3103
3104 /*
3105 * Make sure a hotplug bridge has at least the minimum requested
3106 * number of buses but allow it to grow up to the maximum available
3107 * bus number of there is room.
3108 */
3109 if (bus->self && bus->self->is_hotplug_bridge) {
3110 used_buses = max_t(unsigned int, available_buses,
3111 pci_hotplug_bus_size - 1);
3112 if (max - start < used_buses) {
3113 max = start + used_buses;
3114
3115 /* Do not allocate more buses than we have room left */
3116 if (max > bus->busn_res.end)
3117 max = bus->busn_res.end;
3118
3119 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
3120 &bus->busn_res, max - start);
3121 }
3122 }
3123
3124 /*
3125 * We've scanned the bus and so we know all about what's on
3126 * the other side of any bridges that may be on this bus plus
3127 * any devices.
3128 *
3129 * Return how far we've got finding sub-buses.
3130 */
3131 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
3132 return max;
3133 }
3134
3135 /**
3136 * pci_scan_child_bus() - Scan devices below a bus
3137 * @bus: Bus to scan for devices
3138 *
3139 * Scans devices below @bus including subordinate buses. Returns new
3140 * subordinate number including all the found devices.
3141 */
3142 unsigned int pci_scan_child_bus(struct pci_bus *bus)
3143 {
3144 return pci_scan_child_bus_extend(bus, 0);
3145 }
3146 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3147
3148 /**
3149 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3150 * @bridge: Host bridge to set up
3151 *
3152 * Default empty implementation. Replace with an architecture-specific setup
3153 * routine, if necessary.
3154 */
3155 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3156 {
3157 return 0;
3158 }
3159
3160 void __weak pcibios_add_bus(struct pci_bus *bus)
3161 {
3162 }
3163
3164 void __weak pcibios_remove_bus(struct pci_bus *bus)
3165 {
3166 }
3167
3168 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3169 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3170 {
3171 int error;
3172 struct pci_host_bridge *bridge;
3173
3174 bridge = pci_alloc_host_bridge(0);
3175 if (!bridge)
3176 return NULL;
3177
3178 bridge->dev.parent = parent;
3179
3180 list_splice_init(resources, &bridge->windows);
3181 bridge->sysdata = sysdata;
3182 bridge->busnr = bus;
3183 bridge->ops = ops;
3184
3185 error = pci_register_host_bridge(bridge);
3186 if (error < 0)
3187 goto err_out;
3188
3189 return bridge->bus;
3190
3191 err_out:
3192 kfree(bridge);
3193 return NULL;
3194 }
3195 EXPORT_SYMBOL_GPL(pci_create_root_bus);
3196
3197 int pci_host_probe(struct pci_host_bridge *bridge)
3198 {
3199 struct pci_bus *bus, *child;
3200 int ret;
3201
3202 ret = pci_scan_root_bus_bridge(bridge);
3203 if (ret < 0) {
3204 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3205 return ret;
3206 }
3207
3208 bus = bridge->bus;
3209
3210 /*
3211 * We insert PCI resources into the iomem_resource and
3212 * ioport_resource trees in either pci_bus_claim_resources()
3213 * or pci_bus_assign_resources().
3214 */
3215 if (pci_has_flag(PCI_PROBE_ONLY)) {
3216 pci_bus_claim_resources(bus);
3217 } else {
3218 pci_bus_size_bridges(bus);
3219 pci_bus_assign_resources(bus);
3220
3221 list_for_each_entry(child, &bus->children, node)
3222 pcie_bus_configure_settings(child);
3223 }
3224
3225 pci_bus_add_devices(bus);
3226 return 0;
3227 }
3228 EXPORT_SYMBOL_GPL(pci_host_probe);
3229
3230 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3231 {
3232 struct resource *res = &b->busn_res;
3233 struct resource *parent_res, *conflict;
3234
3235 res->start = bus;
3236 res->end = bus_max;
3237 res->flags = IORESOURCE_BUS;
3238
3239 if (!pci_is_root_bus(b))
3240 parent_res = &b->parent->busn_res;
3241 else {
3242 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3243 res->flags |= IORESOURCE_PCI_FIXED;
3244 }
3245
3246 conflict = request_resource_conflict(parent_res, res);
3247
3248 if (conflict)
3249 dev_info(&b->dev,
3250 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3251 res, pci_is_root_bus(b) ? "domain " : "",
3252 parent_res, conflict->name, conflict);
3253
3254 return conflict == NULL;
3255 }
3256
3257 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3258 {
3259 struct resource *res = &b->busn_res;
3260 struct resource old_res = *res;
3261 resource_size_t size;
3262 int ret;
3263
3264 if (res->start > bus_max)
3265 return -EINVAL;
3266
3267 size = bus_max - res->start + 1;
3268 ret = adjust_resource(res, res->start, size);
3269 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3270 &old_res, ret ? "can not be" : "is", bus_max);
3271
3272 if (!ret && !res->parent)
3273 pci_bus_insert_busn_res(b, res->start, res->end);
3274
3275 return ret;
3276 }
3277
3278 void pci_bus_release_busn_res(struct pci_bus *b)
3279 {
3280 struct resource *res = &b->busn_res;
3281 int ret;
3282
3283 if (!res->flags || !res->parent)
3284 return;
3285
3286 ret = release_resource(res);
3287 dev_info(&b->dev, "busn_res: %pR %s released\n",
3288 res, ret ? "can not be" : "is");
3289 }
3290
3291 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3292 {
3293 struct resource_entry *window;
3294 bool found = false;
3295 struct pci_bus *b;
3296 int max, bus, ret;
3297
3298 if (!bridge)
3299 return -EINVAL;
3300
3301 resource_list_for_each_entry(window, &bridge->windows)
3302 if (window->res->flags & IORESOURCE_BUS) {
3303 found = true;
3304 break;
3305 }
3306
3307 ret = pci_register_host_bridge(bridge);
3308 if (ret < 0)
3309 return ret;
3310
3311 b = bridge->bus;
3312 bus = bridge->busnr;
3313
3314 if (!found) {
3315 dev_info(&b->dev,
3316 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3317 bus);
3318 pci_bus_insert_busn_res(b, bus, 255);
3319 }
3320
3321 max = pci_scan_child_bus(b);
3322
3323 if (!found)
3324 pci_bus_update_busn_res_end(b, max);
3325
3326 return 0;
3327 }
3328 EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3329
3330 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3331 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3332 {
3333 struct resource_entry *window;
3334 bool found = false;
3335 struct pci_bus *b;
3336 int max;
3337
3338 resource_list_for_each_entry(window, resources)
3339 if (window->res->flags & IORESOURCE_BUS) {
3340 found = true;
3341 break;
3342 }
3343
3344 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3345 if (!b)
3346 return NULL;
3347
3348 if (!found) {
3349 dev_info(&b->dev,
3350 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3351 bus);
3352 pci_bus_insert_busn_res(b, bus, 255);
3353 }
3354
3355 max = pci_scan_child_bus(b);
3356
3357 if (!found)
3358 pci_bus_update_busn_res_end(b, max);
3359
3360 return b;
3361 }
3362 EXPORT_SYMBOL(pci_scan_root_bus);
3363
3364 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3365 void *sysdata)
3366 {
3367 LIST_HEAD(resources);
3368 struct pci_bus *b;
3369
3370 pci_add_resource(&resources, &ioport_resource);
3371 pci_add_resource(&resources, &iomem_resource);
3372 pci_add_resource(&resources, &busn_resource);
3373 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3374 if (b) {
3375 pci_scan_child_bus(b);
3376 } else {
3377 pci_free_resource_list(&resources);
3378 }
3379 return b;
3380 }
3381 EXPORT_SYMBOL(pci_scan_bus);
3382
3383 /**
3384 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3385 * @bridge: PCI bridge for the bus to scan
3386 *
3387 * Scan a PCI bus and child buses for new devices, add them,
3388 * and enable them, resizing bridge mmio/io resource if necessary
3389 * and possible. The caller must ensure the child devices are already
3390 * removed for resizing to occur.
3391 *
3392 * Returns the max number of subordinate bus discovered.
3393 */
3394 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3395 {
3396 unsigned int max;
3397 struct pci_bus *bus = bridge->subordinate;
3398
3399 max = pci_scan_child_bus(bus);
3400
3401 pci_assign_unassigned_bridge_resources(bridge);
3402
3403 pci_bus_add_devices(bus);
3404
3405 return max;
3406 }
3407
3408 /**
3409 * pci_rescan_bus - Scan a PCI bus for devices
3410 * @bus: PCI bus to scan
3411 *
3412 * Scan a PCI bus and child buses for new devices, add them,
3413 * and enable them.
3414 *
3415 * Returns the max number of subordinate bus discovered.
3416 */
3417 unsigned int pci_rescan_bus(struct pci_bus *bus)
3418 {
3419 unsigned int max;
3420
3421 max = pci_scan_child_bus(bus);
3422 pci_assign_unassigned_bus_resources(bus);
3423 pci_bus_add_devices(bus);
3424
3425 return max;
3426 }
3427 EXPORT_SYMBOL_GPL(pci_rescan_bus);
3428
3429 /*
3430 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3431 * routines should always be executed under this mutex.
3432 */
3433 static DEFINE_MUTEX(pci_rescan_remove_lock);
3434
3435 void pci_lock_rescan_remove(void)
3436 {
3437 mutex_lock(&pci_rescan_remove_lock);
3438 }
3439 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3440
3441 void pci_unlock_rescan_remove(void)
3442 {
3443 mutex_unlock(&pci_rescan_remove_lock);
3444 }
3445 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3446
3447 static int __init pci_sort_bf_cmp(const struct device *d_a,
3448 const struct device *d_b)
3449 {
3450 const struct pci_dev *a = to_pci_dev(d_a);
3451 const struct pci_dev *b = to_pci_dev(d_b);
3452
3453 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3454 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3455
3456 if (a->bus->number < b->bus->number) return -1;
3457 else if (a->bus->number > b->bus->number) return 1;
3458
3459 if (a->devfn < b->devfn) return -1;
3460 else if (a->devfn > b->devfn) return 1;
3461
3462 return 0;
3463 }
3464
3465 void __init pci_sort_breadthfirst(void)
3466 {
3467 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3468 }
3469
3470 int pci_hp_add_bridge(struct pci_dev *dev)
3471 {
3472 struct pci_bus *parent = dev->bus;
3473 int busnr, start = parent->busn_res.start;
3474 unsigned int available_buses = 0;
3475 int end = parent->busn_res.end;
3476
3477 for (busnr = start; busnr <= end; busnr++) {
3478 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3479 break;
3480 }
3481 if (busnr-- > end) {
3482 pci_err(dev, "No bus number available for hot-added bridge\n");
3483 return -1;
3484 }
3485
3486 /* Scan bridges that are already configured */
3487 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3488
3489 /*
3490 * Distribute the available bus numbers between hotplug-capable
3491 * bridges to make extending the chain later possible.
3492 */
3493 available_buses = end - busnr;
3494
3495 /* Scan bridges that need to be reconfigured */
3496 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3497
3498 if (!dev->subordinate)
3499 return -1;
3500
3501 return 0;
3502 }
3503 EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
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