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Merge tag 'xfs-for-linus-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dgc...
[mirror_ubuntu-artful-kernel.git] / drivers / pci / probe.c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_pci.h>
10 #include <linux/pci_hotplug.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/cpumask.h>
14 #include <linux/pci-aspm.h>
15 #include <linux/aer.h>
16 #include <asm-generic/pci-bridge.h>
17 #include "pci.h"
18
19 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
20 #define CARDBUS_RESERVE_BUSNR 3
21
22 static struct resource busn_resource = {
23 .name = "PCI busn",
24 .start = 0,
25 .end = 255,
26 .flags = IORESOURCE_BUS,
27 };
28
29 /* Ugh. Need to stop exporting this to modules. */
30 LIST_HEAD(pci_root_buses);
31 EXPORT_SYMBOL(pci_root_buses);
32
33 static LIST_HEAD(pci_domain_busn_res_list);
34
35 struct pci_domain_busn_res {
36 struct list_head list;
37 struct resource res;
38 int domain_nr;
39 };
40
41 static struct resource *get_pci_domain_busn_res(int domain_nr)
42 {
43 struct pci_domain_busn_res *r;
44
45 list_for_each_entry(r, &pci_domain_busn_res_list, list)
46 if (r->domain_nr == domain_nr)
47 return &r->res;
48
49 r = kzalloc(sizeof(*r), GFP_KERNEL);
50 if (!r)
51 return NULL;
52
53 r->domain_nr = domain_nr;
54 r->res.start = 0;
55 r->res.end = 0xff;
56 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
57
58 list_add_tail(&r->list, &pci_domain_busn_res_list);
59
60 return &r->res;
61 }
62
63 static int find_anything(struct device *dev, void *data)
64 {
65 return 1;
66 }
67
68 /*
69 * Some device drivers need know if pci is initiated.
70 * Basically, we think pci is not initiated when there
71 * is no device to be found on the pci_bus_type.
72 */
73 int no_pci_devices(void)
74 {
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82 }
83 EXPORT_SYMBOL(no_pci_devices);
84
85 /*
86 * PCI Bus Class
87 */
88 static void release_pcibus_dev(struct device *dev)
89 {
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96 }
97
98 static struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102 };
103
104 static int __init pcibus_class_init(void)
105 {
106 return class_register(&pcibus_class);
107 }
108 postcore_initcall(pcibus_class_init);
109
110 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111 {
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
116 /* Get the lowest of them to find the decode size, and
117 from that the extent. */
118 size = (size & ~(size-1)) - 1;
119
120 /* base == maxbase can be valid only if the BAR has
121 already been programmed with all 1s. */
122 if (base == maxbase && ((base | size) & mask) != mask)
123 return 0;
124
125 return size;
126 }
127
128 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
129 {
130 u32 mem_type;
131 unsigned long flags;
132
133 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
134 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
135 flags |= IORESOURCE_IO;
136 return flags;
137 }
138
139 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
140 flags |= IORESOURCE_MEM;
141 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
142 flags |= IORESOURCE_PREFETCH;
143
144 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
145 switch (mem_type) {
146 case PCI_BASE_ADDRESS_MEM_TYPE_32:
147 break;
148 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
149 /* 1M mem BAR treated as 32-bit BAR */
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_64:
152 flags |= IORESOURCE_MEM_64;
153 break;
154 default:
155 /* mem unknown type treated as 32-bit BAR */
156 break;
157 }
158 return flags;
159 }
160
161 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
162
163 /**
164 * pci_read_base - read a PCI BAR
165 * @dev: the PCI device
166 * @type: type of the BAR
167 * @res: resource buffer to be filled in
168 * @pos: BAR position in the config space
169 *
170 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 */
172 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
173 struct resource *res, unsigned int pos)
174 {
175 u32 l, sz, mask;
176 u64 l64, sz64, mask64;
177 u16 orig_cmd;
178 struct pci_bus_region region, inverted_region;
179
180 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
181
182 /* No printks while decoding is disabled! */
183 if (!dev->mmio_always_on) {
184 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
185 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
186 pci_write_config_word(dev, PCI_COMMAND,
187 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
188 }
189 }
190
191 res->name = pci_name(dev);
192
193 pci_read_config_dword(dev, pos, &l);
194 pci_write_config_dword(dev, pos, l | mask);
195 pci_read_config_dword(dev, pos, &sz);
196 pci_write_config_dword(dev, pos, l);
197
198 /*
199 * All bits set in sz means the device isn't working properly.
200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
202 * 1 must be clear.
203 */
204 if (sz == 0xffffffff)
205 sz = 0;
206
207 /*
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
210 */
211 if (l == 0xffffffff)
212 l = 0;
213
214 if (type == pci_bar_unknown) {
215 res->flags = decode_bar(dev, l);
216 res->flags |= IORESOURCE_SIZEALIGN;
217 if (res->flags & IORESOURCE_IO) {
218 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
219 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
220 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
221 } else {
222 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
223 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
224 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
225 }
226 } else {
227 res->flags |= (l & IORESOURCE_ROM_ENABLE);
228 l64 = l & PCI_ROM_ADDRESS_MASK;
229 sz64 = sz & PCI_ROM_ADDRESS_MASK;
230 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
231 }
232
233 if (res->flags & IORESOURCE_MEM_64) {
234 pci_read_config_dword(dev, pos + 4, &l);
235 pci_write_config_dword(dev, pos + 4, ~0);
236 pci_read_config_dword(dev, pos + 4, &sz);
237 pci_write_config_dword(dev, pos + 4, l);
238
239 l64 |= ((u64)l << 32);
240 sz64 |= ((u64)sz << 32);
241 mask64 |= ((u64)~0 << 32);
242 }
243
244 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
245 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
246
247 if (!sz64)
248 goto fail;
249
250 sz64 = pci_size(l64, sz64, mask64);
251 if (!sz64) {
252 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
253 pos);
254 goto fail;
255 }
256
257 if (res->flags & IORESOURCE_MEM_64) {
258 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
259 && sz64 > 0x100000000ULL) {
260 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
261 res->start = 0;
262 res->end = 0;
263 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
264 pos, (unsigned long long)sz64);
265 goto out;
266 }
267
268 if ((sizeof(pci_bus_addr_t) < 8) && l) {
269 /* Above 32-bit boundary; try to reallocate */
270 res->flags |= IORESOURCE_UNSET;
271 res->start = 0;
272 res->end = sz64;
273 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
274 pos, (unsigned long long)l64);
275 goto out;
276 }
277 }
278
279 region.start = l64;
280 region.end = l64 + sz64;
281
282 pcibios_bus_to_resource(dev->bus, res, &region);
283 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
284
285 /*
286 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
287 * the corresponding resource address (the physical address used by
288 * the CPU. Converting that resource address back to a bus address
289 * should yield the original BAR value:
290 *
291 * resource_to_bus(bus_to_resource(A)) == A
292 *
293 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
294 * be claimed by the device.
295 */
296 if (inverted_region.start != region.start) {
297 res->flags |= IORESOURCE_UNSET;
298 res->start = 0;
299 res->end = region.end - region.start;
300 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
301 pos, (unsigned long long)region.start);
302 }
303
304 goto out;
305
306
307 fail:
308 res->flags = 0;
309 out:
310 if (res->flags)
311 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
312
313 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
314 }
315
316 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
317 {
318 unsigned int pos, reg;
319
320 for (pos = 0; pos < howmany; pos++) {
321 struct resource *res = &dev->resource[pos];
322 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
323 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
324 }
325
326 if (rom) {
327 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
328 dev->rom_base_reg = rom;
329 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
330 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
331 __pci_read_base(dev, pci_bar_mem32, res, rom);
332 }
333 }
334
335 static void pci_read_bridge_io(struct pci_bus *child)
336 {
337 struct pci_dev *dev = child->self;
338 u8 io_base_lo, io_limit_lo;
339 unsigned long io_mask, io_granularity, base, limit;
340 struct pci_bus_region region;
341 struct resource *res;
342
343 io_mask = PCI_IO_RANGE_MASK;
344 io_granularity = 0x1000;
345 if (dev->io_window_1k) {
346 /* Support 1K I/O space granularity */
347 io_mask = PCI_IO_1K_RANGE_MASK;
348 io_granularity = 0x400;
349 }
350
351 res = child->resource[0];
352 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
353 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
354 base = (io_base_lo & io_mask) << 8;
355 limit = (io_limit_lo & io_mask) << 8;
356
357 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
358 u16 io_base_hi, io_limit_hi;
359
360 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
361 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
362 base |= ((unsigned long) io_base_hi << 16);
363 limit |= ((unsigned long) io_limit_hi << 16);
364 }
365
366 if (base <= limit) {
367 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
368 region.start = base;
369 region.end = limit + io_granularity - 1;
370 pcibios_bus_to_resource(dev->bus, res, &region);
371 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
372 }
373 }
374
375 static void pci_read_bridge_mmio(struct pci_bus *child)
376 {
377 struct pci_dev *dev = child->self;
378 u16 mem_base_lo, mem_limit_lo;
379 unsigned long base, limit;
380 struct pci_bus_region region;
381 struct resource *res;
382
383 res = child->resource[1];
384 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
385 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
386 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
387 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 if (base <= limit) {
389 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
390 region.start = base;
391 region.end = limit + 0xfffff;
392 pcibios_bus_to_resource(dev->bus, res, &region);
393 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
394 }
395 }
396
397 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
398 {
399 struct pci_dev *dev = child->self;
400 u16 mem_base_lo, mem_limit_lo;
401 u64 base64, limit64;
402 pci_bus_addr_t base, limit;
403 struct pci_bus_region region;
404 struct resource *res;
405
406 res = child->resource[2];
407 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
408 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
409 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
410 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
411
412 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
413 u32 mem_base_hi, mem_limit_hi;
414
415 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
416 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
417
418 /*
419 * Some bridges set the base > limit by default, and some
420 * (broken) BIOSes do not initialize them. If we find
421 * this, just assume they are not being used.
422 */
423 if (mem_base_hi <= mem_limit_hi) {
424 base64 |= (u64) mem_base_hi << 32;
425 limit64 |= (u64) mem_limit_hi << 32;
426 }
427 }
428
429 base = (pci_bus_addr_t) base64;
430 limit = (pci_bus_addr_t) limit64;
431
432 if (base != base64) {
433 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
434 (unsigned long long) base64);
435 return;
436 }
437
438 if (base <= limit) {
439 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
440 IORESOURCE_MEM | IORESOURCE_PREFETCH;
441 if (res->flags & PCI_PREF_RANGE_TYPE_64)
442 res->flags |= IORESOURCE_MEM_64;
443 region.start = base;
444 region.end = limit + 0xfffff;
445 pcibios_bus_to_resource(dev->bus, res, &region);
446 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
447 }
448 }
449
450 void pci_read_bridge_bases(struct pci_bus *child)
451 {
452 struct pci_dev *dev = child->self;
453 struct resource *res;
454 int i;
455
456 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
457 return;
458
459 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
460 &child->busn_res,
461 dev->transparent ? " (subtractive decode)" : "");
462
463 pci_bus_remove_resources(child);
464 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
465 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
466
467 pci_read_bridge_io(child);
468 pci_read_bridge_mmio(child);
469 pci_read_bridge_mmio_pref(child);
470
471 if (dev->transparent) {
472 pci_bus_for_each_resource(child->parent, res, i) {
473 if (res && res->flags) {
474 pci_bus_add_resource(child, res,
475 PCI_SUBTRACTIVE_DECODE);
476 dev_printk(KERN_DEBUG, &dev->dev,
477 " bridge window %pR (subtractive decode)\n",
478 res);
479 }
480 }
481 }
482 }
483
484 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
485 {
486 struct pci_bus *b;
487
488 b = kzalloc(sizeof(*b), GFP_KERNEL);
489 if (!b)
490 return NULL;
491
492 INIT_LIST_HEAD(&b->node);
493 INIT_LIST_HEAD(&b->children);
494 INIT_LIST_HEAD(&b->devices);
495 INIT_LIST_HEAD(&b->slots);
496 INIT_LIST_HEAD(&b->resources);
497 b->max_bus_speed = PCI_SPEED_UNKNOWN;
498 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
499 #ifdef CONFIG_PCI_DOMAINS_GENERIC
500 if (parent)
501 b->domain_nr = parent->domain_nr;
502 #endif
503 return b;
504 }
505
506 static void pci_release_host_bridge_dev(struct device *dev)
507 {
508 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
509
510 if (bridge->release_fn)
511 bridge->release_fn(bridge);
512
513 pci_free_resource_list(&bridge->windows);
514
515 kfree(bridge);
516 }
517
518 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
519 {
520 struct pci_host_bridge *bridge;
521
522 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
523 if (!bridge)
524 return NULL;
525
526 INIT_LIST_HEAD(&bridge->windows);
527 bridge->bus = b;
528 return bridge;
529 }
530
531 static const unsigned char pcix_bus_speed[] = {
532 PCI_SPEED_UNKNOWN, /* 0 */
533 PCI_SPEED_66MHz_PCIX, /* 1 */
534 PCI_SPEED_100MHz_PCIX, /* 2 */
535 PCI_SPEED_133MHz_PCIX, /* 3 */
536 PCI_SPEED_UNKNOWN, /* 4 */
537 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
538 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
539 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
540 PCI_SPEED_UNKNOWN, /* 8 */
541 PCI_SPEED_66MHz_PCIX_266, /* 9 */
542 PCI_SPEED_100MHz_PCIX_266, /* A */
543 PCI_SPEED_133MHz_PCIX_266, /* B */
544 PCI_SPEED_UNKNOWN, /* C */
545 PCI_SPEED_66MHz_PCIX_533, /* D */
546 PCI_SPEED_100MHz_PCIX_533, /* E */
547 PCI_SPEED_133MHz_PCIX_533 /* F */
548 };
549
550 const unsigned char pcie_link_speed[] = {
551 PCI_SPEED_UNKNOWN, /* 0 */
552 PCIE_SPEED_2_5GT, /* 1 */
553 PCIE_SPEED_5_0GT, /* 2 */
554 PCIE_SPEED_8_0GT, /* 3 */
555 PCI_SPEED_UNKNOWN, /* 4 */
556 PCI_SPEED_UNKNOWN, /* 5 */
557 PCI_SPEED_UNKNOWN, /* 6 */
558 PCI_SPEED_UNKNOWN, /* 7 */
559 PCI_SPEED_UNKNOWN, /* 8 */
560 PCI_SPEED_UNKNOWN, /* 9 */
561 PCI_SPEED_UNKNOWN, /* A */
562 PCI_SPEED_UNKNOWN, /* B */
563 PCI_SPEED_UNKNOWN, /* C */
564 PCI_SPEED_UNKNOWN, /* D */
565 PCI_SPEED_UNKNOWN, /* E */
566 PCI_SPEED_UNKNOWN /* F */
567 };
568
569 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
570 {
571 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
572 }
573 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
574
575 static unsigned char agp_speeds[] = {
576 AGP_UNKNOWN,
577 AGP_1X,
578 AGP_2X,
579 AGP_4X,
580 AGP_8X
581 };
582
583 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
584 {
585 int index = 0;
586
587 if (agpstat & 4)
588 index = 3;
589 else if (agpstat & 2)
590 index = 2;
591 else if (agpstat & 1)
592 index = 1;
593 else
594 goto out;
595
596 if (agp3) {
597 index += 2;
598 if (index == 5)
599 index = 0;
600 }
601
602 out:
603 return agp_speeds[index];
604 }
605
606 static void pci_set_bus_speed(struct pci_bus *bus)
607 {
608 struct pci_dev *bridge = bus->self;
609 int pos;
610
611 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
612 if (!pos)
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
614 if (pos) {
615 u32 agpstat, agpcmd;
616
617 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
618 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
619
620 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
621 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
622 }
623
624 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
625 if (pos) {
626 u16 status;
627 enum pci_bus_speed max;
628
629 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
630 &status);
631
632 if (status & PCI_X_SSTATUS_533MHZ) {
633 max = PCI_SPEED_133MHz_PCIX_533;
634 } else if (status & PCI_X_SSTATUS_266MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_266;
636 } else if (status & PCI_X_SSTATUS_133MHZ) {
637 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
638 max = PCI_SPEED_133MHz_PCIX_ECC;
639 else
640 max = PCI_SPEED_133MHz_PCIX;
641 } else {
642 max = PCI_SPEED_66MHz_PCIX;
643 }
644
645 bus->max_bus_speed = max;
646 bus->cur_bus_speed = pcix_bus_speed[
647 (status & PCI_X_SSTATUS_FREQ) >> 6];
648
649 return;
650 }
651
652 if (pci_is_pcie(bridge)) {
653 u32 linkcap;
654 u16 linksta;
655
656 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
657 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
658
659 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
660 pcie_update_link_speed(bus, linksta);
661 }
662 }
663
664 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
665 {
666 struct irq_domain *d;
667
668 /*
669 * Any firmware interface that can resolve the msi_domain
670 * should be called from here.
671 */
672 d = pci_host_bridge_of_msi_domain(bus);
673
674 return d;
675 }
676
677 static void pci_set_bus_msi_domain(struct pci_bus *bus)
678 {
679 struct irq_domain *d;
680 struct pci_bus *b;
681
682 /*
683 * The bus can be a root bus, a subordinate bus, or a virtual bus
684 * created by an SR-IOV device. Walk up to the first bridge device
685 * found or derive the domain from the host bridge.
686 */
687 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
688 if (b->self)
689 d = dev_get_msi_domain(&b->self->dev);
690 }
691
692 if (!d)
693 d = pci_host_bridge_msi_domain(b);
694
695 dev_set_msi_domain(&bus->dev, d);
696 }
697
698 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
699 struct pci_dev *bridge, int busnr)
700 {
701 struct pci_bus *child;
702 int i;
703 int ret;
704
705 /*
706 * Allocate a new bus, and inherit stuff from the parent..
707 */
708 child = pci_alloc_bus(parent);
709 if (!child)
710 return NULL;
711
712 child->parent = parent;
713 child->ops = parent->ops;
714 child->msi = parent->msi;
715 child->sysdata = parent->sysdata;
716 child->bus_flags = parent->bus_flags;
717
718 /* initialize some portions of the bus device, but don't register it
719 * now as the parent is not properly set up yet.
720 */
721 child->dev.class = &pcibus_class;
722 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
723
724 /*
725 * Set up the primary, secondary and subordinate
726 * bus numbers.
727 */
728 child->number = child->busn_res.start = busnr;
729 child->primary = parent->busn_res.start;
730 child->busn_res.end = 0xff;
731
732 if (!bridge) {
733 child->dev.parent = parent->bridge;
734 goto add_dev;
735 }
736
737 child->self = bridge;
738 child->bridge = get_device(&bridge->dev);
739 child->dev.parent = child->bridge;
740 pci_set_bus_of_node(child);
741 pci_set_bus_speed(child);
742
743 /* Set up default resource pointers and names.. */
744 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
745 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
746 child->resource[i]->name = child->name;
747 }
748 bridge->subordinate = child;
749
750 add_dev:
751 pci_set_bus_msi_domain(child);
752 ret = device_register(&child->dev);
753 WARN_ON(ret < 0);
754
755 pcibios_add_bus(child);
756
757 /* Create legacy_io and legacy_mem files for this bus */
758 pci_create_legacy_files(child);
759
760 return child;
761 }
762
763 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
764 int busnr)
765 {
766 struct pci_bus *child;
767
768 child = pci_alloc_child_bus(parent, dev, busnr);
769 if (child) {
770 down_write(&pci_bus_sem);
771 list_add_tail(&child->node, &parent->children);
772 up_write(&pci_bus_sem);
773 }
774 return child;
775 }
776 EXPORT_SYMBOL(pci_add_new_bus);
777
778 static void pci_enable_crs(struct pci_dev *pdev)
779 {
780 u16 root_cap = 0;
781
782 /* Enable CRS Software Visibility if supported */
783 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
784 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
785 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
786 PCI_EXP_RTCTL_CRSSVE);
787 }
788
789 /*
790 * If it's a bridge, configure it and scan the bus behind it.
791 * For CardBus bridges, we don't scan behind as the devices will
792 * be handled by the bridge driver itself.
793 *
794 * We need to process bridges in two passes -- first we scan those
795 * already configured by the BIOS and after we are done with all of
796 * them, we proceed to assigning numbers to the remaining buses in
797 * order to avoid overlaps between old and new bus numbers.
798 */
799 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
800 {
801 struct pci_bus *child;
802 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
803 u32 buses, i, j = 0;
804 u16 bctl;
805 u8 primary, secondary, subordinate;
806 int broken = 0;
807
808 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
809 primary = buses & 0xFF;
810 secondary = (buses >> 8) & 0xFF;
811 subordinate = (buses >> 16) & 0xFF;
812
813 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
814 secondary, subordinate, pass);
815
816 if (!primary && (primary != bus->number) && secondary && subordinate) {
817 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
818 primary = bus->number;
819 }
820
821 /* Check if setup is sensible at all */
822 if (!pass &&
823 (primary != bus->number || secondary <= bus->number ||
824 secondary > subordinate)) {
825 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
826 secondary, subordinate);
827 broken = 1;
828 }
829
830 /* Disable MasterAbortMode during probing to avoid reporting
831 of bus errors (in some architectures) */
832 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
833 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
834 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
835
836 pci_enable_crs(dev);
837
838 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
839 !is_cardbus && !broken) {
840 unsigned int cmax;
841 /*
842 * Bus already configured by firmware, process it in the first
843 * pass and just note the configuration.
844 */
845 if (pass)
846 goto out;
847
848 /*
849 * The bus might already exist for two reasons: Either we are
850 * rescanning the bus or the bus is reachable through more than
851 * one bridge. The second case can happen with the i450NX
852 * chipset.
853 */
854 child = pci_find_bus(pci_domain_nr(bus), secondary);
855 if (!child) {
856 child = pci_add_new_bus(bus, dev, secondary);
857 if (!child)
858 goto out;
859 child->primary = primary;
860 pci_bus_insert_busn_res(child, secondary, subordinate);
861 child->bridge_ctl = bctl;
862 }
863
864 cmax = pci_scan_child_bus(child);
865 if (cmax > subordinate)
866 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
867 subordinate, cmax);
868 /* subordinate should equal child->busn_res.end */
869 if (subordinate > max)
870 max = subordinate;
871 } else {
872 /*
873 * We need to assign a number to this bus which we always
874 * do in the second pass.
875 */
876 if (!pass) {
877 if (pcibios_assign_all_busses() || broken || is_cardbus)
878 /* Temporarily disable forwarding of the
879 configuration cycles on all bridges in
880 this bus segment to avoid possible
881 conflicts in the second pass between two
882 bridges programmed with overlapping
883 bus ranges. */
884 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
885 buses & ~0xffffff);
886 goto out;
887 }
888
889 /* Clear errors */
890 pci_write_config_word(dev, PCI_STATUS, 0xffff);
891
892 /* Prevent assigning a bus number that already exists.
893 * This can happen when a bridge is hot-plugged, so in
894 * this case we only re-scan this bus. */
895 child = pci_find_bus(pci_domain_nr(bus), max+1);
896 if (!child) {
897 child = pci_add_new_bus(bus, dev, max+1);
898 if (!child)
899 goto out;
900 pci_bus_insert_busn_res(child, max+1, 0xff);
901 }
902 max++;
903 buses = (buses & 0xff000000)
904 | ((unsigned int)(child->primary) << 0)
905 | ((unsigned int)(child->busn_res.start) << 8)
906 | ((unsigned int)(child->busn_res.end) << 16);
907
908 /*
909 * yenta.c forces a secondary latency timer of 176.
910 * Copy that behaviour here.
911 */
912 if (is_cardbus) {
913 buses &= ~0xff000000;
914 buses |= CARDBUS_LATENCY_TIMER << 24;
915 }
916
917 /*
918 * We need to blast all three values with a single write.
919 */
920 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
921
922 if (!is_cardbus) {
923 child->bridge_ctl = bctl;
924 max = pci_scan_child_bus(child);
925 } else {
926 /*
927 * For CardBus bridges, we leave 4 bus numbers
928 * as cards with a PCI-to-PCI bridge can be
929 * inserted later.
930 */
931 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
932 struct pci_bus *parent = bus;
933 if (pci_find_bus(pci_domain_nr(bus),
934 max+i+1))
935 break;
936 while (parent->parent) {
937 if ((!pcibios_assign_all_busses()) &&
938 (parent->busn_res.end > max) &&
939 (parent->busn_res.end <= max+i)) {
940 j = 1;
941 }
942 parent = parent->parent;
943 }
944 if (j) {
945 /*
946 * Often, there are two cardbus bridges
947 * -- try to leave one valid bus number
948 * for each one.
949 */
950 i /= 2;
951 break;
952 }
953 }
954 max += i;
955 }
956 /*
957 * Set the subordinate bus number to its real value.
958 */
959 pci_bus_update_busn_res_end(child, max);
960 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
961 }
962
963 sprintf(child->name,
964 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
965 pci_domain_nr(bus), child->number);
966
967 /* Has only triggered on CardBus, fixup is in yenta_socket */
968 while (bus->parent) {
969 if ((child->busn_res.end > bus->busn_res.end) ||
970 (child->number > bus->busn_res.end) ||
971 (child->number < bus->number) ||
972 (child->busn_res.end < bus->number)) {
973 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
974 &child->busn_res,
975 (bus->number > child->busn_res.end &&
976 bus->busn_res.end < child->number) ?
977 "wholly" : "partially",
978 bus->self->transparent ? " transparent" : "",
979 dev_name(&bus->dev),
980 &bus->busn_res);
981 }
982 bus = bus->parent;
983 }
984
985 out:
986 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
987
988 return max;
989 }
990 EXPORT_SYMBOL(pci_scan_bridge);
991
992 /*
993 * Read interrupt line and base address registers.
994 * The architecture-dependent code can tweak these, of course.
995 */
996 static void pci_read_irq(struct pci_dev *dev)
997 {
998 unsigned char irq;
999
1000 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1001 dev->pin = irq;
1002 if (irq)
1003 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1004 dev->irq = irq;
1005 }
1006
1007 void set_pcie_port_type(struct pci_dev *pdev)
1008 {
1009 int pos;
1010 u16 reg16;
1011 int type;
1012 struct pci_dev *parent;
1013
1014 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1015 if (!pos)
1016 return;
1017 pdev->pcie_cap = pos;
1018 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1019 pdev->pcie_flags_reg = reg16;
1020 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1021 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1022
1023 /*
1024 * A Root Port is always the upstream end of a Link. No PCIe
1025 * component has two Links. Two Links are connected by a Switch
1026 * that has a Port on each Link and internal logic to connect the
1027 * two Ports.
1028 */
1029 type = pci_pcie_type(pdev);
1030 if (type == PCI_EXP_TYPE_ROOT_PORT)
1031 pdev->has_secondary_link = 1;
1032 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1033 type == PCI_EXP_TYPE_DOWNSTREAM) {
1034 parent = pci_upstream_bridge(pdev);
1035
1036 /*
1037 * Usually there's an upstream device (Root Port or Switch
1038 * Downstream Port), but we can't assume one exists.
1039 */
1040 if (parent && !parent->has_secondary_link)
1041 pdev->has_secondary_link = 1;
1042 }
1043 }
1044
1045 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1046 {
1047 u32 reg32;
1048
1049 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1050 if (reg32 & PCI_EXP_SLTCAP_HPC)
1051 pdev->is_hotplug_bridge = 1;
1052 }
1053
1054 /**
1055 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1056 * @dev: PCI device
1057 *
1058 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1059 * when forwarding a type1 configuration request the bridge must check that
1060 * the extended register address field is zero. The bridge is not permitted
1061 * to forward the transactions and must handle it as an Unsupported Request.
1062 * Some bridges do not follow this rule and simply drop the extended register
1063 * bits, resulting in the standard config space being aliased, every 256
1064 * bytes across the entire configuration space. Test for this condition by
1065 * comparing the first dword of each potential alias to the vendor/device ID.
1066 * Known offenders:
1067 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1068 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1069 */
1070 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1071 {
1072 #ifdef CONFIG_PCI_QUIRKS
1073 int pos;
1074 u32 header, tmp;
1075
1076 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1077
1078 for (pos = PCI_CFG_SPACE_SIZE;
1079 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1080 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1081 || header != tmp)
1082 return false;
1083 }
1084
1085 return true;
1086 #else
1087 return false;
1088 #endif
1089 }
1090
1091 /**
1092 * pci_cfg_space_size - get the configuration space size of the PCI device.
1093 * @dev: PCI device
1094 *
1095 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1096 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1097 * access it. Maybe we don't have a way to generate extended config space
1098 * accesses, or the device is behind a reverse Express bridge. So we try
1099 * reading the dword at 0x100 which must either be 0 or a valid extended
1100 * capability header.
1101 */
1102 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1103 {
1104 u32 status;
1105 int pos = PCI_CFG_SPACE_SIZE;
1106
1107 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1108 goto fail;
1109 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1110 goto fail;
1111
1112 return PCI_CFG_SPACE_EXP_SIZE;
1113
1114 fail:
1115 return PCI_CFG_SPACE_SIZE;
1116 }
1117
1118 int pci_cfg_space_size(struct pci_dev *dev)
1119 {
1120 int pos;
1121 u32 status;
1122 u16 class;
1123
1124 class = dev->class >> 8;
1125 if (class == PCI_CLASS_BRIDGE_HOST)
1126 return pci_cfg_space_size_ext(dev);
1127
1128 if (!pci_is_pcie(dev)) {
1129 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1130 if (!pos)
1131 goto fail;
1132
1133 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1134 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1135 goto fail;
1136 }
1137
1138 return pci_cfg_space_size_ext(dev);
1139
1140 fail:
1141 return PCI_CFG_SPACE_SIZE;
1142 }
1143
1144 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1145
1146 void pci_msi_setup_pci_dev(struct pci_dev *dev)
1147 {
1148 /*
1149 * Disable the MSI hardware to avoid screaming interrupts
1150 * during boot. This is the power on reset default so
1151 * usually this should be a noop.
1152 */
1153 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1154 if (dev->msi_cap)
1155 pci_msi_set_enable(dev, 0);
1156
1157 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1158 if (dev->msix_cap)
1159 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1160 }
1161
1162 /**
1163 * pci_setup_device - fill in class and map information of a device
1164 * @dev: the device structure to fill
1165 *
1166 * Initialize the device structure with information about the device's
1167 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1168 * Called at initialisation of the PCI subsystem and by CardBus services.
1169 * Returns 0 on success and negative if unknown type of device (not normal,
1170 * bridge or CardBus).
1171 */
1172 int pci_setup_device(struct pci_dev *dev)
1173 {
1174 u32 class;
1175 u8 hdr_type;
1176 int pos = 0;
1177 struct pci_bus_region region;
1178 struct resource *res;
1179
1180 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1181 return -EIO;
1182
1183 dev->sysdata = dev->bus->sysdata;
1184 dev->dev.parent = dev->bus->bridge;
1185 dev->dev.bus = &pci_bus_type;
1186 dev->hdr_type = hdr_type & 0x7f;
1187 dev->multifunction = !!(hdr_type & 0x80);
1188 dev->error_state = pci_channel_io_normal;
1189 set_pcie_port_type(dev);
1190
1191 pci_dev_assign_slot(dev);
1192 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1193 set this higher, assuming the system even supports it. */
1194 dev->dma_mask = 0xffffffff;
1195
1196 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1197 dev->bus->number, PCI_SLOT(dev->devfn),
1198 PCI_FUNC(dev->devfn));
1199
1200 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1201 dev->revision = class & 0xff;
1202 dev->class = class >> 8; /* upper 3 bytes */
1203
1204 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1205 dev->vendor, dev->device, dev->hdr_type, dev->class);
1206
1207 /* need to have dev->class ready */
1208 dev->cfg_size = pci_cfg_space_size(dev);
1209
1210 /* "Unknown power state" */
1211 dev->current_state = PCI_UNKNOWN;
1212
1213 pci_msi_setup_pci_dev(dev);
1214
1215 /* Early fixups, before probing the BARs */
1216 pci_fixup_device(pci_fixup_early, dev);
1217 /* device class may be changed after fixup */
1218 class = dev->class >> 8;
1219
1220 switch (dev->hdr_type) { /* header type */
1221 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1222 if (class == PCI_CLASS_BRIDGE_PCI)
1223 goto bad;
1224 pci_read_irq(dev);
1225 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1226 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1227 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1228
1229 /*
1230 * Do the ugly legacy mode stuff here rather than broken chip
1231 * quirk code. Legacy mode ATA controllers have fixed
1232 * addresses. These are not always echoed in BAR0-3, and
1233 * BAR0-3 in a few cases contain junk!
1234 */
1235 if (class == PCI_CLASS_STORAGE_IDE) {
1236 u8 progif;
1237 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1238 if ((progif & 1) == 0) {
1239 region.start = 0x1F0;
1240 region.end = 0x1F7;
1241 res = &dev->resource[0];
1242 res->flags = LEGACY_IO_RESOURCE;
1243 pcibios_bus_to_resource(dev->bus, res, &region);
1244 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1245 res);
1246 region.start = 0x3F6;
1247 region.end = 0x3F6;
1248 res = &dev->resource[1];
1249 res->flags = LEGACY_IO_RESOURCE;
1250 pcibios_bus_to_resource(dev->bus, res, &region);
1251 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1252 res);
1253 }
1254 if ((progif & 4) == 0) {
1255 region.start = 0x170;
1256 region.end = 0x177;
1257 res = &dev->resource[2];
1258 res->flags = LEGACY_IO_RESOURCE;
1259 pcibios_bus_to_resource(dev->bus, res, &region);
1260 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1261 res);
1262 region.start = 0x376;
1263 region.end = 0x376;
1264 res = &dev->resource[3];
1265 res->flags = LEGACY_IO_RESOURCE;
1266 pcibios_bus_to_resource(dev->bus, res, &region);
1267 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1268 res);
1269 }
1270 }
1271 break;
1272
1273 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1274 if (class != PCI_CLASS_BRIDGE_PCI)
1275 goto bad;
1276 /* The PCI-to-PCI bridge spec requires that subtractive
1277 decoding (i.e. transparent) bridge must have programming
1278 interface code of 0x01. */
1279 pci_read_irq(dev);
1280 dev->transparent = ((dev->class & 0xff) == 1);
1281 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1282 set_pcie_hotplug_bridge(dev);
1283 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1284 if (pos) {
1285 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1286 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1287 }
1288 break;
1289
1290 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1291 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1292 goto bad;
1293 pci_read_irq(dev);
1294 pci_read_bases(dev, 1, 0);
1295 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1296 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1297 break;
1298
1299 default: /* unknown header */
1300 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1301 dev->hdr_type);
1302 return -EIO;
1303
1304 bad:
1305 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1306 dev->class, dev->hdr_type);
1307 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1308 }
1309
1310 /* We found a fine healthy device, go go go... */
1311 return 0;
1312 }
1313
1314 static void pci_configure_mps(struct pci_dev *dev)
1315 {
1316 struct pci_dev *bridge = pci_upstream_bridge(dev);
1317 int mps, p_mps, rc;
1318
1319 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1320 return;
1321
1322 mps = pcie_get_mps(dev);
1323 p_mps = pcie_get_mps(bridge);
1324
1325 if (mps == p_mps)
1326 return;
1327
1328 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1329 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1330 mps, pci_name(bridge), p_mps);
1331 return;
1332 }
1333
1334 /*
1335 * Fancier MPS configuration is done later by
1336 * pcie_bus_configure_settings()
1337 */
1338 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1339 return;
1340
1341 rc = pcie_set_mps(dev, p_mps);
1342 if (rc) {
1343 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1344 p_mps);
1345 return;
1346 }
1347
1348 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1349 p_mps, mps, 128 << dev->pcie_mpss);
1350 }
1351
1352 static struct hpp_type0 pci_default_type0 = {
1353 .revision = 1,
1354 .cache_line_size = 8,
1355 .latency_timer = 0x40,
1356 .enable_serr = 0,
1357 .enable_perr = 0,
1358 };
1359
1360 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1361 {
1362 u16 pci_cmd, pci_bctl;
1363
1364 if (!hpp)
1365 hpp = &pci_default_type0;
1366
1367 if (hpp->revision > 1) {
1368 dev_warn(&dev->dev,
1369 "PCI settings rev %d not supported; using defaults\n",
1370 hpp->revision);
1371 hpp = &pci_default_type0;
1372 }
1373
1374 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1375 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1376 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1377 if (hpp->enable_serr)
1378 pci_cmd |= PCI_COMMAND_SERR;
1379 if (hpp->enable_perr)
1380 pci_cmd |= PCI_COMMAND_PARITY;
1381 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1382
1383 /* Program bridge control value */
1384 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1385 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1386 hpp->latency_timer);
1387 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1388 if (hpp->enable_serr)
1389 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1390 if (hpp->enable_perr)
1391 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1392 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1393 }
1394 }
1395
1396 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1397 {
1398 if (hpp)
1399 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1400 }
1401
1402 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1403 {
1404 int pos;
1405 u32 reg32;
1406
1407 if (!hpp)
1408 return;
1409
1410 if (hpp->revision > 1) {
1411 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1412 hpp->revision);
1413 return;
1414 }
1415
1416 /*
1417 * Don't allow _HPX to change MPS or MRRS settings. We manage
1418 * those to make sure they're consistent with the rest of the
1419 * platform.
1420 */
1421 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1422 PCI_EXP_DEVCTL_READRQ;
1423 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1424 PCI_EXP_DEVCTL_READRQ);
1425
1426 /* Initialize Device Control Register */
1427 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1428 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1429
1430 /* Initialize Link Control Register */
1431 if (pcie_cap_has_lnkctl(dev))
1432 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1433 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1434
1435 /* Find Advanced Error Reporting Enhanced Capability */
1436 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1437 if (!pos)
1438 return;
1439
1440 /* Initialize Uncorrectable Error Mask Register */
1441 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1442 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1443 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1444
1445 /* Initialize Uncorrectable Error Severity Register */
1446 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1447 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1448 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1449
1450 /* Initialize Correctable Error Mask Register */
1451 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1452 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1453 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1454
1455 /* Initialize Advanced Error Capabilities and Control Register */
1456 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1457 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1458 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1459
1460 /*
1461 * FIXME: The following two registers are not supported yet.
1462 *
1463 * o Secondary Uncorrectable Error Severity Register
1464 * o Secondary Uncorrectable Error Mask Register
1465 */
1466 }
1467
1468 static void pci_configure_device(struct pci_dev *dev)
1469 {
1470 struct hotplug_params hpp;
1471 int ret;
1472
1473 pci_configure_mps(dev);
1474
1475 memset(&hpp, 0, sizeof(hpp));
1476 ret = pci_get_hp_params(dev, &hpp);
1477 if (ret)
1478 return;
1479
1480 program_hpp_type2(dev, hpp.t2);
1481 program_hpp_type1(dev, hpp.t1);
1482 program_hpp_type0(dev, hpp.t0);
1483 }
1484
1485 static void pci_release_capabilities(struct pci_dev *dev)
1486 {
1487 pci_vpd_release(dev);
1488 pci_iov_release(dev);
1489 pci_free_cap_save_buffers(dev);
1490 }
1491
1492 /**
1493 * pci_release_dev - free a pci device structure when all users of it are finished.
1494 * @dev: device that's been disconnected
1495 *
1496 * Will be called only by the device core when all users of this pci device are
1497 * done.
1498 */
1499 static void pci_release_dev(struct device *dev)
1500 {
1501 struct pci_dev *pci_dev;
1502
1503 pci_dev = to_pci_dev(dev);
1504 pci_release_capabilities(pci_dev);
1505 pci_release_of_node(pci_dev);
1506 pcibios_release_device(pci_dev);
1507 pci_bus_put(pci_dev->bus);
1508 kfree(pci_dev->driver_override);
1509 kfree(pci_dev);
1510 }
1511
1512 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1513 {
1514 struct pci_dev *dev;
1515
1516 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1517 if (!dev)
1518 return NULL;
1519
1520 INIT_LIST_HEAD(&dev->bus_list);
1521 dev->dev.type = &pci_dev_type;
1522 dev->bus = pci_bus_get(bus);
1523
1524 return dev;
1525 }
1526 EXPORT_SYMBOL(pci_alloc_dev);
1527
1528 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1529 int crs_timeout)
1530 {
1531 int delay = 1;
1532
1533 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1534 return false;
1535
1536 /* some broken boards return 0 or ~0 if a slot is empty: */
1537 if (*l == 0xffffffff || *l == 0x00000000 ||
1538 *l == 0x0000ffff || *l == 0xffff0000)
1539 return false;
1540
1541 /*
1542 * Configuration Request Retry Status. Some root ports return the
1543 * actual device ID instead of the synthetic ID (0xFFFF) required
1544 * by the PCIe spec. Ignore the device ID and only check for
1545 * (vendor id == 1).
1546 */
1547 while ((*l & 0xffff) == 0x0001) {
1548 if (!crs_timeout)
1549 return false;
1550
1551 msleep(delay);
1552 delay *= 2;
1553 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1554 return false;
1555 /* Card hasn't responded in 60 seconds? Must be stuck. */
1556 if (delay > crs_timeout) {
1557 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1558 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1559 PCI_FUNC(devfn));
1560 return false;
1561 }
1562 }
1563
1564 return true;
1565 }
1566 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1567
1568 /*
1569 * Read the config data for a PCI device, sanity-check it
1570 * and fill in the dev structure...
1571 */
1572 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1573 {
1574 struct pci_dev *dev;
1575 u32 l;
1576
1577 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1578 return NULL;
1579
1580 dev = pci_alloc_dev(bus);
1581 if (!dev)
1582 return NULL;
1583
1584 dev->devfn = devfn;
1585 dev->vendor = l & 0xffff;
1586 dev->device = (l >> 16) & 0xffff;
1587
1588 pci_set_of_node(dev);
1589
1590 if (pci_setup_device(dev)) {
1591 pci_bus_put(dev->bus);
1592 kfree(dev);
1593 return NULL;
1594 }
1595
1596 return dev;
1597 }
1598
1599 static void pci_init_capabilities(struct pci_dev *dev)
1600 {
1601 /* Enhanced Allocation */
1602 pci_ea_init(dev);
1603
1604 /* MSI/MSI-X list */
1605 pci_msi_init_pci_dev(dev);
1606
1607 /* Buffers for saving PCIe and PCI-X capabilities */
1608 pci_allocate_cap_save_buffers(dev);
1609
1610 /* Power Management */
1611 pci_pm_init(dev);
1612
1613 /* Vital Product Data */
1614 pci_vpd_pci22_init(dev);
1615
1616 /* Alternative Routing-ID Forwarding */
1617 pci_configure_ari(dev);
1618
1619 /* Single Root I/O Virtualization */
1620 pci_iov_init(dev);
1621
1622 /* Address Translation Services */
1623 pci_ats_init(dev);
1624
1625 /* Enable ACS P2P upstream forwarding */
1626 pci_enable_acs(dev);
1627
1628 pci_cleanup_aer_error_status_regs(dev);
1629 }
1630
1631 /*
1632 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1633 * devices. Firmware interfaces that can select the MSI domain on a
1634 * per-device basis should be called from here.
1635 */
1636 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1637 {
1638 struct irq_domain *d;
1639
1640 /*
1641 * If a domain has been set through the pcibios_add_device
1642 * callback, then this is the one (platform code knows best).
1643 */
1644 d = dev_get_msi_domain(&dev->dev);
1645 if (d)
1646 return d;
1647
1648 /*
1649 * Let's see if we have a firmware interface able to provide
1650 * the domain.
1651 */
1652 d = pci_msi_get_device_domain(dev);
1653 if (d)
1654 return d;
1655
1656 return NULL;
1657 }
1658
1659 static void pci_set_msi_domain(struct pci_dev *dev)
1660 {
1661 struct irq_domain *d;
1662
1663 /*
1664 * If the platform or firmware interfaces cannot supply a
1665 * device-specific MSI domain, then inherit the default domain
1666 * from the host bridge itself.
1667 */
1668 d = pci_dev_msi_domain(dev);
1669 if (!d)
1670 d = dev_get_msi_domain(&dev->bus->dev);
1671
1672 dev_set_msi_domain(&dev->dev, d);
1673 }
1674
1675 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1676 {
1677 int ret;
1678
1679 pci_configure_device(dev);
1680
1681 device_initialize(&dev->dev);
1682 dev->dev.release = pci_release_dev;
1683
1684 set_dev_node(&dev->dev, pcibus_to_node(bus));
1685 dev->dev.dma_mask = &dev->dma_mask;
1686 dev->dev.dma_parms = &dev->dma_parms;
1687 dev->dev.coherent_dma_mask = 0xffffffffull;
1688 of_pci_dma_configure(dev);
1689
1690 pci_set_dma_max_seg_size(dev, 65536);
1691 pci_set_dma_seg_boundary(dev, 0xffffffff);
1692
1693 /* Fix up broken headers */
1694 pci_fixup_device(pci_fixup_header, dev);
1695
1696 /* moved out from quirk header fixup code */
1697 pci_reassigndev_resource_alignment(dev);
1698
1699 /* Clear the state_saved flag. */
1700 dev->state_saved = false;
1701
1702 /* Initialize various capabilities */
1703 pci_init_capabilities(dev);
1704
1705 /*
1706 * Add the device to our list of discovered devices
1707 * and the bus list for fixup functions, etc.
1708 */
1709 down_write(&pci_bus_sem);
1710 list_add_tail(&dev->bus_list, &bus->devices);
1711 up_write(&pci_bus_sem);
1712
1713 ret = pcibios_add_device(dev);
1714 WARN_ON(ret < 0);
1715
1716 /* Setup MSI irq domain */
1717 pci_set_msi_domain(dev);
1718
1719 /* Notifier could use PCI capabilities */
1720 dev->match_driver = false;
1721 ret = device_add(&dev->dev);
1722 WARN_ON(ret < 0);
1723 }
1724
1725 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1726 {
1727 struct pci_dev *dev;
1728
1729 dev = pci_get_slot(bus, devfn);
1730 if (dev) {
1731 pci_dev_put(dev);
1732 return dev;
1733 }
1734
1735 dev = pci_scan_device(bus, devfn);
1736 if (!dev)
1737 return NULL;
1738
1739 pci_device_add(dev, bus);
1740
1741 return dev;
1742 }
1743 EXPORT_SYMBOL(pci_scan_single_device);
1744
1745 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1746 {
1747 int pos;
1748 u16 cap = 0;
1749 unsigned next_fn;
1750
1751 if (pci_ari_enabled(bus)) {
1752 if (!dev)
1753 return 0;
1754 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1755 if (!pos)
1756 return 0;
1757
1758 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1759 next_fn = PCI_ARI_CAP_NFN(cap);
1760 if (next_fn <= fn)
1761 return 0; /* protect against malformed list */
1762
1763 return next_fn;
1764 }
1765
1766 /* dev may be NULL for non-contiguous multifunction devices */
1767 if (!dev || dev->multifunction)
1768 return (fn + 1) % 8;
1769
1770 return 0;
1771 }
1772
1773 static int only_one_child(struct pci_bus *bus)
1774 {
1775 struct pci_dev *parent = bus->self;
1776
1777 if (!parent || !pci_is_pcie(parent))
1778 return 0;
1779 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1780 return 1;
1781 if (parent->has_secondary_link &&
1782 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1783 return 1;
1784 return 0;
1785 }
1786
1787 /**
1788 * pci_scan_slot - scan a PCI slot on a bus for devices.
1789 * @bus: PCI bus to scan
1790 * @devfn: slot number to scan (must have zero function.)
1791 *
1792 * Scan a PCI slot on the specified PCI bus for devices, adding
1793 * discovered devices to the @bus->devices list. New devices
1794 * will not have is_added set.
1795 *
1796 * Returns the number of new devices found.
1797 */
1798 int pci_scan_slot(struct pci_bus *bus, int devfn)
1799 {
1800 unsigned fn, nr = 0;
1801 struct pci_dev *dev;
1802
1803 if (only_one_child(bus) && (devfn > 0))
1804 return 0; /* Already scanned the entire slot */
1805
1806 dev = pci_scan_single_device(bus, devfn);
1807 if (!dev)
1808 return 0;
1809 if (!dev->is_added)
1810 nr++;
1811
1812 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1813 dev = pci_scan_single_device(bus, devfn + fn);
1814 if (dev) {
1815 if (!dev->is_added)
1816 nr++;
1817 dev->multifunction = 1;
1818 }
1819 }
1820
1821 /* only one slot has pcie device */
1822 if (bus->self && nr)
1823 pcie_aspm_init_link_state(bus->self);
1824
1825 return nr;
1826 }
1827 EXPORT_SYMBOL(pci_scan_slot);
1828
1829 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1830 {
1831 u8 *smpss = data;
1832
1833 if (!pci_is_pcie(dev))
1834 return 0;
1835
1836 /*
1837 * We don't have a way to change MPS settings on devices that have
1838 * drivers attached. A hot-added device might support only the minimum
1839 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1840 * where devices may be hot-added, we limit the fabric MPS to 128 so
1841 * hot-added devices will work correctly.
1842 *
1843 * However, if we hot-add a device to a slot directly below a Root
1844 * Port, it's impossible for there to be other existing devices below
1845 * the port. We don't limit the MPS in this case because we can
1846 * reconfigure MPS on both the Root Port and the hot-added device,
1847 * and there are no other devices involved.
1848 *
1849 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1850 */
1851 if (dev->is_hotplug_bridge &&
1852 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1853 *smpss = 0;
1854
1855 if (*smpss > dev->pcie_mpss)
1856 *smpss = dev->pcie_mpss;
1857
1858 return 0;
1859 }
1860
1861 static void pcie_write_mps(struct pci_dev *dev, int mps)
1862 {
1863 int rc;
1864
1865 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1866 mps = 128 << dev->pcie_mpss;
1867
1868 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1869 dev->bus->self)
1870 /* For "Performance", the assumption is made that
1871 * downstream communication will never be larger than
1872 * the MRRS. So, the MPS only needs to be configured
1873 * for the upstream communication. This being the case,
1874 * walk from the top down and set the MPS of the child
1875 * to that of the parent bus.
1876 *
1877 * Configure the device MPS with the smaller of the
1878 * device MPSS or the bridge MPS (which is assumed to be
1879 * properly configured at this point to the largest
1880 * allowable MPS based on its parent bus).
1881 */
1882 mps = min(mps, pcie_get_mps(dev->bus->self));
1883 }
1884
1885 rc = pcie_set_mps(dev, mps);
1886 if (rc)
1887 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1888 }
1889
1890 static void pcie_write_mrrs(struct pci_dev *dev)
1891 {
1892 int rc, mrrs;
1893
1894 /* In the "safe" case, do not configure the MRRS. There appear to be
1895 * issues with setting MRRS to 0 on a number of devices.
1896 */
1897 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1898 return;
1899
1900 /* For Max performance, the MRRS must be set to the largest supported
1901 * value. However, it cannot be configured larger than the MPS the
1902 * device or the bus can support. This should already be properly
1903 * configured by a prior call to pcie_write_mps.
1904 */
1905 mrrs = pcie_get_mps(dev);
1906
1907 /* MRRS is a R/W register. Invalid values can be written, but a
1908 * subsequent read will verify if the value is acceptable or not.
1909 * If the MRRS value provided is not acceptable (e.g., too large),
1910 * shrink the value until it is acceptable to the HW.
1911 */
1912 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1913 rc = pcie_set_readrq(dev, mrrs);
1914 if (!rc)
1915 break;
1916
1917 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1918 mrrs /= 2;
1919 }
1920
1921 if (mrrs < 128)
1922 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1923 }
1924
1925 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1926 {
1927 int mps, orig_mps;
1928
1929 if (!pci_is_pcie(dev))
1930 return 0;
1931
1932 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1933 pcie_bus_config == PCIE_BUS_DEFAULT)
1934 return 0;
1935
1936 mps = 128 << *(u8 *)data;
1937 orig_mps = pcie_get_mps(dev);
1938
1939 pcie_write_mps(dev, mps);
1940 pcie_write_mrrs(dev);
1941
1942 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1943 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1944 orig_mps, pcie_get_readrq(dev));
1945
1946 return 0;
1947 }
1948
1949 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1950 * parents then children fashion. If this changes, then this code will not
1951 * work as designed.
1952 */
1953 void pcie_bus_configure_settings(struct pci_bus *bus)
1954 {
1955 u8 smpss = 0;
1956
1957 if (!bus->self)
1958 return;
1959
1960 if (!pci_is_pcie(bus->self))
1961 return;
1962
1963 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1964 * to be aware of the MPS of the destination. To work around this,
1965 * simply force the MPS of the entire system to the smallest possible.
1966 */
1967 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1968 smpss = 0;
1969
1970 if (pcie_bus_config == PCIE_BUS_SAFE) {
1971 smpss = bus->self->pcie_mpss;
1972
1973 pcie_find_smpss(bus->self, &smpss);
1974 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1975 }
1976
1977 pcie_bus_configure_set(bus->self, &smpss);
1978 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1979 }
1980 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1981
1982 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1983 {
1984 unsigned int devfn, pass, max = bus->busn_res.start;
1985 struct pci_dev *dev;
1986
1987 dev_dbg(&bus->dev, "scanning bus\n");
1988
1989 /* Go find them, Rover! */
1990 for (devfn = 0; devfn < 0x100; devfn += 8)
1991 pci_scan_slot(bus, devfn);
1992
1993 /* Reserve buses for SR-IOV capability. */
1994 max += pci_iov_bus_range(bus);
1995
1996 /*
1997 * After performing arch-dependent fixup of the bus, look behind
1998 * all PCI-to-PCI bridges on this bus.
1999 */
2000 if (!bus->is_added) {
2001 dev_dbg(&bus->dev, "fixups for bus\n");
2002 pcibios_fixup_bus(bus);
2003 bus->is_added = 1;
2004 }
2005
2006 for (pass = 0; pass < 2; pass++)
2007 list_for_each_entry(dev, &bus->devices, bus_list) {
2008 if (pci_is_bridge(dev))
2009 max = pci_scan_bridge(bus, dev, max, pass);
2010 }
2011
2012 /*
2013 * We've scanned the bus and so we know all about what's on
2014 * the other side of any bridges that may be on this bus plus
2015 * any devices.
2016 *
2017 * Return how far we've got finding sub-buses.
2018 */
2019 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2020 return max;
2021 }
2022 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2023
2024 /**
2025 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2026 * @bridge: Host bridge to set up.
2027 *
2028 * Default empty implementation. Replace with an architecture-specific setup
2029 * routine, if necessary.
2030 */
2031 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2032 {
2033 return 0;
2034 }
2035
2036 void __weak pcibios_add_bus(struct pci_bus *bus)
2037 {
2038 }
2039
2040 void __weak pcibios_remove_bus(struct pci_bus *bus)
2041 {
2042 }
2043
2044 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2045 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2046 {
2047 int error;
2048 struct pci_host_bridge *bridge;
2049 struct pci_bus *b, *b2;
2050 struct resource_entry *window, *n;
2051 struct resource *res;
2052 resource_size_t offset;
2053 char bus_addr[64];
2054 char *fmt;
2055
2056 b = pci_alloc_bus(NULL);
2057 if (!b)
2058 return NULL;
2059
2060 b->sysdata = sysdata;
2061 b->ops = ops;
2062 b->number = b->busn_res.start = bus;
2063 pci_bus_assign_domain_nr(b, parent);
2064 b2 = pci_find_bus(pci_domain_nr(b), bus);
2065 if (b2) {
2066 /* If we already got to this bus through a different bridge, ignore it */
2067 dev_dbg(&b2->dev, "bus already known\n");
2068 goto err_out;
2069 }
2070
2071 bridge = pci_alloc_host_bridge(b);
2072 if (!bridge)
2073 goto err_out;
2074
2075 bridge->dev.parent = parent;
2076 bridge->dev.release = pci_release_host_bridge_dev;
2077 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2078 error = pcibios_root_bridge_prepare(bridge);
2079 if (error) {
2080 kfree(bridge);
2081 goto err_out;
2082 }
2083
2084 error = device_register(&bridge->dev);
2085 if (error) {
2086 put_device(&bridge->dev);
2087 goto err_out;
2088 }
2089 b->bridge = get_device(&bridge->dev);
2090 device_enable_async_suspend(b->bridge);
2091 pci_set_bus_of_node(b);
2092 pci_set_bus_msi_domain(b);
2093
2094 if (!parent)
2095 set_dev_node(b->bridge, pcibus_to_node(b));
2096
2097 b->dev.class = &pcibus_class;
2098 b->dev.parent = b->bridge;
2099 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2100 error = device_register(&b->dev);
2101 if (error)
2102 goto class_dev_reg_err;
2103
2104 pcibios_add_bus(b);
2105
2106 /* Create legacy_io and legacy_mem files for this bus */
2107 pci_create_legacy_files(b);
2108
2109 if (parent)
2110 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2111 else
2112 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2113
2114 /* Add initial resources to the bus */
2115 resource_list_for_each_entry_safe(window, n, resources) {
2116 list_move_tail(&window->node, &bridge->windows);
2117 res = window->res;
2118 offset = window->offset;
2119 if (res->flags & IORESOURCE_BUS)
2120 pci_bus_insert_busn_res(b, bus, res->end);
2121 else
2122 pci_bus_add_resource(b, res, 0);
2123 if (offset) {
2124 if (resource_type(res) == IORESOURCE_IO)
2125 fmt = " (bus address [%#06llx-%#06llx])";
2126 else
2127 fmt = " (bus address [%#010llx-%#010llx])";
2128 snprintf(bus_addr, sizeof(bus_addr), fmt,
2129 (unsigned long long) (res->start - offset),
2130 (unsigned long long) (res->end - offset));
2131 } else
2132 bus_addr[0] = '\0';
2133 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2134 }
2135
2136 down_write(&pci_bus_sem);
2137 list_add_tail(&b->node, &pci_root_buses);
2138 up_write(&pci_bus_sem);
2139
2140 return b;
2141
2142 class_dev_reg_err:
2143 put_device(&bridge->dev);
2144 device_unregister(&bridge->dev);
2145 err_out:
2146 kfree(b);
2147 return NULL;
2148 }
2149 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2150
2151 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2152 {
2153 struct resource *res = &b->busn_res;
2154 struct resource *parent_res, *conflict;
2155
2156 res->start = bus;
2157 res->end = bus_max;
2158 res->flags = IORESOURCE_BUS;
2159
2160 if (!pci_is_root_bus(b))
2161 parent_res = &b->parent->busn_res;
2162 else {
2163 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2164 res->flags |= IORESOURCE_PCI_FIXED;
2165 }
2166
2167 conflict = request_resource_conflict(parent_res, res);
2168
2169 if (conflict)
2170 dev_printk(KERN_DEBUG, &b->dev,
2171 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2172 res, pci_is_root_bus(b) ? "domain " : "",
2173 parent_res, conflict->name, conflict);
2174
2175 return conflict == NULL;
2176 }
2177
2178 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2179 {
2180 struct resource *res = &b->busn_res;
2181 struct resource old_res = *res;
2182 resource_size_t size;
2183 int ret;
2184
2185 if (res->start > bus_max)
2186 return -EINVAL;
2187
2188 size = bus_max - res->start + 1;
2189 ret = adjust_resource(res, res->start, size);
2190 dev_printk(KERN_DEBUG, &b->dev,
2191 "busn_res: %pR end %s updated to %02x\n",
2192 &old_res, ret ? "can not be" : "is", bus_max);
2193
2194 if (!ret && !res->parent)
2195 pci_bus_insert_busn_res(b, res->start, res->end);
2196
2197 return ret;
2198 }
2199
2200 void pci_bus_release_busn_res(struct pci_bus *b)
2201 {
2202 struct resource *res = &b->busn_res;
2203 int ret;
2204
2205 if (!res->flags || !res->parent)
2206 return;
2207
2208 ret = release_resource(res);
2209 dev_printk(KERN_DEBUG, &b->dev,
2210 "busn_res: %pR %s released\n",
2211 res, ret ? "can not be" : "is");
2212 }
2213
2214 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2215 struct pci_ops *ops, void *sysdata,
2216 struct list_head *resources, struct msi_controller *msi)
2217 {
2218 struct resource_entry *window;
2219 bool found = false;
2220 struct pci_bus *b;
2221 int max;
2222
2223 resource_list_for_each_entry(window, resources)
2224 if (window->res->flags & IORESOURCE_BUS) {
2225 found = true;
2226 break;
2227 }
2228
2229 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2230 if (!b)
2231 return NULL;
2232
2233 b->msi = msi;
2234
2235 if (!found) {
2236 dev_info(&b->dev,
2237 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2238 bus);
2239 pci_bus_insert_busn_res(b, bus, 255);
2240 }
2241
2242 max = pci_scan_child_bus(b);
2243
2244 if (!found)
2245 pci_bus_update_busn_res_end(b, max);
2246
2247 return b;
2248 }
2249
2250 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2251 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2252 {
2253 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2254 NULL);
2255 }
2256 EXPORT_SYMBOL(pci_scan_root_bus);
2257
2258 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2259 void *sysdata)
2260 {
2261 LIST_HEAD(resources);
2262 struct pci_bus *b;
2263
2264 pci_add_resource(&resources, &ioport_resource);
2265 pci_add_resource(&resources, &iomem_resource);
2266 pci_add_resource(&resources, &busn_resource);
2267 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2268 if (b) {
2269 pci_scan_child_bus(b);
2270 } else {
2271 pci_free_resource_list(&resources);
2272 }
2273 return b;
2274 }
2275 EXPORT_SYMBOL(pci_scan_bus);
2276
2277 /**
2278 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2279 * @bridge: PCI bridge for the bus to scan
2280 *
2281 * Scan a PCI bus and child buses for new devices, add them,
2282 * and enable them, resizing bridge mmio/io resource if necessary
2283 * and possible. The caller must ensure the child devices are already
2284 * removed for resizing to occur.
2285 *
2286 * Returns the max number of subordinate bus discovered.
2287 */
2288 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2289 {
2290 unsigned int max;
2291 struct pci_bus *bus = bridge->subordinate;
2292
2293 max = pci_scan_child_bus(bus);
2294
2295 pci_assign_unassigned_bridge_resources(bridge);
2296
2297 pci_bus_add_devices(bus);
2298
2299 return max;
2300 }
2301
2302 /**
2303 * pci_rescan_bus - scan a PCI bus for devices.
2304 * @bus: PCI bus to scan
2305 *
2306 * Scan a PCI bus and child buses for new devices, adds them,
2307 * and enables them.
2308 *
2309 * Returns the max number of subordinate bus discovered.
2310 */
2311 unsigned int pci_rescan_bus(struct pci_bus *bus)
2312 {
2313 unsigned int max;
2314
2315 max = pci_scan_child_bus(bus);
2316 pci_assign_unassigned_bus_resources(bus);
2317 pci_bus_add_devices(bus);
2318
2319 return max;
2320 }
2321 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2322
2323 /*
2324 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2325 * routines should always be executed under this mutex.
2326 */
2327 static DEFINE_MUTEX(pci_rescan_remove_lock);
2328
2329 void pci_lock_rescan_remove(void)
2330 {
2331 mutex_lock(&pci_rescan_remove_lock);
2332 }
2333 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2334
2335 void pci_unlock_rescan_remove(void)
2336 {
2337 mutex_unlock(&pci_rescan_remove_lock);
2338 }
2339 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2340
2341 static int __init pci_sort_bf_cmp(const struct device *d_a,
2342 const struct device *d_b)
2343 {
2344 const struct pci_dev *a = to_pci_dev(d_a);
2345 const struct pci_dev *b = to_pci_dev(d_b);
2346
2347 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2348 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2349
2350 if (a->bus->number < b->bus->number) return -1;
2351 else if (a->bus->number > b->bus->number) return 1;
2352
2353 if (a->devfn < b->devfn) return -1;
2354 else if (a->devfn > b->devfn) return 1;
2355
2356 return 0;
2357 }
2358
2359 void __init pci_sort_breadthfirst(void)
2360 {
2361 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2362 }
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