2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <asm-generic/pci-bridge.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 static struct resource busn_resource
= {
23 .flags
= IORESOURCE_BUS
,
26 /* Ugh. Need to stop exporting this to modules. */
27 LIST_HEAD(pci_root_buses
);
28 EXPORT_SYMBOL(pci_root_buses
);
30 static LIST_HEAD(pci_domain_busn_res_list
);
32 struct pci_domain_busn_res
{
33 struct list_head list
;
38 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
40 struct pci_domain_busn_res
*r
;
42 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
43 if (r
->domain_nr
== domain_nr
)
46 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
50 r
->domain_nr
= domain_nr
;
53 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
55 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
60 static int find_anything(struct device
*dev
, void *data
)
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
68 * is no device to be found on the pci_bus_type.
70 int no_pci_devices(void)
75 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
76 no_devices
= (dev
== NULL
);
80 EXPORT_SYMBOL(no_pci_devices
);
85 static void release_pcibus_dev(struct device
*dev
)
87 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
90 put_device(pci_bus
->bridge
);
91 pci_bus_remove_resources(pci_bus
);
92 pci_release_bus_of_node(pci_bus
);
96 static struct class pcibus_class
= {
98 .dev_release
= &release_pcibus_dev
,
99 .dev_groups
= pcibus_groups
,
102 static int __init
pcibus_class_init(void)
104 return class_register(&pcibus_class
);
106 postcore_initcall(pcibus_class_init
);
108 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
110 u64 size
= mask
& maxbase
; /* Find the significant bits */
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size
= (size
& ~(size
-1)) - 1;
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
126 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
131 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
132 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
133 flags
|= IORESOURCE_IO
;
137 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
138 flags
|= IORESOURCE_MEM
;
139 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
140 flags
|= IORESOURCE_PREFETCH
;
142 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
144 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
147 /* 1M mem BAR treated as 32-bit BAR */
149 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
150 flags
|= IORESOURCE_MEM_64
;
153 /* mem unknown type treated as 32-bit BAR */
159 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
162 * pci_read_base - read a PCI BAR
163 * @dev: the PCI device
164 * @type: type of the BAR
165 * @res: resource buffer to be filled in
166 * @pos: BAR position in the config space
168 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
170 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
171 struct resource
*res
, unsigned int pos
)
175 struct pci_bus_region region
, inverted_region
;
176 bool bar_too_big
= false, bar_disabled
= false;
178 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
180 /* No printks while decoding is disabled! */
181 if (!dev
->mmio_always_on
) {
182 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
183 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
184 pci_write_config_word(dev
, PCI_COMMAND
,
185 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
189 res
->name
= pci_name(dev
);
191 pci_read_config_dword(dev
, pos
, &l
);
192 pci_write_config_dword(dev
, pos
, l
| mask
);
193 pci_read_config_dword(dev
, pos
, &sz
);
194 pci_write_config_dword(dev
, pos
, l
);
197 * All bits set in sz means the device isn't working properly.
198 * If the BAR isn't implemented, all bits must be 0. If it's a
199 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
202 if (!sz
|| sz
== 0xffffffff)
206 * I don't know how l can have all bits set. Copied from old code.
207 * Maybe it fixes a bug on some ancient platform.
212 if (type
== pci_bar_unknown
) {
213 res
->flags
= decode_bar(dev
, l
);
214 res
->flags
|= IORESOURCE_SIZEALIGN
;
215 if (res
->flags
& IORESOURCE_IO
) {
216 l
&= PCI_BASE_ADDRESS_IO_MASK
;
217 mask
= PCI_BASE_ADDRESS_IO_MASK
& (u32
) IO_SPACE_LIMIT
;
219 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
220 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
223 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
224 l
&= PCI_ROM_ADDRESS_MASK
;
225 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
228 if (res
->flags
& IORESOURCE_MEM_64
) {
231 u64 mask64
= mask
| (u64
)~0 << 32;
233 pci_read_config_dword(dev
, pos
+ 4, &l
);
234 pci_write_config_dword(dev
, pos
+ 4, ~0);
235 pci_read_config_dword(dev
, pos
+ 4, &sz
);
236 pci_write_config_dword(dev
, pos
+ 4, l
);
238 l64
|= ((u64
)l
<< 32);
239 sz64
|= ((u64
)sz
<< 32);
241 sz64
= pci_size(l64
, sz64
, mask64
);
246 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
251 if ((sizeof(resource_size_t
) < 8) && l
) {
252 /* Address above 32-bit boundary; disable the BAR */
253 pci_write_config_dword(dev
, pos
, 0);
254 pci_write_config_dword(dev
, pos
+ 4, 0);
255 res
->flags
|= IORESOURCE_UNSET
;
261 region
.end
= l64
+ sz64
;
264 sz
= pci_size(l
, sz
, mask
);
273 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
274 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
277 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
278 * the corresponding resource address (the physical address used by
279 * the CPU. Converting that resource address back to a bus address
280 * should yield the original BAR value:
282 * resource_to_bus(bus_to_resource(A)) == A
284 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
285 * be claimed by the device.
287 if (inverted_region
.start
!= region
.start
) {
288 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %pa invalid; forcing reassignment\n",
290 res
->flags
|= IORESOURCE_UNSET
;
291 res
->end
-= res
->start
;
301 if (!dev
->mmio_always_on
&&
302 (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
303 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
306 dev_err(&dev
->dev
, "reg 0x%x: can't handle 64-bit BAR\n", pos
);
307 if (res
->flags
&& !bar_disabled
)
308 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
310 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
313 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
315 unsigned int pos
, reg
;
317 for (pos
= 0; pos
< howmany
; pos
++) {
318 struct resource
*res
= &dev
->resource
[pos
];
319 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
320 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
324 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
325 dev
->rom_base_reg
= rom
;
326 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
327 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
328 IORESOURCE_SIZEALIGN
;
329 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
333 static void pci_read_bridge_io(struct pci_bus
*child
)
335 struct pci_dev
*dev
= child
->self
;
336 u8 io_base_lo
, io_limit_lo
;
337 unsigned long io_mask
, io_granularity
, base
, limit
;
338 struct pci_bus_region region
;
339 struct resource
*res
;
341 io_mask
= PCI_IO_RANGE_MASK
;
342 io_granularity
= 0x1000;
343 if (dev
->io_window_1k
) {
344 /* Support 1K I/O space granularity */
345 io_mask
= PCI_IO_1K_RANGE_MASK
;
346 io_granularity
= 0x400;
349 res
= child
->resource
[0];
350 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
351 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
352 base
= (io_base_lo
& io_mask
) << 8;
353 limit
= (io_limit_lo
& io_mask
) << 8;
355 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
356 u16 io_base_hi
, io_limit_hi
;
358 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
359 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
360 base
|= ((unsigned long) io_base_hi
<< 16);
361 limit
|= ((unsigned long) io_limit_hi
<< 16);
365 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
367 region
.end
= limit
+ io_granularity
- 1;
368 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
369 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
373 static void pci_read_bridge_mmio(struct pci_bus
*child
)
375 struct pci_dev
*dev
= child
->self
;
376 u16 mem_base_lo
, mem_limit_lo
;
377 unsigned long base
, limit
;
378 struct pci_bus_region region
;
379 struct resource
*res
;
381 res
= child
->resource
[1];
382 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
383 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
384 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
385 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
387 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
389 region
.end
= limit
+ 0xfffff;
390 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
391 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
395 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
397 struct pci_dev
*dev
= child
->self
;
398 u16 mem_base_lo
, mem_limit_lo
;
399 unsigned long base
, limit
;
400 struct pci_bus_region region
;
401 struct resource
*res
;
403 res
= child
->resource
[2];
404 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
405 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
406 base
= ((unsigned long) mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
407 limit
= ((unsigned long) mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
409 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
410 u32 mem_base_hi
, mem_limit_hi
;
412 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
413 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
416 * Some bridges set the base > limit by default, and some
417 * (broken) BIOSes do not initialize them. If we find
418 * this, just assume they are not being used.
420 if (mem_base_hi
<= mem_limit_hi
) {
421 #if BITS_PER_LONG == 64
422 base
|= ((unsigned long) mem_base_hi
) << 32;
423 limit
|= ((unsigned long) mem_limit_hi
) << 32;
425 if (mem_base_hi
|| mem_limit_hi
) {
426 dev_err(&dev
->dev
, "can't handle 64-bit "
427 "address space for bridge\n");
434 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
435 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
436 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
437 res
->flags
|= IORESOURCE_MEM_64
;
439 region
.end
= limit
+ 0xfffff;
440 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
441 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
445 void pci_read_bridge_bases(struct pci_bus
*child
)
447 struct pci_dev
*dev
= child
->self
;
448 struct resource
*res
;
451 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
454 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
456 dev
->transparent
? " (subtractive decode)" : "");
458 pci_bus_remove_resources(child
);
459 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
460 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
462 pci_read_bridge_io(child
);
463 pci_read_bridge_mmio(child
);
464 pci_read_bridge_mmio_pref(child
);
466 if (dev
->transparent
) {
467 pci_bus_for_each_resource(child
->parent
, res
, i
) {
469 pci_bus_add_resource(child
, res
,
470 PCI_SUBTRACTIVE_DECODE
);
471 dev_printk(KERN_DEBUG
, &dev
->dev
,
472 " bridge window %pR (subtractive decode)\n",
479 static struct pci_bus
*pci_alloc_bus(void)
483 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
487 INIT_LIST_HEAD(&b
->node
);
488 INIT_LIST_HEAD(&b
->children
);
489 INIT_LIST_HEAD(&b
->devices
);
490 INIT_LIST_HEAD(&b
->slots
);
491 INIT_LIST_HEAD(&b
->resources
);
492 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
493 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
497 static void pci_release_host_bridge_dev(struct device
*dev
)
499 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
501 if (bridge
->release_fn
)
502 bridge
->release_fn(bridge
);
504 pci_free_resource_list(&bridge
->windows
);
509 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
511 struct pci_host_bridge
*bridge
;
513 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
517 INIT_LIST_HEAD(&bridge
->windows
);
522 static const unsigned char pcix_bus_speed
[] = {
523 PCI_SPEED_UNKNOWN
, /* 0 */
524 PCI_SPEED_66MHz_PCIX
, /* 1 */
525 PCI_SPEED_100MHz_PCIX
, /* 2 */
526 PCI_SPEED_133MHz_PCIX
, /* 3 */
527 PCI_SPEED_UNKNOWN
, /* 4 */
528 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
529 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
530 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
531 PCI_SPEED_UNKNOWN
, /* 8 */
532 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
533 PCI_SPEED_100MHz_PCIX_266
, /* A */
534 PCI_SPEED_133MHz_PCIX_266
, /* B */
535 PCI_SPEED_UNKNOWN
, /* C */
536 PCI_SPEED_66MHz_PCIX_533
, /* D */
537 PCI_SPEED_100MHz_PCIX_533
, /* E */
538 PCI_SPEED_133MHz_PCIX_533
/* F */
541 const unsigned char pcie_link_speed
[] = {
542 PCI_SPEED_UNKNOWN
, /* 0 */
543 PCIE_SPEED_2_5GT
, /* 1 */
544 PCIE_SPEED_5_0GT
, /* 2 */
545 PCIE_SPEED_8_0GT
, /* 3 */
546 PCI_SPEED_UNKNOWN
, /* 4 */
547 PCI_SPEED_UNKNOWN
, /* 5 */
548 PCI_SPEED_UNKNOWN
, /* 6 */
549 PCI_SPEED_UNKNOWN
, /* 7 */
550 PCI_SPEED_UNKNOWN
, /* 8 */
551 PCI_SPEED_UNKNOWN
, /* 9 */
552 PCI_SPEED_UNKNOWN
, /* A */
553 PCI_SPEED_UNKNOWN
, /* B */
554 PCI_SPEED_UNKNOWN
, /* C */
555 PCI_SPEED_UNKNOWN
, /* D */
556 PCI_SPEED_UNKNOWN
, /* E */
557 PCI_SPEED_UNKNOWN
/* F */
560 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
562 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
564 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
566 static unsigned char agp_speeds
[] = {
574 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
580 else if (agpstat
& 2)
582 else if (agpstat
& 1)
594 return agp_speeds
[index
];
598 static void pci_set_bus_speed(struct pci_bus
*bus
)
600 struct pci_dev
*bridge
= bus
->self
;
603 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
605 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
609 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
610 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
612 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
613 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
616 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
619 enum pci_bus_speed max
;
621 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
624 if (status
& PCI_X_SSTATUS_533MHZ
) {
625 max
= PCI_SPEED_133MHz_PCIX_533
;
626 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
627 max
= PCI_SPEED_133MHz_PCIX_266
;
628 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
629 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
) {
630 max
= PCI_SPEED_133MHz_PCIX_ECC
;
632 max
= PCI_SPEED_133MHz_PCIX
;
635 max
= PCI_SPEED_66MHz_PCIX
;
638 bus
->max_bus_speed
= max
;
639 bus
->cur_bus_speed
= pcix_bus_speed
[
640 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
645 if (pci_is_pcie(bridge
)) {
649 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
650 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
652 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
653 pcie_update_link_speed(bus
, linksta
);
658 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
659 struct pci_dev
*bridge
, int busnr
)
661 struct pci_bus
*child
;
666 * Allocate a new bus, and inherit stuff from the parent..
668 child
= pci_alloc_bus();
672 child
->parent
= parent
;
673 child
->ops
= parent
->ops
;
674 child
->msi
= parent
->msi
;
675 child
->sysdata
= parent
->sysdata
;
676 child
->bus_flags
= parent
->bus_flags
;
678 /* initialize some portions of the bus device, but don't register it
679 * now as the parent is not properly set up yet.
681 child
->dev
.class = &pcibus_class
;
682 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
685 * Set up the primary, secondary and subordinate
688 child
->number
= child
->busn_res
.start
= busnr
;
689 child
->primary
= parent
->busn_res
.start
;
690 child
->busn_res
.end
= 0xff;
693 child
->dev
.parent
= parent
->bridge
;
697 child
->self
= bridge
;
698 child
->bridge
= get_device(&bridge
->dev
);
699 child
->dev
.parent
= child
->bridge
;
700 pci_set_bus_of_node(child
);
701 pci_set_bus_speed(child
);
703 /* Set up default resource pointers and names.. */
704 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
705 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
706 child
->resource
[i
]->name
= child
->name
;
708 bridge
->subordinate
= child
;
711 ret
= device_register(&child
->dev
);
714 pcibios_add_bus(child
);
716 /* Create legacy_io and legacy_mem files for this bus */
717 pci_create_legacy_files(child
);
722 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
724 struct pci_bus
*child
;
726 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
728 down_write(&pci_bus_sem
);
729 list_add_tail(&child
->node
, &parent
->children
);
730 up_write(&pci_bus_sem
);
736 * If it's a bridge, configure it and scan the bus behind it.
737 * For CardBus bridges, we don't scan behind as the devices will
738 * be handled by the bridge driver itself.
740 * We need to process bridges in two passes -- first we scan those
741 * already configured by the BIOS and after we are done with all of
742 * them, we proceed to assigning numbers to the remaining buses in
743 * order to avoid overlaps between old and new bus numbers.
745 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
747 struct pci_bus
*child
;
748 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
751 u8 primary
, secondary
, subordinate
;
754 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
755 primary
= buses
& 0xFF;
756 secondary
= (buses
>> 8) & 0xFF;
757 subordinate
= (buses
>> 16) & 0xFF;
759 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
760 secondary
, subordinate
, pass
);
762 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
763 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
764 primary
= bus
->number
;
767 /* Check if setup is sensible at all */
769 (primary
!= bus
->number
|| secondary
<= bus
->number
||
770 secondary
> subordinate
|| subordinate
> bus
->busn_res
.end
)) {
771 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
772 secondary
, subordinate
);
776 /* Disable MasterAbortMode during probing to avoid reporting
777 of bus errors (in some architectures) */
778 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
779 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
780 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
782 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
783 !is_cardbus
&& !broken
) {
786 * Bus already configured by firmware, process it in the first
787 * pass and just note the configuration.
793 * The bus might already exist for two reasons: Either we are
794 * rescanning the bus or the bus is reachable through more than
795 * one bridge. The second case can happen with the i450NX
798 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
800 child
= pci_add_new_bus(bus
, dev
, secondary
);
803 child
->primary
= primary
;
804 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
805 child
->bridge_ctl
= bctl
;
808 cmax
= pci_scan_child_bus(child
);
809 if (cmax
> subordinate
)
810 dev_warn(&dev
->dev
, "bridge has subordinate %02x but max busn %02x\n",
812 /* subordinate should equal child->busn_res.end */
813 if (subordinate
> max
)
817 * We need to assign a number to this bus which we always
818 * do in the second pass.
821 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
822 /* Temporarily disable forwarding of the
823 configuration cycles on all bridges in
824 this bus segment to avoid possible
825 conflicts in the second pass between two
826 bridges programmed with overlapping
828 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
833 if (max
>= bus
->busn_res
.end
) {
834 dev_warn(&dev
->dev
, "can't allocate child bus %02x from %pR\n",
835 max
, &bus
->busn_res
);
840 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
842 /* The bus will already exist if we are rescanning */
843 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
845 child
= pci_add_new_bus(bus
, dev
, max
+1);
848 pci_bus_insert_busn_res(child
, max
+1,
852 buses
= (buses
& 0xff000000)
853 | ((unsigned int)(child
->primary
) << 0)
854 | ((unsigned int)(child
->busn_res
.start
) << 8)
855 | ((unsigned int)(child
->busn_res
.end
) << 16);
858 * yenta.c forces a secondary latency timer of 176.
859 * Copy that behaviour here.
862 buses
&= ~0xff000000;
863 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
867 * We need to blast all three values with a single write.
869 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
872 child
->bridge_ctl
= bctl
;
873 max
= pci_scan_child_bus(child
);
876 * For CardBus bridges, we leave 4 bus numbers
877 * as cards with a PCI-to-PCI bridge can be
880 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
881 struct pci_bus
*parent
= bus
;
882 if (pci_find_bus(pci_domain_nr(bus
),
885 while (parent
->parent
) {
886 if ((!pcibios_assign_all_busses()) &&
887 (parent
->busn_res
.end
> max
) &&
888 (parent
->busn_res
.end
<= max
+i
)) {
891 parent
= parent
->parent
;
895 * Often, there are two cardbus bridges
896 * -- try to leave one valid bus number
906 * Set the subordinate bus number to its real value.
908 if (max
> bus
->busn_res
.end
) {
909 dev_warn(&dev
->dev
, "max busn %02x is outside %pR\n",
910 max
, &bus
->busn_res
);
911 max
= bus
->busn_res
.end
;
913 pci_bus_update_busn_res_end(child
, max
);
914 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
918 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
919 pci_domain_nr(bus
), child
->number
);
921 /* Has only triggered on CardBus, fixup is in yenta_socket */
922 while (bus
->parent
) {
923 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
924 (child
->number
> bus
->busn_res
.end
) ||
925 (child
->number
< bus
->number
) ||
926 (child
->busn_res
.end
< bus
->number
)) {
927 dev_info(&child
->dev
, "%pR %s "
928 "hidden behind%s bridge %s %pR\n",
930 (bus
->number
> child
->busn_res
.end
&&
931 bus
->busn_res
.end
< child
->number
) ?
932 "wholly" : "partially",
933 bus
->self
->transparent
? " transparent" : "",
941 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
947 * Read interrupt line and base address registers.
948 * The architecture-dependent code can tweak these, of course.
950 static void pci_read_irq(struct pci_dev
*dev
)
954 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
957 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
961 void set_pcie_port_type(struct pci_dev
*pdev
)
966 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
969 pdev
->pcie_cap
= pos
;
970 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
971 pdev
->pcie_flags_reg
= reg16
;
972 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
973 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
976 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
980 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
981 if (reg32
& PCI_EXP_SLTCAP_HPC
)
982 pdev
->is_hotplug_bridge
= 1;
987 * pci_cfg_space_size - get the configuration space size of the PCI device.
990 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
991 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
992 * access it. Maybe we don't have a way to generate extended config space
993 * accesses, or the device is behind a reverse Express bridge. So we try
994 * reading the dword at 0x100 which must either be 0 or a valid extended
997 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1000 int pos
= PCI_CFG_SPACE_SIZE
;
1002 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1004 if (status
== 0xffffffff)
1007 return PCI_CFG_SPACE_EXP_SIZE
;
1010 return PCI_CFG_SPACE_SIZE
;
1013 int pci_cfg_space_size(struct pci_dev
*dev
)
1019 class = dev
->class >> 8;
1020 if (class == PCI_CLASS_BRIDGE_HOST
)
1021 return pci_cfg_space_size_ext(dev
);
1023 if (!pci_is_pcie(dev
)) {
1024 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1028 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1029 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1033 return pci_cfg_space_size_ext(dev
);
1036 return PCI_CFG_SPACE_SIZE
;
1039 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1042 * pci_setup_device - fill in class and map information of a device
1043 * @dev: the device structure to fill
1045 * Initialize the device structure with information about the device's
1046 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1047 * Called at initialisation of the PCI subsystem and by CardBus services.
1048 * Returns 0 on success and negative if unknown type of device (not normal,
1049 * bridge or CardBus).
1051 int pci_setup_device(struct pci_dev
*dev
)
1055 struct pci_slot
*slot
;
1057 struct pci_bus_region region
;
1058 struct resource
*res
;
1060 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1063 dev
->sysdata
= dev
->bus
->sysdata
;
1064 dev
->dev
.parent
= dev
->bus
->bridge
;
1065 dev
->dev
.bus
= &pci_bus_type
;
1066 dev
->hdr_type
= hdr_type
& 0x7f;
1067 dev
->multifunction
= !!(hdr_type
& 0x80);
1068 dev
->error_state
= pci_channel_io_normal
;
1069 set_pcie_port_type(dev
);
1071 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
1072 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
1075 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1076 set this higher, assuming the system even supports it. */
1077 dev
->dma_mask
= 0xffffffff;
1079 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1080 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1081 PCI_FUNC(dev
->devfn
));
1083 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1084 dev
->revision
= class & 0xff;
1085 dev
->class = class >> 8; /* upper 3 bytes */
1087 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1088 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1090 /* need to have dev->class ready */
1091 dev
->cfg_size
= pci_cfg_space_size(dev
);
1093 /* "Unknown power state" */
1094 dev
->current_state
= PCI_UNKNOWN
;
1096 /* Early fixups, before probing the BARs */
1097 pci_fixup_device(pci_fixup_early
, dev
);
1098 /* device class may be changed after fixup */
1099 class = dev
->class >> 8;
1101 switch (dev
->hdr_type
) { /* header type */
1102 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1103 if (class == PCI_CLASS_BRIDGE_PCI
)
1106 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1107 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1108 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1111 * Do the ugly legacy mode stuff here rather than broken chip
1112 * quirk code. Legacy mode ATA controllers have fixed
1113 * addresses. These are not always echoed in BAR0-3, and
1114 * BAR0-3 in a few cases contain junk!
1116 if (class == PCI_CLASS_STORAGE_IDE
) {
1118 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1119 if ((progif
& 1) == 0) {
1120 region
.start
= 0x1F0;
1122 res
= &dev
->resource
[0];
1123 res
->flags
= LEGACY_IO_RESOURCE
;
1124 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1125 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1127 region
.start
= 0x3F6;
1129 res
= &dev
->resource
[1];
1130 res
->flags
= LEGACY_IO_RESOURCE
;
1131 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1132 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1135 if ((progif
& 4) == 0) {
1136 region
.start
= 0x170;
1138 res
= &dev
->resource
[2];
1139 res
->flags
= LEGACY_IO_RESOURCE
;
1140 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1141 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1143 region
.start
= 0x376;
1145 res
= &dev
->resource
[3];
1146 res
->flags
= LEGACY_IO_RESOURCE
;
1147 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1148 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1154 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1155 if (class != PCI_CLASS_BRIDGE_PCI
)
1157 /* The PCI-to-PCI bridge spec requires that subtractive
1158 decoding (i.e. transparent) bridge must have programming
1159 interface code of 0x01. */
1161 dev
->transparent
= ((dev
->class & 0xff) == 1);
1162 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1163 set_pcie_hotplug_bridge(dev
);
1164 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1166 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1167 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1171 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1172 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1175 pci_read_bases(dev
, 1, 0);
1176 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1177 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1180 default: /* unknown header */
1181 dev_err(&dev
->dev
, "unknown header type %02x, "
1182 "ignoring device\n", dev
->hdr_type
);
1186 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header "
1187 "type %02x)\n", dev
->class, dev
->hdr_type
);
1188 dev
->class = PCI_CLASS_NOT_DEFINED
;
1191 /* We found a fine healthy device, go go go... */
1195 static void pci_release_capabilities(struct pci_dev
*dev
)
1197 pci_vpd_release(dev
);
1198 pci_iov_release(dev
);
1199 pci_free_cap_save_buffers(dev
);
1203 * pci_release_dev - free a pci device structure when all users of it are finished.
1204 * @dev: device that's been disconnected
1206 * Will be called only by the device core when all users of this pci device are
1209 static void pci_release_dev(struct device
*dev
)
1211 struct pci_dev
*pci_dev
;
1213 pci_dev
= to_pci_dev(dev
);
1214 pci_release_capabilities(pci_dev
);
1215 pci_release_of_node(pci_dev
);
1216 pcibios_release_device(pci_dev
);
1217 pci_bus_put(pci_dev
->bus
);
1221 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1223 struct pci_dev
*dev
;
1225 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1229 INIT_LIST_HEAD(&dev
->bus_list
);
1230 dev
->dev
.type
= &pci_dev_type
;
1231 dev
->bus
= pci_bus_get(bus
);
1235 EXPORT_SYMBOL(pci_alloc_dev
);
1237 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1242 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1245 /* some broken boards return 0 or ~0 if a slot is empty: */
1246 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1247 *l
== 0x0000ffff || *l
== 0xffff0000)
1250 /* Configuration request Retry Status */
1251 while (*l
== 0xffff0001) {
1257 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1259 /* Card hasn't responded in 60 seconds? Must be stuck. */
1260 if (delay
> crs_timeout
) {
1261 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
1262 "responding\n", pci_domain_nr(bus
),
1263 bus
->number
, PCI_SLOT(devfn
),
1271 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1274 * Read the config data for a PCI device, sanity-check it
1275 * and fill in the dev structure...
1277 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1279 struct pci_dev
*dev
;
1282 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1285 dev
= pci_alloc_dev(bus
);
1290 dev
->vendor
= l
& 0xffff;
1291 dev
->device
= (l
>> 16) & 0xffff;
1293 pci_set_of_node(dev
);
1295 if (pci_setup_device(dev
)) {
1296 pci_bus_put(dev
->bus
);
1304 static void pci_init_capabilities(struct pci_dev
*dev
)
1306 /* MSI/MSI-X list */
1307 pci_msi_init_pci_dev(dev
);
1309 /* Buffers for saving PCIe and PCI-X capabilities */
1310 pci_allocate_cap_save_buffers(dev
);
1312 /* Power Management */
1315 /* Vital Product Data */
1316 pci_vpd_pci22_init(dev
);
1318 /* Alternative Routing-ID Forwarding */
1319 pci_configure_ari(dev
);
1321 /* Single Root I/O Virtualization */
1324 /* Enable ACS P2P upstream forwarding */
1325 pci_enable_acs(dev
);
1328 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1332 device_initialize(&dev
->dev
);
1333 dev
->dev
.release
= pci_release_dev
;
1335 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1336 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1337 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1338 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1340 pci_set_dma_max_seg_size(dev
, 65536);
1341 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1343 /* Fix up broken headers */
1344 pci_fixup_device(pci_fixup_header
, dev
);
1346 /* moved out from quirk header fixup code */
1347 pci_reassigndev_resource_alignment(dev
);
1349 /* Clear the state_saved flag. */
1350 dev
->state_saved
= false;
1352 /* Initialize various capabilities */
1353 pci_init_capabilities(dev
);
1356 * Add the device to our list of discovered devices
1357 * and the bus list for fixup functions, etc.
1359 down_write(&pci_bus_sem
);
1360 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1361 up_write(&pci_bus_sem
);
1363 ret
= pcibios_add_device(dev
);
1366 /* Notifier could use PCI capabilities */
1367 dev
->match_driver
= false;
1368 ret
= device_add(&dev
->dev
);
1372 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1374 struct pci_dev
*dev
;
1376 dev
= pci_get_slot(bus
, devfn
);
1382 dev
= pci_scan_device(bus
, devfn
);
1386 pci_device_add(dev
, bus
);
1390 EXPORT_SYMBOL(pci_scan_single_device
);
1392 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1398 if (pci_ari_enabled(bus
)) {
1401 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1405 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1406 next_fn
= PCI_ARI_CAP_NFN(cap
);
1408 return 0; /* protect against malformed list */
1413 /* dev may be NULL for non-contiguous multifunction devices */
1414 if (!dev
|| dev
->multifunction
)
1415 return (fn
+ 1) % 8;
1420 static int only_one_child(struct pci_bus
*bus
)
1422 struct pci_dev
*parent
= bus
->self
;
1424 if (!parent
|| !pci_is_pcie(parent
))
1426 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1428 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_DOWNSTREAM
&&
1429 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1435 * pci_scan_slot - scan a PCI slot on a bus for devices.
1436 * @bus: PCI bus to scan
1437 * @devfn: slot number to scan (must have zero function.)
1439 * Scan a PCI slot on the specified PCI bus for devices, adding
1440 * discovered devices to the @bus->devices list. New devices
1441 * will not have is_added set.
1443 * Returns the number of new devices found.
1445 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1447 unsigned fn
, nr
= 0;
1448 struct pci_dev
*dev
;
1450 if (only_one_child(bus
) && (devfn
> 0))
1451 return 0; /* Already scanned the entire slot */
1453 dev
= pci_scan_single_device(bus
, devfn
);
1459 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1460 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1464 dev
->multifunction
= 1;
1468 /* only one slot has pcie device */
1469 if (bus
->self
&& nr
)
1470 pcie_aspm_init_link_state(bus
->self
);
1475 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1479 if (!pci_is_pcie(dev
))
1483 * We don't have a way to change MPS settings on devices that have
1484 * drivers attached. A hot-added device might support only the minimum
1485 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1486 * where devices may be hot-added, we limit the fabric MPS to 128 so
1487 * hot-added devices will work correctly.
1489 * However, if we hot-add a device to a slot directly below a Root
1490 * Port, it's impossible for there to be other existing devices below
1491 * the port. We don't limit the MPS in this case because we can
1492 * reconfigure MPS on both the Root Port and the hot-added device,
1493 * and there are no other devices involved.
1495 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1497 if (dev
->is_hotplug_bridge
&&
1498 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1501 if (*smpss
> dev
->pcie_mpss
)
1502 *smpss
= dev
->pcie_mpss
;
1507 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1511 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1512 mps
= 128 << dev
->pcie_mpss
;
1514 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1516 /* For "Performance", the assumption is made that
1517 * downstream communication will never be larger than
1518 * the MRRS. So, the MPS only needs to be configured
1519 * for the upstream communication. This being the case,
1520 * walk from the top down and set the MPS of the child
1521 * to that of the parent bus.
1523 * Configure the device MPS with the smaller of the
1524 * device MPSS or the bridge MPS (which is assumed to be
1525 * properly configured at this point to the largest
1526 * allowable MPS based on its parent bus).
1528 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1531 rc
= pcie_set_mps(dev
, mps
);
1533 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1536 static void pcie_write_mrrs(struct pci_dev
*dev
)
1540 /* In the "safe" case, do not configure the MRRS. There appear to be
1541 * issues with setting MRRS to 0 on a number of devices.
1543 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1546 /* For Max performance, the MRRS must be set to the largest supported
1547 * value. However, it cannot be configured larger than the MPS the
1548 * device or the bus can support. This should already be properly
1549 * configured by a prior call to pcie_write_mps.
1551 mrrs
= pcie_get_mps(dev
);
1553 /* MRRS is a R/W register. Invalid values can be written, but a
1554 * subsequent read will verify if the value is acceptable or not.
1555 * If the MRRS value provided is not acceptable (e.g., too large),
1556 * shrink the value until it is acceptable to the HW.
1558 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
1559 rc
= pcie_set_readrq(dev
, mrrs
);
1563 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
1568 dev_err(&dev
->dev
, "MRRS was unable to be configured with a "
1569 "safe value. If problems are experienced, try running "
1570 "with pci=pcie_bus_safe.\n");
1573 static void pcie_bus_detect_mps(struct pci_dev
*dev
)
1575 struct pci_dev
*bridge
= dev
->bus
->self
;
1581 mps
= pcie_get_mps(dev
);
1582 p_mps
= pcie_get_mps(bridge
);
1585 dev_warn(&dev
->dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1586 mps
, pci_name(bridge
), p_mps
);
1589 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
1593 if (!pci_is_pcie(dev
))
1596 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1597 pcie_bus_detect_mps(dev
);
1601 mps
= 128 << *(u8
*)data
;
1602 orig_mps
= pcie_get_mps(dev
);
1604 pcie_write_mps(dev
, mps
);
1605 pcie_write_mrrs(dev
);
1607 dev_info(&dev
->dev
, "Max Payload Size set to %4d/%4d (was %4d), "
1608 "Max Read Rq %4d\n", pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
1609 orig_mps
, pcie_get_readrq(dev
));
1614 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1615 * parents then children fashion. If this changes, then this code will not
1618 void pcie_bus_configure_settings(struct pci_bus
*bus
)
1625 if (!pci_is_pcie(bus
->self
))
1628 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1629 * to be aware of the MPS of the destination. To work around this,
1630 * simply force the MPS of the entire system to the smallest possible.
1632 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1635 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
1636 smpss
= bus
->self
->pcie_mpss
;
1638 pcie_find_smpss(bus
->self
, &smpss
);
1639 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
1642 pcie_bus_configure_set(bus
->self
, &smpss
);
1643 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
1645 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
1647 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
1649 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
1650 struct pci_dev
*dev
;
1652 dev_dbg(&bus
->dev
, "scanning bus\n");
1654 /* Go find them, Rover! */
1655 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1656 pci_scan_slot(bus
, devfn
);
1658 /* Reserve buses for SR-IOV capability. */
1659 max
+= pci_iov_bus_range(bus
);
1662 * After performing arch-dependent fixup of the bus, look behind
1663 * all PCI-to-PCI bridges on this bus.
1665 if (!bus
->is_added
) {
1666 dev_dbg(&bus
->dev
, "fixups for bus\n");
1667 pcibios_fixup_bus(bus
);
1671 for (pass
=0; pass
< 2; pass
++)
1672 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1673 if (pci_is_bridge(dev
))
1674 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1678 * We've scanned the bus and so we know all about what's on
1679 * the other side of any bridges that may be on this bus plus
1682 * Return how far we've got finding sub-buses.
1684 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1689 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1690 * @bridge: Host bridge to set up.
1692 * Default empty implementation. Replace with an architecture-specific setup
1693 * routine, if necessary.
1695 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
1700 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
1704 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
1708 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
1709 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
1712 struct pci_host_bridge
*bridge
;
1713 struct pci_bus
*b
, *b2
;
1714 struct pci_host_bridge_window
*window
, *n
;
1715 struct resource
*res
;
1716 resource_size_t offset
;
1720 b
= pci_alloc_bus();
1724 b
->sysdata
= sysdata
;
1726 b
->number
= b
->busn_res
.start
= bus
;
1727 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1729 /* If we already got to this bus through a different bridge, ignore it */
1730 dev_dbg(&b2
->dev
, "bus already known\n");
1734 bridge
= pci_alloc_host_bridge(b
);
1738 bridge
->dev
.parent
= parent
;
1739 bridge
->dev
.release
= pci_release_host_bridge_dev
;
1740 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1741 error
= pcibios_root_bridge_prepare(bridge
);
1747 error
= device_register(&bridge
->dev
);
1749 put_device(&bridge
->dev
);
1752 b
->bridge
= get_device(&bridge
->dev
);
1753 device_enable_async_suspend(b
->bridge
);
1754 pci_set_bus_of_node(b
);
1757 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1759 b
->dev
.class = &pcibus_class
;
1760 b
->dev
.parent
= b
->bridge
;
1761 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1762 error
= device_register(&b
->dev
);
1764 goto class_dev_reg_err
;
1768 /* Create legacy_io and legacy_mem files for this bus */
1769 pci_create_legacy_files(b
);
1772 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1774 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1776 /* Add initial resources to the bus */
1777 list_for_each_entry_safe(window
, n
, resources
, list
) {
1778 list_move_tail(&window
->list
, &bridge
->windows
);
1780 offset
= window
->offset
;
1781 if (res
->flags
& IORESOURCE_BUS
)
1782 pci_bus_insert_busn_res(b
, bus
, res
->end
);
1784 pci_bus_add_resource(b
, res
, 0);
1786 if (resource_type(res
) == IORESOURCE_IO
)
1787 fmt
= " (bus address [%#06llx-%#06llx])";
1789 fmt
= " (bus address [%#010llx-%#010llx])";
1790 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
1791 (unsigned long long) (res
->start
- offset
),
1792 (unsigned long long) (res
->end
- offset
));
1795 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
1798 down_write(&pci_bus_sem
);
1799 list_add_tail(&b
->node
, &pci_root_buses
);
1800 up_write(&pci_bus_sem
);
1805 put_device(&bridge
->dev
);
1806 device_unregister(&bridge
->dev
);
1812 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
1814 struct resource
*res
= &b
->busn_res
;
1815 struct resource
*parent_res
, *conflict
;
1819 res
->flags
= IORESOURCE_BUS
;
1821 if (!pci_is_root_bus(b
))
1822 parent_res
= &b
->parent
->busn_res
;
1824 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
1825 res
->flags
|= IORESOURCE_PCI_FIXED
;
1828 conflict
= request_resource_conflict(parent_res
, res
);
1831 dev_printk(KERN_DEBUG
, &b
->dev
,
1832 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1833 res
, pci_is_root_bus(b
) ? "domain " : "",
1834 parent_res
, conflict
->name
, conflict
);
1836 return conflict
== NULL
;
1839 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
1841 struct resource
*res
= &b
->busn_res
;
1842 struct resource old_res
= *res
;
1843 resource_size_t size
;
1846 if (res
->start
> bus_max
)
1849 size
= bus_max
- res
->start
+ 1;
1850 ret
= adjust_resource(res
, res
->start
, size
);
1851 dev_printk(KERN_DEBUG
, &b
->dev
,
1852 "busn_res: %pR end %s updated to %02x\n",
1853 &old_res
, ret
? "can not be" : "is", bus_max
);
1855 if (!ret
&& !res
->parent
)
1856 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
1861 void pci_bus_release_busn_res(struct pci_bus
*b
)
1863 struct resource
*res
= &b
->busn_res
;
1866 if (!res
->flags
|| !res
->parent
)
1869 ret
= release_resource(res
);
1870 dev_printk(KERN_DEBUG
, &b
->dev
,
1871 "busn_res: %pR %s released\n",
1872 res
, ret
? "can not be" : "is");
1875 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
1876 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
1878 struct pci_host_bridge_window
*window
;
1883 list_for_each_entry(window
, resources
, list
)
1884 if (window
->res
->flags
& IORESOURCE_BUS
) {
1889 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
1895 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1897 pci_bus_insert_busn_res(b
, bus
, 255);
1900 max
= pci_scan_child_bus(b
);
1903 pci_bus_update_busn_res_end(b
, max
);
1905 pci_bus_add_devices(b
);
1908 EXPORT_SYMBOL(pci_scan_root_bus
);
1910 /* Deprecated; use pci_scan_root_bus() instead */
1911 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
,
1912 int bus
, struct pci_ops
*ops
, void *sysdata
)
1914 LIST_HEAD(resources
);
1917 pci_add_resource(&resources
, &ioport_resource
);
1918 pci_add_resource(&resources
, &iomem_resource
);
1919 pci_add_resource(&resources
, &busn_resource
);
1920 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, &resources
);
1922 pci_scan_child_bus(b
);
1924 pci_free_resource_list(&resources
);
1927 EXPORT_SYMBOL(pci_scan_bus_parented
);
1929 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
1932 LIST_HEAD(resources
);
1935 pci_add_resource(&resources
, &ioport_resource
);
1936 pci_add_resource(&resources
, &iomem_resource
);
1937 pci_add_resource(&resources
, &busn_resource
);
1938 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
1940 pci_scan_child_bus(b
);
1941 pci_bus_add_devices(b
);
1943 pci_free_resource_list(&resources
);
1947 EXPORT_SYMBOL(pci_scan_bus
);
1950 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1951 * @bridge: PCI bridge for the bus to scan
1953 * Scan a PCI bus and child buses for new devices, add them,
1954 * and enable them, resizing bridge mmio/io resource if necessary
1955 * and possible. The caller must ensure the child devices are already
1956 * removed for resizing to occur.
1958 * Returns the max number of subordinate bus discovered.
1960 unsigned int __ref
pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
1963 struct pci_bus
*bus
= bridge
->subordinate
;
1965 max
= pci_scan_child_bus(bus
);
1967 pci_assign_unassigned_bridge_resources(bridge
);
1969 pci_bus_add_devices(bus
);
1975 * pci_rescan_bus - scan a PCI bus for devices.
1976 * @bus: PCI bus to scan
1978 * Scan a PCI bus and child buses for new devices, adds them,
1981 * Returns the max number of subordinate bus discovered.
1983 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1987 max
= pci_scan_child_bus(bus
);
1988 pci_assign_unassigned_bus_resources(bus
);
1989 pci_bus_add_devices(bus
);
1993 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1995 EXPORT_SYMBOL(pci_add_new_bus
);
1996 EXPORT_SYMBOL(pci_scan_slot
);
1997 EXPORT_SYMBOL(pci_scan_bridge
);
1998 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
2001 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2002 * routines should always be executed under this mutex.
2004 static DEFINE_MUTEX(pci_rescan_remove_lock
);
2006 void pci_lock_rescan_remove(void)
2008 mutex_lock(&pci_rescan_remove_lock
);
2010 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
2012 void pci_unlock_rescan_remove(void)
2014 mutex_unlock(&pci_rescan_remove_lock
);
2016 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
2018 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
2020 const struct pci_dev
*a
= to_pci_dev(d_a
);
2021 const struct pci_dev
*b
= to_pci_dev(d_b
);
2023 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2024 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2026 if (a
->bus
->number
< b
->bus
->number
) return -1;
2027 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2029 if (a
->devfn
< b
->devfn
) return -1;
2030 else if (a
->devfn
> b
->devfn
) return 1;
2035 void __init
pci_sort_breadthfirst(void)
2037 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);