1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list_sort.h>
25 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
26 #define CARDBUS_RESERVE_BUSNR 3
28 static struct resource busn_resource
= {
32 .flags
= IORESOURCE_BUS
,
35 /* Ugh. Need to stop exporting this to modules. */
36 LIST_HEAD(pci_root_buses
);
37 EXPORT_SYMBOL(pci_root_buses
);
39 static LIST_HEAD(pci_domain_busn_res_list
);
41 struct pci_domain_busn_res
{
42 struct list_head list
;
47 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
49 struct pci_domain_busn_res
*r
;
51 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
52 if (r
->domain_nr
== domain_nr
)
55 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
59 r
->domain_nr
= domain_nr
;
62 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
64 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
70 * Some device drivers need know if PCI is initiated.
71 * Basically, we think PCI is not initiated when there
72 * is no device to be found on the pci_bus_type.
74 int no_pci_devices(void)
79 dev
= bus_find_next_device(&pci_bus_type
, NULL
);
80 no_devices
= (dev
== NULL
);
84 EXPORT_SYMBOL(no_pci_devices
);
89 static void release_pcibus_dev(struct device
*dev
)
91 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
93 put_device(pci_bus
->bridge
);
94 pci_bus_remove_resources(pci_bus
);
95 pci_release_bus_of_node(pci_bus
);
99 static struct class pcibus_class
= {
101 .dev_release
= &release_pcibus_dev
,
102 .dev_groups
= pcibus_groups
,
105 static int __init
pcibus_class_init(void)
107 return class_register(&pcibus_class
);
109 postcore_initcall(pcibus_class_init
);
111 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
113 u64 size
= mask
& maxbase
; /* Find the significant bits */
118 * Get the lowest of them to find the decode size, and from that
121 size
= size
& ~(size
-1);
124 * base == maxbase can be valid only if the BAR has already been
125 * programmed with all 1s.
127 if (base
== maxbase
&& ((base
| (size
- 1)) & mask
) != mask
)
133 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
138 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
139 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
140 flags
|= IORESOURCE_IO
;
144 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
145 flags
|= IORESOURCE_MEM
;
146 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
147 flags
|= IORESOURCE_PREFETCH
;
149 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
151 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
153 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
154 /* 1M mem BAR treated as 32-bit BAR */
156 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
157 flags
|= IORESOURCE_MEM_64
;
160 /* mem unknown type treated as 32-bit BAR */
166 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
169 * __pci_read_base - Read a PCI BAR
170 * @dev: the PCI device
171 * @type: type of the BAR
172 * @res: resource buffer to be filled in
173 * @pos: BAR position in the config space
175 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
177 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
178 struct resource
*res
, unsigned int pos
)
180 u32 l
= 0, sz
= 0, mask
;
181 u64 l64
, sz64
, mask64
;
183 struct pci_bus_region region
, inverted_region
;
185 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
187 /* No printks while decoding is disabled! */
188 if (!dev
->mmio_always_on
) {
189 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
190 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
191 pci_write_config_word(dev
, PCI_COMMAND
,
192 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
196 res
->name
= pci_name(dev
);
198 pci_read_config_dword(dev
, pos
, &l
);
199 pci_write_config_dword(dev
, pos
, l
| mask
);
200 pci_read_config_dword(dev
, pos
, &sz
);
201 pci_write_config_dword(dev
, pos
, l
);
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
209 if (sz
== 0xffffffff)
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
219 if (type
== pci_bar_unknown
) {
220 res
->flags
= decode_bar(dev
, l
);
221 res
->flags
|= IORESOURCE_SIZEALIGN
;
222 if (res
->flags
& IORESOURCE_IO
) {
223 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
224 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
225 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
227 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
228 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
229 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
232 if (l
& PCI_ROM_ADDRESS_ENABLE
)
233 res
->flags
|= IORESOURCE_ROM_ENABLE
;
234 l64
= l
& PCI_ROM_ADDRESS_MASK
;
235 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
236 mask64
= PCI_ROM_ADDRESS_MASK
;
239 if (res
->flags
& IORESOURCE_MEM_64
) {
240 pci_read_config_dword(dev
, pos
+ 4, &l
);
241 pci_write_config_dword(dev
, pos
+ 4, ~0);
242 pci_read_config_dword(dev
, pos
+ 4, &sz
);
243 pci_write_config_dword(dev
, pos
+ 4, l
);
245 l64
|= ((u64
)l
<< 32);
246 sz64
|= ((u64
)sz
<< 32);
247 mask64
|= ((u64
)~0 << 32);
250 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
251 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
256 sz64
= pci_size(l64
, sz64
, mask64
);
258 pci_info(dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
263 if (res
->flags
& IORESOURCE_MEM_64
) {
264 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
265 && sz64
> 0x100000000ULL
) {
266 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
269 pci_err(dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
270 pos
, (unsigned long long)sz64
);
274 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
275 /* Above 32-bit boundary; try to reallocate */
276 res
->flags
|= IORESOURCE_UNSET
;
279 pci_info(dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
280 pos
, (unsigned long long)l64
);
286 region
.end
= l64
+ sz64
- 1;
288 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
289 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
292 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
293 * the corresponding resource address (the physical address used by
294 * the CPU. Converting that resource address back to a bus address
295 * should yield the original BAR value:
297 * resource_to_bus(bus_to_resource(A)) == A
299 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
300 * be claimed by the device.
302 if (inverted_region
.start
!= region
.start
) {
303 res
->flags
|= IORESOURCE_UNSET
;
305 res
->end
= region
.end
- region
.start
;
306 pci_info(dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
307 pos
, (unsigned long long)region
.start
);
317 pci_info(dev
, "reg 0x%x: %pR\n", pos
, res
);
319 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
322 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
324 unsigned int pos
, reg
;
326 if (dev
->non_compliant_bars
)
329 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
333 for (pos
= 0; pos
< howmany
; pos
++) {
334 struct resource
*res
= &dev
->resource
[pos
];
335 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
336 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
340 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
341 dev
->rom_base_reg
= rom
;
342 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
343 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
344 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
348 static void pci_read_bridge_windows(struct pci_dev
*bridge
)
353 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
355 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xe0f0);
356 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
357 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
360 bridge
->io_window
= 1;
363 * DECchip 21050 pass 2 errata: the bridge may miss an address
364 * disconnect boundary by one PCI data phase. Workaround: do not
365 * use prefetching on this device.
367 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
370 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
372 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
374 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
375 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
380 bridge
->pref_window
= 1;
382 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
385 * Bridge claims to have a 64-bit prefetchable memory
386 * window; verify that the upper bits are actually
389 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &pmem
);
390 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
392 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
393 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, pmem
);
395 bridge
->pref_64_window
= 1;
399 static void pci_read_bridge_io(struct pci_bus
*child
)
401 struct pci_dev
*dev
= child
->self
;
402 u8 io_base_lo
, io_limit_lo
;
403 unsigned long io_mask
, io_granularity
, base
, limit
;
404 struct pci_bus_region region
;
405 struct resource
*res
;
407 io_mask
= PCI_IO_RANGE_MASK
;
408 io_granularity
= 0x1000;
409 if (dev
->io_window_1k
) {
410 /* Support 1K I/O space granularity */
411 io_mask
= PCI_IO_1K_RANGE_MASK
;
412 io_granularity
= 0x400;
415 res
= child
->resource
[0];
416 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
417 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
418 base
= (io_base_lo
& io_mask
) << 8;
419 limit
= (io_limit_lo
& io_mask
) << 8;
421 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
422 u16 io_base_hi
, io_limit_hi
;
424 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
425 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
426 base
|= ((unsigned long) io_base_hi
<< 16);
427 limit
|= ((unsigned long) io_limit_hi
<< 16);
431 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
433 region
.end
= limit
+ io_granularity
- 1;
434 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
435 pci_info(dev
, " bridge window %pR\n", res
);
439 static void pci_read_bridge_mmio(struct pci_bus
*child
)
441 struct pci_dev
*dev
= child
->self
;
442 u16 mem_base_lo
, mem_limit_lo
;
443 unsigned long base
, limit
;
444 struct pci_bus_region region
;
445 struct resource
*res
;
447 res
= child
->resource
[1];
448 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
449 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
450 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
451 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
453 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
455 region
.end
= limit
+ 0xfffff;
456 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
457 pci_info(dev
, " bridge window %pR\n", res
);
461 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
463 struct pci_dev
*dev
= child
->self
;
464 u16 mem_base_lo
, mem_limit_lo
;
466 pci_bus_addr_t base
, limit
;
467 struct pci_bus_region region
;
468 struct resource
*res
;
470 res
= child
->resource
[2];
471 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
472 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
473 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
474 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
476 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
477 u32 mem_base_hi
, mem_limit_hi
;
479 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
480 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
483 * Some bridges set the base > limit by default, and some
484 * (broken) BIOSes do not initialize them. If we find
485 * this, just assume they are not being used.
487 if (mem_base_hi
<= mem_limit_hi
) {
488 base64
|= (u64
) mem_base_hi
<< 32;
489 limit64
|= (u64
) mem_limit_hi
<< 32;
493 base
= (pci_bus_addr_t
) base64
;
494 limit
= (pci_bus_addr_t
) limit64
;
496 if (base
!= base64
) {
497 pci_err(dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
498 (unsigned long long) base64
);
503 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
504 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
505 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
506 res
->flags
|= IORESOURCE_MEM_64
;
508 region
.end
= limit
+ 0xfffff;
509 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
510 pci_info(dev
, " bridge window %pR\n", res
);
514 void pci_read_bridge_bases(struct pci_bus
*child
)
516 struct pci_dev
*dev
= child
->self
;
517 struct resource
*res
;
520 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
523 pci_info(dev
, "PCI bridge to %pR%s\n",
525 dev
->transparent
? " (subtractive decode)" : "");
527 pci_bus_remove_resources(child
);
528 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
529 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
531 pci_read_bridge_io(child
);
532 pci_read_bridge_mmio(child
);
533 pci_read_bridge_mmio_pref(child
);
535 if (dev
->transparent
) {
536 pci_bus_for_each_resource(child
->parent
, res
, i
) {
537 if (res
&& res
->flags
) {
538 pci_bus_add_resource(child
, res
,
539 PCI_SUBTRACTIVE_DECODE
);
540 pci_info(dev
, " bridge window %pR (subtractive decode)\n",
547 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
551 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
555 INIT_LIST_HEAD(&b
->node
);
556 INIT_LIST_HEAD(&b
->children
);
557 INIT_LIST_HEAD(&b
->devices
);
558 INIT_LIST_HEAD(&b
->slots
);
559 INIT_LIST_HEAD(&b
->resources
);
560 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
561 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
562 #ifdef CONFIG_PCI_DOMAINS_GENERIC
564 b
->domain_nr
= parent
->domain_nr
;
569 static void pci_release_host_bridge_dev(struct device
*dev
)
571 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
573 if (bridge
->release_fn
)
574 bridge
->release_fn(bridge
);
576 pci_free_resource_list(&bridge
->windows
);
577 pci_free_resource_list(&bridge
->dma_ranges
);
581 static void pci_init_host_bridge(struct pci_host_bridge
*bridge
)
583 INIT_LIST_HEAD(&bridge
->windows
);
584 INIT_LIST_HEAD(&bridge
->dma_ranges
);
587 * We assume we can manage these PCIe features. Some systems may
588 * reserve these for use by the platform itself, e.g., an ACPI BIOS
589 * may implement its own AER handling and use _OSC to prevent the
590 * OS from interfering.
592 bridge
->native_aer
= 1;
593 bridge
->native_pcie_hotplug
= 1;
594 bridge
->native_shpc_hotplug
= 1;
595 bridge
->native_pme
= 1;
596 bridge
->native_ltr
= 1;
597 bridge
->native_dpc
= 1;
599 device_initialize(&bridge
->dev
);
602 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
)
604 struct pci_host_bridge
*bridge
;
606 bridge
= kzalloc(sizeof(*bridge
) + priv
, GFP_KERNEL
);
610 pci_init_host_bridge(bridge
);
611 bridge
->dev
.release
= pci_release_host_bridge_dev
;
615 EXPORT_SYMBOL(pci_alloc_host_bridge
);
617 static void devm_pci_alloc_host_bridge_release(void *data
)
619 pci_free_host_bridge(data
);
622 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
626 struct pci_host_bridge
*bridge
;
628 bridge
= pci_alloc_host_bridge(priv
);
632 bridge
->dev
.parent
= dev
;
634 ret
= devm_add_action_or_reset(dev
, devm_pci_alloc_host_bridge_release
,
639 ret
= devm_of_pci_bridge_init(dev
, bridge
);
645 EXPORT_SYMBOL(devm_pci_alloc_host_bridge
);
647 void pci_free_host_bridge(struct pci_host_bridge
*bridge
)
649 put_device(&bridge
->dev
);
651 EXPORT_SYMBOL(pci_free_host_bridge
);
653 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
654 static const unsigned char pcix_bus_speed
[] = {
655 PCI_SPEED_UNKNOWN
, /* 0 */
656 PCI_SPEED_66MHz_PCIX
, /* 1 */
657 PCI_SPEED_100MHz_PCIX
, /* 2 */
658 PCI_SPEED_133MHz_PCIX
, /* 3 */
659 PCI_SPEED_UNKNOWN
, /* 4 */
660 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
661 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
662 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
663 PCI_SPEED_UNKNOWN
, /* 8 */
664 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
665 PCI_SPEED_100MHz_PCIX_266
, /* A */
666 PCI_SPEED_133MHz_PCIX_266
, /* B */
667 PCI_SPEED_UNKNOWN
, /* C */
668 PCI_SPEED_66MHz_PCIX_533
, /* D */
669 PCI_SPEED_100MHz_PCIX_533
, /* E */
670 PCI_SPEED_133MHz_PCIX_533
/* F */
673 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
674 const unsigned char pcie_link_speed
[] = {
675 PCI_SPEED_UNKNOWN
, /* 0 */
676 PCIE_SPEED_2_5GT
, /* 1 */
677 PCIE_SPEED_5_0GT
, /* 2 */
678 PCIE_SPEED_8_0GT
, /* 3 */
679 PCIE_SPEED_16_0GT
, /* 4 */
680 PCIE_SPEED_32_0GT
, /* 5 */
681 PCIE_SPEED_64_0GT
, /* 6 */
682 PCI_SPEED_UNKNOWN
, /* 7 */
683 PCI_SPEED_UNKNOWN
, /* 8 */
684 PCI_SPEED_UNKNOWN
, /* 9 */
685 PCI_SPEED_UNKNOWN
, /* A */
686 PCI_SPEED_UNKNOWN
, /* B */
687 PCI_SPEED_UNKNOWN
, /* C */
688 PCI_SPEED_UNKNOWN
, /* D */
689 PCI_SPEED_UNKNOWN
, /* E */
690 PCI_SPEED_UNKNOWN
/* F */
692 EXPORT_SYMBOL_GPL(pcie_link_speed
);
694 const char *pci_speed_string(enum pci_bus_speed speed
)
696 /* Indexed by the pci_bus_speed enum */
697 static const char *speed_strings
[] = {
698 "33 MHz PCI", /* 0x00 */
699 "66 MHz PCI", /* 0x01 */
700 "66 MHz PCI-X", /* 0x02 */
701 "100 MHz PCI-X", /* 0x03 */
702 "133 MHz PCI-X", /* 0x04 */
707 "66 MHz PCI-X 266", /* 0x09 */
708 "100 MHz PCI-X 266", /* 0x0a */
709 "133 MHz PCI-X 266", /* 0x0b */
710 "Unknown AGP", /* 0x0c */
715 "66 MHz PCI-X 533", /* 0x11 */
716 "100 MHz PCI-X 533", /* 0x12 */
717 "133 MHz PCI-X 533", /* 0x13 */
718 "2.5 GT/s PCIe", /* 0x14 */
719 "5.0 GT/s PCIe", /* 0x15 */
720 "8.0 GT/s PCIe", /* 0x16 */
721 "16.0 GT/s PCIe", /* 0x17 */
722 "32.0 GT/s PCIe", /* 0x18 */
723 "64.0 GT/s PCIe", /* 0x19 */
726 if (speed
< ARRAY_SIZE(speed_strings
))
727 return speed_strings
[speed
];
730 EXPORT_SYMBOL_GPL(pci_speed_string
);
732 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
734 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
736 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
738 static unsigned char agp_speeds
[] = {
746 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
752 else if (agpstat
& 2)
754 else if (agpstat
& 1)
766 return agp_speeds
[index
];
769 static void pci_set_bus_speed(struct pci_bus
*bus
)
771 struct pci_dev
*bridge
= bus
->self
;
774 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
776 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
780 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
781 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
783 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
784 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
787 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
790 enum pci_bus_speed max
;
792 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
795 if (status
& PCI_X_SSTATUS_533MHZ
) {
796 max
= PCI_SPEED_133MHz_PCIX_533
;
797 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
798 max
= PCI_SPEED_133MHz_PCIX_266
;
799 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
800 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
801 max
= PCI_SPEED_133MHz_PCIX_ECC
;
803 max
= PCI_SPEED_133MHz_PCIX
;
805 max
= PCI_SPEED_66MHz_PCIX
;
808 bus
->max_bus_speed
= max
;
809 bus
->cur_bus_speed
= pcix_bus_speed
[
810 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
815 if (pci_is_pcie(bridge
)) {
819 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
820 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
821 bridge
->link_active_reporting
= !!(linkcap
& PCI_EXP_LNKCAP_DLLLARC
);
823 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
824 pcie_update_link_speed(bus
, linksta
);
828 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
830 struct irq_domain
*d
;
833 * Any firmware interface that can resolve the msi_domain
834 * should be called from here.
836 d
= pci_host_bridge_of_msi_domain(bus
);
838 d
= pci_host_bridge_acpi_msi_domain(bus
);
840 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
842 * If no IRQ domain was found via the OF tree, try looking it up
843 * directly through the fwnode_handle.
846 struct fwnode_handle
*fwnode
= pci_root_bus_fwnode(bus
);
849 d
= irq_find_matching_fwnode(fwnode
,
857 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
859 struct irq_domain
*d
;
863 * The bus can be a root bus, a subordinate bus, or a virtual bus
864 * created by an SR-IOV device. Walk up to the first bridge device
865 * found or derive the domain from the host bridge.
867 for (b
= bus
, d
= NULL
; !d
&& !pci_is_root_bus(b
); b
= b
->parent
) {
869 d
= dev_get_msi_domain(&b
->self
->dev
);
873 d
= pci_host_bridge_msi_domain(b
);
875 dev_set_msi_domain(&bus
->dev
, d
);
878 static int res_cmp(void *priv
, const struct list_head
*a
,
879 const struct list_head
*b
)
881 struct resource_entry
*entry1
, *entry2
;
883 entry1
= container_of(a
, struct resource_entry
, node
);
884 entry2
= container_of(b
, struct resource_entry
, node
);
886 if (entry1
->res
->flags
!= entry2
->res
->flags
)
887 return entry1
->res
->flags
> entry2
->res
->flags
;
889 if (entry1
->offset
!= entry2
->offset
)
890 return entry1
->offset
> entry2
->offset
;
892 return entry1
->res
->start
> entry2
->res
->start
;
895 static int pci_register_host_bridge(struct pci_host_bridge
*bridge
)
897 struct device
*parent
= bridge
->dev
.parent
;
898 struct resource_entry
*window
, *next
, *n
;
899 struct pci_bus
*bus
, *b
;
900 resource_size_t offset
, next_offset
;
901 LIST_HEAD(resources
);
902 struct resource
*res
, *next_res
;
907 bus
= pci_alloc_bus(NULL
);
913 /* Temporarily move resources off the list */
914 list_splice_init(&bridge
->windows
, &resources
);
915 bus
->sysdata
= bridge
->sysdata
;
916 bus
->ops
= bridge
->ops
;
917 bus
->number
= bus
->busn_res
.start
= bridge
->busnr
;
918 #ifdef CONFIG_PCI_DOMAINS_GENERIC
919 bus
->domain_nr
= pci_bus_find_domain_nr(bus
, parent
);
922 b
= pci_find_bus(pci_domain_nr(bus
), bridge
->busnr
);
924 /* Ignore it if we already got here via a different bridge */
925 dev_dbg(&b
->dev
, "bus already known\n");
930 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(bus
),
933 err
= pcibios_root_bridge_prepare(bridge
);
937 err
= device_add(&bridge
->dev
);
939 put_device(&bridge
->dev
);
942 bus
->bridge
= get_device(&bridge
->dev
);
943 device_enable_async_suspend(bus
->bridge
);
944 pci_set_bus_of_node(bus
);
945 pci_set_bus_msi_domain(bus
);
946 if (bridge
->msi_domain
&& !dev_get_msi_domain(&bus
->dev
))
947 bus
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
950 set_dev_node(bus
->bridge
, pcibus_to_node(bus
));
952 bus
->dev
.class = &pcibus_class
;
953 bus
->dev
.parent
= bus
->bridge
;
955 dev_set_name(&bus
->dev
, "%04x:%02x", pci_domain_nr(bus
), bus
->number
);
956 name
= dev_name(&bus
->dev
);
958 err
= device_register(&bus
->dev
);
962 pcibios_add_bus(bus
);
964 if (bus
->ops
->add_bus
) {
965 err
= bus
->ops
->add_bus(bus
);
966 if (WARN_ON(err
< 0))
967 dev_err(&bus
->dev
, "failed to add bus: %d\n", err
);
970 /* Create legacy_io and legacy_mem files for this bus */
971 pci_create_legacy_files(bus
);
974 dev_info(parent
, "PCI host bridge to bus %s\n", name
);
976 pr_info("PCI host bridge to bus %s\n", name
);
978 if (nr_node_ids
> 1 && pcibus_to_node(bus
) == NUMA_NO_NODE
)
979 dev_warn(&bus
->dev
, "Unknown NUMA node; performance will be reduced\n");
981 /* Sort and coalesce contiguous windows */
982 list_sort(NULL
, &resources
, res_cmp
);
983 resource_list_for_each_entry_safe(window
, n
, &resources
) {
984 if (list_is_last(&window
->node
, &resources
))
987 next
= list_next_entry(window
, node
);
988 offset
= window
->offset
;
990 next_offset
= next
->offset
;
991 next_res
= next
->res
;
993 if (res
->flags
!= next_res
->flags
|| offset
!= next_offset
)
996 if (res
->end
+ 1 == next_res
->start
) {
997 next_res
->start
= res
->start
;
998 res
->flags
= res
->start
= res
->end
= 0;
1002 /* Add initial resources to the bus */
1003 resource_list_for_each_entry_safe(window
, n
, &resources
) {
1004 offset
= window
->offset
;
1009 list_move_tail(&window
->node
, &bridge
->windows
);
1011 if (res
->flags
& IORESOURCE_BUS
)
1012 pci_bus_insert_busn_res(bus
, bus
->number
, res
->end
);
1014 pci_bus_add_resource(bus
, res
, 0);
1017 if (resource_type(res
) == IORESOURCE_IO
)
1018 fmt
= " (bus address [%#06llx-%#06llx])";
1020 fmt
= " (bus address [%#010llx-%#010llx])";
1022 snprintf(addr
, sizeof(addr
), fmt
,
1023 (unsigned long long)(res
->start
- offset
),
1024 (unsigned long long)(res
->end
- offset
));
1028 dev_info(&bus
->dev
, "root bus resource %pR%s\n", res
, addr
);
1031 down_write(&pci_bus_sem
);
1032 list_add_tail(&bus
->node
, &pci_root_buses
);
1033 up_write(&pci_bus_sem
);
1038 put_device(&bridge
->dev
);
1039 device_del(&bridge
->dev
);
1046 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev
*bridge
)
1052 * If extended config space isn't accessible on a bridge's primary
1053 * bus, we certainly can't access it on the secondary bus.
1055 if (bridge
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1059 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1060 * extended config space is accessible on the primary, it's also
1061 * accessible on the secondary.
1063 if (pci_is_pcie(bridge
) &&
1064 (pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
||
1065 pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
||
1066 pci_pcie_type(bridge
) == PCI_EXP_TYPE_DOWNSTREAM
))
1070 * For the other bridge types:
1071 * - PCI-to-PCI bridges
1072 * - PCIe-to-PCI/PCI-X forward bridges
1073 * - PCI/PCI-X-to-PCIe reverse bridges
1074 * extended config space on the secondary side is only accessible
1075 * if the bridge supports PCI-X Mode 2.
1077 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
1081 pci_read_config_dword(bridge
, pos
+ PCI_X_STATUS
, &status
);
1082 return status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
);
1085 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
1086 struct pci_dev
*bridge
, int busnr
)
1088 struct pci_bus
*child
;
1089 struct pci_host_bridge
*host
;
1093 /* Allocate a new bus and inherit stuff from the parent */
1094 child
= pci_alloc_bus(parent
);
1098 child
->parent
= parent
;
1099 child
->sysdata
= parent
->sysdata
;
1100 child
->bus_flags
= parent
->bus_flags
;
1102 host
= pci_find_host_bridge(parent
);
1103 if (host
->child_ops
)
1104 child
->ops
= host
->child_ops
;
1106 child
->ops
= parent
->ops
;
1109 * Initialize some portions of the bus device, but don't register
1110 * it now as the parent is not properly set up yet.
1112 child
->dev
.class = &pcibus_class
;
1113 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
1115 /* Set up the primary, secondary and subordinate bus numbers */
1116 child
->number
= child
->busn_res
.start
= busnr
;
1117 child
->primary
= parent
->busn_res
.start
;
1118 child
->busn_res
.end
= 0xff;
1121 child
->dev
.parent
= parent
->bridge
;
1125 child
->self
= bridge
;
1126 child
->bridge
= get_device(&bridge
->dev
);
1127 child
->dev
.parent
= child
->bridge
;
1128 pci_set_bus_of_node(child
);
1129 pci_set_bus_speed(child
);
1132 * Check whether extended config space is accessible on the child
1133 * bus. Note that we currently assume it is always accessible on
1136 if (!pci_bridge_child_ext_cfg_accessible(bridge
)) {
1137 child
->bus_flags
|= PCI_BUS_FLAGS_NO_EXTCFG
;
1138 pci_info(child
, "extended config space not accessible\n");
1141 /* Set up default resource pointers and names */
1142 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
1143 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
1144 child
->resource
[i
]->name
= child
->name
;
1146 bridge
->subordinate
= child
;
1149 pci_set_bus_msi_domain(child
);
1150 ret
= device_register(&child
->dev
);
1153 pcibios_add_bus(child
);
1155 if (child
->ops
->add_bus
) {
1156 ret
= child
->ops
->add_bus(child
);
1157 if (WARN_ON(ret
< 0))
1158 dev_err(&child
->dev
, "failed to add bus: %d\n", ret
);
1161 /* Create legacy_io and legacy_mem files for this bus */
1162 pci_create_legacy_files(child
);
1167 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
1170 struct pci_bus
*child
;
1172 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
1174 down_write(&pci_bus_sem
);
1175 list_add_tail(&child
->node
, &parent
->children
);
1176 up_write(&pci_bus_sem
);
1180 EXPORT_SYMBOL(pci_add_new_bus
);
1182 static void pci_enable_crs(struct pci_dev
*pdev
)
1186 /* Enable CRS Software Visibility if supported */
1187 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
1188 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
1189 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
1190 PCI_EXP_RTCTL_CRSSVE
);
1193 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
1194 unsigned int available_buses
);
1196 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1197 * numbers from EA capability.
1199 * @sec: updated with secondary bus number from EA
1200 * @sub: updated with subordinate bus number from EA
1202 * If @dev is a bridge with EA capability that specifies valid secondary
1203 * and subordinate bus numbers, return true with the bus numbers in @sec
1204 * and @sub. Otherwise return false.
1206 static bool pci_ea_fixed_busnrs(struct pci_dev
*dev
, u8
*sec
, u8
*sub
)
1212 if (dev
->hdr_type
!= PCI_HEADER_TYPE_BRIDGE
)
1215 /* find PCI EA capability in list */
1216 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
1220 offset
= ea
+ PCI_EA_FIRST_ENT
;
1221 pci_read_config_dword(dev
, offset
, &dw
);
1222 ea_sec
= dw
& PCI_EA_SEC_BUS_MASK
;
1223 ea_sub
= (dw
& PCI_EA_SUB_BUS_MASK
) >> PCI_EA_SUB_BUS_SHIFT
;
1224 if (ea_sec
== 0 || ea_sub
< ea_sec
)
1233 * pci_scan_bridge_extend() - Scan buses behind a bridge
1234 * @bus: Parent bus the bridge is on
1235 * @dev: Bridge itself
1236 * @max: Starting subordinate number of buses behind this bridge
1237 * @available_buses: Total number of buses available for this bridge and
1238 * the devices below. After the minimal bus space has
1239 * been allocated the remaining buses will be
1240 * distributed equally between hotplug-capable bridges.
1241 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1242 * that need to be reconfigured.
1244 * If it's a bridge, configure it and scan the bus behind it.
1245 * For CardBus bridges, we don't scan behind as the devices will
1246 * be handled by the bridge driver itself.
1248 * We need to process bridges in two passes -- first we scan those
1249 * already configured by the BIOS and after we are done with all of
1250 * them, we proceed to assigning numbers to the remaining buses in
1251 * order to avoid overlaps between old and new bus numbers.
1253 * Return: New subordinate number covering all buses behind this bridge.
1255 static int pci_scan_bridge_extend(struct pci_bus
*bus
, struct pci_dev
*dev
,
1256 int max
, unsigned int available_buses
,
1259 struct pci_bus
*child
;
1260 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
1261 u32 buses
, i
, j
= 0;
1263 u8 primary
, secondary
, subordinate
;
1266 u8 fixed_sec
, fixed_sub
;
1270 * Make sure the bridge is powered on to be able to access config
1271 * space of devices below it.
1273 pm_runtime_get_sync(&dev
->dev
);
1275 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
1276 primary
= buses
& 0xFF;
1277 secondary
= (buses
>> 8) & 0xFF;
1278 subordinate
= (buses
>> 16) & 0xFF;
1280 pci_dbg(dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1281 secondary
, subordinate
, pass
);
1283 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
1284 pci_warn(dev
, "Primary bus is hard wired to 0\n");
1285 primary
= bus
->number
;
1288 /* Check if setup is sensible at all */
1290 (primary
!= bus
->number
|| secondary
<= bus
->number
||
1291 secondary
> subordinate
)) {
1292 pci_info(dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1293 secondary
, subordinate
);
1298 * Disable Master-Abort Mode during probing to avoid reporting of
1299 * bus errors in some architectures.
1301 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
1302 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
1303 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
1305 pci_enable_crs(dev
);
1307 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
1308 !is_cardbus
&& !broken
) {
1312 * Bus already configured by firmware, process it in the
1313 * first pass and just note the configuration.
1319 * The bus might already exist for two reasons: Either we
1320 * are rescanning the bus or the bus is reachable through
1321 * more than one bridge. The second case can happen with
1322 * the i450NX chipset.
1324 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
1326 child
= pci_add_new_bus(bus
, dev
, secondary
);
1329 child
->primary
= primary
;
1330 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
1331 child
->bridge_ctl
= bctl
;
1334 cmax
= pci_scan_child_bus(child
);
1335 if (cmax
> subordinate
)
1336 pci_warn(dev
, "bridge has subordinate %02x but max busn %02x\n",
1339 /* Subordinate should equal child->busn_res.end */
1340 if (subordinate
> max
)
1345 * We need to assign a number to this bus which we always
1346 * do in the second pass.
1349 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
1352 * Temporarily disable forwarding of the
1353 * configuration cycles on all bridges in
1354 * this bus segment to avoid possible
1355 * conflicts in the second pass between two
1356 * bridges programmed with overlapping bus
1359 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
1365 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
1367 /* Read bus numbers from EA Capability (if present) */
1368 fixed_buses
= pci_ea_fixed_busnrs(dev
, &fixed_sec
, &fixed_sub
);
1370 next_busnr
= fixed_sec
;
1372 next_busnr
= max
+ 1;
1375 * Prevent assigning a bus number that already exists.
1376 * This can happen when a bridge is hot-plugged, so in this
1377 * case we only re-scan this bus.
1379 child
= pci_find_bus(pci_domain_nr(bus
), next_busnr
);
1381 child
= pci_add_new_bus(bus
, dev
, next_busnr
);
1384 pci_bus_insert_busn_res(child
, next_busnr
,
1388 if (available_buses
)
1391 buses
= (buses
& 0xff000000)
1392 | ((unsigned int)(child
->primary
) << 0)
1393 | ((unsigned int)(child
->busn_res
.start
) << 8)
1394 | ((unsigned int)(child
->busn_res
.end
) << 16);
1397 * yenta.c forces a secondary latency timer of 176.
1398 * Copy that behaviour here.
1401 buses
&= ~0xff000000;
1402 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
1405 /* We need to blast all three values with a single write */
1406 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
1409 child
->bridge_ctl
= bctl
;
1410 max
= pci_scan_child_bus_extend(child
, available_buses
);
1414 * For CardBus bridges, we leave 4 bus numbers as
1415 * cards with a PCI-to-PCI bridge can be inserted
1418 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
1419 struct pci_bus
*parent
= bus
;
1420 if (pci_find_bus(pci_domain_nr(bus
),
1423 while (parent
->parent
) {
1424 if ((!pcibios_assign_all_busses()) &&
1425 (parent
->busn_res
.end
> max
) &&
1426 (parent
->busn_res
.end
<= max
+i
)) {
1429 parent
= parent
->parent
;
1434 * Often, there are two CardBus
1435 * bridges -- try to leave one
1436 * valid bus number for each one.
1446 * Set subordinate bus number to its real value.
1447 * If fixed subordinate bus number exists from EA
1448 * capability then use it.
1452 pci_bus_update_busn_res_end(child
, max
);
1453 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
1456 sprintf(child
->name
,
1457 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1458 pci_domain_nr(bus
), child
->number
);
1460 /* Check that all devices are accessible */
1461 while (bus
->parent
) {
1462 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
1463 (child
->number
> bus
->busn_res
.end
) ||
1464 (child
->number
< bus
->number
) ||
1465 (child
->busn_res
.end
< bus
->number
)) {
1466 dev_info(&dev
->dev
, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1474 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
1476 pm_runtime_put(&dev
->dev
);
1482 * pci_scan_bridge() - Scan buses behind a bridge
1483 * @bus: Parent bus the bridge is on
1484 * @dev: Bridge itself
1485 * @max: Starting subordinate number of buses behind this bridge
1486 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1487 * that need to be reconfigured.
1489 * If it's a bridge, configure it and scan the bus behind it.
1490 * For CardBus bridges, we don't scan behind as the devices will
1491 * be handled by the bridge driver itself.
1493 * We need to process bridges in two passes -- first we scan those
1494 * already configured by the BIOS and after we are done with all of
1495 * them, we proceed to assigning numbers to the remaining buses in
1496 * order to avoid overlaps between old and new bus numbers.
1498 * Return: New subordinate number covering all buses behind this bridge.
1500 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
1502 return pci_scan_bridge_extend(bus
, dev
, max
, 0, pass
);
1504 EXPORT_SYMBOL(pci_scan_bridge
);
1507 * Read interrupt line and base address registers.
1508 * The architecture-dependent code can tweak these, of course.
1510 static void pci_read_irq(struct pci_dev
*dev
)
1514 /* VFs are not allowed to use INTx, so skip the config reads */
1515 if (dev
->is_virtfn
) {
1521 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1524 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1528 void set_pcie_port_type(struct pci_dev
*pdev
)
1533 struct pci_dev
*parent
;
1535 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1539 pdev
->pcie_cap
= pos
;
1540 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1541 pdev
->pcie_flags_reg
= reg16
;
1542 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
1543 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
1545 parent
= pci_upstream_bridge(pdev
);
1550 * Some systems do not identify their upstream/downstream ports
1551 * correctly so detect impossible configurations here and correct
1552 * the port type accordingly.
1554 type
= pci_pcie_type(pdev
);
1555 if (type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1557 * If pdev claims to be downstream port but the parent
1558 * device is also downstream port assume pdev is actually
1561 if (pcie_downstream_port(parent
)) {
1562 pci_info(pdev
, "claims to be downstream port but is acting as upstream port, correcting type\n");
1563 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1564 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_UPSTREAM
;
1566 } else if (type
== PCI_EXP_TYPE_UPSTREAM
) {
1568 * If pdev claims to be upstream port but the parent
1569 * device is also upstream port assume pdev is actually
1572 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_UPSTREAM
) {
1573 pci_info(pdev
, "claims to be upstream port but is acting as downstream port, correcting type\n");
1574 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1575 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_DOWNSTREAM
;
1580 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1584 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1585 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1586 pdev
->is_hotplug_bridge
= 1;
1589 static void set_pcie_thunderbolt(struct pci_dev
*dev
)
1594 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
1595 PCI_EXT_CAP_ID_VNDR
))) {
1596 pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
, &header
);
1598 /* Is the device part of a Thunderbolt controller? */
1599 if (dev
->vendor
== PCI_VENDOR_ID_INTEL
&&
1600 PCI_VNDR_HEADER_ID(header
) == PCI_VSEC_ID_INTEL_TBT
) {
1601 dev
->is_thunderbolt
= 1;
1607 static void set_pcie_untrusted(struct pci_dev
*dev
)
1609 struct pci_dev
*parent
;
1612 * If the upstream bridge is untrusted we treat this device
1613 * untrusted as well.
1615 parent
= pci_upstream_bridge(dev
);
1616 if (parent
&& (parent
->untrusted
|| parent
->external_facing
))
1617 dev
->untrusted
= true;
1621 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1624 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1625 * when forwarding a type1 configuration request the bridge must check that
1626 * the extended register address field is zero. The bridge is not permitted
1627 * to forward the transactions and must handle it as an Unsupported Request.
1628 * Some bridges do not follow this rule and simply drop the extended register
1629 * bits, resulting in the standard config space being aliased, every 256
1630 * bytes across the entire configuration space. Test for this condition by
1631 * comparing the first dword of each potential alias to the vendor/device ID.
1633 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1634 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1636 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1638 #ifdef CONFIG_PCI_QUIRKS
1642 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1644 for (pos
= PCI_CFG_SPACE_SIZE
;
1645 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1646 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1658 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1661 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1662 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1663 * access it. Maybe we don't have a way to generate extended config space
1664 * accesses, or the device is behind a reverse Express bridge. So we try
1665 * reading the dword at 0x100 which must either be 0 or a valid extended
1666 * capability header.
1668 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1671 int pos
= PCI_CFG_SPACE_SIZE
;
1673 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1674 return PCI_CFG_SPACE_SIZE
;
1675 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1676 return PCI_CFG_SPACE_SIZE
;
1678 return PCI_CFG_SPACE_EXP_SIZE
;
1681 int pci_cfg_space_size(struct pci_dev
*dev
)
1687 #ifdef CONFIG_PCI_IOV
1689 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1690 * implement a PCIe capability and therefore must implement extended
1691 * config space. We can skip the NO_EXTCFG test below and the
1692 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1693 * the fact that the SR-IOV capability on the PF resides in extended
1694 * config space and must be accessible and non-aliased to have enabled
1695 * support for this VF. This is a micro performance optimization for
1696 * systems supporting many VFs.
1699 return PCI_CFG_SPACE_EXP_SIZE
;
1702 if (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1703 return PCI_CFG_SPACE_SIZE
;
1705 class = dev
->class >> 8;
1706 if (class == PCI_CLASS_BRIDGE_HOST
)
1707 return pci_cfg_space_size_ext(dev
);
1709 if (pci_is_pcie(dev
))
1710 return pci_cfg_space_size_ext(dev
);
1712 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1714 return PCI_CFG_SPACE_SIZE
;
1716 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1717 if (status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
))
1718 return pci_cfg_space_size_ext(dev
);
1720 return PCI_CFG_SPACE_SIZE
;
1723 static u32
pci_class(struct pci_dev
*dev
)
1727 #ifdef CONFIG_PCI_IOV
1729 return dev
->physfn
->sriov
->class;
1731 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1735 static void pci_subsystem_ids(struct pci_dev
*dev
, u16
*vendor
, u16
*device
)
1737 #ifdef CONFIG_PCI_IOV
1738 if (dev
->is_virtfn
) {
1739 *vendor
= dev
->physfn
->sriov
->subsystem_vendor
;
1740 *device
= dev
->physfn
->sriov
->subsystem_device
;
1744 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, vendor
);
1745 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, device
);
1748 static u8
pci_hdr_type(struct pci_dev
*dev
)
1752 #ifdef CONFIG_PCI_IOV
1754 return dev
->physfn
->sriov
->hdr_type
;
1756 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
);
1760 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1763 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1766 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1767 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1769 static int pci_intx_mask_broken(struct pci_dev
*dev
)
1771 u16 orig
, toggle
, new;
1773 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
1774 toggle
= orig
^ PCI_COMMAND_INTX_DISABLE
;
1775 pci_write_config_word(dev
, PCI_COMMAND
, toggle
);
1776 pci_read_config_word(dev
, PCI_COMMAND
, &new);
1778 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
1781 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1782 * r2.3, so strictly speaking, a device is not *broken* if it's not
1783 * writable. But we'll live with the misnomer for now.
1790 static void early_dump_pci_device(struct pci_dev
*pdev
)
1795 pci_info(pdev
, "config space:\n");
1797 for (i
= 0; i
< 256; i
+= 4)
1798 pci_read_config_dword(pdev
, i
, &value
[i
/ 4]);
1800 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
, 16, 1,
1805 * pci_setup_device - Fill in class and map information of a device
1806 * @dev: the device structure to fill
1808 * Initialize the device structure with information about the device's
1809 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1810 * Called at initialisation of the PCI subsystem and by CardBus services.
1811 * Returns 0 on success and negative if unknown type of device (not normal,
1812 * bridge or CardBus).
1814 int pci_setup_device(struct pci_dev
*dev
)
1820 struct pci_bus_region region
;
1821 struct resource
*res
;
1823 hdr_type
= pci_hdr_type(dev
);
1825 dev
->sysdata
= dev
->bus
->sysdata
;
1826 dev
->dev
.parent
= dev
->bus
->bridge
;
1827 dev
->dev
.bus
= &pci_bus_type
;
1828 dev
->hdr_type
= hdr_type
& 0x7f;
1829 dev
->multifunction
= !!(hdr_type
& 0x80);
1830 dev
->error_state
= pci_channel_io_normal
;
1831 set_pcie_port_type(dev
);
1833 pci_dev_assign_slot(dev
);
1836 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1837 * set this higher, assuming the system even supports it.
1839 dev
->dma_mask
= 0xffffffff;
1841 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1842 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1843 PCI_FUNC(dev
->devfn
));
1845 class = pci_class(dev
);
1847 dev
->revision
= class & 0xff;
1848 dev
->class = class >> 8; /* upper 3 bytes */
1851 early_dump_pci_device(dev
);
1853 /* Need to have dev->class ready */
1854 dev
->cfg_size
= pci_cfg_space_size(dev
);
1856 /* Need to have dev->cfg_size ready */
1857 set_pcie_thunderbolt(dev
);
1859 set_pcie_untrusted(dev
);
1861 /* "Unknown power state" */
1862 dev
->current_state
= PCI_UNKNOWN
;
1864 /* Early fixups, before probing the BARs */
1865 pci_fixup_device(pci_fixup_early
, dev
);
1867 pci_info(dev
, "[%04x:%04x] type %02x class %#08x\n",
1868 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1870 /* Device class may be changed after fixup */
1871 class = dev
->class >> 8;
1873 if (dev
->non_compliant_bars
&& !dev
->mmio_always_on
) {
1874 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1875 if (cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) {
1876 pci_info(dev
, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1877 cmd
&= ~PCI_COMMAND_IO
;
1878 cmd
&= ~PCI_COMMAND_MEMORY
;
1879 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1883 dev
->broken_intx_masking
= pci_intx_mask_broken(dev
);
1885 switch (dev
->hdr_type
) { /* header type */
1886 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1887 if (class == PCI_CLASS_BRIDGE_PCI
)
1890 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1892 pci_subsystem_ids(dev
, &dev
->subsystem_vendor
, &dev
->subsystem_device
);
1895 * Do the ugly legacy mode stuff here rather than broken chip
1896 * quirk code. Legacy mode ATA controllers have fixed
1897 * addresses. These are not always echoed in BAR0-3, and
1898 * BAR0-3 in a few cases contain junk!
1900 if (class == PCI_CLASS_STORAGE_IDE
) {
1902 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1903 if ((progif
& 1) == 0) {
1904 region
.start
= 0x1F0;
1906 res
= &dev
->resource
[0];
1907 res
->flags
= LEGACY_IO_RESOURCE
;
1908 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1909 pci_info(dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1911 region
.start
= 0x3F6;
1913 res
= &dev
->resource
[1];
1914 res
->flags
= LEGACY_IO_RESOURCE
;
1915 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1916 pci_info(dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1919 if ((progif
& 4) == 0) {
1920 region
.start
= 0x170;
1922 res
= &dev
->resource
[2];
1923 res
->flags
= LEGACY_IO_RESOURCE
;
1924 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1925 pci_info(dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1927 region
.start
= 0x376;
1929 res
= &dev
->resource
[3];
1930 res
->flags
= LEGACY_IO_RESOURCE
;
1931 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1932 pci_info(dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1938 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1940 * The PCI-to-PCI bridge spec requires that subtractive
1941 * decoding (i.e. transparent) bridge must have programming
1942 * interface code of 0x01.
1945 dev
->transparent
= ((dev
->class & 0xff) == 1);
1946 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1947 pci_read_bridge_windows(dev
);
1948 set_pcie_hotplug_bridge(dev
);
1949 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1951 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1952 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1956 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1957 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1960 pci_read_bases(dev
, 1, 0);
1961 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1962 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1965 default: /* unknown header */
1966 pci_err(dev
, "unknown header type %02x, ignoring device\n",
1971 pci_err(dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1972 dev
->class, dev
->hdr_type
);
1973 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
1976 /* We found a fine healthy device, go go go... */
1980 static void pci_configure_mps(struct pci_dev
*dev
)
1982 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
1983 int mps
, mpss
, p_mps
, rc
;
1985 if (!pci_is_pcie(dev
))
1988 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1993 * For Root Complex Integrated Endpoints, program the maximum
1994 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1996 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_RC_END
) {
1997 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2000 mps
= 128 << dev
->pcie_mpss
;
2001 rc
= pcie_set_mps(dev
, mps
);
2003 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2009 if (!bridge
|| !pci_is_pcie(bridge
))
2012 mps
= pcie_get_mps(dev
);
2013 p_mps
= pcie_get_mps(bridge
);
2018 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
2019 pci_warn(dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2020 mps
, pci_name(bridge
), p_mps
);
2025 * Fancier MPS configuration is done later by
2026 * pcie_bus_configure_settings()
2028 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
2031 mpss
= 128 << dev
->pcie_mpss
;
2032 if (mpss
< p_mps
&& pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
) {
2033 pcie_set_mps(bridge
, mpss
);
2034 pci_info(dev
, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2035 mpss
, p_mps
, 128 << bridge
->pcie_mpss
);
2036 p_mps
= pcie_get_mps(bridge
);
2039 rc
= pcie_set_mps(dev
, p_mps
);
2041 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2046 pci_info(dev
, "Max Payload Size set to %d (was %d, max %d)\n",
2050 int pci_configure_extended_tags(struct pci_dev
*dev
, void *ign
)
2052 struct pci_host_bridge
*host
;
2057 if (!pci_is_pcie(dev
))
2060 ret
= pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
2064 if (!(cap
& PCI_EXP_DEVCAP_EXT_TAG
))
2067 ret
= pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
2071 host
= pci_find_host_bridge(dev
->bus
);
2076 * If some device in the hierarchy doesn't handle Extended Tags
2077 * correctly, make sure they're disabled.
2079 if (host
->no_ext_tags
) {
2080 if (ctl
& PCI_EXP_DEVCTL_EXT_TAG
) {
2081 pci_info(dev
, "disabling Extended Tags\n");
2082 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2083 PCI_EXP_DEVCTL_EXT_TAG
);
2088 if (!(ctl
& PCI_EXP_DEVCTL_EXT_TAG
)) {
2089 pci_info(dev
, "enabling Extended Tags\n");
2090 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
,
2091 PCI_EXP_DEVCTL_EXT_TAG
);
2097 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2098 * @dev: PCI device to query
2100 * Returns true if the device has enabled relaxed ordering attribute.
2102 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
)
2106 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &v
);
2108 return !!(v
& PCI_EXP_DEVCTL_RELAX_EN
);
2110 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled
);
2112 static void pci_configure_relaxed_ordering(struct pci_dev
*dev
)
2114 struct pci_dev
*root
;
2116 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2120 if (!pcie_relaxed_ordering_enabled(dev
))
2124 * For now, we only deal with Relaxed Ordering issues with Root
2125 * Ports. Peer-to-Peer DMA is another can of worms.
2127 root
= pcie_find_root_port(dev
);
2131 if (root
->dev_flags
& PCI_DEV_FLAGS_NO_RELAXED_ORDERING
) {
2132 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2133 PCI_EXP_DEVCTL_RELAX_EN
);
2134 pci_info(dev
, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2138 static void pci_configure_ltr(struct pci_dev
*dev
)
2140 #ifdef CONFIG_PCIEASPM
2141 struct pci_host_bridge
*host
= pci_find_host_bridge(dev
->bus
);
2142 struct pci_dev
*bridge
;
2145 if (!pci_is_pcie(dev
))
2148 /* Read L1 PM substate capabilities */
2149 dev
->l1ss
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_L1SS
);
2151 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2152 if (!(cap
& PCI_EXP_DEVCAP2_LTR
))
2155 pcie_capability_read_dword(dev
, PCI_EXP_DEVCTL2
, &ctl
);
2156 if (ctl
& PCI_EXP_DEVCTL2_LTR_EN
) {
2157 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
) {
2162 bridge
= pci_upstream_bridge(dev
);
2163 if (bridge
&& bridge
->ltr_path
)
2169 if (!host
->native_ltr
)
2173 * Software must not enable LTR in an Endpoint unless the Root
2174 * Complex and all intermediate Switches indicate support for LTR.
2175 * PCIe r4.0, sec 6.18.
2177 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2178 ((bridge
= pci_upstream_bridge(dev
)) &&
2179 bridge
->ltr_path
)) {
2180 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
2181 PCI_EXP_DEVCTL2_LTR_EN
);
2187 static void pci_configure_eetlp_prefix(struct pci_dev
*dev
)
2189 #ifdef CONFIG_PCI_PASID
2190 struct pci_dev
*bridge
;
2194 if (!pci_is_pcie(dev
))
2197 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2198 if (!(cap
& PCI_EXP_DEVCAP2_EE_PREFIX
))
2201 pcie_type
= pci_pcie_type(dev
);
2202 if (pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
2203 pcie_type
== PCI_EXP_TYPE_RC_END
)
2204 dev
->eetlp_prefix_path
= 1;
2206 bridge
= pci_upstream_bridge(dev
);
2207 if (bridge
&& bridge
->eetlp_prefix_path
)
2208 dev
->eetlp_prefix_path
= 1;
2213 static void pci_configure_serr(struct pci_dev
*dev
)
2217 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
2220 * A bridge will not forward ERR_ messages coming from an
2221 * endpoint unless SERR# forwarding is enabled.
2223 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &control
);
2224 if (!(control
& PCI_BRIDGE_CTL_SERR
)) {
2225 control
|= PCI_BRIDGE_CTL_SERR
;
2226 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, control
);
2231 static void pci_configure_device(struct pci_dev
*dev
)
2233 pci_configure_mps(dev
);
2234 pci_configure_extended_tags(dev
, NULL
);
2235 pci_configure_relaxed_ordering(dev
);
2236 pci_configure_ltr(dev
);
2237 pci_configure_eetlp_prefix(dev
);
2238 pci_configure_serr(dev
);
2240 pci_acpi_program_hp_params(dev
);
2243 static void pci_release_capabilities(struct pci_dev
*dev
)
2247 pci_vpd_release(dev
);
2248 pci_iov_release(dev
);
2249 pci_free_cap_save_buffers(dev
);
2253 * pci_release_dev - Free a PCI device structure when all users of it are
2255 * @dev: device that's been disconnected
2257 * Will be called only by the device core when all users of this PCI device are
2260 static void pci_release_dev(struct device
*dev
)
2262 struct pci_dev
*pci_dev
;
2264 pci_dev
= to_pci_dev(dev
);
2265 pci_release_capabilities(pci_dev
);
2266 pci_release_of_node(pci_dev
);
2267 pcibios_release_device(pci_dev
);
2268 pci_bus_put(pci_dev
->bus
);
2269 kfree(pci_dev
->driver_override
);
2270 bitmap_free(pci_dev
->dma_alias_mask
);
2271 dev_dbg(dev
, "device released\n");
2275 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
2277 struct pci_dev
*dev
;
2279 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
2283 INIT_LIST_HEAD(&dev
->bus_list
);
2284 dev
->dev
.type
= &pci_dev_type
;
2285 dev
->bus
= pci_bus_get(bus
);
2289 EXPORT_SYMBOL(pci_alloc_dev
);
2291 static bool pci_bus_crs_vendor_id(u32 l
)
2293 return (l
& 0xffff) == 0x0001;
2296 static bool pci_bus_wait_crs(struct pci_bus
*bus
, int devfn
, u32
*l
,
2301 if (!pci_bus_crs_vendor_id(*l
))
2302 return true; /* not a CRS completion */
2305 return false; /* CRS, but caller doesn't want to wait */
2308 * We got the reserved Vendor ID that indicates a completion with
2309 * Configuration Request Retry Status (CRS). Retry until we get a
2310 * valid Vendor ID or we time out.
2312 while (pci_bus_crs_vendor_id(*l
)) {
2313 if (delay
> timeout
) {
2314 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2315 pci_domain_nr(bus
), bus
->number
,
2316 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2321 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2322 pci_domain_nr(bus
), bus
->number
,
2323 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2328 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2333 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2334 pci_domain_nr(bus
), bus
->number
,
2335 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2340 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2343 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2346 /* Some broken boards return 0 or ~0 if a slot is empty: */
2347 if (*l
== 0xffffffff || *l
== 0x00000000 ||
2348 *l
== 0x0000ffff || *l
== 0xffff0000)
2351 if (pci_bus_crs_vendor_id(*l
))
2352 return pci_bus_wait_crs(bus
, devfn
, l
, timeout
);
2357 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2360 #ifdef CONFIG_PCI_QUIRKS
2361 struct pci_dev
*bridge
= bus
->self
;
2364 * Certain IDT switches have an issue where they improperly trigger
2365 * ACS Source Validation errors on completions for config reads.
2367 if (bridge
&& bridge
->vendor
== PCI_VENDOR_ID_IDT
&&
2368 bridge
->device
== 0x80b5)
2369 return pci_idt_bus_quirk(bus
, devfn
, l
, timeout
);
2372 return pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
2374 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
2377 * Read the config data for a PCI device, sanity-check it,
2378 * and fill in the dev structure.
2380 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
2382 struct pci_dev
*dev
;
2385 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
2388 dev
= pci_alloc_dev(bus
);
2393 dev
->vendor
= l
& 0xffff;
2394 dev
->device
= (l
>> 16) & 0xffff;
2396 pci_set_of_node(dev
);
2398 if (pci_setup_device(dev
)) {
2399 pci_release_of_node(dev
);
2400 pci_bus_put(dev
->bus
);
2408 void pcie_report_downtraining(struct pci_dev
*dev
)
2410 if (!pci_is_pcie(dev
))
2413 /* Look from the device up to avoid downstream ports with no devices */
2414 if ((pci_pcie_type(dev
) != PCI_EXP_TYPE_ENDPOINT
) &&
2415 (pci_pcie_type(dev
) != PCI_EXP_TYPE_LEG_END
) &&
2416 (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
))
2419 /* Multi-function PCIe devices share the same link/status */
2420 if (PCI_FUNC(dev
->devfn
) != 0 || dev
->is_virtfn
)
2423 /* Print link status only if the device is constrained by the fabric */
2424 __pcie_print_link_status(dev
, false);
2427 static void pci_init_capabilities(struct pci_dev
*dev
)
2429 pci_ea_init(dev
); /* Enhanced Allocation */
2430 pci_msi_init(dev
); /* Disable MSI */
2431 pci_msix_init(dev
); /* Disable MSI-X */
2433 /* Buffers for saving PCIe and PCI-X capabilities */
2434 pci_allocate_cap_save_buffers(dev
);
2436 pci_pm_init(dev
); /* Power Management */
2437 pci_vpd_init(dev
); /* Vital Product Data */
2438 pci_configure_ari(dev
); /* Alternative Routing-ID Forwarding */
2439 pci_iov_init(dev
); /* Single Root I/O Virtualization */
2440 pci_ats_init(dev
); /* Address Translation Services */
2441 pci_pri_init(dev
); /* Page Request Interface */
2442 pci_pasid_init(dev
); /* Process Address Space ID */
2443 pci_acs_init(dev
); /* Access Control Services */
2444 pci_ptm_init(dev
); /* Precision Time Measurement */
2445 pci_aer_init(dev
); /* Advanced Error Reporting */
2446 pci_dpc_init(dev
); /* Downstream Port Containment */
2447 pci_rcec_init(dev
); /* Root Complex Event Collector */
2449 pcie_report_downtraining(dev
);
2451 if (pci_probe_reset_function(dev
) == 0)
2456 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2457 * devices. Firmware interfaces that can select the MSI domain on a
2458 * per-device basis should be called from here.
2460 static struct irq_domain
*pci_dev_msi_domain(struct pci_dev
*dev
)
2462 struct irq_domain
*d
;
2465 * If a domain has been set through the pcibios_add_device()
2466 * callback, then this is the one (platform code knows best).
2468 d
= dev_get_msi_domain(&dev
->dev
);
2473 * Let's see if we have a firmware interface able to provide
2476 d
= pci_msi_get_device_domain(dev
);
2483 static void pci_set_msi_domain(struct pci_dev
*dev
)
2485 struct irq_domain
*d
;
2488 * If the platform or firmware interfaces cannot supply a
2489 * device-specific MSI domain, then inherit the default domain
2490 * from the host bridge itself.
2492 d
= pci_dev_msi_domain(dev
);
2494 d
= dev_get_msi_domain(&dev
->bus
->dev
);
2496 dev_set_msi_domain(&dev
->dev
, d
);
2499 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
2503 pci_configure_device(dev
);
2505 device_initialize(&dev
->dev
);
2506 dev
->dev
.release
= pci_release_dev
;
2508 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
2509 dev
->dev
.dma_mask
= &dev
->dma_mask
;
2510 dev
->dev
.dma_parms
= &dev
->dma_parms
;
2511 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
2513 dma_set_max_seg_size(&dev
->dev
, 65536);
2514 dma_set_seg_boundary(&dev
->dev
, 0xffffffff);
2516 /* Fix up broken headers */
2517 pci_fixup_device(pci_fixup_header
, dev
);
2519 pci_reassigndev_resource_alignment(dev
);
2521 dev
->state_saved
= false;
2523 pci_init_capabilities(dev
);
2526 * Add the device to our list of discovered devices
2527 * and the bus list for fixup functions, etc.
2529 down_write(&pci_bus_sem
);
2530 list_add_tail(&dev
->bus_list
, &bus
->devices
);
2531 up_write(&pci_bus_sem
);
2533 ret
= pcibios_add_device(dev
);
2536 /* Set up MSI IRQ domain */
2537 pci_set_msi_domain(dev
);
2539 /* Notifier could use PCI capabilities */
2540 dev
->match_driver
= false;
2541 ret
= device_add(&dev
->dev
);
2545 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
2547 struct pci_dev
*dev
;
2549 dev
= pci_get_slot(bus
, devfn
);
2555 dev
= pci_scan_device(bus
, devfn
);
2559 pci_device_add(dev
, bus
);
2563 EXPORT_SYMBOL(pci_scan_single_device
);
2565 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
2571 if (pci_ari_enabled(bus
)) {
2574 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
2578 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
2579 next_fn
= PCI_ARI_CAP_NFN(cap
);
2581 return 0; /* protect against malformed list */
2586 /* dev may be NULL for non-contiguous multifunction devices */
2587 if (!dev
|| dev
->multifunction
)
2588 return (fn
+ 1) % 8;
2593 static int only_one_child(struct pci_bus
*bus
)
2595 struct pci_dev
*bridge
= bus
->self
;
2598 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2599 * we scan for all possible devices, not just Device 0.
2601 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
2605 * A PCIe Downstream Port normally leads to a Link with only Device
2606 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2607 * only for Device 0 in that situation.
2609 if (bridge
&& pci_is_pcie(bridge
) && pcie_downstream_port(bridge
))
2616 * pci_scan_slot - Scan a PCI slot on a bus for devices
2617 * @bus: PCI bus to scan
2618 * @devfn: slot number to scan (must have zero function)
2620 * Scan a PCI slot on the specified PCI bus for devices, adding
2621 * discovered devices to the @bus->devices list. New devices
2622 * will not have is_added set.
2624 * Returns the number of new devices found.
2626 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
2628 unsigned fn
, nr
= 0;
2629 struct pci_dev
*dev
;
2631 if (only_one_child(bus
) && (devfn
> 0))
2632 return 0; /* Already scanned the entire slot */
2634 dev
= pci_scan_single_device(bus
, devfn
);
2637 if (!pci_dev_is_added(dev
))
2640 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
2641 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2643 if (!pci_dev_is_added(dev
))
2645 dev
->multifunction
= 1;
2649 /* Only one slot has PCIe device */
2650 if (bus
->self
&& nr
)
2651 pcie_aspm_init_link_state(bus
->self
);
2655 EXPORT_SYMBOL(pci_scan_slot
);
2657 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
2661 if (!pci_is_pcie(dev
))
2665 * We don't have a way to change MPS settings on devices that have
2666 * drivers attached. A hot-added device might support only the minimum
2667 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2668 * where devices may be hot-added, we limit the fabric MPS to 128 so
2669 * hot-added devices will work correctly.
2671 * However, if we hot-add a device to a slot directly below a Root
2672 * Port, it's impossible for there to be other existing devices below
2673 * the port. We don't limit the MPS in this case because we can
2674 * reconfigure MPS on both the Root Port and the hot-added device,
2675 * and there are no other devices involved.
2677 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2679 if (dev
->is_hotplug_bridge
&&
2680 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
2683 if (*smpss
> dev
->pcie_mpss
)
2684 *smpss
= dev
->pcie_mpss
;
2689 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
2693 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
2694 mps
= 128 << dev
->pcie_mpss
;
2696 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
2700 * For "Performance", the assumption is made that
2701 * downstream communication will never be larger than
2702 * the MRRS. So, the MPS only needs to be configured
2703 * for the upstream communication. This being the case,
2704 * walk from the top down and set the MPS of the child
2705 * to that of the parent bus.
2707 * Configure the device MPS with the smaller of the
2708 * device MPSS or the bridge MPS (which is assumed to be
2709 * properly configured at this point to the largest
2710 * allowable MPS based on its parent bus).
2712 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
2715 rc
= pcie_set_mps(dev
, mps
);
2717 pci_err(dev
, "Failed attempting to set the MPS\n");
2720 static void pcie_write_mrrs(struct pci_dev
*dev
)
2725 * In the "safe" case, do not configure the MRRS. There appear to be
2726 * issues with setting MRRS to 0 on a number of devices.
2728 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
2732 * For max performance, the MRRS must be set to the largest supported
2733 * value. However, it cannot be configured larger than the MPS the
2734 * device or the bus can support. This should already be properly
2735 * configured by a prior call to pcie_write_mps().
2737 mrrs
= pcie_get_mps(dev
);
2740 * MRRS is a R/W register. Invalid values can be written, but a
2741 * subsequent read will verify if the value is acceptable or not.
2742 * If the MRRS value provided is not acceptable (e.g., too large),
2743 * shrink the value until it is acceptable to the HW.
2745 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
2746 rc
= pcie_set_readrq(dev
, mrrs
);
2750 pci_warn(dev
, "Failed attempting to set the MRRS\n");
2755 pci_err(dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2758 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
2762 if (!pci_is_pcie(dev
))
2765 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
2766 pcie_bus_config
== PCIE_BUS_DEFAULT
)
2769 mps
= 128 << *(u8
*)data
;
2770 orig_mps
= pcie_get_mps(dev
);
2772 pcie_write_mps(dev
, mps
);
2773 pcie_write_mrrs(dev
);
2775 pci_info(dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2776 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
2777 orig_mps
, pcie_get_readrq(dev
));
2783 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2784 * parents then children fashion. If this changes, then this code will not
2787 void pcie_bus_configure_settings(struct pci_bus
*bus
)
2794 if (!pci_is_pcie(bus
->self
))
2798 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2799 * to be aware of the MPS of the destination. To work around this,
2800 * simply force the MPS of the entire system to the smallest possible.
2802 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2805 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
2806 smpss
= bus
->self
->pcie_mpss
;
2808 pcie_find_smpss(bus
->self
, &smpss
);
2809 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
2812 pcie_bus_configure_set(bus
->self
, &smpss
);
2813 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
2815 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
2818 * Called after each bus is probed, but before its children are examined. This
2819 * is marked as __weak because multiple architectures define it.
2821 void __weak
pcibios_fixup_bus(struct pci_bus
*bus
)
2823 /* nothing to do, expected to be removed in the future */
2827 * pci_scan_child_bus_extend() - Scan devices below a bus
2828 * @bus: Bus to scan for devices
2829 * @available_buses: Total number of buses available (%0 does not try to
2830 * extend beyond the minimal)
2832 * Scans devices below @bus including subordinate buses. Returns new
2833 * subordinate number including all the found devices. Passing
2834 * @available_buses causes the remaining bus space to be distributed
2835 * equally between hotplug-capable bridges to allow future extension of the
2838 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
2839 unsigned int available_buses
)
2841 unsigned int used_buses
, normal_bridges
= 0, hotplug_bridges
= 0;
2842 unsigned int start
= bus
->busn_res
.start
;
2843 unsigned int devfn
, fn
, cmax
, max
= start
;
2844 struct pci_dev
*dev
;
2847 dev_dbg(&bus
->dev
, "scanning bus\n");
2849 /* Go find them, Rover! */
2850 for (devfn
= 0; devfn
< 256; devfn
+= 8) {
2851 nr_devs
= pci_scan_slot(bus
, devfn
);
2854 * The Jailhouse hypervisor may pass individual functions of a
2855 * multi-function device to a guest without passing function 0.
2856 * Look for them as well.
2858 if (jailhouse_paravirt() && nr_devs
== 0) {
2859 for (fn
= 1; fn
< 8; fn
++) {
2860 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2862 dev
->multifunction
= 1;
2867 /* Reserve buses for SR-IOV capability */
2868 used_buses
= pci_iov_bus_range(bus
);
2872 * After performing arch-dependent fixup of the bus, look behind
2873 * all PCI-to-PCI bridges on this bus.
2875 if (!bus
->is_added
) {
2876 dev_dbg(&bus
->dev
, "fixups for bus\n");
2877 pcibios_fixup_bus(bus
);
2882 * Calculate how many hotplug bridges and normal bridges there
2883 * are on this bus. We will distribute the additional available
2884 * buses between hotplug bridges.
2886 for_each_pci_bridge(dev
, bus
) {
2887 if (dev
->is_hotplug_bridge
)
2894 * Scan bridges that are already configured. We don't touch them
2895 * unless they are misconfigured (which will be done in the second
2898 for_each_pci_bridge(dev
, bus
) {
2900 max
= pci_scan_bridge_extend(bus
, dev
, max
, 0, 0);
2903 * Reserve one bus for each bridge now to avoid extending
2904 * hotplug bridges too much during the second scan below.
2908 used_buses
+= cmax
- max
- 1;
2911 /* Scan bridges that need to be reconfigured */
2912 for_each_pci_bridge(dev
, bus
) {
2913 unsigned int buses
= 0;
2915 if (!hotplug_bridges
&& normal_bridges
== 1) {
2918 * There is only one bridge on the bus (upstream
2919 * port) so it gets all available buses which it
2920 * can then distribute to the possible hotplug
2923 buses
= available_buses
;
2924 } else if (dev
->is_hotplug_bridge
) {
2927 * Distribute the extra buses between hotplug
2930 buses
= available_buses
/ hotplug_bridges
;
2931 buses
= min(buses
, available_buses
- used_buses
+ 1);
2935 max
= pci_scan_bridge_extend(bus
, dev
, cmax
, buses
, 1);
2936 /* One bus is already accounted so don't add it again */
2938 used_buses
+= max
- cmax
- 1;
2942 * Make sure a hotplug bridge has at least the minimum requested
2943 * number of buses but allow it to grow up to the maximum available
2944 * bus number of there is room.
2946 if (bus
->self
&& bus
->self
->is_hotplug_bridge
) {
2947 used_buses
= max_t(unsigned int, available_buses
,
2948 pci_hotplug_bus_size
- 1);
2949 if (max
- start
< used_buses
) {
2950 max
= start
+ used_buses
;
2952 /* Do not allocate more buses than we have room left */
2953 if (max
> bus
->busn_res
.end
)
2954 max
= bus
->busn_res
.end
;
2956 dev_dbg(&bus
->dev
, "%pR extended by %#02x\n",
2957 &bus
->busn_res
, max
- start
);
2962 * We've scanned the bus and so we know all about what's on
2963 * the other side of any bridges that may be on this bus plus
2966 * Return how far we've got finding sub-buses.
2968 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
2973 * pci_scan_child_bus() - Scan devices below a bus
2974 * @bus: Bus to scan for devices
2976 * Scans devices below @bus including subordinate buses. Returns new
2977 * subordinate number including all the found devices.
2979 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
2981 return pci_scan_child_bus_extend(bus
, 0);
2983 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
2986 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2987 * @bridge: Host bridge to set up
2989 * Default empty implementation. Replace with an architecture-specific setup
2990 * routine, if necessary.
2992 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
2997 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
3001 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
3005 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
3006 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
3009 struct pci_host_bridge
*bridge
;
3011 bridge
= pci_alloc_host_bridge(0);
3015 bridge
->dev
.parent
= parent
;
3017 list_splice_init(resources
, &bridge
->windows
);
3018 bridge
->sysdata
= sysdata
;
3019 bridge
->busnr
= bus
;
3022 error
= pci_register_host_bridge(bridge
);
3029 put_device(&bridge
->dev
);
3032 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
3034 int pci_host_probe(struct pci_host_bridge
*bridge
)
3036 struct pci_bus
*bus
, *child
;
3039 ret
= pci_scan_root_bus_bridge(bridge
);
3041 dev_err(bridge
->dev
.parent
, "Scanning root bridge failed");
3048 * We insert PCI resources into the iomem_resource and
3049 * ioport_resource trees in either pci_bus_claim_resources()
3050 * or pci_bus_assign_resources().
3052 if (pci_has_flag(PCI_PROBE_ONLY
)) {
3053 pci_bus_claim_resources(bus
);
3055 pci_bus_size_bridges(bus
);
3056 pci_bus_assign_resources(bus
);
3058 list_for_each_entry(child
, &bus
->children
, node
)
3059 pcie_bus_configure_settings(child
);
3062 pci_bus_add_devices(bus
);
3065 EXPORT_SYMBOL_GPL(pci_host_probe
);
3067 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
3069 struct resource
*res
= &b
->busn_res
;
3070 struct resource
*parent_res
, *conflict
;
3074 res
->flags
= IORESOURCE_BUS
;
3076 if (!pci_is_root_bus(b
))
3077 parent_res
= &b
->parent
->busn_res
;
3079 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
3080 res
->flags
|= IORESOURCE_PCI_FIXED
;
3083 conflict
= request_resource_conflict(parent_res
, res
);
3087 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3088 res
, pci_is_root_bus(b
) ? "domain " : "",
3089 parent_res
, conflict
->name
, conflict
);
3091 return conflict
== NULL
;
3094 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
3096 struct resource
*res
= &b
->busn_res
;
3097 struct resource old_res
= *res
;
3098 resource_size_t size
;
3101 if (res
->start
> bus_max
)
3104 size
= bus_max
- res
->start
+ 1;
3105 ret
= adjust_resource(res
, res
->start
, size
);
3106 dev_info(&b
->dev
, "busn_res: %pR end %s updated to %02x\n",
3107 &old_res
, ret
? "can not be" : "is", bus_max
);
3109 if (!ret
&& !res
->parent
)
3110 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
3115 void pci_bus_release_busn_res(struct pci_bus
*b
)
3117 struct resource
*res
= &b
->busn_res
;
3120 if (!res
->flags
|| !res
->parent
)
3123 ret
= release_resource(res
);
3124 dev_info(&b
->dev
, "busn_res: %pR %s released\n",
3125 res
, ret
? "can not be" : "is");
3128 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
)
3130 struct resource_entry
*window
;
3138 resource_list_for_each_entry(window
, &bridge
->windows
)
3139 if (window
->res
->flags
& IORESOURCE_BUS
) {
3140 bridge
->busnr
= window
->res
->start
;
3145 ret
= pci_register_host_bridge(bridge
);
3150 bus
= bridge
->busnr
;
3154 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3156 pci_bus_insert_busn_res(b
, bus
, 255);
3159 max
= pci_scan_child_bus(b
);
3162 pci_bus_update_busn_res_end(b
, max
);
3166 EXPORT_SYMBOL(pci_scan_root_bus_bridge
);
3168 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
3169 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
3171 struct resource_entry
*window
;
3176 resource_list_for_each_entry(window
, resources
)
3177 if (window
->res
->flags
& IORESOURCE_BUS
) {
3182 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
3188 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3190 pci_bus_insert_busn_res(b
, bus
, 255);
3193 max
= pci_scan_child_bus(b
);
3196 pci_bus_update_busn_res_end(b
, max
);
3200 EXPORT_SYMBOL(pci_scan_root_bus
);
3202 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
3205 LIST_HEAD(resources
);
3208 pci_add_resource(&resources
, &ioport_resource
);
3209 pci_add_resource(&resources
, &iomem_resource
);
3210 pci_add_resource(&resources
, &busn_resource
);
3211 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
3213 pci_scan_child_bus(b
);
3215 pci_free_resource_list(&resources
);
3219 EXPORT_SYMBOL(pci_scan_bus
);
3222 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3223 * @bridge: PCI bridge for the bus to scan
3225 * Scan a PCI bus and child buses for new devices, add them,
3226 * and enable them, resizing bridge mmio/io resource if necessary
3227 * and possible. The caller must ensure the child devices are already
3228 * removed for resizing to occur.
3230 * Returns the max number of subordinate bus discovered.
3232 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
3235 struct pci_bus
*bus
= bridge
->subordinate
;
3237 max
= pci_scan_child_bus(bus
);
3239 pci_assign_unassigned_bridge_resources(bridge
);
3241 pci_bus_add_devices(bus
);
3247 * pci_rescan_bus - Scan a PCI bus for devices
3248 * @bus: PCI bus to scan
3250 * Scan a PCI bus and child buses for new devices, add them,
3253 * Returns the max number of subordinate bus discovered.
3255 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
3259 max
= pci_scan_child_bus(bus
);
3260 pci_assign_unassigned_bus_resources(bus
);
3261 pci_bus_add_devices(bus
);
3265 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
3268 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3269 * routines should always be executed under this mutex.
3271 static DEFINE_MUTEX(pci_rescan_remove_lock
);
3273 void pci_lock_rescan_remove(void)
3275 mutex_lock(&pci_rescan_remove_lock
);
3277 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
3279 void pci_unlock_rescan_remove(void)
3281 mutex_unlock(&pci_rescan_remove_lock
);
3283 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
3285 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
3286 const struct device
*d_b
)
3288 const struct pci_dev
*a
= to_pci_dev(d_a
);
3289 const struct pci_dev
*b
= to_pci_dev(d_b
);
3291 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
3292 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
3294 if (a
->bus
->number
< b
->bus
->number
) return -1;
3295 else if (a
->bus
->number
> b
->bus
->number
) return 1;
3297 if (a
->devfn
< b
->devfn
) return -1;
3298 else if (a
->devfn
> b
->devfn
) return 1;
3303 void __init
pci_sort_breadthfirst(void)
3305 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);
3308 int pci_hp_add_bridge(struct pci_dev
*dev
)
3310 struct pci_bus
*parent
= dev
->bus
;
3311 int busnr
, start
= parent
->busn_res
.start
;
3312 unsigned int available_buses
= 0;
3313 int end
= parent
->busn_res
.end
;
3315 for (busnr
= start
; busnr
<= end
; busnr
++) {
3316 if (!pci_find_bus(pci_domain_nr(parent
), busnr
))
3319 if (busnr
-- > end
) {
3320 pci_err(dev
, "No bus number available for hot-added bridge\n");
3324 /* Scan bridges that are already configured */
3325 busnr
= pci_scan_bridge(parent
, dev
, busnr
, 0);
3328 * Distribute the available bus numbers between hotplug-capable
3329 * bridges to make extending the chain later possible.
3331 available_buses
= end
- busnr
;
3333 /* Scan bridges that need to be reconfigured */
3334 pci_scan_bridge_extend(parent
, dev
, busnr
, available_buses
, 1);
3336 if (!dev
->subordinate
)
3341 EXPORT_SYMBOL_GPL(pci_hp_add_bridge
);