1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
24 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25 #define CARDBUS_RESERVE_BUSNR 3
27 static struct resource busn_resource
= {
31 .flags
= IORESOURCE_BUS
,
34 /* Ugh. Need to stop exporting this to modules. */
35 LIST_HEAD(pci_root_buses
);
36 EXPORT_SYMBOL(pci_root_buses
);
38 static LIST_HEAD(pci_domain_busn_res_list
);
40 struct pci_domain_busn_res
{
41 struct list_head list
;
46 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
48 struct pci_domain_busn_res
*r
;
50 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
51 if (r
->domain_nr
== domain_nr
)
54 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
58 r
->domain_nr
= domain_nr
;
61 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
63 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
73 int no_pci_devices(void)
78 dev
= bus_find_next_device(&pci_bus_type
, NULL
);
79 no_devices
= (dev
== NULL
);
83 EXPORT_SYMBOL(no_pci_devices
);
88 static void release_pcibus_dev(struct device
*dev
)
90 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
92 put_device(pci_bus
->bridge
);
93 pci_bus_remove_resources(pci_bus
);
94 pci_release_bus_of_node(pci_bus
);
98 static struct class pcibus_class
= {
100 .dev_release
= &release_pcibus_dev
,
101 .dev_groups
= pcibus_groups
,
104 static int __init
pcibus_class_init(void)
106 return class_register(&pcibus_class
);
108 postcore_initcall(pcibus_class_init
);
110 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
112 u64 size
= mask
& maxbase
; /* Find the significant bits */
117 * Get the lowest of them to find the decode size, and from that
120 size
= size
& ~(size
-1);
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
126 if (base
== maxbase
&& ((base
| (size
- 1)) & mask
) != mask
)
132 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
137 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
138 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
139 flags
|= IORESOURCE_IO
;
143 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
144 flags
|= IORESOURCE_MEM
;
145 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
146 flags
|= IORESOURCE_PREFETCH
;
148 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
150 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
153 /* 1M mem BAR treated as 32-bit BAR */
155 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
156 flags
|= IORESOURCE_MEM_64
;
159 /* mem unknown type treated as 32-bit BAR */
165 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
168 * __pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
176 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
177 struct resource
*res
, unsigned int pos
)
179 u32 l
= 0, sz
= 0, mask
;
180 u64 l64
, sz64
, mask64
;
182 struct pci_bus_region region
, inverted_region
;
184 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
186 /* No printks while decoding is disabled! */
187 if (!dev
->mmio_always_on
) {
188 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
189 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
190 pci_write_config_word(dev
, PCI_COMMAND
,
191 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
195 res
->name
= pci_name(dev
);
197 pci_read_config_dword(dev
, pos
, &l
);
198 pci_write_config_dword(dev
, pos
, l
| mask
);
199 pci_read_config_dword(dev
, pos
, &sz
);
200 pci_write_config_dword(dev
, pos
, l
);
203 * All bits set in sz means the device isn't working properly.
204 * If the BAR isn't implemented, all bits must be 0. If it's a
205 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
208 if (sz
== 0xffffffff)
212 * I don't know how l can have all bits set. Copied from old code.
213 * Maybe it fixes a bug on some ancient platform.
218 if (type
== pci_bar_unknown
) {
219 res
->flags
= decode_bar(dev
, l
);
220 res
->flags
|= IORESOURCE_SIZEALIGN
;
221 if (res
->flags
& IORESOURCE_IO
) {
222 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
223 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
224 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
226 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
227 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
228 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
231 if (l
& PCI_ROM_ADDRESS_ENABLE
)
232 res
->flags
|= IORESOURCE_ROM_ENABLE
;
233 l64
= l
& PCI_ROM_ADDRESS_MASK
;
234 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
235 mask64
= PCI_ROM_ADDRESS_MASK
;
238 if (res
->flags
& IORESOURCE_MEM_64
) {
239 pci_read_config_dword(dev
, pos
+ 4, &l
);
240 pci_write_config_dword(dev
, pos
+ 4, ~0);
241 pci_read_config_dword(dev
, pos
+ 4, &sz
);
242 pci_write_config_dword(dev
, pos
+ 4, l
);
244 l64
|= ((u64
)l
<< 32);
245 sz64
|= ((u64
)sz
<< 32);
246 mask64
|= ((u64
)~0 << 32);
249 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
250 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
255 sz64
= pci_size(l64
, sz64
, mask64
);
257 pci_info(dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
262 if (res
->flags
& IORESOURCE_MEM_64
) {
263 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
264 && sz64
> 0x100000000ULL
) {
265 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
268 pci_err(dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
269 pos
, (unsigned long long)sz64
);
273 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
274 /* Above 32-bit boundary; try to reallocate */
275 res
->flags
|= IORESOURCE_UNSET
;
278 pci_info(dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
279 pos
, (unsigned long long)l64
);
285 region
.end
= l64
+ sz64
- 1;
287 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
288 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
296 * resource_to_bus(bus_to_resource(A)) == A
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
301 if (inverted_region
.start
!= region
.start
) {
302 res
->flags
|= IORESOURCE_UNSET
;
304 res
->end
= region
.end
- region
.start
;
305 pci_info(dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
306 pos
, (unsigned long long)region
.start
);
316 pci_info(dev
, "reg 0x%x: %pR\n", pos
, res
);
318 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
321 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
323 unsigned int pos
, reg
;
325 if (dev
->non_compliant_bars
)
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
332 for (pos
= 0; pos
< howmany
; pos
++) {
333 struct resource
*res
= &dev
->resource
[pos
];
334 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
335 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
339 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
340 dev
->rom_base_reg
= rom
;
341 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
342 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
343 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
347 static void pci_read_bridge_windows(struct pci_dev
*bridge
)
352 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
354 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xe0f0);
355 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
356 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
359 bridge
->io_window
= 1;
362 * DECchip 21050 pass 2 errata: the bridge may miss an address
363 * disconnect boundary by one PCI data phase. Workaround: do not
364 * use prefetching on this device.
366 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
369 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
371 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
373 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
374 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
379 bridge
->pref_window
= 1;
381 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
384 * Bridge claims to have a 64-bit prefetchable memory
385 * window; verify that the upper bits are actually
388 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &pmem
);
389 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
391 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
392 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, pmem
);
394 bridge
->pref_64_window
= 1;
398 static void pci_read_bridge_io(struct pci_bus
*child
)
400 struct pci_dev
*dev
= child
->self
;
401 u8 io_base_lo
, io_limit_lo
;
402 unsigned long io_mask
, io_granularity
, base
, limit
;
403 struct pci_bus_region region
;
404 struct resource
*res
;
406 io_mask
= PCI_IO_RANGE_MASK
;
407 io_granularity
= 0x1000;
408 if (dev
->io_window_1k
) {
409 /* Support 1K I/O space granularity */
410 io_mask
= PCI_IO_1K_RANGE_MASK
;
411 io_granularity
= 0x400;
414 res
= child
->resource
[0];
415 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
416 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
417 base
= (io_base_lo
& io_mask
) << 8;
418 limit
= (io_limit_lo
& io_mask
) << 8;
420 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
421 u16 io_base_hi
, io_limit_hi
;
423 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
424 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
425 base
|= ((unsigned long) io_base_hi
<< 16);
426 limit
|= ((unsigned long) io_limit_hi
<< 16);
430 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
432 region
.end
= limit
+ io_granularity
- 1;
433 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
434 pci_info(dev
, " bridge window %pR\n", res
);
438 static void pci_read_bridge_mmio(struct pci_bus
*child
)
440 struct pci_dev
*dev
= child
->self
;
441 u16 mem_base_lo
, mem_limit_lo
;
442 unsigned long base
, limit
;
443 struct pci_bus_region region
;
444 struct resource
*res
;
446 res
= child
->resource
[1];
447 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
448 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
449 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
450 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
452 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
454 region
.end
= limit
+ 0xfffff;
455 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
456 pci_info(dev
, " bridge window %pR\n", res
);
460 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
462 struct pci_dev
*dev
= child
->self
;
463 u16 mem_base_lo
, mem_limit_lo
;
465 pci_bus_addr_t base
, limit
;
466 struct pci_bus_region region
;
467 struct resource
*res
;
469 res
= child
->resource
[2];
470 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
471 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
472 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
473 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
475 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
476 u32 mem_base_hi
, mem_limit_hi
;
478 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
479 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
482 * Some bridges set the base > limit by default, and some
483 * (broken) BIOSes do not initialize them. If we find
484 * this, just assume they are not being used.
486 if (mem_base_hi
<= mem_limit_hi
) {
487 base64
|= (u64
) mem_base_hi
<< 32;
488 limit64
|= (u64
) mem_limit_hi
<< 32;
492 base
= (pci_bus_addr_t
) base64
;
493 limit
= (pci_bus_addr_t
) limit64
;
495 if (base
!= base64
) {
496 pci_err(dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
497 (unsigned long long) base64
);
502 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
503 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
504 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
505 res
->flags
|= IORESOURCE_MEM_64
;
507 region
.end
= limit
+ 0xfffff;
508 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
509 pci_info(dev
, " bridge window %pR\n", res
);
513 void pci_read_bridge_bases(struct pci_bus
*child
)
515 struct pci_dev
*dev
= child
->self
;
516 struct resource
*res
;
519 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
522 pci_info(dev
, "PCI bridge to %pR%s\n",
524 dev
->transparent
? " (subtractive decode)" : "");
526 pci_bus_remove_resources(child
);
527 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
528 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
530 pci_read_bridge_io(child
);
531 pci_read_bridge_mmio(child
);
532 pci_read_bridge_mmio_pref(child
);
534 if (dev
->transparent
) {
535 pci_bus_for_each_resource(child
->parent
, res
, i
) {
536 if (res
&& res
->flags
) {
537 pci_bus_add_resource(child
, res
,
538 PCI_SUBTRACTIVE_DECODE
);
539 pci_info(dev
, " bridge window %pR (subtractive decode)\n",
546 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
550 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
554 INIT_LIST_HEAD(&b
->node
);
555 INIT_LIST_HEAD(&b
->children
);
556 INIT_LIST_HEAD(&b
->devices
);
557 INIT_LIST_HEAD(&b
->slots
);
558 INIT_LIST_HEAD(&b
->resources
);
559 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
560 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
561 #ifdef CONFIG_PCI_DOMAINS_GENERIC
563 b
->domain_nr
= parent
->domain_nr
;
568 static void pci_release_host_bridge_dev(struct device
*dev
)
570 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
572 if (bridge
->release_fn
)
573 bridge
->release_fn(bridge
);
575 pci_free_resource_list(&bridge
->windows
);
576 pci_free_resource_list(&bridge
->dma_ranges
);
580 static void pci_init_host_bridge(struct pci_host_bridge
*bridge
)
582 INIT_LIST_HEAD(&bridge
->windows
);
583 INIT_LIST_HEAD(&bridge
->dma_ranges
);
586 * We assume we can manage these PCIe features. Some systems may
587 * reserve these for use by the platform itself, e.g., an ACPI BIOS
588 * may implement its own AER handling and use _OSC to prevent the
589 * OS from interfering.
591 bridge
->native_aer
= 1;
592 bridge
->native_pcie_hotplug
= 1;
593 bridge
->native_shpc_hotplug
= 1;
594 bridge
->native_pme
= 1;
595 bridge
->native_ltr
= 1;
596 bridge
->native_dpc
= 1;
598 device_initialize(&bridge
->dev
);
601 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
)
603 struct pci_host_bridge
*bridge
;
605 bridge
= kzalloc(sizeof(*bridge
) + priv
, GFP_KERNEL
);
609 pci_init_host_bridge(bridge
);
610 bridge
->dev
.release
= pci_release_host_bridge_dev
;
614 EXPORT_SYMBOL(pci_alloc_host_bridge
);
616 static void devm_pci_alloc_host_bridge_release(void *data
)
618 pci_free_host_bridge(data
);
621 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
625 struct pci_host_bridge
*bridge
;
627 bridge
= pci_alloc_host_bridge(priv
);
631 bridge
->dev
.parent
= dev
;
633 ret
= devm_add_action_or_reset(dev
, devm_pci_alloc_host_bridge_release
,
638 ret
= devm_of_pci_bridge_init(dev
, bridge
);
644 EXPORT_SYMBOL(devm_pci_alloc_host_bridge
);
646 void pci_free_host_bridge(struct pci_host_bridge
*bridge
)
648 put_device(&bridge
->dev
);
650 EXPORT_SYMBOL(pci_free_host_bridge
);
652 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
653 static const unsigned char pcix_bus_speed
[] = {
654 PCI_SPEED_UNKNOWN
, /* 0 */
655 PCI_SPEED_66MHz_PCIX
, /* 1 */
656 PCI_SPEED_100MHz_PCIX
, /* 2 */
657 PCI_SPEED_133MHz_PCIX
, /* 3 */
658 PCI_SPEED_UNKNOWN
, /* 4 */
659 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
660 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
661 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
662 PCI_SPEED_UNKNOWN
, /* 8 */
663 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
664 PCI_SPEED_100MHz_PCIX_266
, /* A */
665 PCI_SPEED_133MHz_PCIX_266
, /* B */
666 PCI_SPEED_UNKNOWN
, /* C */
667 PCI_SPEED_66MHz_PCIX_533
, /* D */
668 PCI_SPEED_100MHz_PCIX_533
, /* E */
669 PCI_SPEED_133MHz_PCIX_533
/* F */
672 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
673 const unsigned char pcie_link_speed
[] = {
674 PCI_SPEED_UNKNOWN
, /* 0 */
675 PCIE_SPEED_2_5GT
, /* 1 */
676 PCIE_SPEED_5_0GT
, /* 2 */
677 PCIE_SPEED_8_0GT
, /* 3 */
678 PCIE_SPEED_16_0GT
, /* 4 */
679 PCIE_SPEED_32_0GT
, /* 5 */
680 PCIE_SPEED_64_0GT
, /* 6 */
681 PCI_SPEED_UNKNOWN
, /* 7 */
682 PCI_SPEED_UNKNOWN
, /* 8 */
683 PCI_SPEED_UNKNOWN
, /* 9 */
684 PCI_SPEED_UNKNOWN
, /* A */
685 PCI_SPEED_UNKNOWN
, /* B */
686 PCI_SPEED_UNKNOWN
, /* C */
687 PCI_SPEED_UNKNOWN
, /* D */
688 PCI_SPEED_UNKNOWN
, /* E */
689 PCI_SPEED_UNKNOWN
/* F */
691 EXPORT_SYMBOL_GPL(pcie_link_speed
);
693 const char *pci_speed_string(enum pci_bus_speed speed
)
695 /* Indexed by the pci_bus_speed enum */
696 static const char *speed_strings
[] = {
697 "33 MHz PCI", /* 0x00 */
698 "66 MHz PCI", /* 0x01 */
699 "66 MHz PCI-X", /* 0x02 */
700 "100 MHz PCI-X", /* 0x03 */
701 "133 MHz PCI-X", /* 0x04 */
706 "66 MHz PCI-X 266", /* 0x09 */
707 "100 MHz PCI-X 266", /* 0x0a */
708 "133 MHz PCI-X 266", /* 0x0b */
709 "Unknown AGP", /* 0x0c */
714 "66 MHz PCI-X 533", /* 0x11 */
715 "100 MHz PCI-X 533", /* 0x12 */
716 "133 MHz PCI-X 533", /* 0x13 */
717 "2.5 GT/s PCIe", /* 0x14 */
718 "5.0 GT/s PCIe", /* 0x15 */
719 "8.0 GT/s PCIe", /* 0x16 */
720 "16.0 GT/s PCIe", /* 0x17 */
721 "32.0 GT/s PCIe", /* 0x18 */
722 "64.0 GT/s PCIe", /* 0x19 */
725 if (speed
< ARRAY_SIZE(speed_strings
))
726 return speed_strings
[speed
];
729 EXPORT_SYMBOL_GPL(pci_speed_string
);
731 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
733 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
735 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
737 static unsigned char agp_speeds
[] = {
745 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
751 else if (agpstat
& 2)
753 else if (agpstat
& 1)
765 return agp_speeds
[index
];
768 static void pci_set_bus_speed(struct pci_bus
*bus
)
770 struct pci_dev
*bridge
= bus
->self
;
773 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
775 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
779 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
780 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
782 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
783 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
786 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
789 enum pci_bus_speed max
;
791 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
794 if (status
& PCI_X_SSTATUS_533MHZ
) {
795 max
= PCI_SPEED_133MHz_PCIX_533
;
796 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
797 max
= PCI_SPEED_133MHz_PCIX_266
;
798 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
799 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
800 max
= PCI_SPEED_133MHz_PCIX_ECC
;
802 max
= PCI_SPEED_133MHz_PCIX
;
804 max
= PCI_SPEED_66MHz_PCIX
;
807 bus
->max_bus_speed
= max
;
808 bus
->cur_bus_speed
= pcix_bus_speed
[
809 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
814 if (pci_is_pcie(bridge
)) {
818 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
819 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
820 bridge
->link_active_reporting
= !!(linkcap
& PCI_EXP_LNKCAP_DLLLARC
);
822 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
823 pcie_update_link_speed(bus
, linksta
);
827 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
829 struct irq_domain
*d
;
832 * Any firmware interface that can resolve the msi_domain
833 * should be called from here.
835 d
= pci_host_bridge_of_msi_domain(bus
);
837 d
= pci_host_bridge_acpi_msi_domain(bus
);
839 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
841 * If no IRQ domain was found via the OF tree, try looking it up
842 * directly through the fwnode_handle.
845 struct fwnode_handle
*fwnode
= pci_root_bus_fwnode(bus
);
848 d
= irq_find_matching_fwnode(fwnode
,
856 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
858 struct irq_domain
*d
;
862 * The bus can be a root bus, a subordinate bus, or a virtual bus
863 * created by an SR-IOV device. Walk up to the first bridge device
864 * found or derive the domain from the host bridge.
866 for (b
= bus
, d
= NULL
; !d
&& !pci_is_root_bus(b
); b
= b
->parent
) {
868 d
= dev_get_msi_domain(&b
->self
->dev
);
872 d
= pci_host_bridge_msi_domain(b
);
874 dev_set_msi_domain(&bus
->dev
, d
);
877 static int pci_register_host_bridge(struct pci_host_bridge
*bridge
)
879 struct device
*parent
= bridge
->dev
.parent
;
880 struct resource_entry
*window
, *n
;
881 struct pci_bus
*bus
, *b
;
882 resource_size_t offset
;
883 LIST_HEAD(resources
);
884 struct resource
*res
;
889 bus
= pci_alloc_bus(NULL
);
895 /* Temporarily move resources off the list */
896 list_splice_init(&bridge
->windows
, &resources
);
897 bus
->sysdata
= bridge
->sysdata
;
898 bus
->ops
= bridge
->ops
;
899 bus
->number
= bus
->busn_res
.start
= bridge
->busnr
;
900 #ifdef CONFIG_PCI_DOMAINS_GENERIC
901 bus
->domain_nr
= pci_bus_find_domain_nr(bus
, parent
);
904 b
= pci_find_bus(pci_domain_nr(bus
), bridge
->busnr
);
906 /* Ignore it if we already got here via a different bridge */
907 dev_dbg(&b
->dev
, "bus already known\n");
912 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(bus
),
915 err
= pcibios_root_bridge_prepare(bridge
);
919 err
= device_add(&bridge
->dev
);
921 put_device(&bridge
->dev
);
924 bus
->bridge
= get_device(&bridge
->dev
);
925 device_enable_async_suspend(bus
->bridge
);
926 pci_set_bus_of_node(bus
);
927 pci_set_bus_msi_domain(bus
);
928 if (bridge
->msi_domain
&& !dev_get_msi_domain(&bus
->dev
) &&
929 !pci_host_of_has_msi_map(parent
))
930 bus
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
933 set_dev_node(bus
->bridge
, pcibus_to_node(bus
));
935 bus
->dev
.class = &pcibus_class
;
936 bus
->dev
.parent
= bus
->bridge
;
938 dev_set_name(&bus
->dev
, "%04x:%02x", pci_domain_nr(bus
), bus
->number
);
939 name
= dev_name(&bus
->dev
);
941 err
= device_register(&bus
->dev
);
945 pcibios_add_bus(bus
);
947 if (bus
->ops
->add_bus
) {
948 err
= bus
->ops
->add_bus(bus
);
949 if (WARN_ON(err
< 0))
950 dev_err(&bus
->dev
, "failed to add bus: %d\n", err
);
953 /* Create legacy_io and legacy_mem files for this bus */
954 pci_create_legacy_files(bus
);
957 dev_info(parent
, "PCI host bridge to bus %s\n", name
);
959 pr_info("PCI host bridge to bus %s\n", name
);
961 if (nr_node_ids
> 1 && pcibus_to_node(bus
) == NUMA_NO_NODE
)
962 dev_warn(&bus
->dev
, "Unknown NUMA node; performance will be reduced\n");
964 /* Add initial resources to the bus */
965 resource_list_for_each_entry_safe(window
, n
, &resources
) {
966 list_move_tail(&window
->node
, &bridge
->windows
);
967 offset
= window
->offset
;
970 if (res
->flags
& IORESOURCE_BUS
)
971 pci_bus_insert_busn_res(bus
, bus
->number
, res
->end
);
973 pci_bus_add_resource(bus
, res
, 0);
976 if (resource_type(res
) == IORESOURCE_IO
)
977 fmt
= " (bus address [%#06llx-%#06llx])";
979 fmt
= " (bus address [%#010llx-%#010llx])";
981 snprintf(addr
, sizeof(addr
), fmt
,
982 (unsigned long long)(res
->start
- offset
),
983 (unsigned long long)(res
->end
- offset
));
987 dev_info(&bus
->dev
, "root bus resource %pR%s\n", res
, addr
);
990 down_write(&pci_bus_sem
);
991 list_add_tail(&bus
->node
, &pci_root_buses
);
992 up_write(&pci_bus_sem
);
997 put_device(&bridge
->dev
);
998 device_del(&bridge
->dev
);
1005 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev
*bridge
)
1011 * If extended config space isn't accessible on a bridge's primary
1012 * bus, we certainly can't access it on the secondary bus.
1014 if (bridge
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1018 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1019 * extended config space is accessible on the primary, it's also
1020 * accessible on the secondary.
1022 if (pci_is_pcie(bridge
) &&
1023 (pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
||
1024 pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
||
1025 pci_pcie_type(bridge
) == PCI_EXP_TYPE_DOWNSTREAM
))
1029 * For the other bridge types:
1030 * - PCI-to-PCI bridges
1031 * - PCIe-to-PCI/PCI-X forward bridges
1032 * - PCI/PCI-X-to-PCIe reverse bridges
1033 * extended config space on the secondary side is only accessible
1034 * if the bridge supports PCI-X Mode 2.
1036 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
1040 pci_read_config_dword(bridge
, pos
+ PCI_X_STATUS
, &status
);
1041 return status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
);
1044 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
1045 struct pci_dev
*bridge
, int busnr
)
1047 struct pci_bus
*child
;
1048 struct pci_host_bridge
*host
;
1052 /* Allocate a new bus and inherit stuff from the parent */
1053 child
= pci_alloc_bus(parent
);
1057 child
->parent
= parent
;
1058 child
->sysdata
= parent
->sysdata
;
1059 child
->bus_flags
= parent
->bus_flags
;
1061 host
= pci_find_host_bridge(parent
);
1062 if (host
->child_ops
)
1063 child
->ops
= host
->child_ops
;
1065 child
->ops
= parent
->ops
;
1068 * Initialize some portions of the bus device, but don't register
1069 * it now as the parent is not properly set up yet.
1071 child
->dev
.class = &pcibus_class
;
1072 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
1074 /* Set up the primary, secondary and subordinate bus numbers */
1075 child
->number
= child
->busn_res
.start
= busnr
;
1076 child
->primary
= parent
->busn_res
.start
;
1077 child
->busn_res
.end
= 0xff;
1080 child
->dev
.parent
= parent
->bridge
;
1084 child
->self
= bridge
;
1085 child
->bridge
= get_device(&bridge
->dev
);
1086 child
->dev
.parent
= child
->bridge
;
1087 pci_set_bus_of_node(child
);
1088 pci_set_bus_speed(child
);
1091 * Check whether extended config space is accessible on the child
1092 * bus. Note that we currently assume it is always accessible on
1095 if (!pci_bridge_child_ext_cfg_accessible(bridge
)) {
1096 child
->bus_flags
|= PCI_BUS_FLAGS_NO_EXTCFG
;
1097 pci_info(child
, "extended config space not accessible\n");
1100 /* Set up default resource pointers and names */
1101 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
1102 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
1103 child
->resource
[i
]->name
= child
->name
;
1105 bridge
->subordinate
= child
;
1108 pci_set_bus_msi_domain(child
);
1109 ret
= device_register(&child
->dev
);
1112 pcibios_add_bus(child
);
1114 if (child
->ops
->add_bus
) {
1115 ret
= child
->ops
->add_bus(child
);
1116 if (WARN_ON(ret
< 0))
1117 dev_err(&child
->dev
, "failed to add bus: %d\n", ret
);
1120 /* Create legacy_io and legacy_mem files for this bus */
1121 pci_create_legacy_files(child
);
1126 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
1129 struct pci_bus
*child
;
1131 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
1133 down_write(&pci_bus_sem
);
1134 list_add_tail(&child
->node
, &parent
->children
);
1135 up_write(&pci_bus_sem
);
1139 EXPORT_SYMBOL(pci_add_new_bus
);
1141 static void pci_enable_crs(struct pci_dev
*pdev
)
1145 /* Enable CRS Software Visibility if supported */
1146 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
1147 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
1148 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
1149 PCI_EXP_RTCTL_CRSSVE
);
1152 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
1153 unsigned int available_buses
);
1155 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1156 * numbers from EA capability.
1158 * @sec: updated with secondary bus number from EA
1159 * @sub: updated with subordinate bus number from EA
1161 * If @dev is a bridge with EA capability that specifies valid secondary
1162 * and subordinate bus numbers, return true with the bus numbers in @sec
1163 * and @sub. Otherwise return false.
1165 static bool pci_ea_fixed_busnrs(struct pci_dev
*dev
, u8
*sec
, u8
*sub
)
1171 if (dev
->hdr_type
!= PCI_HEADER_TYPE_BRIDGE
)
1174 /* find PCI EA capability in list */
1175 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
1179 offset
= ea
+ PCI_EA_FIRST_ENT
;
1180 pci_read_config_dword(dev
, offset
, &dw
);
1181 ea_sec
= dw
& PCI_EA_SEC_BUS_MASK
;
1182 ea_sub
= (dw
& PCI_EA_SUB_BUS_MASK
) >> PCI_EA_SUB_BUS_SHIFT
;
1183 if (ea_sec
== 0 || ea_sub
< ea_sec
)
1192 * pci_scan_bridge_extend() - Scan buses behind a bridge
1193 * @bus: Parent bus the bridge is on
1194 * @dev: Bridge itself
1195 * @max: Starting subordinate number of buses behind this bridge
1196 * @available_buses: Total number of buses available for this bridge and
1197 * the devices below. After the minimal bus space has
1198 * been allocated the remaining buses will be
1199 * distributed equally between hotplug-capable bridges.
1200 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1201 * that need to be reconfigured.
1203 * If it's a bridge, configure it and scan the bus behind it.
1204 * For CardBus bridges, we don't scan behind as the devices will
1205 * be handled by the bridge driver itself.
1207 * We need to process bridges in two passes -- first we scan those
1208 * already configured by the BIOS and after we are done with all of
1209 * them, we proceed to assigning numbers to the remaining buses in
1210 * order to avoid overlaps between old and new bus numbers.
1212 * Return: New subordinate number covering all buses behind this bridge.
1214 static int pci_scan_bridge_extend(struct pci_bus
*bus
, struct pci_dev
*dev
,
1215 int max
, unsigned int available_buses
,
1218 struct pci_bus
*child
;
1219 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
1220 u32 buses
, i
, j
= 0;
1222 u8 primary
, secondary
, subordinate
;
1225 u8 fixed_sec
, fixed_sub
;
1229 * Make sure the bridge is powered on to be able to access config
1230 * space of devices below it.
1232 pm_runtime_get_sync(&dev
->dev
);
1234 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
1235 primary
= buses
& 0xFF;
1236 secondary
= (buses
>> 8) & 0xFF;
1237 subordinate
= (buses
>> 16) & 0xFF;
1239 pci_dbg(dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1240 secondary
, subordinate
, pass
);
1242 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
1243 pci_warn(dev
, "Primary bus is hard wired to 0\n");
1244 primary
= bus
->number
;
1247 /* Check if setup is sensible at all */
1249 (primary
!= bus
->number
|| secondary
<= bus
->number
||
1250 secondary
> subordinate
)) {
1251 pci_info(dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1252 secondary
, subordinate
);
1257 * Disable Master-Abort Mode during probing to avoid reporting of
1258 * bus errors in some architectures.
1260 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
1261 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
1262 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
1264 pci_enable_crs(dev
);
1266 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
1267 !is_cardbus
&& !broken
) {
1271 * Bus already configured by firmware, process it in the
1272 * first pass and just note the configuration.
1278 * The bus might already exist for two reasons: Either we
1279 * are rescanning the bus or the bus is reachable through
1280 * more than one bridge. The second case can happen with
1281 * the i450NX chipset.
1283 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
1285 child
= pci_add_new_bus(bus
, dev
, secondary
);
1288 child
->primary
= primary
;
1289 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
1290 child
->bridge_ctl
= bctl
;
1293 cmax
= pci_scan_child_bus(child
);
1294 if (cmax
> subordinate
)
1295 pci_warn(dev
, "bridge has subordinate %02x but max busn %02x\n",
1298 /* Subordinate should equal child->busn_res.end */
1299 if (subordinate
> max
)
1304 * We need to assign a number to this bus which we always
1305 * do in the second pass.
1308 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
1311 * Temporarily disable forwarding of the
1312 * configuration cycles on all bridges in
1313 * this bus segment to avoid possible
1314 * conflicts in the second pass between two
1315 * bridges programmed with overlapping bus
1318 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
1324 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
1326 /* Read bus numbers from EA Capability (if present) */
1327 fixed_buses
= pci_ea_fixed_busnrs(dev
, &fixed_sec
, &fixed_sub
);
1329 next_busnr
= fixed_sec
;
1331 next_busnr
= max
+ 1;
1334 * Prevent assigning a bus number that already exists.
1335 * This can happen when a bridge is hot-plugged, so in this
1336 * case we only re-scan this bus.
1338 child
= pci_find_bus(pci_domain_nr(bus
), next_busnr
);
1340 child
= pci_add_new_bus(bus
, dev
, next_busnr
);
1343 pci_bus_insert_busn_res(child
, next_busnr
,
1347 if (available_buses
)
1350 buses
= (buses
& 0xff000000)
1351 | ((unsigned int)(child
->primary
) << 0)
1352 | ((unsigned int)(child
->busn_res
.start
) << 8)
1353 | ((unsigned int)(child
->busn_res
.end
) << 16);
1356 * yenta.c forces a secondary latency timer of 176.
1357 * Copy that behaviour here.
1360 buses
&= ~0xff000000;
1361 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
1364 /* We need to blast all three values with a single write */
1365 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
1368 child
->bridge_ctl
= bctl
;
1369 max
= pci_scan_child_bus_extend(child
, available_buses
);
1373 * For CardBus bridges, we leave 4 bus numbers as
1374 * cards with a PCI-to-PCI bridge can be inserted
1377 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
1378 struct pci_bus
*parent
= bus
;
1379 if (pci_find_bus(pci_domain_nr(bus
),
1382 while (parent
->parent
) {
1383 if ((!pcibios_assign_all_busses()) &&
1384 (parent
->busn_res
.end
> max
) &&
1385 (parent
->busn_res
.end
<= max
+i
)) {
1388 parent
= parent
->parent
;
1393 * Often, there are two CardBus
1394 * bridges -- try to leave one
1395 * valid bus number for each one.
1405 * Set subordinate bus number to its real value.
1406 * If fixed subordinate bus number exists from EA
1407 * capability then use it.
1411 pci_bus_update_busn_res_end(child
, max
);
1412 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
1415 sprintf(child
->name
,
1416 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1417 pci_domain_nr(bus
), child
->number
);
1419 /* Check that all devices are accessible */
1420 while (bus
->parent
) {
1421 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
1422 (child
->number
> bus
->busn_res
.end
) ||
1423 (child
->number
< bus
->number
) ||
1424 (child
->busn_res
.end
< bus
->number
)) {
1425 dev_info(&dev
->dev
, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1433 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
1435 pm_runtime_put(&dev
->dev
);
1441 * pci_scan_bridge() - Scan buses behind a bridge
1442 * @bus: Parent bus the bridge is on
1443 * @dev: Bridge itself
1444 * @max: Starting subordinate number of buses behind this bridge
1445 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1446 * that need to be reconfigured.
1448 * If it's a bridge, configure it and scan the bus behind it.
1449 * For CardBus bridges, we don't scan behind as the devices will
1450 * be handled by the bridge driver itself.
1452 * We need to process bridges in two passes -- first we scan those
1453 * already configured by the BIOS and after we are done with all of
1454 * them, we proceed to assigning numbers to the remaining buses in
1455 * order to avoid overlaps between old and new bus numbers.
1457 * Return: New subordinate number covering all buses behind this bridge.
1459 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
1461 return pci_scan_bridge_extend(bus
, dev
, max
, 0, pass
);
1463 EXPORT_SYMBOL(pci_scan_bridge
);
1466 * Read interrupt line and base address registers.
1467 * The architecture-dependent code can tweak these, of course.
1469 static void pci_read_irq(struct pci_dev
*dev
)
1473 /* VFs are not allowed to use INTx, so skip the config reads */
1474 if (dev
->is_virtfn
) {
1480 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1483 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1487 void set_pcie_port_type(struct pci_dev
*pdev
)
1492 struct pci_dev
*parent
;
1494 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1498 pdev
->pcie_cap
= pos
;
1499 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1500 pdev
->pcie_flags_reg
= reg16
;
1501 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
1502 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
1504 parent
= pci_upstream_bridge(pdev
);
1509 * Some systems do not identify their upstream/downstream ports
1510 * correctly so detect impossible configurations here and correct
1511 * the port type accordingly.
1513 type
= pci_pcie_type(pdev
);
1514 if (type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1516 * If pdev claims to be downstream port but the parent
1517 * device is also downstream port assume pdev is actually
1520 if (pcie_downstream_port(parent
)) {
1521 pci_info(pdev
, "claims to be downstream port but is acting as upstream port, correcting type\n");
1522 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1523 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_UPSTREAM
;
1525 } else if (type
== PCI_EXP_TYPE_UPSTREAM
) {
1527 * If pdev claims to be upstream port but the parent
1528 * device is also upstream port assume pdev is actually
1531 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_UPSTREAM
) {
1532 pci_info(pdev
, "claims to be upstream port but is acting as downstream port, correcting type\n");
1533 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1534 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_DOWNSTREAM
;
1539 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1543 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1544 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1545 pdev
->is_hotplug_bridge
= 1;
1548 static void set_pcie_thunderbolt(struct pci_dev
*dev
)
1553 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
1554 PCI_EXT_CAP_ID_VNDR
))) {
1555 pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
, &header
);
1557 /* Is the device part of a Thunderbolt controller? */
1558 if (dev
->vendor
== PCI_VENDOR_ID_INTEL
&&
1559 PCI_VNDR_HEADER_ID(header
) == PCI_VSEC_ID_INTEL_TBT
) {
1560 dev
->is_thunderbolt
= 1;
1566 static void set_pcie_untrusted(struct pci_dev
*dev
)
1568 struct pci_dev
*parent
;
1571 * If the upstream bridge is untrusted we treat this device
1572 * untrusted as well.
1574 parent
= pci_upstream_bridge(dev
);
1575 if (parent
&& (parent
->untrusted
|| parent
->external_facing
))
1576 dev
->untrusted
= true;
1580 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1583 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1584 * when forwarding a type1 configuration request the bridge must check that
1585 * the extended register address field is zero. The bridge is not permitted
1586 * to forward the transactions and must handle it as an Unsupported Request.
1587 * Some bridges do not follow this rule and simply drop the extended register
1588 * bits, resulting in the standard config space being aliased, every 256
1589 * bytes across the entire configuration space. Test for this condition by
1590 * comparing the first dword of each potential alias to the vendor/device ID.
1592 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1593 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1595 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1597 #ifdef CONFIG_PCI_QUIRKS
1601 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1603 for (pos
= PCI_CFG_SPACE_SIZE
;
1604 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1605 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1617 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1620 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1621 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1622 * access it. Maybe we don't have a way to generate extended config space
1623 * accesses, or the device is behind a reverse Express bridge. So we try
1624 * reading the dword at 0x100 which must either be 0 or a valid extended
1625 * capability header.
1627 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1630 int pos
= PCI_CFG_SPACE_SIZE
;
1632 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1633 return PCI_CFG_SPACE_SIZE
;
1634 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1635 return PCI_CFG_SPACE_SIZE
;
1637 return PCI_CFG_SPACE_EXP_SIZE
;
1640 int pci_cfg_space_size(struct pci_dev
*dev
)
1646 #ifdef CONFIG_PCI_IOV
1648 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1649 * implement a PCIe capability and therefore must implement extended
1650 * config space. We can skip the NO_EXTCFG test below and the
1651 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1652 * the fact that the SR-IOV capability on the PF resides in extended
1653 * config space and must be accessible and non-aliased to have enabled
1654 * support for this VF. This is a micro performance optimization for
1655 * systems supporting many VFs.
1658 return PCI_CFG_SPACE_EXP_SIZE
;
1661 if (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1662 return PCI_CFG_SPACE_SIZE
;
1664 class = dev
->class >> 8;
1665 if (class == PCI_CLASS_BRIDGE_HOST
)
1666 return pci_cfg_space_size_ext(dev
);
1668 if (pci_is_pcie(dev
))
1669 return pci_cfg_space_size_ext(dev
);
1671 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1673 return PCI_CFG_SPACE_SIZE
;
1675 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1676 if (status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
))
1677 return pci_cfg_space_size_ext(dev
);
1679 return PCI_CFG_SPACE_SIZE
;
1682 static u32
pci_class(struct pci_dev
*dev
)
1686 #ifdef CONFIG_PCI_IOV
1688 return dev
->physfn
->sriov
->class;
1690 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1694 static void pci_subsystem_ids(struct pci_dev
*dev
, u16
*vendor
, u16
*device
)
1696 #ifdef CONFIG_PCI_IOV
1697 if (dev
->is_virtfn
) {
1698 *vendor
= dev
->physfn
->sriov
->subsystem_vendor
;
1699 *device
= dev
->physfn
->sriov
->subsystem_device
;
1703 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, vendor
);
1704 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, device
);
1707 static u8
pci_hdr_type(struct pci_dev
*dev
)
1711 #ifdef CONFIG_PCI_IOV
1713 return dev
->physfn
->sriov
->hdr_type
;
1715 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
);
1719 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1722 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1725 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1726 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1728 static int pci_intx_mask_broken(struct pci_dev
*dev
)
1730 u16 orig
, toggle
, new;
1732 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
1733 toggle
= orig
^ PCI_COMMAND_INTX_DISABLE
;
1734 pci_write_config_word(dev
, PCI_COMMAND
, toggle
);
1735 pci_read_config_word(dev
, PCI_COMMAND
, &new);
1737 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
1740 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1741 * r2.3, so strictly speaking, a device is not *broken* if it's not
1742 * writable. But we'll live with the misnomer for now.
1749 static void early_dump_pci_device(struct pci_dev
*pdev
)
1754 pci_info(pdev
, "config space:\n");
1756 for (i
= 0; i
< 256; i
+= 4)
1757 pci_read_config_dword(pdev
, i
, &value
[i
/ 4]);
1759 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
, 16, 1,
1764 * pci_setup_device - Fill in class and map information of a device
1765 * @dev: the device structure to fill
1767 * Initialize the device structure with information about the device's
1768 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1769 * Called at initialisation of the PCI subsystem and by CardBus services.
1770 * Returns 0 on success and negative if unknown type of device (not normal,
1771 * bridge or CardBus).
1773 int pci_setup_device(struct pci_dev
*dev
)
1779 struct pci_bus_region region
;
1780 struct resource
*res
;
1782 hdr_type
= pci_hdr_type(dev
);
1784 dev
->sysdata
= dev
->bus
->sysdata
;
1785 dev
->dev
.parent
= dev
->bus
->bridge
;
1786 dev
->dev
.bus
= &pci_bus_type
;
1787 dev
->hdr_type
= hdr_type
& 0x7f;
1788 dev
->multifunction
= !!(hdr_type
& 0x80);
1789 dev
->error_state
= pci_channel_io_normal
;
1790 set_pcie_port_type(dev
);
1792 pci_dev_assign_slot(dev
);
1795 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1796 * set this higher, assuming the system even supports it.
1798 dev
->dma_mask
= 0xffffffff;
1800 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1801 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1802 PCI_FUNC(dev
->devfn
));
1804 class = pci_class(dev
);
1806 dev
->revision
= class & 0xff;
1807 dev
->class = class >> 8; /* upper 3 bytes */
1810 early_dump_pci_device(dev
);
1812 /* Need to have dev->class ready */
1813 dev
->cfg_size
= pci_cfg_space_size(dev
);
1815 /* Need to have dev->cfg_size ready */
1816 set_pcie_thunderbolt(dev
);
1818 set_pcie_untrusted(dev
);
1820 /* "Unknown power state" */
1821 dev
->current_state
= PCI_UNKNOWN
;
1823 /* Early fixups, before probing the BARs */
1824 pci_fixup_device(pci_fixup_early
, dev
);
1826 pci_info(dev
, "[%04x:%04x] type %02x class %#08x\n",
1827 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1829 /* Device class may be changed after fixup */
1830 class = dev
->class >> 8;
1832 if (dev
->non_compliant_bars
&& !dev
->mmio_always_on
) {
1833 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1834 if (cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) {
1835 pci_info(dev
, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1836 cmd
&= ~PCI_COMMAND_IO
;
1837 cmd
&= ~PCI_COMMAND_MEMORY
;
1838 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1842 dev
->broken_intx_masking
= pci_intx_mask_broken(dev
);
1844 switch (dev
->hdr_type
) { /* header type */
1845 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1846 if (class == PCI_CLASS_BRIDGE_PCI
)
1849 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1851 pci_subsystem_ids(dev
, &dev
->subsystem_vendor
, &dev
->subsystem_device
);
1854 * Do the ugly legacy mode stuff here rather than broken chip
1855 * quirk code. Legacy mode ATA controllers have fixed
1856 * addresses. These are not always echoed in BAR0-3, and
1857 * BAR0-3 in a few cases contain junk!
1859 if (class == PCI_CLASS_STORAGE_IDE
) {
1861 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1862 if ((progif
& 1) == 0) {
1863 region
.start
= 0x1F0;
1865 res
= &dev
->resource
[0];
1866 res
->flags
= LEGACY_IO_RESOURCE
;
1867 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1868 pci_info(dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1870 region
.start
= 0x3F6;
1872 res
= &dev
->resource
[1];
1873 res
->flags
= LEGACY_IO_RESOURCE
;
1874 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1875 pci_info(dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1878 if ((progif
& 4) == 0) {
1879 region
.start
= 0x170;
1881 res
= &dev
->resource
[2];
1882 res
->flags
= LEGACY_IO_RESOURCE
;
1883 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1884 pci_info(dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1886 region
.start
= 0x376;
1888 res
= &dev
->resource
[3];
1889 res
->flags
= LEGACY_IO_RESOURCE
;
1890 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1891 pci_info(dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1897 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1899 * The PCI-to-PCI bridge spec requires that subtractive
1900 * decoding (i.e. transparent) bridge must have programming
1901 * interface code of 0x01.
1904 dev
->transparent
= ((dev
->class & 0xff) == 1);
1905 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1906 pci_read_bridge_windows(dev
);
1907 set_pcie_hotplug_bridge(dev
);
1908 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1910 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1911 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1915 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1916 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1919 pci_read_bases(dev
, 1, 0);
1920 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1921 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1924 default: /* unknown header */
1925 pci_err(dev
, "unknown header type %02x, ignoring device\n",
1930 pci_err(dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1931 dev
->class, dev
->hdr_type
);
1932 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
1935 /* We found a fine healthy device, go go go... */
1939 static void pci_configure_mps(struct pci_dev
*dev
)
1941 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
1942 int mps
, mpss
, p_mps
, rc
;
1944 if (!pci_is_pcie(dev
))
1947 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
1952 * For Root Complex Integrated Endpoints, program the maximum
1953 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
1955 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_RC_END
) {
1956 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1959 mps
= 128 << dev
->pcie_mpss
;
1960 rc
= pcie_set_mps(dev
, mps
);
1962 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1968 if (!bridge
|| !pci_is_pcie(bridge
))
1971 mps
= pcie_get_mps(dev
);
1972 p_mps
= pcie_get_mps(bridge
);
1977 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1978 pci_warn(dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1979 mps
, pci_name(bridge
), p_mps
);
1984 * Fancier MPS configuration is done later by
1985 * pcie_bus_configure_settings()
1987 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
1990 mpss
= 128 << dev
->pcie_mpss
;
1991 if (mpss
< p_mps
&& pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
) {
1992 pcie_set_mps(bridge
, mpss
);
1993 pci_info(dev
, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
1994 mpss
, p_mps
, 128 << bridge
->pcie_mpss
);
1995 p_mps
= pcie_get_mps(bridge
);
1998 rc
= pcie_set_mps(dev
, p_mps
);
2000 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2005 pci_info(dev
, "Max Payload Size set to %d (was %d, max %d)\n",
2009 int pci_configure_extended_tags(struct pci_dev
*dev
, void *ign
)
2011 struct pci_host_bridge
*host
;
2016 if (!pci_is_pcie(dev
))
2019 ret
= pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
2023 if (!(cap
& PCI_EXP_DEVCAP_EXT_TAG
))
2026 ret
= pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
2030 host
= pci_find_host_bridge(dev
->bus
);
2035 * If some device in the hierarchy doesn't handle Extended Tags
2036 * correctly, make sure they're disabled.
2038 if (host
->no_ext_tags
) {
2039 if (ctl
& PCI_EXP_DEVCTL_EXT_TAG
) {
2040 pci_info(dev
, "disabling Extended Tags\n");
2041 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2042 PCI_EXP_DEVCTL_EXT_TAG
);
2047 if (!(ctl
& PCI_EXP_DEVCTL_EXT_TAG
)) {
2048 pci_info(dev
, "enabling Extended Tags\n");
2049 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
,
2050 PCI_EXP_DEVCTL_EXT_TAG
);
2056 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2057 * @dev: PCI device to query
2059 * Returns true if the device has enabled relaxed ordering attribute.
2061 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
)
2065 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &v
);
2067 return !!(v
& PCI_EXP_DEVCTL_RELAX_EN
);
2069 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled
);
2071 static void pci_configure_relaxed_ordering(struct pci_dev
*dev
)
2073 struct pci_dev
*root
;
2075 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2079 if (!pcie_relaxed_ordering_enabled(dev
))
2083 * For now, we only deal with Relaxed Ordering issues with Root
2084 * Ports. Peer-to-Peer DMA is another can of worms.
2086 root
= pcie_find_root_port(dev
);
2090 if (root
->dev_flags
& PCI_DEV_FLAGS_NO_RELAXED_ORDERING
) {
2091 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2092 PCI_EXP_DEVCTL_RELAX_EN
);
2093 pci_info(dev
, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2097 static void pci_configure_ltr(struct pci_dev
*dev
)
2099 #ifdef CONFIG_PCIEASPM
2100 struct pci_host_bridge
*host
= pci_find_host_bridge(dev
->bus
);
2101 struct pci_dev
*bridge
;
2104 if (!pci_is_pcie(dev
))
2107 /* Read L1 PM substate capabilities */
2108 dev
->l1ss
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_L1SS
);
2110 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2111 if (!(cap
& PCI_EXP_DEVCAP2_LTR
))
2114 pcie_capability_read_dword(dev
, PCI_EXP_DEVCTL2
, &ctl
);
2115 if (ctl
& PCI_EXP_DEVCTL2_LTR_EN
) {
2116 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
) {
2121 bridge
= pci_upstream_bridge(dev
);
2122 if (bridge
&& bridge
->ltr_path
)
2128 if (!host
->native_ltr
)
2132 * Software must not enable LTR in an Endpoint unless the Root
2133 * Complex and all intermediate Switches indicate support for LTR.
2134 * PCIe r4.0, sec 6.18.
2136 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2137 ((bridge
= pci_upstream_bridge(dev
)) &&
2138 bridge
->ltr_path
)) {
2139 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
2140 PCI_EXP_DEVCTL2_LTR_EN
);
2146 static void pci_configure_eetlp_prefix(struct pci_dev
*dev
)
2148 #ifdef CONFIG_PCI_PASID
2149 struct pci_dev
*bridge
;
2153 if (!pci_is_pcie(dev
))
2156 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2157 if (!(cap
& PCI_EXP_DEVCAP2_EE_PREFIX
))
2160 pcie_type
= pci_pcie_type(dev
);
2161 if (pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
2162 pcie_type
== PCI_EXP_TYPE_RC_END
)
2163 dev
->eetlp_prefix_path
= 1;
2165 bridge
= pci_upstream_bridge(dev
);
2166 if (bridge
&& bridge
->eetlp_prefix_path
)
2167 dev
->eetlp_prefix_path
= 1;
2172 static void pci_configure_serr(struct pci_dev
*dev
)
2176 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
2179 * A bridge will not forward ERR_ messages coming from an
2180 * endpoint unless SERR# forwarding is enabled.
2182 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &control
);
2183 if (!(control
& PCI_BRIDGE_CTL_SERR
)) {
2184 control
|= PCI_BRIDGE_CTL_SERR
;
2185 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, control
);
2190 static void pci_configure_device(struct pci_dev
*dev
)
2192 pci_configure_mps(dev
);
2193 pci_configure_extended_tags(dev
, NULL
);
2194 pci_configure_relaxed_ordering(dev
);
2195 pci_configure_ltr(dev
);
2196 pci_configure_eetlp_prefix(dev
);
2197 pci_configure_serr(dev
);
2199 pci_acpi_program_hp_params(dev
);
2202 static void pci_release_capabilities(struct pci_dev
*dev
)
2206 pci_vpd_release(dev
);
2207 pci_iov_release(dev
);
2208 pci_free_cap_save_buffers(dev
);
2212 * pci_release_dev - Free a PCI device structure when all users of it are
2214 * @dev: device that's been disconnected
2216 * Will be called only by the device core when all users of this PCI device are
2219 static void pci_release_dev(struct device
*dev
)
2221 struct pci_dev
*pci_dev
;
2223 pci_dev
= to_pci_dev(dev
);
2224 pci_release_capabilities(pci_dev
);
2225 pci_release_of_node(pci_dev
);
2226 pcibios_release_device(pci_dev
);
2227 pci_bus_put(pci_dev
->bus
);
2228 kfree(pci_dev
->driver_override
);
2229 bitmap_free(pci_dev
->dma_alias_mask
);
2233 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
2235 struct pci_dev
*dev
;
2237 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
2241 INIT_LIST_HEAD(&dev
->bus_list
);
2242 dev
->dev
.type
= &pci_dev_type
;
2243 dev
->bus
= pci_bus_get(bus
);
2247 EXPORT_SYMBOL(pci_alloc_dev
);
2249 static bool pci_bus_crs_vendor_id(u32 l
)
2251 return (l
& 0xffff) == 0x0001;
2254 static bool pci_bus_wait_crs(struct pci_bus
*bus
, int devfn
, u32
*l
,
2259 if (!pci_bus_crs_vendor_id(*l
))
2260 return true; /* not a CRS completion */
2263 return false; /* CRS, but caller doesn't want to wait */
2266 * We got the reserved Vendor ID that indicates a completion with
2267 * Configuration Request Retry Status (CRS). Retry until we get a
2268 * valid Vendor ID or we time out.
2270 while (pci_bus_crs_vendor_id(*l
)) {
2271 if (delay
> timeout
) {
2272 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2273 pci_domain_nr(bus
), bus
->number
,
2274 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2279 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2280 pci_domain_nr(bus
), bus
->number
,
2281 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2286 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2291 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2292 pci_domain_nr(bus
), bus
->number
,
2293 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2298 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2301 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2304 /* Some broken boards return 0 or ~0 if a slot is empty: */
2305 if (*l
== 0xffffffff || *l
== 0x00000000 ||
2306 *l
== 0x0000ffff || *l
== 0xffff0000)
2309 if (pci_bus_crs_vendor_id(*l
))
2310 return pci_bus_wait_crs(bus
, devfn
, l
, timeout
);
2315 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2318 #ifdef CONFIG_PCI_QUIRKS
2319 struct pci_dev
*bridge
= bus
->self
;
2322 * Certain IDT switches have an issue where they improperly trigger
2323 * ACS Source Validation errors on completions for config reads.
2325 if (bridge
&& bridge
->vendor
== PCI_VENDOR_ID_IDT
&&
2326 bridge
->device
== 0x80b5)
2327 return pci_idt_bus_quirk(bus
, devfn
, l
, timeout
);
2330 return pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
2332 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
2335 * Read the config data for a PCI device, sanity-check it,
2336 * and fill in the dev structure.
2338 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
2340 struct pci_dev
*dev
;
2343 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
2346 dev
= pci_alloc_dev(bus
);
2351 dev
->vendor
= l
& 0xffff;
2352 dev
->device
= (l
>> 16) & 0xffff;
2354 pci_set_of_node(dev
);
2356 if (pci_setup_device(dev
)) {
2357 pci_release_of_node(dev
);
2358 pci_bus_put(dev
->bus
);
2366 void pcie_report_downtraining(struct pci_dev
*dev
)
2368 if (!pci_is_pcie(dev
))
2371 /* Look from the device up to avoid downstream ports with no devices */
2372 if ((pci_pcie_type(dev
) != PCI_EXP_TYPE_ENDPOINT
) &&
2373 (pci_pcie_type(dev
) != PCI_EXP_TYPE_LEG_END
) &&
2374 (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
))
2377 /* Multi-function PCIe devices share the same link/status */
2378 if (PCI_FUNC(dev
->devfn
) != 0 || dev
->is_virtfn
)
2381 /* Print link status only if the device is constrained by the fabric */
2382 __pcie_print_link_status(dev
, false);
2385 static void pci_init_capabilities(struct pci_dev
*dev
)
2387 pci_ea_init(dev
); /* Enhanced Allocation */
2388 pci_msi_init(dev
); /* Disable MSI */
2389 pci_msix_init(dev
); /* Disable MSI-X */
2391 /* Buffers for saving PCIe and PCI-X capabilities */
2392 pci_allocate_cap_save_buffers(dev
);
2394 pci_pm_init(dev
); /* Power Management */
2395 pci_vpd_init(dev
); /* Vital Product Data */
2396 pci_configure_ari(dev
); /* Alternative Routing-ID Forwarding */
2397 pci_iov_init(dev
); /* Single Root I/O Virtualization */
2398 pci_ats_init(dev
); /* Address Translation Services */
2399 pci_pri_init(dev
); /* Page Request Interface */
2400 pci_pasid_init(dev
); /* Process Address Space ID */
2401 pci_acs_init(dev
); /* Access Control Services */
2402 pci_ptm_init(dev
); /* Precision Time Measurement */
2403 pci_aer_init(dev
); /* Advanced Error Reporting */
2404 pci_dpc_init(dev
); /* Downstream Port Containment */
2405 pci_rcec_init(dev
); /* Root Complex Event Collector */
2407 pcie_report_downtraining(dev
);
2409 if (pci_probe_reset_function(dev
) == 0)
2414 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2415 * devices. Firmware interfaces that can select the MSI domain on a
2416 * per-device basis should be called from here.
2418 static struct irq_domain
*pci_dev_msi_domain(struct pci_dev
*dev
)
2420 struct irq_domain
*d
;
2423 * If a domain has been set through the pcibios_add_device()
2424 * callback, then this is the one (platform code knows best).
2426 d
= dev_get_msi_domain(&dev
->dev
);
2431 * Let's see if we have a firmware interface able to provide
2434 d
= pci_msi_get_device_domain(dev
);
2441 static void pci_set_msi_domain(struct pci_dev
*dev
)
2443 struct irq_domain
*d
;
2446 * If the platform or firmware interfaces cannot supply a
2447 * device-specific MSI domain, then inherit the default domain
2448 * from the host bridge itself.
2450 d
= pci_dev_msi_domain(dev
);
2452 d
= dev_get_msi_domain(&dev
->bus
->dev
);
2454 dev_set_msi_domain(&dev
->dev
, d
);
2457 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
2461 pci_configure_device(dev
);
2463 device_initialize(&dev
->dev
);
2464 dev
->dev
.release
= pci_release_dev
;
2466 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
2467 dev
->dev
.dma_mask
= &dev
->dma_mask
;
2468 dev
->dev
.dma_parms
= &dev
->dma_parms
;
2469 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
2471 dma_set_max_seg_size(&dev
->dev
, 65536);
2472 dma_set_seg_boundary(&dev
->dev
, 0xffffffff);
2474 /* Fix up broken headers */
2475 pci_fixup_device(pci_fixup_header
, dev
);
2477 pci_reassigndev_resource_alignment(dev
);
2479 dev
->state_saved
= false;
2481 pci_init_capabilities(dev
);
2484 * Add the device to our list of discovered devices
2485 * and the bus list for fixup functions, etc.
2487 down_write(&pci_bus_sem
);
2488 list_add_tail(&dev
->bus_list
, &bus
->devices
);
2489 up_write(&pci_bus_sem
);
2491 ret
= pcibios_add_device(dev
);
2494 /* Set up MSI IRQ domain */
2495 pci_set_msi_domain(dev
);
2497 /* Notifier could use PCI capabilities */
2498 dev
->match_driver
= false;
2499 ret
= device_add(&dev
->dev
);
2503 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
2505 struct pci_dev
*dev
;
2507 dev
= pci_get_slot(bus
, devfn
);
2513 dev
= pci_scan_device(bus
, devfn
);
2517 pci_device_add(dev
, bus
);
2521 EXPORT_SYMBOL(pci_scan_single_device
);
2523 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
2529 if (pci_ari_enabled(bus
)) {
2532 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
2536 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
2537 next_fn
= PCI_ARI_CAP_NFN(cap
);
2539 return 0; /* protect against malformed list */
2544 /* dev may be NULL for non-contiguous multifunction devices */
2545 if (!dev
|| dev
->multifunction
)
2546 return (fn
+ 1) % 8;
2551 static int only_one_child(struct pci_bus
*bus
)
2553 struct pci_dev
*bridge
= bus
->self
;
2556 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2557 * we scan for all possible devices, not just Device 0.
2559 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
2563 * A PCIe Downstream Port normally leads to a Link with only Device
2564 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2565 * only for Device 0 in that situation.
2567 if (bridge
&& pci_is_pcie(bridge
) && pcie_downstream_port(bridge
))
2574 * pci_scan_slot - Scan a PCI slot on a bus for devices
2575 * @bus: PCI bus to scan
2576 * @devfn: slot number to scan (must have zero function)
2578 * Scan a PCI slot on the specified PCI bus for devices, adding
2579 * discovered devices to the @bus->devices list. New devices
2580 * will not have is_added set.
2582 * Returns the number of new devices found.
2584 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
2586 unsigned fn
, nr
= 0;
2587 struct pci_dev
*dev
;
2589 if (only_one_child(bus
) && (devfn
> 0))
2590 return 0; /* Already scanned the entire slot */
2592 dev
= pci_scan_single_device(bus
, devfn
);
2595 if (!pci_dev_is_added(dev
))
2598 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
2599 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2601 if (!pci_dev_is_added(dev
))
2603 dev
->multifunction
= 1;
2607 /* Only one slot has PCIe device */
2608 if (bus
->self
&& nr
)
2609 pcie_aspm_init_link_state(bus
->self
);
2613 EXPORT_SYMBOL(pci_scan_slot
);
2615 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
2619 if (!pci_is_pcie(dev
))
2623 * We don't have a way to change MPS settings on devices that have
2624 * drivers attached. A hot-added device might support only the minimum
2625 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2626 * where devices may be hot-added, we limit the fabric MPS to 128 so
2627 * hot-added devices will work correctly.
2629 * However, if we hot-add a device to a slot directly below a Root
2630 * Port, it's impossible for there to be other existing devices below
2631 * the port. We don't limit the MPS in this case because we can
2632 * reconfigure MPS on both the Root Port and the hot-added device,
2633 * and there are no other devices involved.
2635 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2637 if (dev
->is_hotplug_bridge
&&
2638 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
2641 if (*smpss
> dev
->pcie_mpss
)
2642 *smpss
= dev
->pcie_mpss
;
2647 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
2651 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
2652 mps
= 128 << dev
->pcie_mpss
;
2654 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
2658 * For "Performance", the assumption is made that
2659 * downstream communication will never be larger than
2660 * the MRRS. So, the MPS only needs to be configured
2661 * for the upstream communication. This being the case,
2662 * walk from the top down and set the MPS of the child
2663 * to that of the parent bus.
2665 * Configure the device MPS with the smaller of the
2666 * device MPSS or the bridge MPS (which is assumed to be
2667 * properly configured at this point to the largest
2668 * allowable MPS based on its parent bus).
2670 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
2673 rc
= pcie_set_mps(dev
, mps
);
2675 pci_err(dev
, "Failed attempting to set the MPS\n");
2678 static void pcie_write_mrrs(struct pci_dev
*dev
)
2683 * In the "safe" case, do not configure the MRRS. There appear to be
2684 * issues with setting MRRS to 0 on a number of devices.
2686 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
2690 * For max performance, the MRRS must be set to the largest supported
2691 * value. However, it cannot be configured larger than the MPS the
2692 * device or the bus can support. This should already be properly
2693 * configured by a prior call to pcie_write_mps().
2695 mrrs
= pcie_get_mps(dev
);
2698 * MRRS is a R/W register. Invalid values can be written, but a
2699 * subsequent read will verify if the value is acceptable or not.
2700 * If the MRRS value provided is not acceptable (e.g., too large),
2701 * shrink the value until it is acceptable to the HW.
2703 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
2704 rc
= pcie_set_readrq(dev
, mrrs
);
2708 pci_warn(dev
, "Failed attempting to set the MRRS\n");
2713 pci_err(dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2716 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
2720 if (!pci_is_pcie(dev
))
2723 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
2724 pcie_bus_config
== PCIE_BUS_DEFAULT
)
2727 mps
= 128 << *(u8
*)data
;
2728 orig_mps
= pcie_get_mps(dev
);
2730 pcie_write_mps(dev
, mps
);
2731 pcie_write_mrrs(dev
);
2733 pci_info(dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2734 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
2735 orig_mps
, pcie_get_readrq(dev
));
2741 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2742 * parents then children fashion. If this changes, then this code will not
2745 void pcie_bus_configure_settings(struct pci_bus
*bus
)
2752 if (!pci_is_pcie(bus
->self
))
2756 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2757 * to be aware of the MPS of the destination. To work around this,
2758 * simply force the MPS of the entire system to the smallest possible.
2760 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2763 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
2764 smpss
= bus
->self
->pcie_mpss
;
2766 pcie_find_smpss(bus
->self
, &smpss
);
2767 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
2770 pcie_bus_configure_set(bus
->self
, &smpss
);
2771 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
2773 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
2776 * Called after each bus is probed, but before its children are examined. This
2777 * is marked as __weak because multiple architectures define it.
2779 void __weak
pcibios_fixup_bus(struct pci_bus
*bus
)
2781 /* nothing to do, expected to be removed in the future */
2785 * pci_scan_child_bus_extend() - Scan devices below a bus
2786 * @bus: Bus to scan for devices
2787 * @available_buses: Total number of buses available (%0 does not try to
2788 * extend beyond the minimal)
2790 * Scans devices below @bus including subordinate buses. Returns new
2791 * subordinate number including all the found devices. Passing
2792 * @available_buses causes the remaining bus space to be distributed
2793 * equally between hotplug-capable bridges to allow future extension of the
2796 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
2797 unsigned int available_buses
)
2799 unsigned int used_buses
, normal_bridges
= 0, hotplug_bridges
= 0;
2800 unsigned int start
= bus
->busn_res
.start
;
2801 unsigned int devfn
, fn
, cmax
, max
= start
;
2802 struct pci_dev
*dev
;
2805 dev_dbg(&bus
->dev
, "scanning bus\n");
2807 /* Go find them, Rover! */
2808 for (devfn
= 0; devfn
< 256; devfn
+= 8) {
2809 nr_devs
= pci_scan_slot(bus
, devfn
);
2812 * The Jailhouse hypervisor may pass individual functions of a
2813 * multi-function device to a guest without passing function 0.
2814 * Look for them as well.
2816 if (jailhouse_paravirt() && nr_devs
== 0) {
2817 for (fn
= 1; fn
< 8; fn
++) {
2818 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2820 dev
->multifunction
= 1;
2825 /* Reserve buses for SR-IOV capability */
2826 used_buses
= pci_iov_bus_range(bus
);
2830 * After performing arch-dependent fixup of the bus, look behind
2831 * all PCI-to-PCI bridges on this bus.
2833 if (!bus
->is_added
) {
2834 dev_dbg(&bus
->dev
, "fixups for bus\n");
2835 pcibios_fixup_bus(bus
);
2840 * Calculate how many hotplug bridges and normal bridges there
2841 * are on this bus. We will distribute the additional available
2842 * buses between hotplug bridges.
2844 for_each_pci_bridge(dev
, bus
) {
2845 if (dev
->is_hotplug_bridge
)
2852 * Scan bridges that are already configured. We don't touch them
2853 * unless they are misconfigured (which will be done in the second
2856 for_each_pci_bridge(dev
, bus
) {
2858 max
= pci_scan_bridge_extend(bus
, dev
, max
, 0, 0);
2861 * Reserve one bus for each bridge now to avoid extending
2862 * hotplug bridges too much during the second scan below.
2866 used_buses
+= cmax
- max
- 1;
2869 /* Scan bridges that need to be reconfigured */
2870 for_each_pci_bridge(dev
, bus
) {
2871 unsigned int buses
= 0;
2873 if (!hotplug_bridges
&& normal_bridges
== 1) {
2876 * There is only one bridge on the bus (upstream
2877 * port) so it gets all available buses which it
2878 * can then distribute to the possible hotplug
2881 buses
= available_buses
;
2882 } else if (dev
->is_hotplug_bridge
) {
2885 * Distribute the extra buses between hotplug
2888 buses
= available_buses
/ hotplug_bridges
;
2889 buses
= min(buses
, available_buses
- used_buses
+ 1);
2893 max
= pci_scan_bridge_extend(bus
, dev
, cmax
, buses
, 1);
2894 /* One bus is already accounted so don't add it again */
2896 used_buses
+= max
- cmax
- 1;
2900 * Make sure a hotplug bridge has at least the minimum requested
2901 * number of buses but allow it to grow up to the maximum available
2902 * bus number of there is room.
2904 if (bus
->self
&& bus
->self
->is_hotplug_bridge
) {
2905 used_buses
= max_t(unsigned int, available_buses
,
2906 pci_hotplug_bus_size
- 1);
2907 if (max
- start
< used_buses
) {
2908 max
= start
+ used_buses
;
2910 /* Do not allocate more buses than we have room left */
2911 if (max
> bus
->busn_res
.end
)
2912 max
= bus
->busn_res
.end
;
2914 dev_dbg(&bus
->dev
, "%pR extended by %#02x\n",
2915 &bus
->busn_res
, max
- start
);
2920 * We've scanned the bus and so we know all about what's on
2921 * the other side of any bridges that may be on this bus plus
2924 * Return how far we've got finding sub-buses.
2926 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
2931 * pci_scan_child_bus() - Scan devices below a bus
2932 * @bus: Bus to scan for devices
2934 * Scans devices below @bus including subordinate buses. Returns new
2935 * subordinate number including all the found devices.
2937 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
2939 return pci_scan_child_bus_extend(bus
, 0);
2941 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
2944 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
2945 * @bridge: Host bridge to set up
2947 * Default empty implementation. Replace with an architecture-specific setup
2948 * routine, if necessary.
2950 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
2955 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
2959 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
2963 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
2964 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2967 struct pci_host_bridge
*bridge
;
2969 bridge
= pci_alloc_host_bridge(0);
2973 bridge
->dev
.parent
= parent
;
2975 list_splice_init(resources
, &bridge
->windows
);
2976 bridge
->sysdata
= sysdata
;
2977 bridge
->busnr
= bus
;
2980 error
= pci_register_host_bridge(bridge
);
2987 put_device(&bridge
->dev
);
2990 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
2992 int pci_host_probe(struct pci_host_bridge
*bridge
)
2994 struct pci_bus
*bus
, *child
;
2997 ret
= pci_scan_root_bus_bridge(bridge
);
2999 dev_err(bridge
->dev
.parent
, "Scanning root bridge failed");
3006 * We insert PCI resources into the iomem_resource and
3007 * ioport_resource trees in either pci_bus_claim_resources()
3008 * or pci_bus_assign_resources().
3010 if (pci_has_flag(PCI_PROBE_ONLY
)) {
3011 pci_bus_claim_resources(bus
);
3013 pci_bus_size_bridges(bus
);
3014 pci_bus_assign_resources(bus
);
3016 list_for_each_entry(child
, &bus
->children
, node
)
3017 pcie_bus_configure_settings(child
);
3020 pci_bus_add_devices(bus
);
3023 EXPORT_SYMBOL_GPL(pci_host_probe
);
3025 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
3027 struct resource
*res
= &b
->busn_res
;
3028 struct resource
*parent_res
, *conflict
;
3032 res
->flags
= IORESOURCE_BUS
;
3034 if (!pci_is_root_bus(b
))
3035 parent_res
= &b
->parent
->busn_res
;
3037 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
3038 res
->flags
|= IORESOURCE_PCI_FIXED
;
3041 conflict
= request_resource_conflict(parent_res
, res
);
3045 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3046 res
, pci_is_root_bus(b
) ? "domain " : "",
3047 parent_res
, conflict
->name
, conflict
);
3049 return conflict
== NULL
;
3052 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
3054 struct resource
*res
= &b
->busn_res
;
3055 struct resource old_res
= *res
;
3056 resource_size_t size
;
3059 if (res
->start
> bus_max
)
3062 size
= bus_max
- res
->start
+ 1;
3063 ret
= adjust_resource(res
, res
->start
, size
);
3064 dev_info(&b
->dev
, "busn_res: %pR end %s updated to %02x\n",
3065 &old_res
, ret
? "can not be" : "is", bus_max
);
3067 if (!ret
&& !res
->parent
)
3068 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
3073 void pci_bus_release_busn_res(struct pci_bus
*b
)
3075 struct resource
*res
= &b
->busn_res
;
3078 if (!res
->flags
|| !res
->parent
)
3081 ret
= release_resource(res
);
3082 dev_info(&b
->dev
, "busn_res: %pR %s released\n",
3083 res
, ret
? "can not be" : "is");
3086 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
)
3088 struct resource_entry
*window
;
3096 resource_list_for_each_entry(window
, &bridge
->windows
)
3097 if (window
->res
->flags
& IORESOURCE_BUS
) {
3098 bridge
->busnr
= window
->res
->start
;
3103 ret
= pci_register_host_bridge(bridge
);
3108 bus
= bridge
->busnr
;
3112 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3114 pci_bus_insert_busn_res(b
, bus
, 255);
3117 max
= pci_scan_child_bus(b
);
3120 pci_bus_update_busn_res_end(b
, max
);
3124 EXPORT_SYMBOL(pci_scan_root_bus_bridge
);
3126 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
3127 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
3129 struct resource_entry
*window
;
3134 resource_list_for_each_entry(window
, resources
)
3135 if (window
->res
->flags
& IORESOURCE_BUS
) {
3140 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
3146 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3148 pci_bus_insert_busn_res(b
, bus
, 255);
3151 max
= pci_scan_child_bus(b
);
3154 pci_bus_update_busn_res_end(b
, max
);
3158 EXPORT_SYMBOL(pci_scan_root_bus
);
3160 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
3163 LIST_HEAD(resources
);
3166 pci_add_resource(&resources
, &ioport_resource
);
3167 pci_add_resource(&resources
, &iomem_resource
);
3168 pci_add_resource(&resources
, &busn_resource
);
3169 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
3171 pci_scan_child_bus(b
);
3173 pci_free_resource_list(&resources
);
3177 EXPORT_SYMBOL(pci_scan_bus
);
3180 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3181 * @bridge: PCI bridge for the bus to scan
3183 * Scan a PCI bus and child buses for new devices, add them,
3184 * and enable them, resizing bridge mmio/io resource if necessary
3185 * and possible. The caller must ensure the child devices are already
3186 * removed for resizing to occur.
3188 * Returns the max number of subordinate bus discovered.
3190 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
3193 struct pci_bus
*bus
= bridge
->subordinate
;
3195 max
= pci_scan_child_bus(bus
);
3197 pci_assign_unassigned_bridge_resources(bridge
);
3199 pci_bus_add_devices(bus
);
3205 * pci_rescan_bus - Scan a PCI bus for devices
3206 * @bus: PCI bus to scan
3208 * Scan a PCI bus and child buses for new devices, add them,
3211 * Returns the max number of subordinate bus discovered.
3213 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
3217 max
= pci_scan_child_bus(bus
);
3218 pci_assign_unassigned_bus_resources(bus
);
3219 pci_bus_add_devices(bus
);
3223 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
3226 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3227 * routines should always be executed under this mutex.
3229 static DEFINE_MUTEX(pci_rescan_remove_lock
);
3231 void pci_lock_rescan_remove(void)
3233 mutex_lock(&pci_rescan_remove_lock
);
3235 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
3237 void pci_unlock_rescan_remove(void)
3239 mutex_unlock(&pci_rescan_remove_lock
);
3241 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
3243 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
3244 const struct device
*d_b
)
3246 const struct pci_dev
*a
= to_pci_dev(d_a
);
3247 const struct pci_dev
*b
= to_pci_dev(d_b
);
3249 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
3250 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
3252 if (a
->bus
->number
< b
->bus
->number
) return -1;
3253 else if (a
->bus
->number
> b
->bus
->number
) return 1;
3255 if (a
->devfn
< b
->devfn
) return -1;
3256 else if (a
->devfn
> b
->devfn
) return 1;
3261 void __init
pci_sort_breadthfirst(void)
3263 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);
3266 int pci_hp_add_bridge(struct pci_dev
*dev
)
3268 struct pci_bus
*parent
= dev
->bus
;
3269 int busnr
, start
= parent
->busn_res
.start
;
3270 unsigned int available_buses
= 0;
3271 int end
= parent
->busn_res
.end
;
3273 for (busnr
= start
; busnr
<= end
; busnr
++) {
3274 if (!pci_find_bus(pci_domain_nr(parent
), busnr
))
3277 if (busnr
-- > end
) {
3278 pci_err(dev
, "No bus number available for hot-added bridge\n");
3282 /* Scan bridges that are already configured */
3283 busnr
= pci_scan_bridge(parent
, dev
, busnr
, 0);
3286 * Distribute the available bus numbers between hotplug-capable
3287 * bridges to make extending the chain later possible.
3289 available_buses
= end
- busnr
;
3291 /* Scan bridges that need to be reconfigured */
3292 pci_scan_bridge_extend(parent
, dev
, busnr
, available_buses
, 1);
3294 if (!dev
->subordinate
)
3299 EXPORT_SYMBOL_GPL(pci_hp_add_bridge
);