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Merge tag 'wireless-drivers-for-davem-2018-01-17' of git://git.kernel.org/pub/scm...
[mirror_ubuntu-bionic-kernel.git] / drivers / pci / quirks.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file contains work-arounds for many known PCI hardware
4 * bugs. Devices present only on certain architectures (host
5 * bridges et cetera) should be handled in arch-specific code.
6 *
7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 *
9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 *
11 * Init/reset quirks for USB host controllers should be in the
12 * USB quirks file, where their drivers can access reuse it.
13 */
14
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
22 #include <linux/kallsyms.h>
23 #include <linux/dmi.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/ktime.h>
28 #include <linux/mm.h>
29 #include <linux/platform_data/x86/apple.h>
30 #include <asm/dma.h> /* isa_dma_bridge_buggy */
31 #include "pci.h"
32
33 /*
34 * Decoding should be disabled for a PCI device during BAR sizing to avoid
35 * conflict. But doing so may cause problems on host bridge and perhaps other
36 * key system devices. For devices that need to have mmio decoding always-on,
37 * we need to set the dev->mmio_always_on bit.
38 */
39 static void quirk_mmio_always_on(struct pci_dev *dev)
40 {
41 dev->mmio_always_on = 1;
42 }
43 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
45
46 /* The Mellanox Tavor device gives false positive parity errors
47 * Mark this device with a broken_parity_status, to allow
48 * PCI scanning code to "skip" this now blacklisted device.
49 */
50 static void quirk_mellanox_tavor(struct pci_dev *dev)
51 {
52 dev->broken_parity_status = 1; /* This device gives false positives */
53 }
54 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
56
57 /* Deal with broken BIOSes that neglect to enable passive release,
58 which can cause problems in combination with the 82441FX/PPro MTRRs */
59 static void quirk_passive_release(struct pci_dev *dev)
60 {
61 struct pci_dev *d = NULL;
62 unsigned char dlc;
63
64 /* We have to make sure a particular bit is set in the PIIX3
65 ISA bridge, so we have to go out and find it. */
66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
67 pci_read_config_byte(d, 0x82, &dlc);
68 if (!(dlc & 1<<1)) {
69 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
70 dlc |= 1<<1;
71 pci_write_config_byte(d, 0x82, dlc);
72 }
73 }
74 }
75 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77
78 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
79 but VIA don't answer queries. If you happen to have good contacts at VIA
80 ask them for me please -- Alan
81
82 This appears to be BIOS not version dependent. So presumably there is a
83 chipset level fix */
84
85 static void quirk_isa_dma_hangs(struct pci_dev *dev)
86 {
87 if (!isa_dma_bridge_buggy) {
88 isa_dma_bridge_buggy = 1;
89 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
90 }
91 }
92 /*
93 * Its not totally clear which chipsets are the problematic ones
94 * We know 82C586 and 82C596 variants are affected.
95 */
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103
104 /*
105 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
106 * for some HT machines to use C4 w/o hanging.
107 */
108 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
109 {
110 u32 pmbase;
111 u16 pm1a;
112
113 pci_read_config_dword(dev, 0x40, &pmbase);
114 pmbase = pmbase & 0xff80;
115 pm1a = inw(pmbase);
116
117 if (pm1a & 0x10) {
118 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
119 outw(0x10, pmbase);
120 }
121 }
122 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123
124 /*
125 * Chipsets where PCI->PCI transfers vanish or hang
126 */
127 static void quirk_nopcipci(struct pci_dev *dev)
128 {
129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
130 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
131 pci_pci_problems |= PCIPCI_FAIL;
132 }
133 }
134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
136
137 static void quirk_nopciamd(struct pci_dev *dev)
138 {
139 u8 rev;
140 pci_read_config_byte(dev, 0x08, &rev);
141 if (rev == 0x13) {
142 /* Erratum 24 */
143 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
144 pci_pci_problems |= PCIAGP_FAIL;
145 }
146 }
147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148
149 /*
150 * Triton requires workarounds to be used by the drivers
151 */
152 static void quirk_triton(struct pci_dev *dev)
153 {
154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
155 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
156 pci_pci_problems |= PCIPCI_TRITON;
157 }
158 }
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
162 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163
164 /*
165 * VIA Apollo KT133 needs PCI latency patch
166 * Made according to a windows driver based patch by George E. Breese
167 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
168 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
169 * the info on which Mr Breese based his work.
170 *
171 * Updated based on further information from the site and also on
172 * information provided by VIA
173 */
174 static void quirk_vialatency(struct pci_dev *dev)
175 {
176 struct pci_dev *p;
177 u8 busarb;
178 /* Ok we have a potential problem chipset here. Now see if we have
179 a buggy southbridge */
180
181 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 if (p != NULL) {
183 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
184 /* Check for buggy part revisions */
185 if (p->revision < 0x40 || p->revision > 0x42)
186 goto exit;
187 } else {
188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
189 if (p == NULL) /* No problem parts */
190 goto exit;
191 /* Check for buggy part revisions */
192 if (p->revision < 0x10 || p->revision > 0x12)
193 goto exit;
194 }
195
196 /*
197 * Ok we have the problem. Now set the PCI master grant to
198 * occur every master grant. The apparent bug is that under high
199 * PCI load (quite common in Linux of course) you can get data
200 * loss when the CPU is held off the bus for 3 bus master requests
201 * This happens to include the IDE controllers....
202 *
203 * VIA only apply this fix when an SB Live! is present but under
204 * both Linux and Windows this isn't enough, and we have seen
205 * corruption without SB Live! but with things like 3 UDMA IDE
206 * controllers. So we ignore that bit of the VIA recommendation..
207 */
208
209 pci_read_config_byte(dev, 0x76, &busarb);
210 /* Set bit 4 and bi 5 of byte 76 to 0x01
211 "Master priority rotation on every PCI master grant */
212 busarb &= ~(1<<5);
213 busarb |= (1<<4);
214 pci_write_config_byte(dev, 0x76, busarb);
215 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
216 exit:
217 pci_dev_put(p);
218 }
219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
220 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
222 /* Must restore this on a resume from RAM */
223 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
226
227 /*
228 * VIA Apollo VP3 needs ETBF on BT848/878
229 */
230 static void quirk_viaetbf(struct pci_dev *dev)
231 {
232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
233 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
234 pci_pci_problems |= PCIPCI_VIAETBF;
235 }
236 }
237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
238
239 static void quirk_vsfx(struct pci_dev *dev)
240 {
241 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
242 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
243 pci_pci_problems |= PCIPCI_VSFX;
244 }
245 }
246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
247
248 /*
249 * Ali Magik requires workarounds to be used by the drivers
250 * that DMA to AGP space. Latency must be set to 0xA and triton
251 * workaround applied too
252 * [Info kindly provided by ALi]
253 */
254 static void quirk_alimagik(struct pci_dev *dev)
255 {
256 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
257 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
258 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
259 }
260 }
261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
263
264 /*
265 * Natoma has some interesting boundary conditions with Zoran stuff
266 * at least
267 */
268 static void quirk_natoma(struct pci_dev *dev)
269 {
270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
271 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
272 pci_pci_problems |= PCIPCI_NATOMA;
273 }
274 }
275 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
276 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
277 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
278 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
279 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
280 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
281
282 /*
283 * This chip can cause PCI parity errors if config register 0xA0 is read
284 * while DMAs are occurring.
285 */
286 static void quirk_citrine(struct pci_dev *dev)
287 {
288 dev->cfg_size = 0xA0;
289 }
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291
292 /*
293 * This chip can cause bus lockups if config addresses above 0x600
294 * are read or written.
295 */
296 static void quirk_nfp6000(struct pci_dev *dev)
297 {
298 dev->cfg_size = 0x600;
299 }
300 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
302 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
303
304 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
305 static void quirk_extend_bar_to_page(struct pci_dev *dev)
306 {
307 int i;
308
309 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
310 struct resource *r = &dev->resource[i];
311
312 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
313 r->end = PAGE_SIZE - 1;
314 r->start = 0;
315 r->flags |= IORESOURCE_UNSET;
316 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
317 i, r);
318 }
319 }
320 }
321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
322
323 /*
324 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
325 * If it's needed, re-allocate the region.
326 */
327 static void quirk_s3_64M(struct pci_dev *dev)
328 {
329 struct resource *r = &dev->resource[0];
330
331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
332 r->flags |= IORESOURCE_UNSET;
333 r->start = 0;
334 r->end = 0x3ffffff;
335 }
336 }
337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
339
340 static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
341 const char *name)
342 {
343 u32 region;
344 struct pci_bus_region bus_region;
345 struct resource *res = dev->resource + pos;
346
347 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
348
349 if (!region)
350 return;
351
352 res->name = pci_name(dev);
353 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
354 res->flags |=
355 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
356 region &= ~(size - 1);
357
358 /* Convert from PCI bus to resource space */
359 bus_region.start = region;
360 bus_region.end = region + size - 1;
361 pcibios_bus_to_resource(dev->bus, res, &bus_region);
362
363 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
364 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
365 }
366
367 /*
368 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
369 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
370 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
371 * (which conflicts w/ BAR1's memory range).
372 *
373 * CS553x's ISA PCI BARs may also be read-only (ref:
374 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
375 */
376 static void quirk_cs5536_vsa(struct pci_dev *dev)
377 {
378 static char *name = "CS5536 ISA bridge";
379
380 if (pci_resource_len(dev, 0) != 8) {
381 quirk_io(dev, 0, 8, name); /* SMB */
382 quirk_io(dev, 1, 256, name); /* GPIO */
383 quirk_io(dev, 2, 64, name); /* MFGPT */
384 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
385 name);
386 }
387 }
388 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
389
390 static void quirk_io_region(struct pci_dev *dev, int port,
391 unsigned size, int nr, const char *name)
392 {
393 u16 region;
394 struct pci_bus_region bus_region;
395 struct resource *res = dev->resource + nr;
396
397 pci_read_config_word(dev, port, &region);
398 region &= ~(size - 1);
399
400 if (!region)
401 return;
402
403 res->name = pci_name(dev);
404 res->flags = IORESOURCE_IO;
405
406 /* Convert from PCI bus to resource space */
407 bus_region.start = region;
408 bus_region.end = region + size - 1;
409 pcibios_bus_to_resource(dev->bus, res, &bus_region);
410
411 if (!pci_claim_resource(dev, nr))
412 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
413 }
414
415 /*
416 * ATI Northbridge setups MCE the processor if you even
417 * read somewhere between 0x3b0->0x3bb or read 0x3d3
418 */
419 static void quirk_ati_exploding_mce(struct pci_dev *dev)
420 {
421 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
422 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
423 request_region(0x3b0, 0x0C, "RadeonIGP");
424 request_region(0x3d3, 0x01, "RadeonIGP");
425 }
426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
427
428 /*
429 * In the AMD NL platform, this device ([1022:7912]) has a class code of
430 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
431 * claim it.
432 * But the dwc3 driver is a more specific driver for this device, and we'd
433 * prefer to use it instead of xhci. To prevent xhci from claiming the
434 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
435 * defines as "USB device (not host controller)". The dwc3 driver can then
436 * claim it based on its Vendor and Device ID.
437 */
438 static void quirk_amd_nl_class(struct pci_dev *pdev)
439 {
440 u32 class = pdev->class;
441
442 /* Use "USB Device (not host controller)" class */
443 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
444 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
445 class, pdev->class);
446 }
447 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
448 quirk_amd_nl_class);
449
450 /*
451 * Let's make the southbridge information explicit instead
452 * of having to worry about people probing the ACPI areas,
453 * for example.. (Yes, it happens, and if you read the wrong
454 * ACPI register it will put the machine to sleep with no
455 * way of waking it up again. Bummer).
456 *
457 * ALI M7101: Two IO regions pointed to by words at
458 * 0xE0 (64 bytes of ACPI registers)
459 * 0xE2 (32 bytes of SMB registers)
460 */
461 static void quirk_ali7101_acpi(struct pci_dev *dev)
462 {
463 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
464 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
465 }
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
467
468 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
469 {
470 u32 devres;
471 u32 mask, size, base;
472
473 pci_read_config_dword(dev, port, &devres);
474 if ((devres & enable) != enable)
475 return;
476 mask = (devres >> 16) & 15;
477 base = devres & 0xffff;
478 size = 16;
479 for (;;) {
480 unsigned bit = size >> 1;
481 if ((bit & mask) == bit)
482 break;
483 size = bit;
484 }
485 /*
486 * For now we only print it out. Eventually we'll want to
487 * reserve it (at least if it's in the 0x1000+ range), but
488 * let's get enough confirmation reports first.
489 */
490 base &= -size;
491 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
492 base + size - 1);
493 }
494
495 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
496 {
497 u32 devres;
498 u32 mask, size, base;
499
500 pci_read_config_dword(dev, port, &devres);
501 if ((devres & enable) != enable)
502 return;
503 base = devres & 0xffff0000;
504 mask = (devres & 0x3f) << 16;
505 size = 128 << 16;
506 for (;;) {
507 unsigned bit = size >> 1;
508 if ((bit & mask) == bit)
509 break;
510 size = bit;
511 }
512 /*
513 * For now we only print it out. Eventually we'll want to
514 * reserve it, but let's get enough confirmation reports first.
515 */
516 base &= -size;
517 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
518 base + size - 1);
519 }
520
521 /*
522 * PIIX4 ACPI: Two IO regions pointed to by longwords at
523 * 0x40 (64 bytes of ACPI registers)
524 * 0x90 (16 bytes of SMB registers)
525 * and a few strange programmable PIIX4 device resources.
526 */
527 static void quirk_piix4_acpi(struct pci_dev *dev)
528 {
529 u32 res_a;
530
531 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
532 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
533
534 /* Device resource A has enables for some of the other ones */
535 pci_read_config_dword(dev, 0x5c, &res_a);
536
537 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
538 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
539
540 /* Device resource D is just bitfields for static resources */
541
542 /* Device 12 enabled? */
543 if (res_a & (1 << 29)) {
544 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
545 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
546 }
547 /* Device 13 enabled? */
548 if (res_a & (1 << 30)) {
549 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
550 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
551 }
552 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
553 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
554 }
555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
557
558 #define ICH_PMBASE 0x40
559 #define ICH_ACPI_CNTL 0x44
560 #define ICH4_ACPI_EN 0x10
561 #define ICH6_ACPI_EN 0x80
562 #define ICH4_GPIOBASE 0x58
563 #define ICH4_GPIO_CNTL 0x5c
564 #define ICH4_GPIO_EN 0x10
565 #define ICH6_GPIOBASE 0x48
566 #define ICH6_GPIO_CNTL 0x4c
567 #define ICH6_GPIO_EN 0x10
568
569 /*
570 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
571 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
572 * 0x58 (64 bytes of GPIO I/O space)
573 */
574 static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
575 {
576 u8 enable;
577
578 /*
579 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
580 * with low legacy (and fixed) ports. We don't know the decoding
581 * priority and can't tell whether the legacy device or the one created
582 * here is really at that address. This happens on boards with broken
583 * BIOSes.
584 */
585
586 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
587 if (enable & ICH4_ACPI_EN)
588 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
589 "ICH4 ACPI/GPIO/TCO");
590
591 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
592 if (enable & ICH4_GPIO_EN)
593 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
594 "ICH4 GPIO");
595 }
596 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
597 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
598 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
599 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
602 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
603 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
604 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
606
607 static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
608 {
609 u8 enable;
610
611 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
612 if (enable & ICH6_ACPI_EN)
613 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
614 "ICH6 ACPI/GPIO/TCO");
615
616 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
617 if (enable & ICH6_GPIO_EN)
618 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
619 "ICH6 GPIO");
620 }
621
622 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
623 {
624 u32 val;
625 u32 size, base;
626
627 pci_read_config_dword(dev, reg, &val);
628
629 /* Enabled? */
630 if (!(val & 1))
631 return;
632 base = val & 0xfffc;
633 if (dynsize) {
634 /*
635 * This is not correct. It is 16, 32 or 64 bytes depending on
636 * register D31:F0:ADh bits 5:4.
637 *
638 * But this gets us at least _part_ of it.
639 */
640 size = 16;
641 } else {
642 size = 128;
643 }
644 base &= ~(size-1);
645
646 /* Just print it out for now. We should reserve it after more debugging */
647 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
648 }
649
650 static void quirk_ich6_lpc(struct pci_dev *dev)
651 {
652 /* Shared ACPI/GPIO decode with all ICH6+ */
653 ich6_lpc_acpi_gpio(dev);
654
655 /* ICH6-specific generic IO decode */
656 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
657 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
658 }
659 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
660 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
661
662 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
663 {
664 u32 val;
665 u32 mask, base;
666
667 pci_read_config_dword(dev, reg, &val);
668
669 /* Enabled? */
670 if (!(val & 1))
671 return;
672
673 /*
674 * IO base in bits 15:2, mask in bits 23:18, both
675 * are dword-based
676 */
677 base = val & 0xfffc;
678 mask = (val >> 16) & 0xfc;
679 mask |= 3;
680
681 /* Just print it out for now. We should reserve it after more debugging */
682 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
683 }
684
685 /* ICH7-10 has the same common LPC generic IO decode registers */
686 static void quirk_ich7_lpc(struct pci_dev *dev)
687 {
688 /* We share the common ACPI/GPIO decode with ICH6 */
689 ich6_lpc_acpi_gpio(dev);
690
691 /* And have 4 ICH7+ generic decodes */
692 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
693 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
694 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
695 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
696 }
697 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
699 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
702 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
703 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
704 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
705 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
706 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
707 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
708 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
709 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
710
711 /*
712 * VIA ACPI: One IO region pointed to by longword at
713 * 0x48 or 0x20 (256 bytes of ACPI registers)
714 */
715 static void quirk_vt82c586_acpi(struct pci_dev *dev)
716 {
717 if (dev->revision & 0x10)
718 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
719 "vt82c586 ACPI");
720 }
721 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
722
723 /*
724 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
725 * 0x48 (256 bytes of ACPI registers)
726 * 0x70 (128 bytes of hardware monitoring register)
727 * 0x90 (16 bytes of SMB registers)
728 */
729 static void quirk_vt82c686_acpi(struct pci_dev *dev)
730 {
731 quirk_vt82c586_acpi(dev);
732
733 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
734 "vt82c686 HW-mon");
735
736 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
737 }
738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
739
740 /*
741 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
742 * 0x88 (128 bytes of power management registers)
743 * 0xd0 (16 bytes of SMB registers)
744 */
745 static void quirk_vt8235_acpi(struct pci_dev *dev)
746 {
747 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
748 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
749 }
750 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
751
752 /*
753 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
754 * Disable fast back-to-back on the secondary bus segment
755 */
756 static void quirk_xio2000a(struct pci_dev *dev)
757 {
758 struct pci_dev *pdev;
759 u16 command;
760
761 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
762 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
763 pci_read_config_word(pdev, PCI_COMMAND, &command);
764 if (command & PCI_COMMAND_FAST_BACK)
765 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
766 }
767 }
768 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
769 quirk_xio2000a);
770
771 #ifdef CONFIG_X86_IO_APIC
772
773 #include <asm/io_apic.h>
774
775 /*
776 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
777 * devices to the external APIC.
778 *
779 * TODO: When we have device-specific interrupt routers,
780 * this code will go away from quirks.
781 */
782 static void quirk_via_ioapic(struct pci_dev *dev)
783 {
784 u8 tmp;
785
786 if (nr_ioapics < 1)
787 tmp = 0; /* nothing routed to external APIC */
788 else
789 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
790
791 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
792 tmp == 0 ? "Disa" : "Ena");
793
794 /* Offset 0x58: External APIC IRQ output control */
795 pci_write_config_byte(dev, 0x58, tmp);
796 }
797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
798 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
799
800 /*
801 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
802 * This leads to doubled level interrupt rates.
803 * Set this bit to get rid of cycle wastage.
804 * Otherwise uncritical.
805 */
806 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
807 {
808 u8 misc_control2;
809 #define BYPASS_APIC_DEASSERT 8
810
811 pci_read_config_byte(dev, 0x5B, &misc_control2);
812 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
813 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
814 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
815 }
816 }
817 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
818 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
819
820 /*
821 * The AMD io apic can hang the box when an apic irq is masked.
822 * We check all revs >= B0 (yet not in the pre production!) as the bug
823 * is currently marked NoFix
824 *
825 * We have multiple reports of hangs with this chipset that went away with
826 * noapic specified. For the moment we assume it's the erratum. We may be wrong
827 * of course. However the advice is demonstrably good even if so..
828 */
829 static void quirk_amd_ioapic(struct pci_dev *dev)
830 {
831 if (dev->revision >= 0x02) {
832 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
833 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
834 }
835 }
836 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
837 #endif /* CONFIG_X86_IO_APIC */
838
839 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
840
841 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
842 {
843 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
844 if (dev->subsystem_device == 0xa118)
845 dev->sriov->link = dev->devfn;
846 }
847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
848 #endif
849
850 /*
851 * Some settings of MMRBC can lead to data corruption so block changes.
852 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
853 */
854 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
855 {
856 if (dev->subordinate && dev->revision <= 0x12) {
857 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
858 dev->revision);
859 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
860 }
861 }
862 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
863
864 /*
865 * FIXME: it is questionable that quirk_via_acpi
866 * is needed. It shows up as an ISA bridge, and does not
867 * support the PCI_INTERRUPT_LINE register at all. Therefore
868 * it seems like setting the pci_dev's 'irq' to the
869 * value of the ACPI SCI interrupt is only done for convenience.
870 * -jgarzik
871 */
872 static void quirk_via_acpi(struct pci_dev *d)
873 {
874 /*
875 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
876 */
877 u8 irq;
878 pci_read_config_byte(d, 0x42, &irq);
879 irq &= 0xf;
880 if (irq && (irq != 2))
881 d->irq = irq;
882 }
883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
884 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
885
886
887 /*
888 * VIA bridges which have VLink
889 */
890
891 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
892
893 static void quirk_via_bridge(struct pci_dev *dev)
894 {
895 /* See what bridge we have and find the device ranges */
896 switch (dev->device) {
897 case PCI_DEVICE_ID_VIA_82C686:
898 /* The VT82C686 is special, it attaches to PCI and can have
899 any device number. All its subdevices are functions of
900 that single device. */
901 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
902 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
903 break;
904 case PCI_DEVICE_ID_VIA_8237:
905 case PCI_DEVICE_ID_VIA_8237A:
906 via_vlink_dev_lo = 15;
907 break;
908 case PCI_DEVICE_ID_VIA_8235:
909 via_vlink_dev_lo = 16;
910 break;
911 case PCI_DEVICE_ID_VIA_8231:
912 case PCI_DEVICE_ID_VIA_8233_0:
913 case PCI_DEVICE_ID_VIA_8233A:
914 case PCI_DEVICE_ID_VIA_8233C_0:
915 via_vlink_dev_lo = 17;
916 break;
917 }
918 }
919 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
920 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
921 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
922 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
924 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
925 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
926 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
927
928 /**
929 * quirk_via_vlink - VIA VLink IRQ number update
930 * @dev: PCI device
931 *
932 * If the device we are dealing with is on a PIC IRQ we need to
933 * ensure that the IRQ line register which usually is not relevant
934 * for PCI cards, is actually written so that interrupts get sent
935 * to the right place.
936 * We only do this on systems where a VIA south bridge was detected,
937 * and only for VIA devices on the motherboard (see quirk_via_bridge
938 * above).
939 */
940
941 static void quirk_via_vlink(struct pci_dev *dev)
942 {
943 u8 irq, new_irq;
944
945 /* Check if we have VLink at all */
946 if (via_vlink_dev_lo == -1)
947 return;
948
949 new_irq = dev->irq;
950
951 /* Don't quirk interrupts outside the legacy IRQ range */
952 if (!new_irq || new_irq > 15)
953 return;
954
955 /* Internal device ? */
956 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
957 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
958 return;
959
960 /* This is an internal VLink device on a PIC interrupt. The BIOS
961 ought to have set this but may not have, so we redo it */
962
963 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
964 if (new_irq != irq) {
965 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
966 irq, new_irq);
967 udelay(15); /* unknown if delay really needed */
968 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
969 }
970 }
971 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
972
973 /*
974 * VIA VT82C598 has its device ID settable and many BIOSes
975 * set it to the ID of VT82C597 for backward compatibility.
976 * We need to switch it off to be able to recognize the real
977 * type of the chip.
978 */
979 static void quirk_vt82c598_id(struct pci_dev *dev)
980 {
981 pci_write_config_byte(dev, 0xfc, 0);
982 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
983 }
984 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
985
986 /*
987 * CardBus controllers have a legacy base address that enables them
988 * to respond as i82365 pcmcia controllers. We don't want them to
989 * do this even if the Linux CardBus driver is not loaded, because
990 * the Linux i82365 driver does not (and should not) handle CardBus.
991 */
992 static void quirk_cardbus_legacy(struct pci_dev *dev)
993 {
994 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
995 }
996 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
998 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
999 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
1000
1001 /*
1002 * Following the PCI ordering rules is optional on the AMD762. I'm not
1003 * sure what the designers were smoking but let's not inhale...
1004 *
1005 * To be fair to AMD, it follows the spec by default, its BIOS people
1006 * who turn it off!
1007 */
1008 static void quirk_amd_ordering(struct pci_dev *dev)
1009 {
1010 u32 pcic;
1011 pci_read_config_dword(dev, 0x4C, &pcic);
1012 if ((pcic & 6) != 6) {
1013 pcic |= 6;
1014 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1015 pci_write_config_dword(dev, 0x4C, pcic);
1016 pci_read_config_dword(dev, 0x84, &pcic);
1017 pcic |= (1 << 23); /* Required in this mode */
1018 pci_write_config_dword(dev, 0x84, pcic);
1019 }
1020 }
1021 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1022 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1023
1024 /*
1025 * DreamWorks provided workaround for Dunord I-3000 problem
1026 *
1027 * This card decodes and responds to addresses not apparently
1028 * assigned to it. We force a larger allocation to ensure that
1029 * nothing gets put too close to it.
1030 */
1031 static void quirk_dunord(struct pci_dev *dev)
1032 {
1033 struct resource *r = &dev->resource[1];
1034
1035 r->flags |= IORESOURCE_UNSET;
1036 r->start = 0;
1037 r->end = 0xffffff;
1038 }
1039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1040
1041 /*
1042 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1043 * is subtractive decoding (transparent), and does indicate this
1044 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1045 * instead of 0x01.
1046 */
1047 static void quirk_transparent_bridge(struct pci_dev *dev)
1048 {
1049 dev->transparent = 1;
1050 }
1051 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1052 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1053
1054 /*
1055 * Common misconfiguration of the MediaGX/Geode PCI master that will
1056 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
1057 * datasheets found at http://www.national.com/analog for info on what
1058 * these bits do. <christer@weinigel.se>
1059 */
1060 static void quirk_mediagx_master(struct pci_dev *dev)
1061 {
1062 u8 reg;
1063
1064 pci_read_config_byte(dev, 0x41, &reg);
1065 if (reg & 2) {
1066 reg &= ~2;
1067 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1068 reg);
1069 pci_write_config_byte(dev, 0x41, reg);
1070 }
1071 }
1072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1073 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1074
1075 /*
1076 * Ensure C0 rev restreaming is off. This is normally done by
1077 * the BIOS but in the odd case it is not the results are corruption
1078 * hence the presence of a Linux check
1079 */
1080 static void quirk_disable_pxb(struct pci_dev *pdev)
1081 {
1082 u16 config;
1083
1084 if (pdev->revision != 0x04) /* Only C0 requires this */
1085 return;
1086 pci_read_config_word(pdev, 0x40, &config);
1087 if (config & (1<<6)) {
1088 config &= ~(1<<6);
1089 pci_write_config_word(pdev, 0x40, config);
1090 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
1091 }
1092 }
1093 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1094 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1095
1096 static void quirk_amd_ide_mode(struct pci_dev *pdev)
1097 {
1098 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
1099 u8 tmp;
1100
1101 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1102 if (tmp == 0x01) {
1103 pci_read_config_byte(pdev, 0x40, &tmp);
1104 pci_write_config_byte(pdev, 0x40, tmp|1);
1105 pci_write_config_byte(pdev, 0x9, 1);
1106 pci_write_config_byte(pdev, 0xa, 6);
1107 pci_write_config_byte(pdev, 0x40, tmp);
1108
1109 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1110 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
1111 }
1112 }
1113 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1114 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1115 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1118 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1119 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1120 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1121
1122 /*
1123 * Serverworks CSB5 IDE does not fully support native mode
1124 */
1125 static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1126 {
1127 u8 prog;
1128 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1129 if (prog & 5) {
1130 prog &= ~5;
1131 pdev->class &= ~5;
1132 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1133 /* PCI layer will sort out resources */
1134 }
1135 }
1136 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1137
1138 /*
1139 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1140 */
1141 static void quirk_ide_samemode(struct pci_dev *pdev)
1142 {
1143 u8 prog;
1144
1145 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1146
1147 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1148 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
1149 prog &= ~5;
1150 pdev->class &= ~5;
1151 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1152 }
1153 }
1154 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1155
1156 /*
1157 * Some ATA devices break if put into D3
1158 */
1159
1160 static void quirk_no_ata_d3(struct pci_dev *pdev)
1161 {
1162 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1163 }
1164 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1165 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1167 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1168 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1169 /* ALi loses some register settings that we cannot then restore */
1170 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1171 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1172 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1173 occur when mode detecting */
1174 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1175 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1176
1177 /* This was originally an Alpha specific thing, but it really fits here.
1178 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1179 */
1180 static void quirk_eisa_bridge(struct pci_dev *dev)
1181 {
1182 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1183 }
1184 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1185
1186
1187 /*
1188 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1189 * is not activated. The myth is that Asus said that they do not want the
1190 * users to be irritated by just another PCI Device in the Win98 device
1191 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1192 * package 2.7.0 for details)
1193 *
1194 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1195 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
1196 * becomes necessary to do this tweak in two steps -- the chosen trigger
1197 * is either the Host bridge (preferred) or on-board VGA controller.
1198 *
1199 * Note that we used to unhide the SMBus that way on Toshiba laptops
1200 * (Satellite A40 and Tecra M2) but then found that the thermal management
1201 * was done by SMM code, which could cause unsynchronized concurrent
1202 * accesses to the SMBus registers, with potentially bad effects. Thus you
1203 * should be very careful when adding new entries: if SMM is accessing the
1204 * Intel SMBus, this is a very good reason to leave it hidden.
1205 *
1206 * Likewise, many recent laptops use ACPI for thermal management. If the
1207 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1208 * natively, and keeping the SMBus hidden is the right thing to do. If you
1209 * are about to add an entry in the table below, please first disassemble
1210 * the DSDT and double-check that there is no code accessing the SMBus.
1211 */
1212 static int asus_hides_smbus;
1213
1214 static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1215 {
1216 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1217 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1218 switch (dev->subsystem_device) {
1219 case 0x8025: /* P4B-LX */
1220 case 0x8070: /* P4B */
1221 case 0x8088: /* P4B533 */
1222 case 0x1626: /* L3C notebook */
1223 asus_hides_smbus = 1;
1224 }
1225 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1226 switch (dev->subsystem_device) {
1227 case 0x80b1: /* P4GE-V */
1228 case 0x80b2: /* P4PE */
1229 case 0x8093: /* P4B533-V */
1230 asus_hides_smbus = 1;
1231 }
1232 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1233 switch (dev->subsystem_device) {
1234 case 0x8030: /* P4T533 */
1235 asus_hides_smbus = 1;
1236 }
1237 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1238 switch (dev->subsystem_device) {
1239 case 0x8070: /* P4G8X Deluxe */
1240 asus_hides_smbus = 1;
1241 }
1242 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1243 switch (dev->subsystem_device) {
1244 case 0x80c9: /* PU-DLS */
1245 asus_hides_smbus = 1;
1246 }
1247 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1248 switch (dev->subsystem_device) {
1249 case 0x1751: /* M2N notebook */
1250 case 0x1821: /* M5N notebook */
1251 case 0x1897: /* A6L notebook */
1252 asus_hides_smbus = 1;
1253 }
1254 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1255 switch (dev->subsystem_device) {
1256 case 0x184b: /* W1N notebook */
1257 case 0x186a: /* M6Ne notebook */
1258 asus_hides_smbus = 1;
1259 }
1260 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1261 switch (dev->subsystem_device) {
1262 case 0x80f2: /* P4P800-X */
1263 asus_hides_smbus = 1;
1264 }
1265 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1266 switch (dev->subsystem_device) {
1267 case 0x1882: /* M6V notebook */
1268 case 0x1977: /* A6VA notebook */
1269 asus_hides_smbus = 1;
1270 }
1271 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1272 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1273 switch (dev->subsystem_device) {
1274 case 0x088C: /* HP Compaq nc8000 */
1275 case 0x0890: /* HP Compaq nc6000 */
1276 asus_hides_smbus = 1;
1277 }
1278 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1279 switch (dev->subsystem_device) {
1280 case 0x12bc: /* HP D330L */
1281 case 0x12bd: /* HP D530 */
1282 case 0x006a: /* HP Compaq nx9500 */
1283 asus_hides_smbus = 1;
1284 }
1285 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1286 switch (dev->subsystem_device) {
1287 case 0x12bf: /* HP xw4100 */
1288 asus_hides_smbus = 1;
1289 }
1290 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1291 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1292 switch (dev->subsystem_device) {
1293 case 0xC00C: /* Samsung P35 notebook */
1294 asus_hides_smbus = 1;
1295 }
1296 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1297 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1298 switch (dev->subsystem_device) {
1299 case 0x0058: /* Compaq Evo N620c */
1300 asus_hides_smbus = 1;
1301 }
1302 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1303 switch (dev->subsystem_device) {
1304 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1305 /* Motherboard doesn't have Host bridge
1306 * subvendor/subdevice IDs, therefore checking
1307 * its on-board VGA controller */
1308 asus_hides_smbus = 1;
1309 }
1310 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1311 switch (dev->subsystem_device) {
1312 case 0x00b8: /* Compaq Evo D510 CMT */
1313 case 0x00b9: /* Compaq Evo D510 SFF */
1314 case 0x00ba: /* Compaq Evo D510 USDT */
1315 /* Motherboard doesn't have Host bridge
1316 * subvendor/subdevice IDs and on-board VGA
1317 * controller is disabled if an AGP card is
1318 * inserted, therefore checking USB UHCI
1319 * Controller #1 */
1320 asus_hides_smbus = 1;
1321 }
1322 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1323 switch (dev->subsystem_device) {
1324 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1325 /* Motherboard doesn't have host bridge
1326 * subvendor/subdevice IDs, therefore checking
1327 * its on-board VGA controller */
1328 asus_hides_smbus = 1;
1329 }
1330 }
1331 }
1332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1337 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1342
1343 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1345 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1346
1347 static void asus_hides_smbus_lpc(struct pci_dev *dev)
1348 {
1349 u16 val;
1350
1351 if (likely(!asus_hides_smbus))
1352 return;
1353
1354 pci_read_config_word(dev, 0xF2, &val);
1355 if (val & 0x8) {
1356 pci_write_config_word(dev, 0xF2, val & (~0x8));
1357 pci_read_config_word(dev, 0xF2, &val);
1358 if (val & 0x8)
1359 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1360 val);
1361 else
1362 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1363 }
1364 }
1365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1369 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1370 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1372 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1373 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1374 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1375 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1376 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1377 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1378 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1379
1380 /* It appears we just have one such device. If not, we have a warning */
1381 static void __iomem *asus_rcba_base;
1382 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1383 {
1384 u32 rcba;
1385
1386 if (likely(!asus_hides_smbus))
1387 return;
1388 WARN_ON(asus_rcba_base);
1389
1390 pci_read_config_dword(dev, 0xF0, &rcba);
1391 /* use bits 31:14, 16 kB aligned */
1392 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1393 if (asus_rcba_base == NULL)
1394 return;
1395 }
1396
1397 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1398 {
1399 u32 val;
1400
1401 if (likely(!asus_hides_smbus || !asus_rcba_base))
1402 return;
1403 /* read the Function Disable register, dword mode only */
1404 val = readl(asus_rcba_base + 0x3418);
1405 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1406 }
1407
1408 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1409 {
1410 if (likely(!asus_hides_smbus || !asus_rcba_base))
1411 return;
1412 iounmap(asus_rcba_base);
1413 asus_rcba_base = NULL;
1414 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1415 }
1416
1417 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1418 {
1419 asus_hides_smbus_lpc_ich6_suspend(dev);
1420 asus_hides_smbus_lpc_ich6_resume_early(dev);
1421 asus_hides_smbus_lpc_ich6_resume(dev);
1422 }
1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1424 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1425 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1426 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1427
1428 /*
1429 * SiS 96x south bridge: BIOS typically hides SMBus device...
1430 */
1431 static void quirk_sis_96x_smbus(struct pci_dev *dev)
1432 {
1433 u8 val = 0;
1434 pci_read_config_byte(dev, 0x77, &val);
1435 if (val & 0x10) {
1436 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1437 pci_write_config_byte(dev, 0x77, val & ~0x10);
1438 }
1439 }
1440 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1441 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1442 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1443 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1444 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1445 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1446 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1447 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1448
1449 /*
1450 * ... This is further complicated by the fact that some SiS96x south
1451 * bridges pretend to be 85C503/5513 instead. In that case see if we
1452 * spotted a compatible north bridge to make sure.
1453 * (pci_find_device doesn't work yet)
1454 *
1455 * We can also enable the sis96x bit in the discovery register..
1456 */
1457 #define SIS_DETECT_REGISTER 0x40
1458
1459 static void quirk_sis_503(struct pci_dev *dev)
1460 {
1461 u8 reg;
1462 u16 devid;
1463
1464 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1465 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1466 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1467 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1468 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1469 return;
1470 }
1471
1472 /*
1473 * Ok, it now shows up as a 96x.. run the 96x quirk by
1474 * hand in case it has already been processed.
1475 * (depends on link order, which is apparently not guaranteed)
1476 */
1477 dev->device = devid;
1478 quirk_sis_96x_smbus(dev);
1479 }
1480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1481 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1482
1483
1484 /*
1485 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1486 * and MC97 modem controller are disabled when a second PCI soundcard is
1487 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1488 * -- bjd
1489 */
1490 static void asus_hides_ac97_lpc(struct pci_dev *dev)
1491 {
1492 u8 val;
1493 int asus_hides_ac97 = 0;
1494
1495 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1496 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1497 asus_hides_ac97 = 1;
1498 }
1499
1500 if (!asus_hides_ac97)
1501 return;
1502
1503 pci_read_config_byte(dev, 0x50, &val);
1504 if (val & 0xc0) {
1505 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1506 pci_read_config_byte(dev, 0x50, &val);
1507 if (val & 0xc0)
1508 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1509 val);
1510 else
1511 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1512 }
1513 }
1514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1515 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1516
1517 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1518
1519 /*
1520 * If we are using libata we can drive this chip properly but must
1521 * do this early on to make the additional device appear during
1522 * the PCI scanning.
1523 */
1524 static void quirk_jmicron_ata(struct pci_dev *pdev)
1525 {
1526 u32 conf1, conf5, class;
1527 u8 hdr;
1528
1529 /* Only poke fn 0 */
1530 if (PCI_FUNC(pdev->devfn))
1531 return;
1532
1533 pci_read_config_dword(pdev, 0x40, &conf1);
1534 pci_read_config_dword(pdev, 0x80, &conf5);
1535
1536 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1537 conf5 &= ~(1 << 24); /* Clear bit 24 */
1538
1539 switch (pdev->device) {
1540 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1541 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
1542 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
1543 /* The controller should be in single function ahci mode */
1544 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1545 break;
1546
1547 case PCI_DEVICE_ID_JMICRON_JMB365:
1548 case PCI_DEVICE_ID_JMICRON_JMB366:
1549 /* Redirect IDE second PATA port to the right spot */
1550 conf5 |= (1 << 24);
1551 /* Fall through */
1552 case PCI_DEVICE_ID_JMICRON_JMB361:
1553 case PCI_DEVICE_ID_JMICRON_JMB363:
1554 case PCI_DEVICE_ID_JMICRON_JMB369:
1555 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1556 /* Set the class codes correctly and then direct IDE 0 */
1557 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
1558 break;
1559
1560 case PCI_DEVICE_ID_JMICRON_JMB368:
1561 /* The controller should be in single function IDE mode */
1562 conf1 |= 0x00C00000; /* Set 22, 23 */
1563 break;
1564 }
1565
1566 pci_write_config_dword(pdev, 0x40, conf1);
1567 pci_write_config_dword(pdev, 0x80, conf5);
1568
1569 /* Update pdev accordingly */
1570 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1571 pdev->hdr_type = hdr & 0x7f;
1572 pdev->multifunction = !!(hdr & 0x80);
1573
1574 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1575 pdev->class = class >> 8;
1576 }
1577 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1578 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1579 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1580 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1581 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1582 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1583 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1584 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1585 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1586 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1587 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1588 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1589 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1590 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1591 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1592 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1593 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1594 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1595
1596 #endif
1597
1598 static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1599 {
1600 if (dev->multifunction) {
1601 device_disable_async_suspend(&dev->dev);
1602 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1603 }
1604 }
1605 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1606 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1609
1610 #ifdef CONFIG_X86_IO_APIC
1611 static void quirk_alder_ioapic(struct pci_dev *pdev)
1612 {
1613 int i;
1614
1615 if ((pdev->class >> 8) != 0xff00)
1616 return;
1617
1618 /* the first BAR is the location of the IO APIC...we must
1619 * not touch this (and it's already covered by the fixmap), so
1620 * forcibly insert it into the resource tree */
1621 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1622 insert_resource(&iomem_resource, &pdev->resource[0]);
1623
1624 /* The next five BARs all seem to be rubbish, so just clean
1625 * them out */
1626 for (i = 1; i < 6; i++)
1627 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1628 }
1629 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1630 #endif
1631
1632 static void quirk_pcie_mch(struct pci_dev *pdev)
1633 {
1634 pdev->no_msi = 1;
1635 }
1636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1637 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1638 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1639 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, quirk_pcie_mch);
1640
1641
1642 /*
1643 * It's possible for the MSI to get corrupted if shpc and acpi
1644 * are used together on certain PXH-based systems.
1645 */
1646 static void quirk_pcie_pxh(struct pci_dev *dev)
1647 {
1648 dev->no_msi = 1;
1649 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1650 }
1651 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1652 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1653 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1654 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1655 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1656
1657 /*
1658 * Some Intel PCI Express chipsets have trouble with downstream
1659 * device power management.
1660 */
1661 static void quirk_intel_pcie_pm(struct pci_dev *dev)
1662 {
1663 pci_pm_d3_delay = 120;
1664 dev->no_d1d2 = 1;
1665 }
1666
1667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1668 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1669 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1670 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1671 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1672 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1673 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1674 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1675 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1676 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1677 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1678 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1680 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1682 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1688
1689 static void quirk_radeon_pm(struct pci_dev *dev)
1690 {
1691 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1692 dev->subsystem_device == 0x00e2) {
1693 if (dev->d3_delay < 20) {
1694 dev->d3_delay = 20;
1695 dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
1696 dev->d3_delay);
1697 }
1698 }
1699 }
1700 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1701
1702 #ifdef CONFIG_X86_IO_APIC
1703 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1704 {
1705 noioapicreroute = 1;
1706 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1707
1708 return 0;
1709 }
1710
1711 static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1712 /*
1713 * Systems to exclude from boot interrupt reroute quirks
1714 */
1715 {
1716 .callback = dmi_disable_ioapicreroute,
1717 .ident = "ASUSTek Computer INC. M2N-LR",
1718 .matches = {
1719 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1720 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1721 },
1722 },
1723 {}
1724 };
1725
1726 /*
1727 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1728 * remap the original interrupt in the linux kernel to the boot interrupt, so
1729 * that a PCI device's interrupt handler is installed on the boot interrupt
1730 * line instead.
1731 */
1732 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1733 {
1734 dmi_check_system(boot_interrupt_dmi_table);
1735 if (noioapicquirk || noioapicreroute)
1736 return;
1737
1738 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1739 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1740 dev->vendor, dev->device);
1741 }
1742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1743 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1744 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1746 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1747 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1748 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1749 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1750 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1751 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1752 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1753 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1754 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1755 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1756 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1757 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1758
1759 /*
1760 * On some chipsets we can disable the generation of legacy INTx boot
1761 * interrupts.
1762 */
1763
1764 /*
1765 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1766 * 300641-004US, section 5.7.3.
1767 */
1768 #define INTEL_6300_IOAPIC_ABAR 0x40
1769 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1770
1771 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1772 {
1773 u16 pci_config_word;
1774
1775 if (noioapicquirk)
1776 return;
1777
1778 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1779 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1780 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1781
1782 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1783 dev->vendor, dev->device);
1784 }
1785 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1786 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1787
1788 /*
1789 * disable boot interrupts on HT-1000
1790 */
1791 #define BC_HT1000_FEATURE_REG 0x64
1792 #define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1793 #define BC_HT1000_MAP_IDX 0xC00
1794 #define BC_HT1000_MAP_DATA 0xC01
1795
1796 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1797 {
1798 u32 pci_config_dword;
1799 u8 irq;
1800
1801 if (noioapicquirk)
1802 return;
1803
1804 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1805 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1806 BC_HT1000_PIC_REGS_ENABLE);
1807
1808 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1809 outb(irq, BC_HT1000_MAP_IDX);
1810 outb(0x00, BC_HT1000_MAP_DATA);
1811 }
1812
1813 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1814
1815 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1816 dev->vendor, dev->device);
1817 }
1818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1819 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1820
1821 /*
1822 * disable boot interrupts on AMD and ATI chipsets
1823 */
1824 /*
1825 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1826 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1827 * (due to an erratum).
1828 */
1829 #define AMD_813X_MISC 0x40
1830 #define AMD_813X_NOIOAMODE (1<<0)
1831 #define AMD_813X_REV_B1 0x12
1832 #define AMD_813X_REV_B2 0x13
1833
1834 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1835 {
1836 u32 pci_config_dword;
1837
1838 if (noioapicquirk)
1839 return;
1840 if ((dev->revision == AMD_813X_REV_B1) ||
1841 (dev->revision == AMD_813X_REV_B2))
1842 return;
1843
1844 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1845 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1846 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1847
1848 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1849 dev->vendor, dev->device);
1850 }
1851 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1852 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1853 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1854 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1855
1856 #define AMD_8111_PCI_IRQ_ROUTING 0x56
1857
1858 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1859 {
1860 u16 pci_config_word;
1861
1862 if (noioapicquirk)
1863 return;
1864
1865 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1866 if (!pci_config_word) {
1867 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1868 dev->vendor, dev->device);
1869 return;
1870 }
1871 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1872 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1873 dev->vendor, dev->device);
1874 }
1875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1876 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1877 #endif /* CONFIG_X86_IO_APIC */
1878
1879 /*
1880 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1881 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1882 * Re-allocate the region if needed...
1883 */
1884 static void quirk_tc86c001_ide(struct pci_dev *dev)
1885 {
1886 struct resource *r = &dev->resource[0];
1887
1888 if (r->start & 0x8) {
1889 r->flags |= IORESOURCE_UNSET;
1890 r->start = 0;
1891 r->end = 0xf;
1892 }
1893 }
1894 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1895 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1896 quirk_tc86c001_ide);
1897
1898 /*
1899 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1900 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1901 * being read correctly if bit 7 of the base address is set.
1902 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1903 * Re-allocate the regions to a 256-byte boundary if necessary.
1904 */
1905 static void quirk_plx_pci9050(struct pci_dev *dev)
1906 {
1907 unsigned int bar;
1908
1909 /* Fixed in revision 2 (PCI 9052). */
1910 if (dev->revision >= 2)
1911 return;
1912 for (bar = 0; bar <= 1; bar++)
1913 if (pci_resource_len(dev, bar) == 0x80 &&
1914 (pci_resource_start(dev, bar) & 0x80)) {
1915 struct resource *r = &dev->resource[bar];
1916 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1917 bar);
1918 r->flags |= IORESOURCE_UNSET;
1919 r->start = 0;
1920 r->end = 0xff;
1921 }
1922 }
1923 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1924 quirk_plx_pci9050);
1925 /*
1926 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1927 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1928 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1929 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1930 *
1931 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1932 * driver.
1933 */
1934 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1935 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1936
1937 static void quirk_netmos(struct pci_dev *dev)
1938 {
1939 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1940 unsigned int num_serial = dev->subsystem_device & 0xf;
1941
1942 /*
1943 * These Netmos parts are multiport serial devices with optional
1944 * parallel ports. Even when parallel ports are present, they
1945 * are identified as class SERIAL, which means the serial driver
1946 * will claim them. To prevent this, mark them as class OTHER.
1947 * These combo devices should be claimed by parport_serial.
1948 *
1949 * The subdevice ID is of the form 0x00PS, where <P> is the number
1950 * of parallel ports and <S> is the number of serial ports.
1951 */
1952 switch (dev->device) {
1953 case PCI_DEVICE_ID_NETMOS_9835:
1954 /* Well, this rule doesn't hold for the following 9835 device */
1955 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1956 dev->subsystem_device == 0x0299)
1957 return;
1958 case PCI_DEVICE_ID_NETMOS_9735:
1959 case PCI_DEVICE_ID_NETMOS_9745:
1960 case PCI_DEVICE_ID_NETMOS_9845:
1961 case PCI_DEVICE_ID_NETMOS_9855:
1962 if (num_parallel) {
1963 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1964 dev->device, num_parallel, num_serial);
1965 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1966 (dev->class & 0xff);
1967 }
1968 }
1969 }
1970 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1971 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1972
1973 /*
1974 * Quirk non-zero PCI functions to route VPD access through function 0 for
1975 * devices that share VPD resources between functions. The functions are
1976 * expected to be identical devices.
1977 */
1978 static void quirk_f0_vpd_link(struct pci_dev *dev)
1979 {
1980 struct pci_dev *f0;
1981
1982 if (!PCI_FUNC(dev->devfn))
1983 return;
1984
1985 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1986 if (!f0)
1987 return;
1988
1989 if (f0->vpd && dev->class == f0->class &&
1990 dev->vendor == f0->vendor && dev->device == f0->device)
1991 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1992
1993 pci_dev_put(f0);
1994 }
1995 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1996 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1997
1998 static void quirk_e100_interrupt(struct pci_dev *dev)
1999 {
2000 u16 command, pmcsr;
2001 u8 __iomem *csr;
2002 u8 cmd_hi;
2003
2004 switch (dev->device) {
2005 /* PCI IDs taken from drivers/net/e100.c */
2006 case 0x1029:
2007 case 0x1030 ... 0x1034:
2008 case 0x1038 ... 0x103E:
2009 case 0x1050 ... 0x1057:
2010 case 0x1059:
2011 case 0x1064 ... 0x106B:
2012 case 0x1091 ... 0x1095:
2013 case 0x1209:
2014 case 0x1229:
2015 case 0x2449:
2016 case 0x2459:
2017 case 0x245D:
2018 case 0x27DC:
2019 break;
2020 default:
2021 return;
2022 }
2023
2024 /*
2025 * Some firmware hands off the e100 with interrupts enabled,
2026 * which can cause a flood of interrupts if packets are
2027 * received before the driver attaches to the device. So
2028 * disable all e100 interrupts here. The driver will
2029 * re-enable them when it's ready.
2030 */
2031 pci_read_config_word(dev, PCI_COMMAND, &command);
2032
2033 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2034 return;
2035
2036 /*
2037 * Check that the device is in the D0 power state. If it's not,
2038 * there is no point to look any further.
2039 */
2040 if (dev->pm_cap) {
2041 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2042 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2043 return;
2044 }
2045
2046 /* Convert from PCI bus to resource space. */
2047 csr = ioremap(pci_resource_start(dev, 0), 8);
2048 if (!csr) {
2049 dev_warn(&dev->dev, "Can't map e100 registers\n");
2050 return;
2051 }
2052
2053 cmd_hi = readb(csr + 3);
2054 if (cmd_hi == 0) {
2055 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
2056 writeb(1, csr + 3);
2057 }
2058
2059 iounmap(csr);
2060 }
2061 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2062 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2063
2064 /*
2065 * The 82575 and 82598 may experience data corruption issues when transitioning
2066 * out of L0S. To prevent this we need to disable L0S on the PCIe link.
2067 */
2068 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2069 {
2070 dev_info(&dev->dev, "Disabling L0s\n");
2071 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2072 }
2073 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2075 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2077 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2081 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2083 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2087
2088 static void fixup_rev1_53c810(struct pci_dev *dev)
2089 {
2090 u32 class = dev->class;
2091
2092 /*
2093 * rev 1 ncr53c810 chips don't set the class at all which means
2094 * they don't get their resources remapped. Fix that here.
2095 */
2096 if (class)
2097 return;
2098
2099 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2100 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2101 class, dev->class);
2102 }
2103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2104
2105 /* Enable 1k I/O space granularity on the Intel P64H2 */
2106 static void quirk_p64h2_1k_io(struct pci_dev *dev)
2107 {
2108 u16 en1k;
2109
2110 pci_read_config_word(dev, 0x40, &en1k);
2111
2112 if (en1k & 0x200) {
2113 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
2114 dev->io_window_1k = 1;
2115 }
2116 }
2117 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2118
2119 /* Under some circumstances, AER is not linked with extended capabilities.
2120 * Force it to be linked by setting the corresponding control bit in the
2121 * config space.
2122 */
2123 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2124 {
2125 uint8_t b;
2126 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2127 if (!(b & 0x20)) {
2128 pci_write_config_byte(dev, 0xf41, b | 0x20);
2129 dev_info(&dev->dev, "Linking AER extended capability\n");
2130 }
2131 }
2132 }
2133 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2134 quirk_nvidia_ck804_pcie_aer_ext_cap);
2135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2136 quirk_nvidia_ck804_pcie_aer_ext_cap);
2137
2138 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2139 {
2140 /*
2141 * Disable PCI Bus Parking and PCI Master read caching on CX700
2142 * which causes unspecified timing errors with a VT6212L on the PCI
2143 * bus leading to USB2.0 packet loss.
2144 *
2145 * This quirk is only enabled if a second (on the external PCI bus)
2146 * VT6212L is found -- the CX700 core itself also contains a USB
2147 * host controller with the same PCI ID as the VT6212L.
2148 */
2149
2150 /* Count VT6212L instances */
2151 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2152 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2153 uint8_t b;
2154
2155 /* p should contain the first (internal) VT6212L -- see if we have
2156 an external one by searching again */
2157 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2158 if (!p)
2159 return;
2160 pci_dev_put(p);
2161
2162 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2163 if (b & 0x40) {
2164 /* Turn off PCI Bus Parking */
2165 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2166
2167 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
2168 }
2169 }
2170
2171 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2172 if (b != 0) {
2173 /* Turn off PCI Master read caching */
2174 pci_write_config_byte(dev, 0x72, 0x0);
2175
2176 /* Set PCI Master Bus time-out to "1x16 PCLK" */
2177 pci_write_config_byte(dev, 0x75, 0x1);
2178
2179 /* Disable "Read FIFO Timer" */
2180 pci_write_config_byte(dev, 0x77, 0x0);
2181
2182 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
2183 }
2184 }
2185 }
2186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2187
2188 /*
2189 * If a device follows the VPD format spec, the PCI core will not read or
2190 * write past the VPD End Tag. But some vendors do not follow the VPD
2191 * format spec, so we can't tell how much data is safe to access. Devices
2192 * may behave unpredictably if we access too much. Blacklist these devices
2193 * so we don't touch VPD at all.
2194 */
2195 static void quirk_blacklist_vpd(struct pci_dev *dev)
2196 {
2197 if (dev->vpd) {
2198 dev->vpd->len = 0;
2199 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
2200 }
2201 }
2202
2203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2204 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2208 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2215 quirk_blacklist_vpd);
2216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
2217
2218 /*
2219 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2220 * VPD end tag will hang the device. This problem was initially
2221 * observed when a vpd entry was created in sysfs
2222 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2223 * will dump 32k of data. Reading a full 32k will cause an access
2224 * beyond the VPD end tag causing the device to hang. Once the device
2225 * is hung, the bnx2 driver will not be able to reset the device.
2226 * We believe that it is legal to read beyond the end tag and
2227 * therefore the solution is to limit the read/write length.
2228 */
2229 static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2230 {
2231 /*
2232 * Only disable the VPD capability for 5706, 5706S, 5708,
2233 * 5708S and 5709 rev. A
2234 */
2235 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
2236 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
2237 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
2238 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
2239 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2240 (dev->revision & 0xf0) == 0x0)) {
2241 if (dev->vpd)
2242 dev->vpd->len = 0x80;
2243 }
2244 }
2245
2246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2247 PCI_DEVICE_ID_NX2_5706,
2248 quirk_brcm_570x_limit_vpd);
2249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2250 PCI_DEVICE_ID_NX2_5706S,
2251 quirk_brcm_570x_limit_vpd);
2252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2253 PCI_DEVICE_ID_NX2_5708,
2254 quirk_brcm_570x_limit_vpd);
2255 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2256 PCI_DEVICE_ID_NX2_5708S,
2257 quirk_brcm_570x_limit_vpd);
2258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2259 PCI_DEVICE_ID_NX2_5709,
2260 quirk_brcm_570x_limit_vpd);
2261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2262 PCI_DEVICE_ID_NX2_5709S,
2263 quirk_brcm_570x_limit_vpd);
2264
2265 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2266 {
2267 u32 rev;
2268
2269 pci_read_config_dword(dev, 0xf4, &rev);
2270
2271 /* Only CAP the MRRS if the device is a 5719 A0 */
2272 if (rev == 0x05719000) {
2273 int readrq = pcie_get_readrq(dev);
2274 if (readrq > 2048)
2275 pcie_set_readrq(dev, 2048);
2276 }
2277 }
2278
2279 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2280 PCI_DEVICE_ID_TIGON3_5719,
2281 quirk_brcm_5719_limit_mrrs);
2282
2283 #ifdef CONFIG_PCIE_IPROC_PLATFORM
2284 static void quirk_paxc_bridge(struct pci_dev *pdev)
2285 {
2286 /* The PCI config space is shared with the PAXC root port and the first
2287 * Ethernet device. So, we need to workaround this by telling the PCI
2288 * code that the bridge is not an Ethernet device.
2289 */
2290 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2291 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2292
2293 /* MPSS is not being set properly (as it is currently 0). This is
2294 * because that area of the PCI config space is hard coded to zero, and
2295 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2296 * so that the MPS can be set to the real max value.
2297 */
2298 pdev->pcie_mpss = 2;
2299 }
2300 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2301 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2302 #endif
2303
2304 /* Originally in EDAC sources for i82875P:
2305 * Intel tells BIOS developers to hide device 6 which
2306 * configures the overflow device access containing
2307 * the DRBs - this is where we expose device 6.
2308 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2309 */
2310 static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2311 {
2312 u8 reg;
2313
2314 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2315 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2316 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2317 }
2318 }
2319
2320 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2321 quirk_unhide_mch_dev6);
2322 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2323 quirk_unhide_mch_dev6);
2324
2325 #ifdef CONFIG_TILEPRO
2326 /*
2327 * The Tilera TILEmpower tilepro platform needs to set the link speed
2328 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2329 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2330 * capability register of the PEX8624 PCIe switch. The switch
2331 * supports link speed auto negotiation, but falsely sets
2332 * the link speed to 5GT/s.
2333 */
2334 static void quirk_tile_plx_gen1(struct pci_dev *dev)
2335 {
2336 if (tile_plx_gen1) {
2337 pci_write_config_dword(dev, 0x98, 0x1);
2338 mdelay(50);
2339 }
2340 }
2341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2342 #endif /* CONFIG_TILEPRO */
2343
2344 #ifdef CONFIG_PCI_MSI
2345 /* Some chipsets do not support MSI. We cannot easily rely on setting
2346 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2347 * some other buses controlled by the chipset even if Linux is not
2348 * aware of it. Instead of setting the flag on all buses in the
2349 * machine, simply disable MSI globally.
2350 */
2351 static void quirk_disable_all_msi(struct pci_dev *dev)
2352 {
2353 pci_no_msi();
2354 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
2355 }
2356 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2357 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2358 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2359 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2360 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2361 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2362 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2363 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2364
2365 /* Disable MSI on chipsets that are known to not support it */
2366 static void quirk_disable_msi(struct pci_dev *dev)
2367 {
2368 if (dev->subordinate) {
2369 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2370 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2371 }
2372 }
2373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2376
2377 /*
2378 * The APC bridge device in AMD 780 family northbridges has some random
2379 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2380 * we use the possible vendor/device IDs of the host bridge for the
2381 * declared quirk, and search for the APC bridge by slot number.
2382 */
2383 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2384 {
2385 struct pci_dev *apc_bridge;
2386
2387 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2388 if (apc_bridge) {
2389 if (apc_bridge->device == 0x9602)
2390 quirk_disable_msi(apc_bridge);
2391 pci_dev_put(apc_bridge);
2392 }
2393 }
2394 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2395 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2396
2397 /* Go through the list of Hypertransport capabilities and
2398 * return 1 if a HT MSI capability is found and enabled */
2399 static int msi_ht_cap_enabled(struct pci_dev *dev)
2400 {
2401 int pos, ttl = PCI_FIND_CAP_TTL;
2402
2403 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2404 while (pos && ttl--) {
2405 u8 flags;
2406
2407 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2408 &flags) == 0) {
2409 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
2410 flags & HT_MSI_FLAGS_ENABLE ?
2411 "enabled" : "disabled");
2412 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2413 }
2414
2415 pos = pci_find_next_ht_capability(dev, pos,
2416 HT_CAPTYPE_MSI_MAPPING);
2417 }
2418 return 0;
2419 }
2420
2421 /* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2422 static void quirk_msi_ht_cap(struct pci_dev *dev)
2423 {
2424 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2425 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2426 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2427 }
2428 }
2429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2430 quirk_msi_ht_cap);
2431
2432 /* The nVidia CK804 chipset may have 2 HT MSI mappings.
2433 * MSI are supported if the MSI capability set in any of these mappings.
2434 */
2435 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2436 {
2437 struct pci_dev *pdev;
2438
2439 if (!dev->subordinate)
2440 return;
2441
2442 /* check HT MSI cap on this chipset and the root one.
2443 * a single one having MSI is enough to be sure that MSI are supported.
2444 */
2445 pdev = pci_get_slot(dev->bus, 0);
2446 if (!pdev)
2447 return;
2448 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2449 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
2450 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2451 }
2452 pci_dev_put(pdev);
2453 }
2454 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2455 quirk_nvidia_ck804_msi_ht_cap);
2456
2457 /* Force enable MSI mapping capability on HT bridges */
2458 static void ht_enable_msi_mapping(struct pci_dev *dev)
2459 {
2460 int pos, ttl = PCI_FIND_CAP_TTL;
2461
2462 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2463 while (pos && ttl--) {
2464 u8 flags;
2465
2466 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2467 &flags) == 0) {
2468 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2469
2470 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2471 flags | HT_MSI_FLAGS_ENABLE);
2472 }
2473 pos = pci_find_next_ht_capability(dev, pos,
2474 HT_CAPTYPE_MSI_MAPPING);
2475 }
2476 }
2477 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2478 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2479 ht_enable_msi_mapping);
2480
2481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2482 ht_enable_msi_mapping);
2483
2484 /* The P5N32-SLI motherboards from Asus have a problem with msi
2485 * for the MCP55 NIC. It is not yet determined whether the msi problem
2486 * also affects other devices. As for now, turn off msi for this device.
2487 */
2488 static void nvenet_msi_disable(struct pci_dev *dev)
2489 {
2490 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2491
2492 if (board_name &&
2493 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2494 strstr(board_name, "P5N32-E SLI"))) {
2495 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
2496 dev->no_msi = 1;
2497 }
2498 }
2499 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2500 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2501 nvenet_msi_disable);
2502
2503 /*
2504 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2505 * config register. This register controls the routing of legacy
2506 * interrupts from devices that route through the MCP55. If this register
2507 * is misprogrammed, interrupts are only sent to the BSP, unlike
2508 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2509 * having this register set properly prevents kdump from booting up
2510 * properly, so let's make sure that we have it set correctly.
2511 * Note that this is an undocumented register.
2512 */
2513 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2514 {
2515 u32 cfg;
2516
2517 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2518 return;
2519
2520 pci_read_config_dword(dev, 0x74, &cfg);
2521
2522 if (cfg & ((1 << 2) | (1 << 15))) {
2523 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2524 cfg &= ~((1 << 2) | (1 << 15));
2525 pci_write_config_dword(dev, 0x74, cfg);
2526 }
2527 }
2528
2529 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2530 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2531 nvbridge_check_legacy_irq_routing);
2532
2533 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2534 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2535 nvbridge_check_legacy_irq_routing);
2536
2537 static int ht_check_msi_mapping(struct pci_dev *dev)
2538 {
2539 int pos, ttl = PCI_FIND_CAP_TTL;
2540 int found = 0;
2541
2542 /* check if there is HT MSI cap or enabled on this device */
2543 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2544 while (pos && ttl--) {
2545 u8 flags;
2546
2547 if (found < 1)
2548 found = 1;
2549 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2550 &flags) == 0) {
2551 if (flags & HT_MSI_FLAGS_ENABLE) {
2552 if (found < 2) {
2553 found = 2;
2554 break;
2555 }
2556 }
2557 }
2558 pos = pci_find_next_ht_capability(dev, pos,
2559 HT_CAPTYPE_MSI_MAPPING);
2560 }
2561
2562 return found;
2563 }
2564
2565 static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2566 {
2567 struct pci_dev *dev;
2568 int pos;
2569 int i, dev_no;
2570 int found = 0;
2571
2572 dev_no = host_bridge->devfn >> 3;
2573 for (i = dev_no + 1; i < 0x20; i++) {
2574 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2575 if (!dev)
2576 continue;
2577
2578 /* found next host bridge ?*/
2579 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2580 if (pos != 0) {
2581 pci_dev_put(dev);
2582 break;
2583 }
2584
2585 if (ht_check_msi_mapping(dev)) {
2586 found = 1;
2587 pci_dev_put(dev);
2588 break;
2589 }
2590 pci_dev_put(dev);
2591 }
2592
2593 return found;
2594 }
2595
2596 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2597 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2598
2599 static int is_end_of_ht_chain(struct pci_dev *dev)
2600 {
2601 int pos, ctrl_off;
2602 int end = 0;
2603 u16 flags, ctrl;
2604
2605 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2606
2607 if (!pos)
2608 goto out;
2609
2610 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2611
2612 ctrl_off = ((flags >> 10) & 1) ?
2613 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2614 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2615
2616 if (ctrl & (1 << 6))
2617 end = 1;
2618
2619 out:
2620 return end;
2621 }
2622
2623 static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2624 {
2625 struct pci_dev *host_bridge;
2626 int pos;
2627 int i, dev_no;
2628 int found = 0;
2629
2630 dev_no = dev->devfn >> 3;
2631 for (i = dev_no; i >= 0; i--) {
2632 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2633 if (!host_bridge)
2634 continue;
2635
2636 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2637 if (pos != 0) {
2638 found = 1;
2639 break;
2640 }
2641 pci_dev_put(host_bridge);
2642 }
2643
2644 if (!found)
2645 return;
2646
2647 /* don't enable end_device/host_bridge with leaf directly here */
2648 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2649 host_bridge_with_leaf(host_bridge))
2650 goto out;
2651
2652 /* root did that ! */
2653 if (msi_ht_cap_enabled(host_bridge))
2654 goto out;
2655
2656 ht_enable_msi_mapping(dev);
2657
2658 out:
2659 pci_dev_put(host_bridge);
2660 }
2661
2662 static void ht_disable_msi_mapping(struct pci_dev *dev)
2663 {
2664 int pos, ttl = PCI_FIND_CAP_TTL;
2665
2666 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2667 while (pos && ttl--) {
2668 u8 flags;
2669
2670 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2671 &flags) == 0) {
2672 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
2673
2674 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2675 flags & ~HT_MSI_FLAGS_ENABLE);
2676 }
2677 pos = pci_find_next_ht_capability(dev, pos,
2678 HT_CAPTYPE_MSI_MAPPING);
2679 }
2680 }
2681
2682 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2683 {
2684 struct pci_dev *host_bridge;
2685 int pos;
2686 int found;
2687
2688 if (!pci_msi_enabled())
2689 return;
2690
2691 /* check if there is HT MSI cap or enabled on this device */
2692 found = ht_check_msi_mapping(dev);
2693
2694 /* no HT MSI CAP */
2695 if (found == 0)
2696 return;
2697
2698 /*
2699 * HT MSI mapping should be disabled on devices that are below
2700 * a non-Hypertransport host bridge. Locate the host bridge...
2701 */
2702 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2703 if (host_bridge == NULL) {
2704 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2705 return;
2706 }
2707
2708 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2709 if (pos != 0) {
2710 /* Host bridge is to HT */
2711 if (found == 1) {
2712 /* it is not enabled, try to enable it */
2713 if (all)
2714 ht_enable_msi_mapping(dev);
2715 else
2716 nv_ht_enable_msi_mapping(dev);
2717 }
2718 goto out;
2719 }
2720
2721 /* HT MSI is not enabled */
2722 if (found == 1)
2723 goto out;
2724
2725 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2726 ht_disable_msi_mapping(dev);
2727
2728 out:
2729 pci_dev_put(host_bridge);
2730 }
2731
2732 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2733 {
2734 return __nv_msi_ht_cap_quirk(dev, 1);
2735 }
2736
2737 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2738 {
2739 return __nv_msi_ht_cap_quirk(dev, 0);
2740 }
2741
2742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2743 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2744
2745 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2746 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2747
2748 static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2749 {
2750 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2751 }
2752 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2753 {
2754 struct pci_dev *p;
2755
2756 /* SB700 MSI issue will be fixed at HW level from revision A21,
2757 * we need check PCI REVISION ID of SMBus controller to get SB700
2758 * revision.
2759 */
2760 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2761 NULL);
2762 if (!p)
2763 return;
2764
2765 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2766 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2767 pci_dev_put(p);
2768 }
2769 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2770 {
2771 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2772 if (dev->revision < 0x18) {
2773 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2774 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2775 }
2776 }
2777 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2778 PCI_DEVICE_ID_TIGON3_5780,
2779 quirk_msi_intx_disable_bug);
2780 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2781 PCI_DEVICE_ID_TIGON3_5780S,
2782 quirk_msi_intx_disable_bug);
2783 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2784 PCI_DEVICE_ID_TIGON3_5714,
2785 quirk_msi_intx_disable_bug);
2786 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2787 PCI_DEVICE_ID_TIGON3_5714S,
2788 quirk_msi_intx_disable_bug);
2789 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2790 PCI_DEVICE_ID_TIGON3_5715,
2791 quirk_msi_intx_disable_bug);
2792 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2793 PCI_DEVICE_ID_TIGON3_5715S,
2794 quirk_msi_intx_disable_bug);
2795
2796 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2797 quirk_msi_intx_disable_ati_bug);
2798 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2799 quirk_msi_intx_disable_ati_bug);
2800 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2801 quirk_msi_intx_disable_ati_bug);
2802 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2803 quirk_msi_intx_disable_ati_bug);
2804 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2805 quirk_msi_intx_disable_ati_bug);
2806
2807 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2808 quirk_msi_intx_disable_bug);
2809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2810 quirk_msi_intx_disable_bug);
2811 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2812 quirk_msi_intx_disable_bug);
2813
2814 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2815 quirk_msi_intx_disable_bug);
2816 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2817 quirk_msi_intx_disable_bug);
2818 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2819 quirk_msi_intx_disable_bug);
2820 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2821 quirk_msi_intx_disable_bug);
2822 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2823 quirk_msi_intx_disable_bug);
2824 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2825 quirk_msi_intx_disable_bug);
2826 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2827 quirk_msi_intx_disable_qca_bug);
2828 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2829 quirk_msi_intx_disable_qca_bug);
2830 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2831 quirk_msi_intx_disable_qca_bug);
2832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2833 quirk_msi_intx_disable_qca_bug);
2834 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2835 quirk_msi_intx_disable_qca_bug);
2836 #endif /* CONFIG_PCI_MSI */
2837
2838 /* Allow manual resource allocation for PCI hotplug bridges
2839 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2840 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2841 * kernel fails to allocate resources when hotplug device is
2842 * inserted and PCI bus is rescanned.
2843 */
2844 static void quirk_hotplug_bridge(struct pci_dev *dev)
2845 {
2846 dev->is_hotplug_bridge = 1;
2847 }
2848
2849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2850
2851 /*
2852 * This is a quirk for the Ricoh MMC controller found as a part of
2853 * some mulifunction chips.
2854
2855 * This is very similar and based on the ricoh_mmc driver written by
2856 * Philip Langdale. Thank you for these magic sequences.
2857 *
2858 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2859 * and one or both of cardbus or firewire.
2860 *
2861 * It happens that they implement SD and MMC
2862 * support as separate controllers (and PCI functions). The linux SDHCI
2863 * driver supports MMC cards but the chip detects MMC cards in hardware
2864 * and directs them to the MMC controller - so the SDHCI driver never sees
2865 * them.
2866 *
2867 * To get around this, we must disable the useless MMC controller.
2868 * At that point, the SDHCI controller will start seeing them
2869 * It seems to be the case that the relevant PCI registers to deactivate the
2870 * MMC controller live on PCI function 0, which might be the cardbus controller
2871 * or the firewire controller, depending on the particular chip in question
2872 *
2873 * This has to be done early, because as soon as we disable the MMC controller
2874 * other pci functions shift up one level, e.g. function #2 becomes function
2875 * #1, and this will confuse the pci core.
2876 */
2877
2878 #ifdef CONFIG_MMC_RICOH_MMC
2879 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2880 {
2881 /* disable via cardbus interface */
2882 u8 write_enable;
2883 u8 write_target;
2884 u8 disable;
2885
2886 /* disable must be done via function #0 */
2887 if (PCI_FUNC(dev->devfn))
2888 return;
2889
2890 pci_read_config_byte(dev, 0xB7, &disable);
2891 if (disable & 0x02)
2892 return;
2893
2894 pci_read_config_byte(dev, 0x8E, &write_enable);
2895 pci_write_config_byte(dev, 0x8E, 0xAA);
2896 pci_read_config_byte(dev, 0x8D, &write_target);
2897 pci_write_config_byte(dev, 0x8D, 0xB7);
2898 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2899 pci_write_config_byte(dev, 0x8E, write_enable);
2900 pci_write_config_byte(dev, 0x8D, write_target);
2901
2902 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2903 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2904 }
2905 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2906 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2907
2908 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2909 {
2910 /* disable via firewire interface */
2911 u8 write_enable;
2912 u8 disable;
2913
2914 /* disable must be done via function #0 */
2915 if (PCI_FUNC(dev->devfn))
2916 return;
2917 /*
2918 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
2919 * certain types of SD/MMC cards. Lowering the SD base
2920 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2921 *
2922 * 0x150 - SD2.0 mode enable for changing base clock
2923 * frequency to 50Mhz
2924 * 0xe1 - Base clock frequency
2925 * 0x32 - 50Mhz new clock frequency
2926 * 0xf9 - Key register for 0x150
2927 * 0xfc - key register for 0xe1
2928 */
2929 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2930 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2931 pci_write_config_byte(dev, 0xf9, 0xfc);
2932 pci_write_config_byte(dev, 0x150, 0x10);
2933 pci_write_config_byte(dev, 0xf9, 0x00);
2934 pci_write_config_byte(dev, 0xfc, 0x01);
2935 pci_write_config_byte(dev, 0xe1, 0x32);
2936 pci_write_config_byte(dev, 0xfc, 0x00);
2937
2938 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2939 }
2940
2941 pci_read_config_byte(dev, 0xCB, &disable);
2942
2943 if (disable & 0x02)
2944 return;
2945
2946 pci_read_config_byte(dev, 0xCA, &write_enable);
2947 pci_write_config_byte(dev, 0xCA, 0x57);
2948 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2949 pci_write_config_byte(dev, 0xCA, write_enable);
2950
2951 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2952 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2953
2954 }
2955 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2956 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2957 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2958 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2959 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2960 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2961 #endif /*CONFIG_MMC_RICOH_MMC*/
2962
2963 #ifdef CONFIG_DMAR_TABLE
2964 #define VTUNCERRMSK_REG 0x1ac
2965 #define VTD_MSK_SPEC_ERRORS (1 << 31)
2966 /*
2967 * This is a quirk for masking vt-d spec defined errors to platform error
2968 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2969 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2970 * on the RAS config settings of the platform) when a vt-d fault happens.
2971 * The resulting SMI caused the system to hang.
2972 *
2973 * VT-d spec related errors are already handled by the VT-d OS code, so no
2974 * need to report the same error through other channels.
2975 */
2976 static void vtd_mask_spec_errors(struct pci_dev *dev)
2977 {
2978 u32 word;
2979
2980 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2981 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2982 }
2983 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2984 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2985 #endif
2986
2987 static void fixup_ti816x_class(struct pci_dev *dev)
2988 {
2989 u32 class = dev->class;
2990
2991 /* TI 816x devices do not have class code set when in PCIe boot mode */
2992 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2993 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2994 class, dev->class);
2995 }
2996 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2997 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2998
2999 /* Some PCIe devices do not work reliably with the claimed maximum
3000 * payload size supported.
3001 */
3002 static void fixup_mpss_256(struct pci_dev *dev)
3003 {
3004 dev->pcie_mpss = 1; /* 256 bytes */
3005 }
3006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3007 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
3008 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3009 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
3010 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
3011 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
3012
3013 /* Intel 5000 and 5100 Memory controllers have an errata with read completion
3014 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
3015 * Since there is no way of knowing what the PCIE MPS on each fabric will be
3016 * until all of the devices are discovered and buses walked, read completion
3017 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3018 * it is possible to hotplug a device with MPS of 256B.
3019 */
3020 static void quirk_intel_mc_errata(struct pci_dev *dev)
3021 {
3022 int err;
3023 u16 rcc;
3024
3025 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
3026 pcie_bus_config == PCIE_BUS_DEFAULT)
3027 return;
3028
3029 /* Intel errata specifies bits to change but does not say what they are.
3030 * Keeping them magical until such time as the registers and values can
3031 * be explained.
3032 */
3033 err = pci_read_config_word(dev, 0x48, &rcc);
3034 if (err) {
3035 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
3036 return;
3037 }
3038
3039 if (!(rcc & (1 << 10)))
3040 return;
3041
3042 rcc &= ~(1 << 10);
3043
3044 err = pci_write_config_word(dev, 0x48, rcc);
3045 if (err) {
3046 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
3047 return;
3048 }
3049
3050 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
3051 }
3052 /* Intel 5000 series memory controllers and ports 2-7 */
3053 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3054 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3057 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3058 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3059 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3060 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3061 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3062 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3063 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3064 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3065 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3066 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3067 /* Intel 5100 series memory controllers and ports 2-7 */
3068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3069 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3070 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3071 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3074 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3075 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3076 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3077 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3078 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3079
3080
3081 /*
3082 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3083 * work around this, query the size it should be configured to by the device and
3084 * modify the resource end to correspond to this new size.
3085 */
3086 static void quirk_intel_ntb(struct pci_dev *dev)
3087 {
3088 int rc;
3089 u8 val;
3090
3091 rc = pci_read_config_byte(dev, 0x00D0, &val);
3092 if (rc)
3093 return;
3094
3095 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3096
3097 rc = pci_read_config_byte(dev, 0x00D1, &val);
3098 if (rc)
3099 return;
3100
3101 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3102 }
3103 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3104 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3105
3106 static ktime_t fixup_debug_start(struct pci_dev *dev,
3107 void (*fn)(struct pci_dev *dev))
3108 {
3109 ktime_t calltime = 0;
3110
3111 dev_dbg(&dev->dev, "calling %pF\n", fn);
3112 if (initcall_debug) {
3113 pr_debug("calling %pF @ %i for %s\n",
3114 fn, task_pid_nr(current), dev_name(&dev->dev));
3115 calltime = ktime_get();
3116 }
3117
3118 return calltime;
3119 }
3120
3121 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3122 void (*fn)(struct pci_dev *dev))
3123 {
3124 ktime_t delta, rettime;
3125 unsigned long long duration;
3126
3127 if (initcall_debug) {
3128 rettime = ktime_get();
3129 delta = ktime_sub(rettime, calltime);
3130 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3131 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3132 fn, duration, dev_name(&dev->dev));
3133 }
3134 }
3135
3136 /*
3137 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3138 * even though no one is handling them (f.e. i915 driver is never loaded).
3139 * Additionally the interrupt destination is not set up properly
3140 * and the interrupt ends up -somewhere-.
3141 *
3142 * These spurious interrupts are "sticky" and the kernel disables
3143 * the (shared) interrupt line after 100.000+ generated interrupts.
3144 *
3145 * Fix it by disabling the still enabled interrupts.
3146 * This resolves crashes often seen on monitor unplug.
3147 */
3148 #define I915_DEIER_REG 0x4400c
3149 static void disable_igfx_irq(struct pci_dev *dev)
3150 {
3151 void __iomem *regs = pci_iomap(dev, 0, 0);
3152 if (regs == NULL) {
3153 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3154 return;
3155 }
3156
3157 /* Check if any interrupt line is still enabled */
3158 if (readl(regs + I915_DEIER_REG) != 0) {
3159 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3160
3161 writel(0, regs + I915_DEIER_REG);
3162 }
3163
3164 pci_iounmap(dev, regs);
3165 }
3166 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3167 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3168 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3169
3170 /*
3171 * PCI devices which are on Intel chips can skip the 10ms delay
3172 * before entering D3 mode.
3173 */
3174 static void quirk_remove_d3_delay(struct pci_dev *dev)
3175 {
3176 dev->d3_delay = 0;
3177 }
3178 /* C600 Series devices do not need 10ms d3_delay */
3179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3182 /* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3183 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3184 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3186 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3187 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3189 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3190 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3192 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3193 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3194 /* Intel Cherrytrail devices do not need 10ms d3_delay */
3195 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3199 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3202 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3204
3205 /*
3206 * Some devices may pass our check in pci_intx_mask_supported() if
3207 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3208 * support this feature.
3209 */
3210 static void quirk_broken_intx_masking(struct pci_dev *dev)
3211 {
3212 dev->broken_intx_masking = 1;
3213 }
3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3215 quirk_broken_intx_masking);
3216 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3217 quirk_broken_intx_masking);
3218
3219 /*
3220 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3221 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3222 *
3223 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3224 */
3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3226 quirk_broken_intx_masking);
3227
3228 /*
3229 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3230 * DisINTx can be set but the interrupt status bit is non-functional.
3231 */
3232 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3233 quirk_broken_intx_masking);
3234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3235 quirk_broken_intx_masking);
3236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3237 quirk_broken_intx_masking);
3238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3239 quirk_broken_intx_masking);
3240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3241 quirk_broken_intx_masking);
3242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3243 quirk_broken_intx_masking);
3244 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3245 quirk_broken_intx_masking);
3246 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3247 quirk_broken_intx_masking);
3248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3249 quirk_broken_intx_masking);
3250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3251 quirk_broken_intx_masking);
3252 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3253 quirk_broken_intx_masking);
3254 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3255 quirk_broken_intx_masking);
3256 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3257 quirk_broken_intx_masking);
3258 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3259 quirk_broken_intx_masking);
3260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3261 quirk_broken_intx_masking);
3262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3263 quirk_broken_intx_masking);
3264
3265 static u16 mellanox_broken_intx_devs[] = {
3266 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3267 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3268 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3269 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3270 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3271 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3272 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3273 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3274 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3275 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3276 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3277 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3278 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3279 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3280 };
3281
3282 #define CONNECTX_4_CURR_MAX_MINOR 99
3283 #define CONNECTX_4_INTX_SUPPORT_MINOR 14
3284
3285 /*
3286 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3287 * If so, don't mark it as broken.
3288 * FW minor > 99 means older FW version format and no INTx masking support.
3289 * FW minor < 14 means new FW version format and no INTx masking support.
3290 */
3291 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3292 {
3293 __be32 __iomem *fw_ver;
3294 u16 fw_major;
3295 u16 fw_minor;
3296 u16 fw_subminor;
3297 u32 fw_maj_min;
3298 u32 fw_sub_min;
3299 int i;
3300
3301 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3302 if (pdev->device == mellanox_broken_intx_devs[i]) {
3303 pdev->broken_intx_masking = 1;
3304 return;
3305 }
3306 }
3307
3308 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3309 * support so shouldn't be checked further
3310 */
3311 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3312 return;
3313
3314 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3315 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3316 return;
3317
3318 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3319 if (pci_enable_device_mem(pdev)) {
3320 dev_warn(&pdev->dev, "Can't enable device memory\n");
3321 return;
3322 }
3323
3324 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3325 if (!fw_ver) {
3326 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3327 goto out;
3328 }
3329
3330 /* Reading from resource space should be 32b aligned */
3331 fw_maj_min = ioread32be(fw_ver);
3332 fw_sub_min = ioread32be(fw_ver + 1);
3333 fw_major = fw_maj_min & 0xffff;
3334 fw_minor = fw_maj_min >> 16;
3335 fw_subminor = fw_sub_min & 0xffff;
3336 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3337 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3338 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3339 fw_major, fw_minor, fw_subminor, pdev->device ==
3340 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3341 pdev->broken_intx_masking = 1;
3342 }
3343
3344 iounmap(fw_ver);
3345
3346 out:
3347 pci_disable_device(pdev);
3348 }
3349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3350 mellanox_check_broken_intx_masking);
3351
3352 static void quirk_no_bus_reset(struct pci_dev *dev)
3353 {
3354 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3355 }
3356
3357 /*
3358 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3359 * The device will throw a Link Down error on AER-capable systems and
3360 * regardless of AER, config space of the device is never accessible again
3361 * and typically causes the system to hang or reset when access is attempted.
3362 * http://www.spinics.net/lists/linux-pci/msg34797.html
3363 */
3364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3365 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3367 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3368
3369 /*
3370 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
3371 * reset when used with certain child devices. After the reset, config
3372 * accesses to the child may fail.
3373 */
3374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3375
3376 static void quirk_no_pm_reset(struct pci_dev *dev)
3377 {
3378 /*
3379 * We can't do a bus reset on root bus devices, but an ineffective
3380 * PM reset may be better than nothing.
3381 */
3382 if (!pci_is_root_bus(dev->bus))
3383 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3384 }
3385
3386 /*
3387 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3388 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3389 * to have no effect on the device: it retains the framebuffer contents and
3390 * monitor sync. Advertising this support makes other layers, like VFIO,
3391 * assume pci_reset_function() is viable for this device. Mark it as
3392 * unavailable to skip it when testing reset methods.
3393 */
3394 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3395 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3396
3397 /*
3398 * Thunderbolt controllers with broken MSI hotplug signaling:
3399 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3400 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3401 */
3402 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3403 {
3404 if (pdev->is_hotplug_bridge &&
3405 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3406 pdev->revision <= 1))
3407 pdev->no_msi = 1;
3408 }
3409 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3410 quirk_thunderbolt_hotplug_msi);
3411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3412 quirk_thunderbolt_hotplug_msi);
3413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3414 quirk_thunderbolt_hotplug_msi);
3415 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3416 quirk_thunderbolt_hotplug_msi);
3417 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3418 quirk_thunderbolt_hotplug_msi);
3419
3420 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3421 {
3422 pci_set_vpd_size(dev, 8192);
3423 }
3424
3425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x20, quirk_chelsio_extend_vpd);
3426 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x21, quirk_chelsio_extend_vpd);
3427 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x22, quirk_chelsio_extend_vpd);
3428 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x23, quirk_chelsio_extend_vpd);
3429 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x24, quirk_chelsio_extend_vpd);
3430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x25, quirk_chelsio_extend_vpd);
3431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x26, quirk_chelsio_extend_vpd);
3432 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x30, quirk_chelsio_extend_vpd);
3433 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x31, quirk_chelsio_extend_vpd);
3434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x32, quirk_chelsio_extend_vpd);
3435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x35, quirk_chelsio_extend_vpd);
3436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x36, quirk_chelsio_extend_vpd);
3437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x37, quirk_chelsio_extend_vpd);
3438
3439 #ifdef CONFIG_ACPI
3440 /*
3441 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3442 *
3443 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3444 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3445 * be present after resume if a device was plugged in before suspend.
3446 *
3447 * The thunderbolt controller consists of a pcie switch with downstream
3448 * bridges leading to the NHI and to the tunnel pci bridges.
3449 *
3450 * This quirk cuts power to the whole chip. Therefore we have to apply it
3451 * during suspend_noirq of the upstream bridge.
3452 *
3453 * Power is automagically restored before resume. No action is needed.
3454 */
3455 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3456 {
3457 acpi_handle bridge, SXIO, SXFP, SXLV;
3458
3459 if (!x86_apple_machine)
3460 return;
3461 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3462 return;
3463 bridge = ACPI_HANDLE(&dev->dev);
3464 if (!bridge)
3465 return;
3466 /*
3467 * SXIO and SXLV are present only on machines requiring this quirk.
3468 * TB bridges in external devices might have the same device id as those
3469 * on the host, but they will not have the associated ACPI methods. This
3470 * implicitly checks that we are at the right bridge.
3471 */
3472 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3473 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3474 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3475 return;
3476 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3477
3478 /* magic sequence */
3479 acpi_execute_simple_method(SXIO, NULL, 1);
3480 acpi_execute_simple_method(SXFP, NULL, 0);
3481 msleep(300);
3482 acpi_execute_simple_method(SXLV, NULL, 0);
3483 acpi_execute_simple_method(SXIO, NULL, 0);
3484 acpi_execute_simple_method(SXLV, NULL, 0);
3485 }
3486 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3487 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3488 quirk_apple_poweroff_thunderbolt);
3489
3490 /*
3491 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3492 *
3493 * During suspend the thunderbolt controller is reset and all pci
3494 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3495 * during resume. We have to manually wait for the NHI since there is
3496 * no parent child relationship between the NHI and the tunneled
3497 * bridges.
3498 */
3499 static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3500 {
3501 struct pci_dev *sibling = NULL;
3502 struct pci_dev *nhi = NULL;
3503
3504 if (!x86_apple_machine)
3505 return;
3506 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3507 return;
3508 /*
3509 * Find the NHI and confirm that we are a bridge on the tb host
3510 * controller and not on a tb endpoint.
3511 */
3512 sibling = pci_get_slot(dev->bus, 0x0);
3513 if (sibling == dev)
3514 goto out; /* we are the downstream bridge to the NHI */
3515 if (!sibling || !sibling->subordinate)
3516 goto out;
3517 nhi = pci_get_slot(sibling->subordinate, 0x0);
3518 if (!nhi)
3519 goto out;
3520 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3521 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3522 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3523 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3524 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3525 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3526 goto out;
3527 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3528 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3529 out:
3530 pci_dev_put(nhi);
3531 pci_dev_put(sibling);
3532 }
3533 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3534 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3535 quirk_apple_wait_for_thunderbolt);
3536 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3537 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3538 quirk_apple_wait_for_thunderbolt);
3539 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3540 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3541 quirk_apple_wait_for_thunderbolt);
3542 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3543 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3544 quirk_apple_wait_for_thunderbolt);
3545 #endif
3546
3547 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3548 struct pci_fixup *end)
3549 {
3550 ktime_t calltime;
3551
3552 for (; f < end; f++)
3553 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3554 f->class == (u32) PCI_ANY_ID) &&
3555 (f->vendor == dev->vendor ||
3556 f->vendor == (u16) PCI_ANY_ID) &&
3557 (f->device == dev->device ||
3558 f->device == (u16) PCI_ANY_ID)) {
3559 calltime = fixup_debug_start(dev, f->hook);
3560 f->hook(dev);
3561 fixup_debug_report(dev, calltime, f->hook);
3562 }
3563 }
3564
3565 extern struct pci_fixup __start_pci_fixups_early[];
3566 extern struct pci_fixup __end_pci_fixups_early[];
3567 extern struct pci_fixup __start_pci_fixups_header[];
3568 extern struct pci_fixup __end_pci_fixups_header[];
3569 extern struct pci_fixup __start_pci_fixups_final[];
3570 extern struct pci_fixup __end_pci_fixups_final[];
3571 extern struct pci_fixup __start_pci_fixups_enable[];
3572 extern struct pci_fixup __end_pci_fixups_enable[];
3573 extern struct pci_fixup __start_pci_fixups_resume[];
3574 extern struct pci_fixup __end_pci_fixups_resume[];
3575 extern struct pci_fixup __start_pci_fixups_resume_early[];
3576 extern struct pci_fixup __end_pci_fixups_resume_early[];
3577 extern struct pci_fixup __start_pci_fixups_suspend[];
3578 extern struct pci_fixup __end_pci_fixups_suspend[];
3579 extern struct pci_fixup __start_pci_fixups_suspend_late[];
3580 extern struct pci_fixup __end_pci_fixups_suspend_late[];
3581
3582 static bool pci_apply_fixup_final_quirks;
3583
3584 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3585 {
3586 struct pci_fixup *start, *end;
3587
3588 switch (pass) {
3589 case pci_fixup_early:
3590 start = __start_pci_fixups_early;
3591 end = __end_pci_fixups_early;
3592 break;
3593
3594 case pci_fixup_header:
3595 start = __start_pci_fixups_header;
3596 end = __end_pci_fixups_header;
3597 break;
3598
3599 case pci_fixup_final:
3600 if (!pci_apply_fixup_final_quirks)
3601 return;
3602 start = __start_pci_fixups_final;
3603 end = __end_pci_fixups_final;
3604 break;
3605
3606 case pci_fixup_enable:
3607 start = __start_pci_fixups_enable;
3608 end = __end_pci_fixups_enable;
3609 break;
3610
3611 case pci_fixup_resume:
3612 start = __start_pci_fixups_resume;
3613 end = __end_pci_fixups_resume;
3614 break;
3615
3616 case pci_fixup_resume_early:
3617 start = __start_pci_fixups_resume_early;
3618 end = __end_pci_fixups_resume_early;
3619 break;
3620
3621 case pci_fixup_suspend:
3622 start = __start_pci_fixups_suspend;
3623 end = __end_pci_fixups_suspend;
3624 break;
3625
3626 case pci_fixup_suspend_late:
3627 start = __start_pci_fixups_suspend_late;
3628 end = __end_pci_fixups_suspend_late;
3629 break;
3630
3631 default:
3632 /* stupid compiler warning, you would think with an enum... */
3633 return;
3634 }
3635 pci_do_fixups(dev, start, end);
3636 }
3637 EXPORT_SYMBOL(pci_fixup_device);
3638
3639
3640 static int __init pci_apply_final_quirks(void)
3641 {
3642 struct pci_dev *dev = NULL;
3643 u8 cls = 0;
3644 u8 tmp;
3645
3646 if (pci_cache_line_size)
3647 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3648 pci_cache_line_size << 2);
3649
3650 pci_apply_fixup_final_quirks = true;
3651 for_each_pci_dev(dev) {
3652 pci_fixup_device(pci_fixup_final, dev);
3653 /*
3654 * If arch hasn't set it explicitly yet, use the CLS
3655 * value shared by all PCI devices. If there's a
3656 * mismatch, fall back to the default value.
3657 */
3658 if (!pci_cache_line_size) {
3659 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3660 if (!cls)
3661 cls = tmp;
3662 if (!tmp || cls == tmp)
3663 continue;
3664
3665 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3666 cls << 2, tmp << 2,
3667 pci_dfl_cache_line_size << 2);
3668 pci_cache_line_size = pci_dfl_cache_line_size;
3669 }
3670 }
3671
3672 if (!pci_cache_line_size) {
3673 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3674 cls << 2, pci_dfl_cache_line_size << 2);
3675 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3676 }
3677
3678 return 0;
3679 }
3680
3681 fs_initcall_sync(pci_apply_final_quirks);
3682
3683 /*
3684 * Following are device-specific reset methods which can be used to
3685 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3686 * not available.
3687 */
3688 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3689 {
3690 /*
3691 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3692 *
3693 * The 82599 supports FLR on VFs, but FLR support is reported only
3694 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3695 * Thus we must call pcie_flr() directly without first checking if it is
3696 * supported.
3697 */
3698 if (!probe)
3699 pcie_flr(dev);
3700 return 0;
3701 }
3702
3703 #define SOUTH_CHICKEN2 0xc2004
3704 #define PCH_PP_STATUS 0xc7200
3705 #define PCH_PP_CONTROL 0xc7204
3706 #define MSG_CTL 0x45010
3707 #define NSDE_PWR_STATE 0xd0100
3708 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3709
3710 static int reset_ivb_igd(struct pci_dev *dev, int probe)
3711 {
3712 void __iomem *mmio_base;
3713 unsigned long timeout;
3714 u32 val;
3715
3716 if (probe)
3717 return 0;
3718
3719 mmio_base = pci_iomap(dev, 0, 0);
3720 if (!mmio_base)
3721 return -ENOMEM;
3722
3723 iowrite32(0x00000002, mmio_base + MSG_CTL);
3724
3725 /*
3726 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3727 * driver loaded sets the right bits. However, this's a reset and
3728 * the bits have been set by i915 previously, so we clobber
3729 * SOUTH_CHICKEN2 register directly here.
3730 */
3731 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3732
3733 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3734 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3735
3736 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3737 do {
3738 val = ioread32(mmio_base + PCH_PP_STATUS);
3739 if ((val & 0xb0000000) == 0)
3740 goto reset_complete;
3741 msleep(10);
3742 } while (time_before(jiffies, timeout));
3743 dev_warn(&dev->dev, "timeout during reset\n");
3744
3745 reset_complete:
3746 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3747
3748 pci_iounmap(dev, mmio_base);
3749 return 0;
3750 }
3751
3752 /*
3753 * Device-specific reset method for Chelsio T4-based adapters.
3754 */
3755 static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3756 {
3757 u16 old_command;
3758 u16 msix_flags;
3759
3760 /*
3761 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3762 * that we have no device-specific reset method.
3763 */
3764 if ((dev->device & 0xf000) != 0x4000)
3765 return -ENOTTY;
3766
3767 /*
3768 * If this is the "probe" phase, return 0 indicating that we can
3769 * reset this device.
3770 */
3771 if (probe)
3772 return 0;
3773
3774 /*
3775 * T4 can wedge if there are DMAs in flight within the chip and Bus
3776 * Master has been disabled. We need to have it on till the Function
3777 * Level Reset completes. (BUS_MASTER is disabled in
3778 * pci_reset_function()).
3779 */
3780 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3781 pci_write_config_word(dev, PCI_COMMAND,
3782 old_command | PCI_COMMAND_MASTER);
3783
3784 /*
3785 * Perform the actual device function reset, saving and restoring
3786 * configuration information around the reset.
3787 */
3788 pci_save_state(dev);
3789
3790 /*
3791 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3792 * are disabled when an MSI-X interrupt message needs to be delivered.
3793 * So we briefly re-enable MSI-X interrupts for the duration of the
3794 * FLR. The pci_restore_state() below will restore the original
3795 * MSI-X state.
3796 */
3797 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3798 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3799 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3800 msix_flags |
3801 PCI_MSIX_FLAGS_ENABLE |
3802 PCI_MSIX_FLAGS_MASKALL);
3803
3804 pcie_flr(dev);
3805
3806 /*
3807 * Restore the configuration information (BAR values, etc.) including
3808 * the original PCI Configuration Space Command word, and return
3809 * success.
3810 */
3811 pci_restore_state(dev);
3812 pci_write_config_word(dev, PCI_COMMAND, old_command);
3813 return 0;
3814 }
3815
3816 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3817 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3818 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3819
3820 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3821 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3822 reset_intel_82599_sfp_virtfn },
3823 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3824 reset_ivb_igd },
3825 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3826 reset_ivb_igd },
3827 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3828 reset_chelsio_generic_dev },
3829 { 0 }
3830 };
3831
3832 /*
3833 * These device-specific reset methods are here rather than in a driver
3834 * because when a host assigns a device to a guest VM, the host may need
3835 * to reset the device but probably doesn't have a driver for it.
3836 */
3837 int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3838 {
3839 const struct pci_dev_reset_methods *i;
3840
3841 for (i = pci_dev_reset_methods; i->reset; i++) {
3842 if ((i->vendor == dev->vendor ||
3843 i->vendor == (u16)PCI_ANY_ID) &&
3844 (i->device == dev->device ||
3845 i->device == (u16)PCI_ANY_ID))
3846 return i->reset(dev, probe);
3847 }
3848
3849 return -ENOTTY;
3850 }
3851
3852 static void quirk_dma_func0_alias(struct pci_dev *dev)
3853 {
3854 if (PCI_FUNC(dev->devfn) != 0)
3855 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3856 }
3857
3858 /*
3859 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3860 *
3861 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3862 */
3863 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3864 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3865
3866 static void quirk_dma_func1_alias(struct pci_dev *dev)
3867 {
3868 if (PCI_FUNC(dev->devfn) != 1)
3869 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3870 }
3871
3872 /*
3873 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3874 * SKUs function 1 is present and is a legacy IDE controller, in other
3875 * SKUs this function is not present, making this a ghost requester.
3876 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3877 */
3878 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3879 quirk_dma_func1_alias);
3880 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3881 quirk_dma_func1_alias);
3882 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3883 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3884 quirk_dma_func1_alias);
3885 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3886 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3887 quirk_dma_func1_alias);
3888 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3889 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3890 quirk_dma_func1_alias);
3891 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3892 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3893 quirk_dma_func1_alias);
3894 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3895 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3896 quirk_dma_func1_alias);
3897 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3898 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3899 quirk_dma_func1_alias);
3900 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3901 quirk_dma_func1_alias);
3902 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3903 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3904 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3905 quirk_dma_func1_alias);
3906 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3907 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3908 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3909 quirk_dma_func1_alias);
3910
3911 /*
3912 * Some devices DMA with the wrong devfn, not just the wrong function.
3913 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3914 * the alias is "fixed" and independent of the device devfn.
3915 *
3916 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3917 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3918 * single device on the secondary bus. In reality, the single exposed
3919 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3920 * that provides a bridge to the internal bus of the I/O processor. The
3921 * controller supports private devices, which can be hidden from PCI config
3922 * space. In the case of the Adaptec 3405, a private device at 01.0
3923 * appears to be the DMA engine, which therefore needs to become a DMA
3924 * alias for the device.
3925 */
3926 static const struct pci_device_id fixed_dma_alias_tbl[] = {
3927 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3928 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3929 .driver_data = PCI_DEVFN(1, 0) },
3930 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3931 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3932 .driver_data = PCI_DEVFN(1, 0) },
3933 { 0 }
3934 };
3935
3936 static void quirk_fixed_dma_alias(struct pci_dev *dev)
3937 {
3938 const struct pci_device_id *id;
3939
3940 id = pci_match_id(fixed_dma_alias_tbl, dev);
3941 if (id)
3942 pci_add_dma_alias(dev, id->driver_data);
3943 }
3944
3945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3946
3947 /*
3948 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3949 * using the wrong DMA alias for the device. Some of these devices can be
3950 * used as either forward or reverse bridges, so we need to test whether the
3951 * device is operating in the correct mode. We could probably apply this
3952 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3953 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3954 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3955 */
3956 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3957 {
3958 if (!pci_is_root_bus(pdev->bus) &&
3959 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3960 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3961 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3962 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3963 }
3964 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3965 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3966 quirk_use_pcie_bridge_dma_alias);
3967 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3968 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3969 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3970 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3971 /* ITE 8893 has the same problem as the 8892 */
3972 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
3973 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3974 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3975
3976 /*
3977 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3978 * be added as aliases to the DMA device in order to allow buffer access
3979 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3980 * programmed in the EEPROM.
3981 */
3982 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3983 {
3984 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3985 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3986 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3987 }
3988 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3989 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3990
3991 /*
3992 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are
3993 * associated not at the root bus, but at a bridge below. This quirk avoids
3994 * generating invalid DMA aliases.
3995 */
3996 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
3997 {
3998 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
3999 }
4000 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
4001 quirk_bridge_cavm_thrx2_pcie_root);
4002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
4003 quirk_bridge_cavm_thrx2_pcie_root);
4004
4005 /*
4006 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4007 * class code. Fix it.
4008 */
4009 static void quirk_tw686x_class(struct pci_dev *pdev)
4010 {
4011 u32 class = pdev->class;
4012
4013 /* Use "Multimedia controller" class */
4014 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
4015 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
4016 class, pdev->class);
4017 }
4018 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
4019 quirk_tw686x_class);
4020 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
4021 quirk_tw686x_class);
4022 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
4023 quirk_tw686x_class);
4024 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4025 quirk_tw686x_class);
4026
4027 /*
4028 * Some devices have problems with Transaction Layer Packets with the Relaxed
4029 * Ordering Attribute set. Such devices should mark themselves and other
4030 * Device Drivers should check before sending TLPs with RO set.
4031 */
4032 static void quirk_relaxedordering_disable(struct pci_dev *dev)
4033 {
4034 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4035 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4036 }
4037
4038 /*
4039 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4040 * Complex has a Flow Control Credit issue which can cause performance
4041 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4042 */
4043 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4044 quirk_relaxedordering_disable);
4045 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4046 quirk_relaxedordering_disable);
4047 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4048 quirk_relaxedordering_disable);
4049 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4050 quirk_relaxedordering_disable);
4051 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4052 quirk_relaxedordering_disable);
4053 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4054 quirk_relaxedordering_disable);
4055 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4056 quirk_relaxedordering_disable);
4057 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4058 quirk_relaxedordering_disable);
4059 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4060 quirk_relaxedordering_disable);
4061 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4062 quirk_relaxedordering_disable);
4063 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4064 quirk_relaxedordering_disable);
4065 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4066 quirk_relaxedordering_disable);
4067 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4068 quirk_relaxedordering_disable);
4069 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4070 quirk_relaxedordering_disable);
4071 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4072 quirk_relaxedordering_disable);
4073 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4074 quirk_relaxedordering_disable);
4075 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4076 quirk_relaxedordering_disable);
4077 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4078 quirk_relaxedordering_disable);
4079 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4080 quirk_relaxedordering_disable);
4081 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4082 quirk_relaxedordering_disable);
4083 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4084 quirk_relaxedordering_disable);
4085 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4086 quirk_relaxedordering_disable);
4087 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4088 quirk_relaxedordering_disable);
4089 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4090 quirk_relaxedordering_disable);
4091 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4092 quirk_relaxedordering_disable);
4093 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4094 quirk_relaxedordering_disable);
4095 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4096 quirk_relaxedordering_disable);
4097 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4098 quirk_relaxedordering_disable);
4099
4100 /*
4101 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4102 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4103 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4104 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4105 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4106 * November 10, 2010). As a result, on this platform we can't use Relaxed
4107 * Ordering for Upstream TLPs.
4108 */
4109 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4110 quirk_relaxedordering_disable);
4111 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4112 quirk_relaxedordering_disable);
4113 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4114 quirk_relaxedordering_disable);
4115
4116 /*
4117 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4118 * values for the Attribute as were supplied in the header of the
4119 * corresponding Request, except as explicitly allowed when IDO is used."
4120 *
4121 * If a non-compliant device generates a completion with a different
4122 * attribute than the request, the receiver may accept it (which itself
4123 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4124 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4125 * device access timeout.
4126 *
4127 * If the non-compliant device generates completions with zero attributes
4128 * (instead of copying the attributes from the request), we can work around
4129 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4130 * upstream devices so they always generate requests with zero attributes.
4131 *
4132 * This affects other devices under the same Root Port, but since these
4133 * attributes are performance hints, there should be no functional problem.
4134 *
4135 * Note that Configuration Space accesses are never supposed to have TLP
4136 * Attributes, so we're safe waiting till after any Configuration Space
4137 * accesses to do the Root Port fixup.
4138 */
4139 static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4140 {
4141 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4142
4143 if (!root_port) {
4144 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4145 return;
4146 }
4147
4148 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4149 dev_name(&pdev->dev));
4150 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4151 PCI_EXP_DEVCTL_RELAX_EN |
4152 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4153 }
4154
4155 /*
4156 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4157 * Completion it generates.
4158 */
4159 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4160 {
4161 /*
4162 * This mask/compare operation selects for Physical Function 4 on a
4163 * T5. We only need to fix up the Root Port once for any of the
4164 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4165 * 0x54xx so we use that one,
4166 */
4167 if ((pdev->device & 0xff00) == 0x5400)
4168 quirk_disable_root_port_attributes(pdev);
4169 }
4170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4171 quirk_chelsio_T5_disable_root_port_attributes);
4172
4173 /*
4174 * AMD has indicated that the devices below do not support peer-to-peer
4175 * in any system where they are found in the southbridge with an AMD
4176 * IOMMU in the system. Multifunction devices that do not support
4177 * peer-to-peer between functions can claim to support a subset of ACS.
4178 * Such devices effectively enable request redirect (RR) and completion
4179 * redirect (CR) since all transactions are redirected to the upstream
4180 * root complex.
4181 *
4182 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4183 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4184 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4185 *
4186 * 1002:4385 SBx00 SMBus Controller
4187 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4188 * 1002:4383 SBx00 Azalia (Intel HDA)
4189 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4190 * 1002:4384 SBx00 PCI to PCI Bridge
4191 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
4192 *
4193 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4194 *
4195 * 1022:780f [AMD] FCH PCI Bridge
4196 * 1022:7809 [AMD] FCH USB OHCI Controller
4197 */
4198 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4199 {
4200 #ifdef CONFIG_ACPI
4201 struct acpi_table_header *header = NULL;
4202 acpi_status status;
4203
4204 /* Targeting multifunction devices on the SB (appears on root bus) */
4205 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4206 return -ENODEV;
4207
4208 /* The IVRS table describes the AMD IOMMU */
4209 status = acpi_get_table("IVRS", 0, &header);
4210 if (ACPI_FAILURE(status))
4211 return -ENODEV;
4212
4213 /* Filter out flags not applicable to multifunction */
4214 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4215
4216 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4217 #else
4218 return -ENODEV;
4219 #endif
4220 }
4221
4222 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4223 {
4224 /*
4225 * Effectively selects all downstream ports for whole ThunderX 1
4226 * family by 0xf800 mask (which represents 8 SoCs), while the lower
4227 * bits of device ID are used to indicate which subdevice is used
4228 * within the SoC.
4229 */
4230 return (pci_is_pcie(dev) &&
4231 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4232 ((dev->device & 0xf800) == 0xa000));
4233 }
4234
4235 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4236 {
4237 /*
4238 * Cavium root ports don't advertise an ACS capability. However,
4239 * the RTL internally implements similar protection as if ACS had
4240 * Request Redirection, Completion Redirection, Source Validation,
4241 * and Upstream Forwarding features enabled. Assert that the
4242 * hardware implements and enables equivalent ACS functionality for
4243 * these flags.
4244 */
4245 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4246
4247 if (!pci_quirk_cavium_acs_match(dev))
4248 return -ENOTTY;
4249
4250 return acs_flags ? 0 : 1;
4251 }
4252
4253 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4254 {
4255 /*
4256 * X-Gene root matching this quirk do not allow peer-to-peer
4257 * transactions with others, allowing masking out these bits as if they
4258 * were unimplemented in the ACS capability.
4259 */
4260 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4261
4262 return acs_flags ? 0 : 1;
4263 }
4264
4265 /*
4266 * Many Intel PCH root ports do provide ACS-like features to disable peer
4267 * transactions and validate bus numbers in requests, but do not provide an
4268 * actual PCIe ACS capability. This is the list of device IDs known to fall
4269 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4270 */
4271 static const u16 pci_quirk_intel_pch_acs_ids[] = {
4272 /* Ibexpeak PCH */
4273 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4274 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4275 /* Cougarpoint PCH */
4276 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4277 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4278 /* Pantherpoint PCH */
4279 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4280 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4281 /* Lynxpoint-H PCH */
4282 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4283 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4284 /* Lynxpoint-LP PCH */
4285 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4286 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4287 /* Wildcat PCH */
4288 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4289 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4290 /* Patsburg (X79) PCH */
4291 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4292 /* Wellsburg (X99) PCH */
4293 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4294 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4295 /* Lynx Point (9 series) PCH */
4296 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4297 };
4298
4299 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4300 {
4301 int i;
4302
4303 /* Filter out a few obvious non-matches first */
4304 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4305 return false;
4306
4307 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4308 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4309 return true;
4310
4311 return false;
4312 }
4313
4314 #define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4315
4316 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4317 {
4318 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4319 INTEL_PCH_ACS_FLAGS : 0;
4320
4321 if (!pci_quirk_intel_pch_acs_match(dev))
4322 return -ENOTTY;
4323
4324 return acs_flags & ~flags ? 0 : 1;
4325 }
4326
4327 /*
4328 * These QCOM root ports do provide ACS-like features to disable peer
4329 * transactions and validate bus numbers in requests, but do not provide an
4330 * actual PCIe ACS capability. Hardware supports source validation but it
4331 * will report the issue as Completer Abort instead of ACS Violation.
4332 * Hardware doesn't support peer-to-peer and each root port is a root
4333 * complex with unique segment numbers. It is not possible for one root
4334 * port to pass traffic to another root port. All PCIe transactions are
4335 * terminated inside the root port.
4336 */
4337 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4338 {
4339 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4340 int ret = acs_flags & ~flags ? 0 : 1;
4341
4342 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4343
4344 return ret;
4345 }
4346
4347 /*
4348 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4349 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4350 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4351 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4352 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4353 * control register is at offset 8 instead of 6 and we should probably use
4354 * dword accesses to them. This applies to the following PCI Device IDs, as
4355 * found in volume 1 of the datasheet[2]:
4356 *
4357 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4358 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4359 *
4360 * N.B. This doesn't fix what lspci shows.
4361 *
4362 * The 100 series chipset specification update includes this as errata #23[3].
4363 *
4364 * The 200 series chipset (Union Point) has the same bug according to the
4365 * specification update (Intel 200 Series Chipset Family Platform Controller
4366 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4367 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4368 * chipset include:
4369 *
4370 * 0xa290-0xa29f PCI Express Root port #{0-16}
4371 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4372 *
4373 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4374 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4375 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4376 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4377 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4378 */
4379 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4380 {
4381 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4382 return false;
4383
4384 switch (dev->device) {
4385 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4386 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
4387 return true;
4388 }
4389
4390 return false;
4391 }
4392
4393 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4394
4395 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4396 {
4397 int pos;
4398 u32 cap, ctrl;
4399
4400 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4401 return -ENOTTY;
4402
4403 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4404 if (!pos)
4405 return -ENOTTY;
4406
4407 /* see pci_acs_flags_enabled() */
4408 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4409 acs_flags &= (cap | PCI_ACS_EC);
4410
4411 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4412
4413 return acs_flags & ~ctrl ? 0 : 1;
4414 }
4415
4416 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4417 {
4418 /*
4419 * SV, TB, and UF are not relevant to multifunction endpoints.
4420 *
4421 * Multifunction devices are only required to implement RR, CR, and DT
4422 * in their ACS capability if they support peer-to-peer transactions.
4423 * Devices matching this quirk have been verified by the vendor to not
4424 * perform peer-to-peer with other functions, allowing us to mask out
4425 * these bits as if they were unimplemented in the ACS capability.
4426 */
4427 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4428 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4429
4430 return acs_flags ? 0 : 1;
4431 }
4432
4433 static const struct pci_dev_acs_enabled {
4434 u16 vendor;
4435 u16 device;
4436 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4437 } pci_dev_acs_enabled[] = {
4438 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4439 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4440 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4441 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4442 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4443 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4444 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4445 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4446 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4447 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4448 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4449 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4450 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4451 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4452 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4453 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4454 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4455 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4456 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4457 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4458 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4459 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4460 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4461 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4462 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4463 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4464 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4465 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4466 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4467 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4468 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4469 /* 82580 */
4470 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4471 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4472 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4473 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4474 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4475 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4476 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4477 /* 82576 */
4478 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4479 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4480 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4481 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4482 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4483 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4484 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4485 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4486 /* 82575 */
4487 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4488 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4489 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4490 /* I350 */
4491 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4492 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4493 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4494 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4495 /* 82571 (Quads omitted due to non-ACS switch) */
4496 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4497 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4498 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4499 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4500 /* I219 */
4501 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4502 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4503 /* QCOM QDF2xxx root ports */
4504 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4505 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4506 /* Intel PCH root ports */
4507 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4508 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4509 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4510 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4511 /* Cavium ThunderX */
4512 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4513 /* APM X-Gene */
4514 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4515 { 0 }
4516 };
4517
4518 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4519 {
4520 const struct pci_dev_acs_enabled *i;
4521 int ret;
4522
4523 /*
4524 * Allow devices that do not expose standard PCIe ACS capabilities
4525 * or control to indicate their support here. Multi-function express
4526 * devices which do not allow internal peer-to-peer between functions,
4527 * but do not implement PCIe ACS may wish to return true here.
4528 */
4529 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4530 if ((i->vendor == dev->vendor ||
4531 i->vendor == (u16)PCI_ANY_ID) &&
4532 (i->device == dev->device ||
4533 i->device == (u16)PCI_ANY_ID)) {
4534 ret = i->acs_enabled(dev, acs_flags);
4535 if (ret >= 0)
4536 return ret;
4537 }
4538 }
4539
4540 return -ENOTTY;
4541 }
4542
4543 /* Config space offset of Root Complex Base Address register */
4544 #define INTEL_LPC_RCBA_REG 0xf0
4545 /* 31:14 RCBA address */
4546 #define INTEL_LPC_RCBA_MASK 0xffffc000
4547 /* RCBA Enable */
4548 #define INTEL_LPC_RCBA_ENABLE (1 << 0)
4549
4550 /* Backbone Scratch Pad Register */
4551 #define INTEL_BSPR_REG 0x1104
4552 /* Backbone Peer Non-Posted Disable */
4553 #define INTEL_BSPR_REG_BPNPD (1 << 8)
4554 /* Backbone Peer Posted Disable */
4555 #define INTEL_BSPR_REG_BPPD (1 << 9)
4556
4557 /* Upstream Peer Decode Configuration Register */
4558 #define INTEL_UPDCR_REG 0x1114
4559 /* 5:0 Peer Decode Enable bits */
4560 #define INTEL_UPDCR_REG_MASK 0x3f
4561
4562 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4563 {
4564 u32 rcba, bspr, updcr;
4565 void __iomem *rcba_mem;
4566
4567 /*
4568 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4569 * are D28:F* and therefore get probed before LPC, thus we can't
4570 * use pci_get_slot/pci_read_config_dword here.
4571 */
4572 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4573 INTEL_LPC_RCBA_REG, &rcba);
4574 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4575 return -EINVAL;
4576
4577 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4578 PAGE_ALIGN(INTEL_UPDCR_REG));
4579 if (!rcba_mem)
4580 return -ENOMEM;
4581
4582 /*
4583 * The BSPR can disallow peer cycles, but it's set by soft strap and
4584 * therefore read-only. If both posted and non-posted peer cycles are
4585 * disallowed, we're ok. If either are allowed, then we need to use
4586 * the UPDCR to disable peer decodes for each port. This provides the
4587 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4588 */
4589 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4590 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4591 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4592 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4593 if (updcr & INTEL_UPDCR_REG_MASK) {
4594 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4595 updcr &= ~INTEL_UPDCR_REG_MASK;
4596 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4597 }
4598 }
4599
4600 iounmap(rcba_mem);
4601 return 0;
4602 }
4603
4604 /* Miscellaneous Port Configuration register */
4605 #define INTEL_MPC_REG 0xd8
4606 /* MPC: Invalid Receive Bus Number Check Enable */
4607 #define INTEL_MPC_REG_IRBNCE (1 << 26)
4608
4609 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4610 {
4611 u32 mpc;
4612
4613 /*
4614 * When enabled, the IRBNCE bit of the MPC register enables the
4615 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4616 * ensures that requester IDs fall within the bus number range
4617 * of the bridge. Enable if not already.
4618 */
4619 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4620 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4621 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4622 mpc |= INTEL_MPC_REG_IRBNCE;
4623 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4624 }
4625 }
4626
4627 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4628 {
4629 if (!pci_quirk_intel_pch_acs_match(dev))
4630 return -ENOTTY;
4631
4632 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4633 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4634 return 0;
4635 }
4636
4637 pci_quirk_enable_intel_rp_mpc_acs(dev);
4638
4639 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4640
4641 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4642
4643 return 0;
4644 }
4645
4646 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4647 {
4648 int pos;
4649 u32 cap, ctrl;
4650
4651 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4652 return -ENOTTY;
4653
4654 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4655 if (!pos)
4656 return -ENOTTY;
4657
4658 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4659 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4660
4661 ctrl |= (cap & PCI_ACS_SV);
4662 ctrl |= (cap & PCI_ACS_RR);
4663 ctrl |= (cap & PCI_ACS_CR);
4664 ctrl |= (cap & PCI_ACS_UF);
4665
4666 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4667
4668 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4669
4670 return 0;
4671 }
4672
4673 static const struct pci_dev_enable_acs {
4674 u16 vendor;
4675 u16 device;
4676 int (*enable_acs)(struct pci_dev *dev);
4677 } pci_dev_enable_acs[] = {
4678 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4679 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4680 { 0 }
4681 };
4682
4683 int pci_dev_specific_enable_acs(struct pci_dev *dev)
4684 {
4685 const struct pci_dev_enable_acs *i;
4686 int ret;
4687
4688 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4689 if ((i->vendor == dev->vendor ||
4690 i->vendor == (u16)PCI_ANY_ID) &&
4691 (i->device == dev->device ||
4692 i->device == (u16)PCI_ANY_ID)) {
4693 ret = i->enable_acs(dev);
4694 if (ret >= 0)
4695 return ret;
4696 }
4697 }
4698
4699 return -ENOTTY;
4700 }
4701
4702 /*
4703 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4704 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4705 * Next Capability pointer in the MSI Capability Structure should point to
4706 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4707 * the list.
4708 */
4709 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4710 {
4711 int pos, i = 0;
4712 u8 next_cap;
4713 u16 reg16, *cap;
4714 struct pci_cap_saved_state *state;
4715
4716 /* Bail if the hardware bug is fixed */
4717 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4718 return;
4719
4720 /* Bail if MSI Capability Structure is not found for some reason */
4721 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4722 if (!pos)
4723 return;
4724
4725 /*
4726 * Bail if Next Capability pointer in the MSI Capability Structure
4727 * is not the expected incorrect 0x00.
4728 */
4729 pci_read_config_byte(pdev, pos + 1, &next_cap);
4730 if (next_cap)
4731 return;
4732
4733 /*
4734 * PCIe Capability Structure is expected to be at 0x50 and should
4735 * terminate the list (Next Capability pointer is 0x00). Verify
4736 * Capability Id and Next Capability pointer is as expected.
4737 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4738 * to correctly set kernel data structures which have already been
4739 * set incorrectly due to the hardware bug.
4740 */
4741 pos = 0x50;
4742 pci_read_config_word(pdev, pos, &reg16);
4743 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4744 u32 status;
4745 #ifndef PCI_EXP_SAVE_REGS
4746 #define PCI_EXP_SAVE_REGS 7
4747 #endif
4748 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4749
4750 pdev->pcie_cap = pos;
4751 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4752 pdev->pcie_flags_reg = reg16;
4753 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4754 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4755
4756 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4757 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4758 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4759 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4760
4761 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4762 return;
4763
4764 /*
4765 * Save PCIE cap
4766 */
4767 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4768 if (!state)
4769 return;
4770
4771 state->cap.cap_nr = PCI_CAP_ID_EXP;
4772 state->cap.cap_extended = 0;
4773 state->cap.size = size;
4774 cap = (u16 *)&state->cap.data[0];
4775 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4776 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4777 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4778 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4779 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4780 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4781 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4782 hlist_add_head(&state->next, &pdev->saved_cap_space);
4783 }
4784 }
4785 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4786
4787 /* FLR may cause some 82579 devices to hang. */
4788 static void quirk_intel_no_flr(struct pci_dev *dev)
4789 {
4790 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4791 }
4792 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4793 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4794
4795 static void quirk_no_ext_tags(struct pci_dev *pdev)
4796 {
4797 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4798
4799 if (!bridge)
4800 return;
4801
4802 bridge->no_ext_tags = 1;
4803 dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
4804
4805 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4806 }
4807 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
4808 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4809 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4810
4811 #ifdef CONFIG_PCI_ATS
4812 /*
4813 * Some devices have a broken ATS implementation causing IOMMU stalls.
4814 * Don't use ATS for those devices.
4815 */
4816 static void quirk_no_ats(struct pci_dev *pdev)
4817 {
4818 dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
4819 pdev->ats_cap = 0;
4820 }
4821
4822 /* AMD Stoney platform GPU */
4823 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4824 #endif /* CONFIG_PCI_ATS */
4825
4826 /* Freescale PCIe doesn't support MSI in RC mode */
4827 static void quirk_fsl_no_msi(struct pci_dev *pdev)
4828 {
4829 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4830 pdev->no_msi = 1;
4831 }
4832 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
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